A peak retrieval and feature extraction method suitable for environments with strong electromagnetic interference
By employing an attention-enhanced temporal convolutional network and a dual-RAM ping-pong buffer mechanism in a strong electromagnetic interference environment, real-time detection of signal peaks and continuous data output are achieved, solving the real-time and continuous problems of signal peak detection in existing technologies and improving anti-interference capability and data processing accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA UNIV OF SCI & TECH
- Filing Date
- 2026-04-16
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies struggle to achieve real-time, accurate detection of signal peaks and continuous data output in environments with strong electromagnetic interference, and also suffer from false peaks and data loss issues.
A peak detection method based on attention-enhanced temporal convolutional networks is adopted, which is combined with a continuous comparison method and a dual RAM ping-pong buffer mechanism to achieve real-time detection of signal peaks and continuous data output.
High real-time performance and strong anti-interference capability of signal peaks were achieved in strong electromagnetic interference environments, ensuring the continuity and accuracy of the data processing link and avoiding false peaks and data loss.
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Abstract
Description
[0001] This invention relates to the field of signal processing and high-speed data acquisition technology, specifically to a peak retrieval and feature extraction method and system suitable for environments with strong electromagnetic interference, which can realize real-time detection of signal peaks and stable output of feature parameters under high-speed sampling conditions. Background Technology
[0002] In nuclear fusion devices, power system transient monitoring, and strong electromagnetic industrial environments, the voltage, current, and other signals collected by sensors are often accompanied by complex electromagnetic interference. These signals are characterized by strong transients, high randomness, and severe noise superposition. Their effective information is often reflected in characteristic parameters such as peak amplitude, pulse width, and peak interval.
[0003] Commonly used peak detection methods in existing technologies mainly include threshold decision method, sliding window method, and differential method. Among them, threshold decision method relies on a fixed threshold and is difficult to adapt to changes in signal amplitude; sliding window method has high computational complexity and is difficult to achieve real-time processing under high-speed sampling conditions; differential method is sensitive to noise and is prone to generating false peaks.
[0004] Furthermore, in high-speed data acquisition systems, peak detection and data output often suffer from processing bottlenecks, leading to data loss or discontinuous output, which makes it difficult to meet the real-time and reliability requirements of fusion devices and other strong electromagnetic environments.
[0005] Therefore, it is necessary to propose a peak retrieval and feature extraction method with high real-time performance, high anti-interference capability, and continuous data output capability. Summary of the Invention
[0006] This invention aims to address the problems of nonlinearity, insufficient temporal feature extraction, and inaccurate quality correlation modeling in existing technologies, and provides a quality-related fault detection method based on attention-enhanced temporal convolutional networks.
[0007] Compared with the prior art, the present invention has the following advantages and technical effects:
[0008] A continuous comparison method is used for real-time peak detection, which is simple in structure and suitable for hardware implementation. A threshold filtering mechanism is introduced to improve the accuracy of peak detection under interference-resistant environments. After feature extraction, a dual-RAM ping-pong caching mechanism is employed to achieve continuous storage and uninterrupted output of feature data. This invention is designed to address the characteristics of numerous irregular and transient signals and strong electromagnetic noise interference present in fusion environments, focusing not only on the accuracy of peak retrieval but also on the continuity and real-time performance of the data processing link.
[0009] Specifically, the steps include the following:
[0010] S1: Acquire the input signal to be processed;
[0011] S2: Set the peak upper threshold V min , min ,
[0016] ,
[0015] , , , ,
[0017] and the peak lower threshold V th_down , and the difference between the two forms a hysteresis window. The trigger and end logic of the peak search interval is as follows:
[0012] When the sampling signal jumps from below V th_up to above V th_up , and there is no unfinished peak search process at present, mark entering the effective peak search interval; when the sampling signal drops from above V th_down to below V th_down , mark the end of the current peak search interval and stop peak retrieval;
[0013] S3: Continuously sample the input signal and construct a continuous comparison model based on a sliding window. The core logic of continuous comparison is: within the effective peak search interval, the amplitude sorting results of the sampling signals are cached in real time through multiple-level registers. Compare the amplitude of the current sampling point with that of the adjacent sampling point to obtain candidate peak points; The present invention selects a five-point sliding window, and the specific steps are as follows:
[0014] Set 5-level 16-bit peak cache registers rawdata_max0 ~ rawdata_max4, where rawdata_max0 is the real-time maximum value within the peak search interval, and rawdata_max1 ~ rawdata_max4 are the second to fifth largest values in sequence. The initial values of the registers are all 0; within the peak search interval, at each sampling clock cycle, compare the current sampling value x(n) with each level of cache register in sequence:
[0015] If x(n)>rawdata_max0, the values of all registers are shifted backward in sequence, and rawdata_max0 is updated to the current sampling value x(n); if rawdata_max1<x(n)<rawdata_max0, max1~max4 are shifted backward in sequence, and rawdata_max1 is updated to the current sampling value x(n); and so on, complete the successive comparison and update of the subsequent registers, ensuring that within each clock cycle, the registers always cache the top 5 sampling values within the peak search interval.
[0016] S4: Limit the pulse width. The specific steps are to set the minimum pulse width threshold W min [[ID=
[0018] If rawdata_max4 > 0, meaning there are at least 5 valid high-amplitude sampling points within the interval, the average of max1 to max4 is taken as the final result; if rawdata_max2 > 0 and rawdata_max4 = 0, the average of max1 and max2 is taken as the final result; if there is only a single valid peak point, rawdata_max0 is directly taken as the final peak amplitude. This serves to resist spikes and jitter.
[0019] S6: Extract features from the selected valid peak points to obtain characteristic parameters such as peak amplitude, peak position and pulse width;
[0020] S7: Write the feature parameters into a dual RAM ping-pong cache structure, and achieve continuous storage and uninterrupted output of peak feature data through an alternating read-write mechanism; the specific steps are as follows:
[0021] A ping-pong cache is implemented using two dual-port Block RAMs, as a single RAM chip can hardly simultaneously satisfy real-time accumulation and data output without interrupting sampling. The core logic of the ping-pong cache is that when one RAM is in a write state, the other RAM is in a read state. When the number of peak-finding intervals reaches the RAM depth threshold or when the stored feature value needs to be read, the read and write states of the two RAMs are automatically switched.
[0022] The process of implementing ping-pong buffering using a state machine within the FPGA, specifically the state transition logic is as follows:
[0023] (1) First, it is in the IDLE state, which is idle;
[0024] (2) After starting work, it enters the RAM_CLEAR state. The ping-pong controller marks RAM1 as "write buffer" and RAM2 as "read buffer". Both RAMs are cleared and wait for peak data input.
[0025] (3) Entering RAM2 write + RAM1 wait state, under the drive of the 80MHz ADC sampling clock, the valid peak data output by the peak retrieval module is continuously written to RAM2; at this time, RAM1 is in the "reading" state and no data is written.
[0026] (4) Until the end of a time window, i.e., after skip_en=1, enter the RMA2 read + RAM1 write state. RAM2 starts to read the result of this frame sequentially and send it into FIFO. At the same time, the peak value of the next frame starts to be written into RAM1.
[0027] (5) Similarly, when the next time window ends, it enters the RAM1 read + RAM2 write state, which is symmetrical to the previous state. This state becomes RAM1 data statistics and RAM2 write.
[0028] The two RAM chips then alternate in a loop to store data, thus ensuring that the entire frame can be output without pausing data acquisition during continuous sampling and statistics.
[0029] S8: Output the peak characteristic data for use by the host computer or subsequent processing module. Attached Figure Description
[0030] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0031] Figure 1 This is a flowchart of peak retrieval and feature extraction according to an embodiment of the present invention;
[0032] Figure 2 This is a state machine transition diagram for a dual RAM ping-pong cache embodiment of the present invention;
[0033] Figure 3 This is a waveform simulation diagram of peak retrieval and feature extraction in an embodiment of the present invention;
[0034] Figure 4 This is a waveform simulation diagram of the dual RAM ping-pong buffer in an embodiment of the present invention; Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.
[0036] Figure 1 The flowcharts illustrating peak retrieval and feature extraction in this case study are provided, explaining the functions of peak retrieval and feature extraction.
[0037] Figure 2 The state machine transition diagram after feature extraction with dual RAM ping-pong cache is illustrated.
[0038] The peak retrieval and feature extraction method applicable to strong electromagnetic interference environments, as described in this invention, includes the following steps:
[0039] S1: Acquire the input signal to be processed;
[0040] S2: Set the peak threshold V th_up With the peak threshold V th_down The difference between the two forms a hysteresis window. The triggering and termination logic of the peak-finding interval is as follows:
[0041] When the sampling signal is below V th_upJump to higher than V th_up and when there is no unfinished peak search process currently, mark entering the effective peak search interval; when the sampling signal drops from higher than V th_down to lower than V th_down , mark the end of the current peak search interval and stop peak retrieval;
[0042] S3: Continuously sample the input signal and construct a continuous comparison model based on a sliding window. The core logic of continuous comparison is: within the effective peak search interval, the amplitude sorting results of the sampling signal are cached in real time through multiple-stage registers. Compare the amplitude of the current sampling point with that of the adjacent sampling point to obtain candidate peak points; The present invention selects a five-point sliding window, and the specific steps are as follows:
[0043] Set 5-level 16-bit peak cache registers rawdata_max0 ~ rawdata_max4, where rawdata_max0 is the real-time maximum value within the peak search interval, and rawdata_max1 ~ rawdata_max4 are the second to fifth largest values in turn. The initial values of the registers are all 0; within the peak search interval, at each sampling clock cycle, compare the current sampling value x(n) with each level of cache register in turn:
[0044] If x(n)>rawdata_max0, then the values of all registers are shifted backward in turn, and rawdata_max0 is updated to the current sampling value x(n); if rawdata_max1<x(n)<rawdata_max0, then max1~max4 are shifted backward in turn, and rawdata_max1 is updated to the current sampling value x(n); and so on, complete the successive comparison and update of the subsequent registers, ensuring that within each clock cycle, the registers always cache the top 5 large sampling values within the peak search interval.
[0045] S4: Limit the pulse width. The specific steps are to set the minimum pulse width threshold W min . After the peak search interval ends, first calculate the number of sampling periods W during which the interval lasts. If W<W min , it is determined that it is a false peak caused by electromagnetic interference, and directly discard the detection result of this interval without performing feature storage.
[0046] S5: To address the problem that the extreme value of a single sampling point is vulnerable to noise interference, after the peak search interval ends, optimize the effective peak result; the specific content is:
[0047] If rawdata_max4 > 0, meaning there are at least 5 valid high-amplitude sampling points within the interval, the average of max1 to max4 is taken as the final result; if rawdata_max2 > 0 and rawdata_max4 = 0, the average of max1 and max2 is taken as the final result; if there is only a single valid peak point, rawdata_max0 is directly taken as the final peak amplitude. This serves to resist spikes and jitter.
[0048] S6: Extract features from the selected valid peak points to obtain characteristic parameters such as peak amplitude, peak position and pulse width;
[0049] S7: Write the feature parameters into a dual RAM ping-pong cache structure, and achieve continuous storage and uninterrupted output of peak feature data through an alternating read-write mechanism; the specific steps are as follows:
[0050] A ping-pong cache is implemented using two dual-port Block RAMs, as a single RAM chip can hardly simultaneously satisfy real-time accumulation and data output without interrupting sampling. The core logic of the ping-pong cache is that when one RAM is in a write state, the other RAM is in a read state. When the number of peak-finding intervals reaches the RAM depth threshold or when the stored feature value needs to be read, the read and write states of the two RAMs are automatically switched.
[0051] The process of implementing ping-pong buffering using a state machine within the FPGA, specifically the state transition logic is as follows:
[0052] (1) First, it is in the IDLE state, which is idle;
[0053] (2) After starting work, it enters the RAM_CLEAR state. The ping-pong controller marks RAM1 as "write buffer" and RAM2 as "read buffer". Both RAMs are cleared and wait for peak data input.
[0054] (3) Entering RAM2 write + RAM1 wait state, under the drive of the 80MHz ADC sampling clock, the valid peak data output by the peak retrieval module is continuously written to RAM2; at this time, RAM1 is in the "reading" state and no data is written.
[0055] (4) Until the end of a time window, i.e., after skip_en=1, enter the RMA2 read + RAM1 write state. RAM2 starts to read the result of this frame sequentially and send it into FIFO. At the same time, the peak value of the next frame starts to be written into RAM1.
[0056] (5) Similarly, when the next time window ends, it enters the RAM1 read + RAM2 write state, which is symmetrical to the previous state. This state becomes RAM1 data statistics and RAM2 write.
[0057] The two RAM chips then alternate in a loop to store data, thus ensuring that the entire frame can be output without pausing data acquisition during continuous sampling and statistics.
[0058] S8: Output the peak characteristic data for use by the host computer or subsequent processing module.
[0059] This case was simulated using Vivado's built-in simulation function. The waveform simulation diagram of the feature extraction function based on the continuous comparison method is shown below. Figure 3 As shown in the figure, numbers 1, 2, and 3 correspond to the peak-finding enable interval, the update process of the five candidate peak registers, and the final peak output result, respectively.
[0060] In this case, the upper and lower thresholds are set to 16'h6100 and 16'h5fff, respectively. As shown by variable 1 in the diagram, when the input data `rawdata` rises above the set upper threshold, the module initiates the peak-finding process, and the signal `search_en` is set high. During the period when `search_en` is valid, it indicates that the input signal is within the search interval of a valid pulse, and the module begins continuous comparison and peak extraction of the sampled data within this interval. Simultaneously, when the input signal decreases and falls below the lower threshold, the peak-finding process ends, and `search_en` is pulled low.
[0061] The variable labeled 2 in the figure shows the dynamic update results of the five registers rawdata_max0 to rawdata_max4 during a peak-finding process. The simulation waveforms demonstrate that, following the design principle of the "continuous comparison method," it sorts and saves the larger sample values appearing in the current pulse interval in real time.
[0062] The variable labeled 3 in the figure gives the simulation result of the final peak output rawdata_max_peak, which is 16′h64bf. It is calculated by "removing the maximum value and averaging the remaining four larger values".
[0063] The waveform simulation diagram of the ping-pong caching process using dual RAM after feature extraction is shown below. Figure 4 As shown in the figure. In the figure, the labels 1, 2, and 3 correspond to the state machine state changes, the time window trigger signal, and the read / write address changes of the dual RAM, respectively.
[0064] The state machine's state[4:0] changes can be observed from the variables labeled 1 in the diagram. According to the design, the state machine has five main states: Idle, ram_clear, wram2, rram2_wram1, and rram1_wram2; corresponding to state values 01, 02, 04, 08, and 10 respectively. At the start of the simulation, the system first enters the ram_clear state. It can be seen that when ram1_clear_end and ram2_clear_end go high, it indicates that the initialization and clearing of RAM1 and RAM2 are complete. Subsequently, the state machine enters the wram2 state, at which point the system only writes spectral data statistics to RAM2.
[0065] When the single-spectrum time-end signal skip_en in variable 2 goes high, the state machine switches from wram2 state to rram2_wram1 state. In this state, the system begins to sequentially read the spectrum data obtained from the previous time window statistics in RAM2, while simultaneously writing the new statistical results into RAM1. The state then cycles between reading RAM1 and writing RAM2 and vice versa, and the dual-port RAM read / write address in variable 3 also changes accordingly. As shown in the figure, the state machine runs stably in the expected order, and each state transition is correctly triggered by the time window signal skip_en, indicating that the control logic design is correct.
Claims
1. A peak retrieval and feature extraction method suitable for environments with strong electromagnetic interference, characterized in that, It includes the following steps: S1: Obtain the input signal to be processed; S2: Set the peak threshold V th_up With peak threshold V th_down The difference between the two forms a hysteresis window. The triggering and termination logic of the peak-finding interval is as follows: When the sampling signal is below V th_up Jump to above V th_up If there are no incomplete peak-finding processes, mark the entry into the valid peak-finding interval; when the sampled signal is higher than V... th_down Drop below V th_down When the current peak-finding interval ends, stop peak retrieval; S3: Continuously sample the input signal and construct a continuous comparison model based on a sliding window. The core logic of continuous comparison is: within the effective peak searching interval, the amplitude sorting results of the sampled signals are cached in real time through a multi-level register. Compare the amplitude of the current sampling point with that of the adjacent sampling point to obtain candidate peak points; S4: Limit the pulse width. The specific steps are to set a minimum pulse width threshold W. min After the peak-finding interval ends, first calculate the number of sampling periods W for the duration of the interval. If W <W min If the peak value is false, it is determined to be caused by electromagnetic interference, and the detection results for that interval are discarded without feature storage. S5: In view of the problem that the extreme value of a single sampling point is vulnerable to noise interference, optimize the effective peak result after the peak searching interval ends; S6: Extract features from the screened effective peak points to obtain characteristic parameters such as peak amplitude, peak position, and pulse width; S7: Write the characteristic parameters into a dual-RAM ping-pong buffer structure, and realize the continuous storage and interruption-free output of peak characteristic data through an alternating read-write mechanism; S8: Output the peak characteristic data for use by the host computer or subsequent processing modules.
2. For continuously sampling the input signal according to claim 1 and constructing a continuous comparison model based on a sliding window, the present invention selects a five-point sliding window. The specific steps are as follows: Set five 16-bit peak cache registers rawdata_max0 to rawdata_max4, where rawdata_max0 is the real-time maximum value within the peak searching interval, and rawdata_max1 to rawdata_max4 are the second to fifth largest values in sequence. The initial values of the registers are all 0; within the peak searching interval, compare the current sampling value x(n) with each level of cache register in turn for each sampling clock cycle: If x(n)>rawdata_max0, the values of all registers are shifted backward in sequence, and rawdata_max0 is updated to the current sampling value x(n); if rawdata_max1<x(n)<rawdata_max0, max1 to max4 are shifted backward in sequence, and rawdata_max1 is updated to the current sampling value x(n); and so on, complete the successive comparison and update of the subsequent registers, ensuring that within each clock cycle, the registers always cache the top 5 largest sampling values within the peak searching interval.
3. For optimizing the effective peak result after the peak searching interval ends in view of the problem that the extreme value of a single sampling point is vulnerable to noise interference according to claim 1, the specific content is as follows: If rawdata_max4>0, that is, there are at least 5 effective high-amplitude sampling points within the interval, take the average value of max1 to max4 as the final result; if rawdata_max2>0 and rawdata_max4=0, take the average value of max1 and max2 as the final result; if there is only a single effective peak point, directly take rawdata_max0 as the final peak amplitude. It plays a role in anti-spike and jitter processing.
4. For writing the characteristic parameters into a dual-RAM ping-pong buffer structure and realizing the continuous storage and interruption-free output of peak characteristic data through an alternating read-write mechanism according to claim 1, the specific steps are as follows: A ping-pong cache is implemented using two dual-port Block RAMs, as a single RAM chip can hardly simultaneously satisfy real-time accumulation and data output without interrupting sampling. The core logic of the ping-pong cache is that when one RAM is in a write state, the other RAM is in a read state. When the number of peak-finding intervals reaches the RAM depth threshold or when the stored feature value needs to be read, the read / write state of the two RAMs is automatically switched. The process of implementing ping-pong buffering using a state machine within the FPGA, specifically the state transition logic is as follows: (1) First, it is in the IDLE state, which is idle; (2) After starting work, it enters the RAM_CLEAR state. The ping-pong controller marks RAM1 as "write buffer" and RAM2 as "read buffer". Both RAMs are cleared and wait for peak data input. (3) Entering RAM2 write + RAM1 wait state, under the drive of the 80MHz ADC sampling clock, the valid peak data output by the peak retrieval module is continuously written to RAM2; at this time, RAM1 is in the "reading" state and no data is written. (4) Until the end of a time window, i.e., after skip_en=1, enter the RMA2 read + RAM1 write state. RAM2 starts to read the result of this frame sequentially and send it into FIFO. At the same time, the peak value of the next frame starts to be written into RAM1. (5) Similarly, when the next time window ends, it enters the RAM1 read + RAM2 write state, which is symmetrical to the previous state. This state becomes RAM1 data statistics and RAM2 write. The two RAM chips then alternate in a loop to store data, thus ensuring that the entire frame can be output without pausing data acquisition during continuous sampling and statistics.