Chip cycling test apparatus

Abstract

This application relates to a chip cycle testing device, comprising: a test board; a control board; a connection module including a first adapter board, a second adapter board, and an electrical connector, the electrical connector connecting the first adapter board and the second adapter board, the first adapter board connecting to the test board, and the second adapter board connecting to the control board; and a temperature chamber including an inner chamber and an outer chamber. The inner chamber has a working area for mounting the test board; the outer chamber has a transition area for accommodating the connection module, with openings on both sides of the transition area to allow the connection module to connect to the control board outside the outer chamber and to the test board in the working area. The inner chamber has an opening in the chamber wall adjacent to the working area to allow the test board to connect to the connection module. This invention can isolate heat / cold air in the inner chamber during high / low temperature testing, preventing the control board from overheating and condensing, thus preventing damage to the control board and test failure.

Description

Technical Field

[0001] This application relates to testing equipment for semiconductor devices, and more particularly to a chip cycle testing device. Background Technology

[0002] With the rapid development of technology, integrated circuits are playing an increasingly important role, requiring various tests during production and maintenance to prevent defective products from entering the market. Currently, the complexity of integrated circuits is gradually increasing with their development, leading to greater difficulty and higher costs in chip testing. Integrated circuit testing mainly includes functional testing, performance testing, electrical parameter testing, temperature testing, environmental testing, leakage testing, and reliability testing. Temperature cycling is one of the reliability tests conducted after chip packaging. This test involves writing the same test vector (usually an all-"1" test vector) to the chip in a predetermined ambient temperature environment and then erasing it. This process is repeated multiple times to determine if the chip has failed, thus verifying its reliability.

[0003] Exemplary chip cycle testing equipment is prone to high-temperature crashes or condensation during three-temperature (low temperature, normal temperature, high temperature) cycle testing. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip cycle testing device suitable for three-temperature cycle testing.

[0005] A chip cycle testing device includes: a test board for mounting the chip under test; a control board for acquiring the number of cycle tests sent by a host computer and sending test vectors to the test board, and also for receiving the output of the chip under test fed back by the test board, and storing chip test result information obtained based on the output of the chip under test; a connection module including a first adapter board, a second adapter board, and an electrical connector, wherein the electrical connector is used to connect the first adapter board and the second adapter board, the first adapter board is used to connect to the test board, and the second adapter board is used to connect to the control board; and a temperature chamber. The chamber includes an inner chamber and an outer chamber. The inner chamber includes a temperature control module and has a working area for mounting the test board. The outer chamber is located on one side of the inner chamber and has a transition area for accommodating the connection module. The outer chamber has openings on both sides of the transition area to allow the connection module to connect to the control board outside the outer chamber and to the test board in the working area. The inner chamber has an opening in the chamber wall adjacent to the working area to allow the test board to connect to the connection module.

[0006] The aforementioned chip cycle testing equipment has a transition area set in the outer body of the temperature chamber to house the connection module. The control board is connected to the test board through the connection module. During high / low temperature testing, it can isolate the heat / cold air inside the temperature chamber, avoiding high temperature crashes or condensation on the control board, thus preventing damage to the control board and test failure.

[0007] In one embodiment, the inner body of the temperature chamber includes air duct areas located on both sides and below the working area, the air duct areas being separated from the working area by partitions, the partitions on both sides of the working area being provided with air holes, and the temperature regulation module being located in the air duct areas.

[0008] In one embodiment, the transition zone is filled with thermal insulation material.

[0009] In one embodiment, the control board includes: a communication module for communicating with a host computer; a control module for acquiring the number of cyclic tests sent by the host computer and generating test vectors, the control module also being used to send pin configuration instructions; an input / output module for configuring the pins of the test board according to the pin configuration instructions, so that the pins of the test board match the pins of the connected chip under test; the input / output module also being used to send test vectors to the test board and receive the output of the chip under test fed back by the test board; and a storage unit for storing chip test result information obtained based on the output of the chip under test.

[0010] In one embodiment, the chip cycle test equipment further includes a camera and a chip identification module. The chip identification module is used to determine the type of chip under test based on the chip image acquired by the camera, and the pin configuration instructions correspond to the type of chip under test.

[0011] In one embodiment, the control board further includes an adjustable power supply, and the control module is further configured to adjust the power supply voltage output by the adjustable power supply, and the test board acquires the power supply voltage as the operating voltage of the chip under test.

[0012] In one embodiment, the control board further includes a digital-to-analog converter (DAC) for converting the power supply voltage adjustment signal sent by the control module into an analog signal. The adjustable power supply includes: a voltage follower connected to the output terminal of the DAC for outputting a stable voltage that matches the analog signal; and a synchronous voltage drop chip connected to the output terminal of the voltage follower for adjusting the power supply voltage according to the voltage output by the voltage follower.

[0013] In one embodiment, the communication module is a half-duplex communication module, which includes a switching circuit and an RS485 transceiver. The receive output enable terminal and the transmit output enable terminal of the RS485 transceiver are connected to the switching circuit. When the switching circuit is turned on, the RS485 transceiver is valid for receiving and transmitting, and outputs a logic "0". When the switching circuit is turned off, the transmit is invalid, and outputs a logic "1".

[0014] In one embodiment, the control module is further configured to acquire time parameters sent by the host computer and verify whether the function timing is correct based on the time parameters.

[0015] In one embodiment, the control module is further configured to acquire the consecutive failure count parameter sent by the host computer, and stop sending the test vector of the chip under test when any chip under test reaches the consecutive failure count.

[0016] In one embodiment, the chip test result information includes the number of cyclic tests when the chip under test is determined to be faulty. Attached Figure Description

[0017] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0018] Figure 1 This is an overall framework diagram of a chip cycle test device in one embodiment of this application.

[0019] Figure 2 This is a front view of the incubator in one embodiment of this application.

[0020] Figure 3 This is a side view of the incubator in one embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the connection module in one embodiment of this application.

[0022] Figure 5 This is a perspective view of an incubator in one embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the transition area in one embodiment of this application.

[0024] Figure 7 This is a schematic diagram of the connection between the inner body and the outer body of the incubator in one embodiment of this application.

[0025] Figure 8This is a schematic diagram of the positioning holes in the transition zone in one embodiment of this application.

[0026] Figure 9 This is a schematic diagram of the circuit structure of the control board in one embodiment of this application.

[0027] Figure 10 This is a schematic diagram of the circuit structure of the control board in another embodiment of this application.

[0028] Figure 11 This is a structural diagram of an adjustable power supply according to an embodiment of this application.

[0029] Figure 12 This is a circuit diagram of an adjustable power supply in one embodiment of this application.

[0030] Figure 13 This is a structural diagram of the communication module in one embodiment of this application.

[0031] Figure 14 This is a circuit schematic diagram of the communication module in one embodiment of this application. Detailed Implementation

[0032] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0038] See Figure 1 One embodiment of the chip cycle testing equipment of this application includes a control board 20, a test board 30, a temperature chamber 40, and a connection module 430. Figure 1 (Not shown in the image). Test board 30 is used to mount the chip under test. Control board 20 is used to obtain the number of loop tests sent by the host computer 10 and send test vectors to test board 30. It is also used to receive the output of the chip under test fed back by test board 30, and to store chip test result information obtained based on the output of the chip under test. Each control board 20 corresponds to one chip under test, providing data (including test vectors) and signals to one chip under test, and receiving the data output (feedback) by that chip under test.

[0039] See Figure 4 The connection module 430 includes a first adapter plate 432, a second adapter plate 434, and an electrical connector 433. The electrical connector 433 is used to connect the first adapter plate 432 and the second adapter plate 434. The first adapter plate 432 is used to connect the test board 30. The second adapter plate 434 is used to connect the control board 20.

[0040] Figure 2 This is a front view of the incubator 40 in one embodiment of this application. Figure 3 This is a side view of an incubator 40 according to one embodiment of this application. The incubator 40 includes an inner incubator body 410 and an outer incubator body 420. The inner incubator body 410 includes a temperature regulation module ( Figure 2 (Not shown in the image) The inner body 410 of the temperature chamber has a working area 411 for mounting the test plate 30. The outer body 420 of the temperature chamber is located on one side of the inner body 410, and the outer body 420 has a transition area 421 for accommodating the connecting module 430. The outer body 420 has openings on both sides of the transition area 421. Figure 3(as indicated by the middle arrow) so that the connection module 430 can be connected to the control board 20 located outside the outer body 420 of the temperature chamber, and to the test board 30 located in the working area 411. The inner body 410 of the temperature chamber has an opening in the chamber wall adjacent to the working area 411 so that the test board 30 can be connected to the connection module 430.

[0041] In the aforementioned chip cycle testing equipment, the temperature chamber 40 has a transition area 421 set in the outer body 420 of the temperature chamber to house the connection module 430. The control board 20 is connected to the test board 30 through the connection module 430. During high temperature / low temperature testing, the heat / cold air in the inner body 410 of the temperature chamber can be isolated to prevent the control board 20 from freezing due to high temperature or condensation, thus preventing damage to the control board 20 and test failure.

[0042] See Figure 2 and Figure 5 In one embodiment of this application, the inner body 410 of the incubator includes air duct areas 412 located on both sides and below the working area 411. Figure 5 The visible area within the chamber 410 shown (observable through an observation window) is the working area 411. The air duct area 412 and the working area 411 are separated by a partition 414. The partition 414 on both sides of the working area 411 has vents to allow air circulation between the air duct area 412 and the working area 411. Figure 2 The arrows indicate the direction of airflow within the chamber 410. The temperature control module is located in the air duct area 412.

[0043] In one embodiment of this application, the space in the transition zone 421, excluding the connecting module 430, is filled with thermal insulation material. In one embodiment of this application, the thermal insulation material is ultrafine glass wool.

[0044] In one embodiment of this application, the first adapter plate 432 is provided with gold finger slots 431 on both sides. Figure 4 Only one side of the gold finger slot 431 is shown, one side of which is used to insert the electrical connector 433, and the other side of the gold finger slot 431 is used to insert the test board 30. The second adapter plate 434 has gold finger slots 435 on both sides. Figure 4 The image only shows one side of the gold finger slot 435, where one side of the gold finger slot 435 is used to insert the electrical connector 433, and the other side of the gold finger slot 435 is used to insert the control board 20. In one embodiment of this application, the electrical connector 433 consists of two connecting boards.

[0045] The structure of the incubator 40 is illustrated below through a specific embodiment:

[0046] The outer body 420 of the incubator is made of double-sided galvanized steel sheet with electrostatic powder coating (gray-white orange peel) for rust and corrosion protection. An observation window is located on the side of the working area 411 opposite the opening (used to house the connection module 430). The observation window is fitted with multi-layered hollow coated glass. The observation window is equipped with an anti-condensation feature, specifically an electric heating device, to prevent water vapor condensation and maintain a clear view at all times. The insulation layer inside the incubator 40 uses ultra-fine glass wool with a thickness of 100mm. The inner body 410 of the incubator is equipped with a sample rack 416. Figure 5 In the illustrated embodiment, the sample rack 416 consists of two stainless steel sample racks with a load-bearing capacity (uniformly distributed) of 15 kg per layer, and the height is adjustable. The door and frame of the incubator 40 are also equipped with anti-condensation features, specifically using an electric heating device (automatically adjustable) to prevent frost and condensation. The door uses a double-layer silicone rubber seal to ensure a good seal and prevent heat leakage.

[0047] To establish a connection between the external control board 20 and the internal test board 30 of the temperature chamber 40, holes need to be drilled in the chamber body to form a transition area 421 in the outer body 420 of the temperature chamber. See [link / reference needed]. Figure 6 The two sides of the cutout are a first adapter board 432 and a second adapter board 434, each with a gold finger slot. These two adapter boards are connected by the gold finger slot and an electrical connector 433, thus forming a connection module 430. The pin order on the test board 30 is mapped one-to-one to the control board side through two conversions by the connection module 430.

[0048] After determining the dimensions of the first adapter plate 432 and the second adapter plate 434, and the opening dimensions of the transition area 421, the positions of the positioning holes will be determined. Specifically, the positioning hole size is M3, and the positioning holes on the first adapter plate 432 and the second adapter plate 434 correspond one-to-one with the positioning holes on the housing. See [reference needed]. Figure 7 and Figure 8 .

[0049] Because of the opening in the transition zone 421, the interior of the chamber 410 is not completely sealed. Therefore, the chamber must be sealed after the connection module 430 is installed. When installing the connection module 430, insulation material (glass wool) needs to be filled into the empty space inside the transition zone 421 to prevent heat from being conducted through the transition zone 421, which could cause the control board 20 to overheat and malfunction or condensation. After the insulation material is filled and the connection module 430 is installed, high and low temperature resistant sealant needs to be applied to the joints to further ensure a tight seal.

[0050] The chamber 410 employs a three-channel airflow structure, ensuring even heat distribution across all test boards 30 and resulting in good temperature uniformity for the tested chips within the chamber. Specifically, the temperature control module in the airflow zone 412 includes a heating unit and a cooling unit. Hot / cold air circulates continuously within the chamber 410 via a fan in the airflow zone 412 to heat or cool the chips, supporting cyclic testing within an ambient temperature range of -40℃ to 150℃.

[0051] The high and low temperature test chambers in related technologies employ a structure that forces air circulation within the chamber, with air outlet at the top and return air at the bottom. This air outlet method is technologically mature, well-equipped, low-cost, and compact, although the uniformity within the chamber is generally acceptable, meeting the standard requirements for temperature uniformity. However, this circulation method is not ideal in some special situations. When the tested item has a large area and is parallel to the air outlet or return air inlet, one direction will always be leeward, creating a wind speed difference. This wind speed difference affects the rate of temperature change on both sides of the tested item. This is only assuming one layer of tested items is placed in the chamber; if multiple layers of tested items are placed, the data between each layer will differ, which is particularly evident in the new energy battery and semiconductor chip industries. When using high and low temperature test chambers in related technologies, even several batteries or chips produced from the same batch of R&D sample production lines can show significant differences in test data when placed in different positions and within the same row within the same high and low temperature chamber, making it difficult for R&D personnel to determine the actual capabilities of the product.

[0052] The test board 30 in this embodiment has a large area, and multiple chips under test need to be placed on one test board 30. The sample rack 416 can hold multiple layers of test boards 30, and the air circulation method in the aforementioned related technologies cannot meet the requirements. The incubator 40 in this embodiment changes the air circulation method, adopting an air circulation method more suitable for testing scenarios with multiple chips and multiple layers of test boards 30 overlapping. See also Figure 2 The chip under test and the multilayer test board 30 are placed in the working area 411. Air duct areas 412 are distributed in three regions: the left, right, and lower parts of the working area 411, forming a three-air duct structure. The partitions 414 between the left and right sides of the working area 411 and the air duct areas 412 (see...) Figure 5 It has pores on it. Figure 2 The arrows indicate the airflow direction within the chamber 410, and the temperature control module is located in the air duct area 412 at the bottom of the working area 411. Therefore, this air duct arrangement allows air to flow laterally within the working area 411, ensuring even flow across each test board 30. This results in a more uniform temperature distribution within the chamber 410, leading to more accurate testing of the chip under test.

[0053] The test board 30 inside the chamber 410 carries the chip under test. A connection module 430 is embedded inside the chamber 40, connecting the test board 30 inside the chamber 40 to the control board 20 outside the chamber 40. The control board 20 performs functions such as controlling the operation timing of the chip under test, recording operation data, and communicating with the host computer 10. After the connection module 430 is fixed to the chamber wall, the test board 30 can be pushed in along the sample rack 416, and the gold fingers on the test board 30 will insert into the gold finger slots 431 on the first adapter board 432 to complete the connection. The sample rack 416 can hold 10 test boards 30, and each test board 30 can hold 8 chips under test. The host computer 10 is electrically connected to the temperature regulation module inside the chamber 410 and is used to set the temperature inside the chamber 410.

[0054] One exemplary cyclic testing approach is to use a test machine to perform cyclic testing, while another exemplary cyclic testing approach is to use a dedicated cyclic testing device.

[0055] For the solution of using a test machine to perform cyclic testing on chips, operators can control the entire cyclic testing process by writing test programs that are compatible with the test machine. The advantages of this solution mainly include the ability to freely set the number of tests in the cyclic test, the state of each chip pin, and the specific locations of multiple failure checkpoints throughout the cyclic test. However, using this solution for cyclic testing has the following problems: 1. Test machines are expensive; if the machine time is only used for running cyclic tests, the testing cost will be high. 2. The parallel testing capability of the test machine is insufficient; a single test machine cannot support multiple chips undergoing cyclic testing simultaneously. 3. The operators using the test machine have high skill requirements, and the training period for such operators is long. 4. For chips with the same package type but different power supply pin locations, each chip needs to have its own redesigned test board for cyclic testing, lacking versatility.

[0056] For solutions using dedicated Cycling equipment for cyclic testing, operators simply set the number of test cycles in the software panel and connect the corresponding hardware to begin testing. Its advantage lies in its low operator skill requirement; simple operation is all that's needed to run the cyclic test program. Dedicated Cycling equipment can test multiple chips in parallel, and the instruments are relatively inexpensive, significantly reducing the testing cost of cyclic testing. However, this solution has disadvantages. The equipment only supports stimulating the chip, meaning it unilaterally sends test vectors to the chip without comparing its output, lacking real-time monitoring capabilities. Once the number of test cycles is set, the system completes the test in one go, without being able to stop the test midway based on the test results (such as detecting chip failure). This not only wastes testing time but also relies solely on the testing machine to determine whether the chip is qualified, making it impossible to obtain the number of Cycling cycles at the time of chip failure. Similar to testing machines, this dedicated Cycling equipment also lacks versatility; a single test board cannot support Cycling testing of chips with the same package but different power pin configurations.

[0057] Figure 9 This is a schematic diagram of the circuit structure of the control board 20 in one embodiment of this application. The control board 20 includes a communication module 210, a control module 220, an input / output module 230, and a storage unit (…). Figure 9 (Not shown in the diagram). Communication module 210 is used to communicate with host computer 10. Control module 220 is used to obtain the number of loop tests sent by host computer 10 and generate test vectors. Control module 220 is also used to send pin configuration instructions. Input / output module 230 is a configurable I / O port used to configure the pins of test board 30 according to pin configuration instructions so that the pins of test board 30 match the pins of the connected chip under test. Input / output module 230 is also used to send test vectors to test board 30 and receive the output of chip under test fed back by test board 30. Storage unit is used to store chip test result information obtained based on the output of chip under test.

[0058] The aforementioned chip cycle testing equipment features a configurable I / O port for its input / output module 230. This module can configure the pins on the test board 30 to match the order of the chip under test according to pin configuration instructions, thus ensuring compatibility with chips of the same package but different pin arrangements. By storing chip test results in the storage unit, the entire cycle testing process of the chip under test can be monitored in real time, including writing, reading, and erasing.

[0059] In one embodiment of this application, the control module 220 is an MCU (Micro Control Unit), and the storage unit is a register in the MCU.

[0060] See Figure 10In one embodiment of this application, the control board 20 further includes an adjustable power supply 240. The control module 220 is also used to adjust the power supply voltage output by the adjustable power supply 240, and the test board 30 obtains this power supply voltage as the operating voltage of the corresponding chip under test. By setting the adjustable power supply 240, it is possible to further accommodate chips under test with different operating voltages, thereby further expanding the versatility of the chip cycle testing equipment.

[0061] See Figure 11 In one embodiment of this application, the control board 20 further includes a digital-to-analog converter (DAC). The DAC converts the power supply voltage adjustment signal sent by the control module 220 into an analog signal. The adjustable power supply includes a voltage follower and a synchronous dropout chip. The voltage follower is connected to the output of the DAC and outputs a stable voltage that matches the analog signal. The synchronous dropout chip is connected to the output of the voltage follower and adjusts the power supply voltage output by the adjustable power supply 240 according to the voltage output by the voltage follower.

[0062] Figure 12 This is a circuit schematic of the adjustable power supply 240 in one embodiment of this application. The 0-9V linear voltage regulation can be achieved by using the on-chip peripheral DAC of the MCU and the synchronous voltage drop chip TMI3359. The DAC can output a 0-3.3V voltage as feedback for the TMI3359 to achieve linear adjustment from 0-9V. Figure 12 The power supply voltage POWER_H output by the adjustable power supply 240 is ((R42+R44)×Ufb) / R42. The DAC converts the power supply voltage adjustment signal sent by the control module 220 into a voltage signal PA4. After passing through the voltage follower composed of U15 (LMV321 chip), it is connected to the feedback pin FB of the synchronous voltage drop chip TMI3359. In this way, the power supply voltage output by POWER_H can be adjusted by inputting data from 0 to 0xffff.

[0063] In one embodiment of this application, the chip cyclic testing device further includes a camera and a chip identification module. The camera is used to photograph each chip under test on the test board 30, and the chip identification module determines the type of chip under test based on the chip image acquired by the camera. Since the types of chips tested by the chip cyclic testing device are limited, if each chip has distinguishable port characteristics, feature patterns of various chip ports can be pre-made. The chip identification module can determine the type of chip under test based on the chip image captured by the camera and the feature patterns. Then, the host computer 10 sends the corresponding test logic and test vector to the control module 220 for cyclic testing. In one embodiment of this application, the chip identification module can be implemented by software and installed in the host computer 10. Since the chip identification module can identify the type of chip under test, the chip cyclic testing device can achieve the goal of not placing the chips under test in a certain proportion in terms of quantity, nor is it necessary to divide each type of chip into specific areas of the test board 30. The test board 30 can support the mixed placement of multiple chips in any proportion, and the host computer 10 can obtain information about which type of chip is at each position and obtain the correct test results.

[0064] In one embodiment of this application, the communication module 210 is a half-duplex communication module. See also... Figure 13 The communication module 210 includes a switching circuit and an RS485 transceiver. The RS485 transceiver's receive output enable pin... The transmit output enable terminal DE is connected to the switching circuit. Both the transmit terminal TX and the receive terminal RX are high (i.e., logic "1") when idle. When the switching circuit is on, the RS485 transceiver is valid for both receive and transmit, and the output is logic "0". When the switching circuit is off, transmit is invalid, and the output is logic "1".

[0065] Figure 14 This is a circuit schematic diagram of the communication module 210 in one embodiment of this application. The communication module 210 is an automatic transmit / receive 485 circuit, which, compared with traditional 485 circuits, does not require a separate control chip to control the transmit / receive state. Receive output enable terminal. Active low, transmit output enable pin DE is active high. Resistor R19, NMOS transistor Q1, and resistor R17 form a switching circuit. When idle, both the transmit pin TX and the receive pin RX are high (i.e., logic "1"), and the communication module 210 is half-duplex.

[0066] Data reception: NMOS transistor Q1 is turned on and grounded; receive output enable pin. It works; it can receive data.

[0067] When TX=0, NMOS transistor Q1 is turned off, the transmit output enable terminal DE is active, and pin D of the TP8485E chip is grounded, so the output is 0.

[0068] When TX=1, NMOS transistor Q1 is turned on, and the transmit output enable pin DE is invalid. However, according to the output characteristics of the TP8485E chip, when the receive output enable pin... When the transmit output enable terminal DE is invalid, all outputs are high, so the output is 1.

[0069] The communication module 210 also includes an SM712 chip for electrostatic protection of the RS485 interface.

[0070] In one embodiment of this application, the control module 220 is further configured to acquire the time parameters sent by the host computer 10 and verify whether the function timing is correct based on the time parameters.

[0071] In one embodiment of this application, the control module 220 is further configured to acquire the consecutive failure count parameter sent by the host computer 10, and stop sending test vectors to the chip under test when any chip under test reaches the consecutive failure count. Stopping the testing of the chip under test when it reaches a preset consecutive failure count can improve testing efficiency. Since memory chips have a critical state when they fail, in one embodiment of this application, the chip cyclic testing device stops the cyclic testing of the chip under test by setting a consecutive failure count. That is, if the feedback signal returned by the chip under test indicates that the chip has failed (e.g., test vector write failure or erase failure), and the number of consecutive occurrences of the signal indicating failure reaches a preset number (i.e., the consecutive failure count parameter), then the cyclic testing of the chip under test is stopped to save testing time.

[0072] In one embodiment of this application, the chip test result information stored in the storage unit includes the number of cyclic tests when the chip under test is determined to be faulty.

[0073] In one embodiment of this application, each chip-fixed position of the test board 30 is provided with multiple pins for connecting the chip under test. The input / output module 230 configures each pin of the chip-fixed position as one of the pre-configured pin types according to the pin configuration instructions sent by the control module 220.

[0074] Chips under test (DUTs) with identical packages can be plugged into the same chip mounting position on the test board 30; that is, chips of different types but with the same package can be plugged into the same chip mounting position. However, the pin arrangements and functions of chips of different types but with the same package may not be the same. To address this, this application designs the input / output module 230 as a configurable I / O port, which allows each pin of the chip mounting position to be independently configured into one of the pre-configured pin types (e.g., input, output, power supply, ground, and floating). Therefore, one chip mounting position can support cyclic testing of chips with the same package type but different pin arrangements / functions, enhancing the versatility of the chip cyclic testing equipment.

[0075] In one embodiment of this application, the chip under test is a QFP100 packaged memory chip.

[0076] In one embodiment of this application, the chip cycle testing equipment adopts a room temperature test control system for memory chips based on an RS485 bus. A test program for the chip under test (DUT) is written using an MCU to achieve continuous functional operation of the DUT. Some timing parameters can be set via the RS485 bus and the host computer 10 to test the chip's functionality under different timing conditions. First, the FreeMODBUS protocol is ported to the MCU (model GD32F470ZGT6) to ensure normal communication. Then, the MCU is used to implement the functional timing of the DUT and verify the correctness of each timing sequence. After ensuring the basic timing is correct, continuous functional operation of the entire chip is implemented. Before full-chip operation, reserved time parameters and the number of operations need to be set through the communication module 210. During full-chip operation, key operation information such as the number of successes, failures, and failure rate needs to be recorded. Simultaneously, the host computer 10 can monitor the operation information of multiple DUTs simultaneously through corresponding software, thereby achieving parallel testing and monitoring.

[0077] In one embodiment of this application, the control board 20 further includes a 24V power supply module connected to the control module 220, using the commonly used industrial voltage 24V as the operating power supply for the control board 20. The control board 20 interacts with the host computer 10 via the RS485+FREEMODBUS protocol, and each signal input / output module 230 and an adjustable power supply 240 are connected to the test board 30 via gold fingers.

[0078] In one embodiment of this application, the host computer 10 uses KingSCADA software to quickly build a monitoring and control interface, uses the 485 bus to send and receive data, and sets a total of 80 device addresses through KingSCADA software. Each device address corresponds to a control board 20 and a chip under test (10 test boards 30, each test board can install 8 chips). The purpose of controlling and monitoring the working status of a single chip under test is achieved by polling and reading / writing the device.

[0079] The control board 20 communicates with the host computer 10 via FreeMODBUS-RTU. The MCU allocates 30 readable and writable registers to store relevant parameters (such as timing parameters, operating status, number of operations, etc.). After executing the chip's function operation, it returns all parameters in the current registers. When the host computer 10 sends a write command, the parameter values ​​in the registers will be updated and reset.

[0080] Based on all the above embodiments, this application combines the advantages of the two aforementioned cyclic testing schemes, overcomes the disadvantages of the two related technical solutions, improves the versatility of the testing equipment, increases the efficiency of cyclic testing, and reduces testing costs. The embodiments of this application have the following beneficial effects:

[0081] (1) Supports three-temperature (low temperature, room temperature, high temperature) cycling tests for QFP100 packaged memory chips, and has strong versatility;

[0082] (2) Cycling tests can be performed on one or more chips, and the number of tests can be set freely according to requirements;

[0083] (3) The entire Cycling test process of the chip can be monitored in real time, including writing, reading and erasing, so the Cycling count at the time of failure of the chip can be obtained;

[0084] (4) Since memory chips have a critical state when they fail, the number of consecutive failures can be set to stop the operation of the chip, saving test time;

[0085] (5) The timing of reading, writing and erasing the chip can be set as required, and the voltage of the power supply pin can be controlled;

[0086] (6) Supports Cycling testing in environments ranging from -40℃ to 150℃;

[0087] (7) The operation requirements for operators are very low and the equipment maintenance is simple.

[0088] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip cycle testing device, characterized in that, include: A test board is used to mount the chip under test. The control board is used to obtain the number of cyclic tests sent by the host computer and send test vectors to the test board. It is also used to receive the output of the chip under test fed back by the test board and store chip test result information based on the output of the chip under test. The connection module includes a first adapter board, a second adapter board, and an electrical connector. The electrical connector is used to connect the first adapter board and the second adapter board. The first adapter board is used to connect the test board, and the second adapter board is used to connect the control board. A temperature chamber includes an inner chamber and an outer chamber. The inner chamber includes a temperature control module and has a working area for mounting the test board. The outer chamber is located on one side of the inner chamber and has a transition area for accommodating the connection module. The outer chamber has openings on both sides of the transition area to allow the connection module to connect to the control board outside the outer chamber and to the test board in the working area. The inner chamber has an opening in the chamber wall adjacent to the working area to allow the test board to connect to the connection module.

2. The chip cycle testing equipment according to claim 1, characterized in that, The inner body of the temperature chamber includes air duct areas located on both sides and below the working area. The air duct areas are separated from the working area by partitions. The partitions on both sides of the working area are provided with air holes. The temperature regulation module is located in the air duct areas.

3. The chip cycle testing equipment according to claim 1, characterized in that, The transition zone is filled with thermal insulation material.

4. The chip cycle testing equipment according to claim 1, characterized in that, The control panel includes: The communication module is used to communicate with the host computer. The control module is used to obtain the number of loop tests sent by the host computer and generate test vectors. The control module is also used to send pin configuration instructions. The input / output module is used to configure the pins of the test board according to the pin configuration instructions so that the pins of the test board match the pins of the connected chip under test; the input / output module is also used to send test vectors to the test board and receive the output of the chip under test fed back by the test board. The storage unit is used to store chip test result information obtained based on the output of the chip under test.

5. The chip cycle testing equipment according to claim 4, characterized in that, It also includes a camera and a chip identification module. The chip identification module is used to determine the type of chip under test based on the chip image acquired by the camera. The pin configuration instructions correspond to the type of chip under test.

6. The chip cycle testing equipment according to claim 4, characterized in that, The control board also includes an adjustable power supply, and the control module is further used to adjust the power supply voltage output by the adjustable power supply. The test board obtains the power supply voltage as the operating voltage of the chip under test.

7. The chip cycle testing equipment according to claim 6, characterized in that, The control board further includes a digital-to-analog converter (DAC), which converts the power supply voltage adjustment signal sent by the control module into an analog signal. The adjustable power supply includes: A voltage follower, connected to the output of the digital-to-analog converter, is used to output a stable voltage that matches the analog signal; A synchronous voltage drop chip is connected to the output terminal of the voltage follower and is used to adjust the power supply voltage according to the voltage output by the voltage follower.

8. The chip cycle testing equipment according to claim 4, characterized in that, The communication module is a half-duplex communication module, which includes a switching circuit and an RS485 transceiver. The receive output enable terminal and the transmit output enable terminal of the RS485 transceiver are connected to the switching circuit. When the switching circuit is turned on, the RS485 transceiver is valid for receiving and transmitting, and outputs logic 0. When the switching circuit is turned off, the transmit is invalid, and outputs logic 1.

9. The chip cycle testing equipment according to claim 4, characterized in that, The control module is also used to acquire the time parameters and consecutive failure count parameters sent by the host computer, verify whether the function timing is correct according to the time parameters, and stop sending the test vector of the chip under test when any chip under test reaches the consecutive failure count parameter.

10. The chip cycle testing equipment according to claim 4, characterized in that, The chip test result information includes the number of cyclic tests when the tested chip is determined to be faulty.

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