An adaptive chip electrical reliability test system

Abstract

This invention proposes an adaptive chip electrical reliability testing system, comprising: a dynamic excitation generation module that generates dynamic excitation applied to the adaptive chip based on a preset scenario script; an internal signal monitoring module that distributes and collects node signals from multiple functional circuits of the adaptive chip to obtain a chip behavior data stream; a behavior reliability assessment module that determines the dynamic reliability entropy based on the chip behavior data stream and the dynamic excitation, and evaluates the quantitative score of the adaptive adjustment loop based on the dynamic reliability entropy; and a digital twin analysis module that provides simulation data, compares the simulation data with measured parameters to obtain the corresponding deviation contribution, and evaluates the reliability result of the adaptive chip based on the deviation contribution. This invention monitors the node signals inside the chip, making the operating behavior white-boxed, converting static data into a dynamic behavior process, capturing faults caused by various functional circuits; calculating and analyzing the deviation contribution, accurately locating the cause of the fault, and achieving early degradation warning.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to an adaptive chip electrical reliability testing system. Background Technology

[0002] As integrated circuits enter the post-Moore's Law era, adaptive chips with dynamic adjustment capabilities for parameters such as voltage and frequency have become core components meeting the high-performance and high-energy-efficiency requirements of fields such as artificial intelligence and 5G communication (5th Generation Mobile Communication Technology). However, the internal adaptive closed-loop mechanism upon which such chips rely—the "perception-decision-execution" mechanism—introduces reliability risks not present in traditional chips. The dynamic adjustment process itself may become unstable under aging effects, noise interference, or extreme load conditions.

[0003] Currently, there are two methods for monitoring adaptive chips. The first is to integrate real-time monitoring and parameter adjustment circuits within the chip to achieve online hardening; the second is to conduct offline verification and screening through accelerated stress testing under external high temperature and high pressure. In-depth analysis reveals that both of these approaches have fundamental flaws. On the one hand, while built-in enhancement circuits can achieve active compensation, they themselves become new potential failure points, and their performance and aging trajectory cannot be assessed externally. On the other hand, traditional aging tests place the chip in a fixed extreme state, making it difficult to reproduce key dynamic stress scenarios such as mode switching and load jumps in actual operation. This results in a large number of transient faults directly related to adaptive behavior failing to be triggered and observed, forming a "dynamic blind spot." Furthermore, existing methods rely solely on static terminal indicators such as power consumption and functional accuracy, failing to quantify the reliability of key behaviors such as response speed and decision accuracy. Moreover, after a fault occurs, the inability to obtain internal loop data leads to a "black box guessing" dilemma. Summary of the Invention

[0004] This invention provides an adaptive chip electrical reliability testing system to solve the technical problems mentioned above, such as the inability to assess the working performance and aging trajectory from the outside, the inability to trigger and observe a large number of transient faults directly related to "adaptive behavior", the formation of "dynamic blind spots", and the "black box guessing" dilemma after a fault occurs because the internal loop data cannot be viewed.

[0005] This invention provides an adaptive chip electrical reliability testing system, comprising: The dynamic stimulus generation module generates dynamic stimuli to be applied to the adaptive chip according to a preset scenario script. The dynamic stimulus includes at least one of port voltage, load current and clock frequency. An internal signal monitoring module, which is connected to the adaptive chip, performs distributed sampling of multiple functional circuits in the adaptive chip during the application of the dynamic excitation to obtain a time-synchronized chip behavior data stream; A behavior reliability assessment module, which is connected to the dynamic excitation generation module and the internal signal monitoring module respectively, determines the dynamic reliability entropy characterizing the deviation of the adaptive chip behavior features based on the chip behavior data stream and the dynamic excitation, and evaluates the quantitative score of the adaptive adjustment loop formed by different functional circuits in the adaptive chip based on the dynamic reliability entropy. The digital twin analysis module is connected to the internal signal monitoring module and the behavior reliability assessment module, respectively. It generates simulation data based on the preset scenario script, compares the chip behavior data stream and the dynamic reliability entropy with the corresponding simulation data to determine the deviation contribution of multiple functional circuits, and evaluates the reliability result of the adaptive chip based on the deviation contribution.

[0006] In one embodiment of the present invention, the dynamic excitation generation module includes: a programmable power sequence unit that generates the port voltage according to the preset scenario script; an electronic load control unit that generates the load current according to the preset scenario script; a frequency generation unit that generates the clock frequency according to the preset scenario script; and an excitation generation unit that controls at least two of the programmable power sequence unit, the electronic load control unit, and the frequency generation unit to output synchronously to form a dynamic excitation with a predetermined timing relationship.

[0007] In one embodiment of the present invention, the internal signal monitoring module includes: a signal acquisition unit for acquiring data packets output by each of the functional circuits; a timestamp marking unit for adding timestamps to each of the data packets according to a global reference clock; and a data alignment unit for reordering and aligning the data packets based on the timestamps to generate the chip behavior data stream.

[0008] In one embodiment of the present invention, the behavioral reliability assessment module includes: a data preparation unit, which receives the dynamic stimulus and the chip behavior data stream and performs time alignment; an entropy determination unit, which calculates at least one dynamic reliability entropy based on the time-aligned dynamic stimulus and the chip behavior data stream, wherein the dynamic reliability entropy includes at least path entropy, and the path entropy is used to characterize the randomness of the selection of the adaptive adjustment loop; and an assessment unit, which converts the dynamic reliability entropy into the quantitative score based on a preset scoring mapping relationship.

[0009] In one embodiment of the present invention, the entropy determination unit includes: a path extraction subunit, which analyzes the adaptive adjustment loop activated in each dynamic excitation cycle based on the node signal output by the decision function circuit of the adaptive chip; a probability determination subunit, which counts the activation frequency of each adaptive adjustment loop based on the repeatedly applied dynamic excitation, and determines a probability parameter based on the activation frequency; and an entropy calculation subunit, which calculates the path entropy based on the probability parameter and the information entropy relationship.

[0010] In one embodiment of the present invention, the behavioral reliability assessment module further includes: a data feedback unit, which generates an assessment report based on the dynamic reliability entropy and the quantitative score, and dynamically adjusts the preset scenario script based on the assessment report.

[0011] In one embodiment of the present invention, the digital twin analysis module includes: a simulation generation unit, which, driven by the preset scenario script, generates expected values ​​of measured parameters using behavioral sub-models corresponding to each of the functional circuits, wherein the measured parameters include the chip behavior data stream and the dynamic reliability entropy; a deviation analysis unit, which determines the deviation data of each measured parameter according to the measured parameters and the corresponding expected values, and analyzes the deviation contribution of each of the functional circuits to the total deviation of the adaptive chip based on the deviation data; and a fault diagnosis unit, which performs fault identification on each deviation contribution based on preset fault mapping rules to generate the reliability result.

[0012] In one embodiment of the present invention, the deviation analysis unit includes: a relationship construction subunit, which constructs a sensitivity analysis model characterizing each of the functional circuits to the total deviation based on the signal transmission relationship between the multiple behavioral sub-models; and a deviation determination subunit, which inputs the deviation data into the sensitivity analysis model to determine the deviation contribution of each of the functional circuits.

[0013] In one embodiment of the present invention, the behavior sub-model includes: a first behavior sub-model for transmitting and outputting the acquired data inside the adaptive chip; a second behavior sub-model for determining a mode control signal based on the output of the first behavior sub-model and a preset parameter threshold; and a third behavior sub-model for calculating target parameters based on the mode control signal and a preset variable function.

[0014] In one embodiment of the present invention, the fault diagnosis unit includes: a first diagnosis unit, which determines that the adaptive chip has a first behavior fault when the deviation contribution in the weight of the first behavior sub-model exceeds a first preset threshold; a second diagnosis unit, which determines that the adaptive chip has a second behavior fault when the deviation contribution in the weight of the second behavior sub-model exceeds a second preset threshold; and a third diagnosis unit, which determines that the adaptive chip has a third behavior fault when the deviation contribution in the weight of the third behavior sub-model exceeds a third preset threshold.

[0015] The beneficial effects of this invention are as follows: This invention proposes an adaptive chip electrical reliability testing system, which includes: a dynamic excitation generation module that generates dynamic excitation applied to the adaptive chip based on a preset scenario script; an internal signal monitoring module that collects node signals of multiple functional circuits of the adaptive chip in a distributed manner to obtain chip behavior data stream; a behavior reliability assessment module that determines dynamic reliability entropy based on the chip behavior data stream and dynamic excitation, and assesses the quantitative score of the adaptive adjustment loop formed by different functional circuits based on the dynamic reliability entropy; and a digital twin analysis module that generates simulation data based on the preset scenario script, compares the simulation data with the chip behavior data stream and dynamic reliability entropy respectively, determines the deviation contribution of the functional circuits, and then assesses the reliability result of the adaptive chip based on the deviation contribution. This invention monitors the adaptive adjustment loop inside the chip to achieve white-box operation and process visualization under dynamic excitation, transforming the test object from static functional results into dynamic behavioral processes. It can directly capture faults caused by various functional circuits, making up for the dynamic blind spots of traditional static testing. At the same time, it introduces dynamic reliability entropy to quantitatively characterize the adaptive adjustment behavior, elevating reliability assessment from qualitative analysis to quantitative analysis. In addition, through real-time comparison of measured data with high-fidelity models and analysis of deviation contribution, it can not only achieve early degradation warning, but also accurately locate the abnormal occurrence link. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a block diagram of the adaptive chip electrical reliability testing system provided in an embodiment of the present invention.

[0018] Figure reference numerals: 100-Adaptive chip electrical reliability testing system; 110-Dynamic excitation generation module; 120-Internal signal monitoring module; 130-Behavioral reliability assessment module; 140-Digital twin analysis module. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0022] As integrated circuits enter the post-Moore's Law era, adaptive chips with dynamic adjustment capabilities for parameters such as voltage and frequency have become core components meeting the high-performance and high-energy-efficiency requirements of fields such as artificial intelligence and fifth-generation mobile communication technology (5G). However, the internal adaptive closed loop on which such chips rely, namely the "perception-decision-execution" mechanism, introduces reliability risks that traditional chips do not possess: the dynamic adjustment process itself may become unstable under aging effects, noise interference, or extreme load conditions.

[0023] Currently, there are two main technical approaches for reliability monitoring of adaptive chips. One is to integrate real-time monitoring and parameter adjustment circuits within the chip to achieve online hardening; the other is to conduct offline verification and screening through accelerated stress testing such as high temperature and high pressure. In-depth analysis reveals that both of these approaches have fundamental flaws. On the one hand, while built-in enhancement circuits can achieve active compensation, they themselves become new potential failure points, and their performance and aging trajectory cannot be assessed externally. On the other hand, traditional aging tests place the chip in a fixed extreme state, making it difficult to reproduce key dynamic stress scenarios such as mode switching and load jumps in actual operation. This results in a large number of transient faults directly related to adaptive behavior not being triggered or observed, forming a "dynamic blind spot." Furthermore, existing methods rely solely on static terminal indicators such as power consumption and functional accuracy, failing to quantify the reliability of key behaviors such as adjustment response speed and decision accuracy. Moreover, after a fault occurs, the inability to obtain internal loop data leads to a "black box guessing" dilemma.

[0024] To solve the technical problems mentioned above, such as Figure 1 As shown, this application provides an adaptive chip electrical reliability testing system, which includes: The dynamic stimulus generation module 110 generates dynamic stimuli to be applied to the adaptive chip according to a preset scenario script. The dynamic stimuli include at least one of port voltage, load current and clock frequency. The internal signal monitoring module 120 is connected to the adaptive chip and performs distributed sampling of multiple functional circuits of the adaptive chip during the application of dynamic excitation to obtain a time-synchronized chip behavior data stream. The behavioral reliability assessment module 130 is connected to the dynamic excitation generation module 110 and the internal signal monitoring module 120 respectively. It determines the dynamic reliability entropy that characterizes the deviation of the adaptive chip's behavioral features based on the chip behavior data stream and dynamic excitation, and evaluates the quantitative score of the adaptive adjustment loop formed by different functional circuits in the adaptive chip based on the dynamic reliability entropy. The digital twin analysis module 140 is connected to the internal signal monitoring module 120 and the behavior reliability assessment module 130 respectively. It generates simulation data based on a preset scenario script, compares the chip behavior data stream and dynamic reliability entropy with the corresponding simulation data to determine the deviation contribution of multiple functional circuits, and evaluates the reliability result of the adaptive chip based on the deviation contribution.

[0025] like Figure 1As shown, the adaptive chip electrical reliability testing system 100 includes a dynamic stimulus generation module 110, an internal signal monitoring module 120, a behavioral reliability assessment module 130, and a digital twin analysis module 140. The input of the dynamic stimulus generation module 110 is connected to a preset scenario script, and it generates dynamic stimuli based on the preset scenario script. The dynamic stimuli include at least one of port voltage, load current, and clock frequency. The internal signal detection module 120 is connected to the adaptive chip. During the application of dynamic stimuli to the adaptive chip, it performs distributed sampling on multiple functional circuits in the adaptive chip, that is, it collects node signals from the sensing function circuit, decision function circuit, and execution function circuit in the adaptive chip to obtain a time-synchronized chip behavioral data stream. The input of the behavioral reliability assessment module 130 is connected to both the dynamic stimulus generation module 110 and the internal signal detection module 120. It calculates the dynamic reliability entropy based on the chip behavioral data stream and the dynamic stimuli, and quantitatively assesses the quantitative score of the adaptive adjustment loop in the adaptive chip based on the dynamic reliability entropy. The dynamic reliability entropy can be used to measure the stability of the internal decision function circuit of the adaptive chip when the adaptive adjustment loop faces dynamic stimuli. The digital twin analysis module 140 is connected to the internal signal monitoring module 120 and the behavior reliability assessment module 130, respectively. The digital twin analysis module 140 integrates behavior sub-models corresponding to multiple functional circuits in the adaptive chip. Under the same preset scenario script stimulus, the chip behavior data stream and dynamic reliability entropy are compared and analyzed with the corresponding simulation data in real time to obtain the deviation contribution. Finally, the reliability result of the adaptive chip is evaluated based on the deviation contribution of each node. The reliability result includes the fault location of the adaptive chip and the chip reliability degradation trend.

[0026] In detail, the dynamic excitation generation module 110 includes: a programmable power sequence unit that generates port voltage according to a preset scenario script; an electronic load control unit that generates load current according to a preset scenario script; a frequency generation unit that generates clock frequency according to a preset scenario script; and an excitation generation unit that controls at least two of the programmable power sequence unit, the electronic load control unit, and the frequency generation unit to output synchronously to form a dynamic excitation with a predetermined timing relationship.

[0027] Specifically, the dynamic excitation generation module 110 includes a programmable power sequence unit, an electronic load control unit, a frequency generation unit, and an excitation generation unit. The programmable power sequence unit includes a digital control interface, a precision digital-to-analog converter, and a power amplifier. The programmable power sequence unit generates port voltages with programmable amplitude, slope, and duration according to a preset scenario script. The electronic load control unit includes a pulse width modulation controller and a field-effect transistor array. The electronic load control unit changes the duty cycle according to the preset scenario script to dynamically simulate changing load current. The frequency generation unit includes a digital phase-locked loop and a variable frequency divider. The frequency generation unit generates a clock frequency with programmable frequency, phase, or modulation mode according to the preset scenario script. The excitation generation unit is connected to the programmable power sequence unit, the electronic load control unit, and the frequency generation unit. Driven by the preset scenario script, the excitation generation unit simultaneously controls at least two of the programmable power sequence unit, the electronic load control unit, and the frequency generation unit to generate dynamic excitations with predetermined timing relationships. The predetermined timing relationship is achieved through a unified time base and a synchronous triggering mechanism, which enables at least two of the port voltage, load current and clock frequency to change in tandem according to a preset phase relationship, thereby simulating the complex power scenario of multi-parameter interconnection in actual work.

[0028] For example, phase relationship coordination includes voltage-current coordination and clock-current coordination. Voltage-current coordination refers to the timing changes in which the port voltage and load current are out of phase or in phase, thereby simulating power network voltage drop, sudden load increase, or sudden load decrease scenarios. Clock-current coordination refers to the clock frequency and load current changing in phase, thereby simulating the scenario of a synchronous surge in load and power consumption of an adaptive chip.

[0029] A pre-defined scenario script is a structured, programmable sequence of instructions used to precisely control programmable power sequence units, electronic load control units, and frequency generation units, enabling the excitation generation units to generate dynamically changing excitations in a coordinated manner. The pre-defined scenario script defines the target output values ​​of each unit in the form of a timestamp-parameter vector, and is uniformly parsed and synchronously triggered by a global reference clock.

[0030] For example, the preset scenario script defines a test cycle with a total duration of 30 milliseconds; the first stage: from 0 to 10 milliseconds (in the steady state stage), the port voltage is maintained at 1.00V, the load current is maintained at 0.1A, and the clock frequency is maintained at 100MHz, so that the adaptive chip is in a light-load quiet state; starting from the 10.0 millisecond, the port voltage, load current and clock frequency change every 0.2 milliseconds, the port voltage decreases from 1.00V to 0.95V with a linear slope, and the load current increases from 0.1A to 1.8A with a linear slope; the port voltage and load current are perfectly aligned in time, but change in opposite directions, forming an anti-phase timing change, thereby simulating the voltage drop scenario caused by a sudden surge in load.

[0031] The second stage: from 10.2 milliseconds to 20.0 milliseconds, the port voltage is maintained at 1.8A, while the clock frequency is linearly increased from 100MHz to 900MHz. This time, there is a delay in the in-phase relationship, which simulates the dynamic adjustment process of the adaptive adjustment loop inside the adaptive chip to try to improve computing power in order to compensate for insufficient voltage.

[0032] The third stage: the recovery stage from 20.0 ms to 20.5 ms, during which the port voltage recovers from 0.95V to 1.00V, while the load current drops sharply from 1.8A to 0.1A, thus simulating load removal.

[0033] In the fourth phase, from 20.5 milliseconds to 30.0 milliseconds, the clock frequency linearly drops from 900MHz to 100MHz, completing a full test cycle.

[0034] XML is a relatively "heavyweight" markup language with a more rigorous syntax, similar to HTML (Hypertext Markup Language). It focuses on describing the structure and meaning of data. JSON (JavaScript Object Notation) is a lightweight data-interchange format.

[0035] The dynamic excitation generation module 110 loads a preset scenario script (usually predefined in a structured text format such as JSON or XML), and parses and executes the corresponding instruction sequence based on the time base. Based on the above operation mode, the predefined multi-parameter collaborative change logic with complex timing relationships in the preset scenario script is accurately converted into the actual electrical stress of the adaptive chip, thereby verifying the behavior and reliability of the adaptive chip under dynamic stress.

[0036] In detail, the internal signal monitoring module 120 includes: a signal acquisition unit, which acquires data packets output by each functional circuit; a timestamp marking unit, which adds timestamps to each data packet according to the global reference clock; and a data alignment unit, which reorders and aligns the data packets based on the timestamps to generate a chip behavior data stream.

[0037] Specifically, the signal acquisition unit includes multiple local sampling sub-units, each located near the end of a different signal acquisition link. Each local sampling sub-unit includes an analog-to-digital converter and a phase-locked loop (PLL). The PLL is connected to the device providing the global reference clock via a low-skew clock distribution network, ensuring that the sampling clock of each local sampling sub-unit is locked to the global reference clock, resulting in the acquisition and output of multiple data packets. At the instant of each acquired data packet, a timestamp unit adds a high-resolution timestamp to the data packet based on the global reference clock, with an accuracy down to the nanosecond level. The data alignment unit identifies the fixed delays caused by the differences between the various signal acquisition links and reorders and aligns all data packets according to the timestamps in the data packets to compensate for the fixed delays, generating a chip behavior data stream with all data packets strictly synchronized on the timeline. This design ensures that even in a distributed acquisition architecture, the captured multi-node behaviors are comparable in timing, laying a solid foundation for subsequent analysis of loop dynamic behavior.

[0038] Among them, reordering refers to arranging data according to the sampling time marked by the timestamp rather than the data arrival time, and alignment refers to compensating for the fixed transmission delay of each signal acquisition link in order to reconstruct a time-synchronized chip behavior data stream across multiple functional circuits.

[0039] It should be noted that the internal signal monitoring module 120 acquires chip behavior data streams in a "non-intrusive" manner, utilizing the infrastructure designed within the adaptive chip itself. Specifically, the hardware front-end adapter of the internal signal monitoring module 120 connects to the internal network of the adaptive chip via standard test access ports, such as JTAG (Joint Test Action Group) and SWD (Serial Wire Debug), or a dedicated observation multiplexer specifically designed for observation within the adaptive chip. During the design phase, the adaptive chip has already connected the key nodes of its adaptive regulation loop to the corresponding ports or multiplexers. Therefore, the internal signal monitoring module 120 does not require the introduction of external probes or damage to the chip package; it can directly access the node signals of the functional circuits within the adaptive chip via debug commands or configuration registers, achieving truly non-intrusive data capture.

[0040] In detail, the behavioral reliability assessment module 130 includes: a data preparation unit that receives dynamic stimulus and chip behavior data stream and performs time alignment; an entropy determination unit that calculates at least one dynamic reliability entropy based on the time-aligned dynamic stimulus and chip behavior data stream, wherein the dynamic reliability entropy includes at least path entropy, and path entropy is used to characterize the randomness of the selection of the adaptive adjustment loop; and an assessment unit that converts the dynamic reliability entropy into a quantitative score based on a preset scoring mapping relationship.

[0041] Specifically, the behavioral reliability assessment module 130 includes a data alignment unit, an entropy determination unit, and an evaluation unit. The data alignment unit receives dynamic stimuli and chip behavior data streams, and aligns the chip behavior data streams and corresponding dynamic stimuli in time. The entropy determination unit calculates one or more dynamic reliability entropies based on the aligned dynamic stimuli and chip behavior data streams. The dynamic reliability entropy includes at least the path entropy based on the randomness of the selection of the adaptive adjustment loop, and may also include entropy indicators of deviation from other feedback adjustment behavioral characteristics. The evaluation unit, based on a preset scoring mapping relationship, converts the value, trend, and fluctuation rate of the dynamic reliability entropy into quantitative scores for the stability, consistency, and predictability of the adaptive adjustment loop, respectively. The preset scoring mapping relationship includes: ① comparing the value of the dynamic reliability entropy with a preset entropy threshold range to determine the stability score; ② determining the consistency score based on the degree of fluctuation of the time series of dynamic reliability; and ③ determining the predictability score based on the rate of change of the dynamic reliability entropy.

[0042] More specifically, the entropy determination unit includes: a path extraction subunit, which analyzes the adaptive adjustment loops activated in each dynamic excitation cycle based on the node signals output by the decision function circuit of the adaptive chip; a probability determination subunit, which counts the activation frequency of each adaptive adjustment loop based on the repeatedly applied dynamic excitation, and determines the probability parameter based on the activation frequency; and an entropy calculation subunit, which calculates the path entropy based on the probability parameter and the information entropy relationship.

[0043] Specifically, the entropy determination unit includes a path extraction subunit, a probability determination subunit, and an entropy calculation subunit. The path extraction subunit analyzes the node signals output from the decision function circuit of the adaptive chip to identify the activated adaptive adjustment loops within each dynamic excitation cycle. The probability determination subunit, under repeated identical dynamic excitations, counts the activation frequency of each adaptive adjustment loop and calculates the probability parameter for the selection of each adaptive adjustment loop. The entropy calculation subunit inputs the probability parameter into the information entropy relation to calculate the path entropy.

[0044] For example, the method for calculating dynamic reliability entropy is as follows: from the chip behavior data stream, the state signal of the decision function circuit in the adaptive chip (i.e., the digital logic circuit inside the adaptive chip that makes pattern judgment based on the sensing signal and generates control instructions) indicates the adaptive adjustment loop that is activated in each dynamic excitation cycle (i.e., the specific operating mode selected by the adaptive chip in response to dynamic excitation, such as pulse width modulation mode, pulse frequency modulation mode or sleep mode).

[0045] Under repeated dynamic excitation, the frequency of activation of each adaptive adjustment loop is counted, and the probability parameter of each selected loop is calculated (i.e., the proportion of the frequency of each path to the total number of occurrences, such as 78% for pulse width modulation mode, 18% for pulse frequency modulation mode, and 4% for sleep mode). The path entropy value is obtained by running the information entropy relation through the probability parameter.

[0046] In one specific embodiment, firstly, the status signal of the decision function circuit of the adaptive chip is captured through a dedicated mode indicator pin or an access interface to the internal status register. The status signal is a 2-bit digital code; 00 represents pulse width modulation mode, 01 represents pulse frequency modulation mode, and 10 represents sleep mode. During the response to each dynamic stimulus (such as a load step), the status signal is continuously monitored; and based on a preset parsing rule (identifying the longest-lasting and most stable mode code), the dominant and stable mode code within a stimulus cycle is parsed into the adaptive adjustment loop selected by the adaptive chip for this stimulus cycle.

[0047] Secondly, the same preset scenario script (e.g., "load current jumps from 0.5A to 1.5A") was applied 100 times. The main adaptive regulation loop selected by the adaptive chip in each response was recorded. The statistical results are shown in Table 1: Table 1. Number of selections for the adaptive adjustment loop and corresponding probability parameters

[0048] Finally, based on the probability parameters in Table 1, the path entropy (i.e., the dynamic reliability entropy index reflecting the randomness of adaptive adjustment loop selection) is calculated in the information entropy relation. The information entropy relation is shown in expression (1): (1) Where H represents path entropy and Pi is a probability parameter.

[0049] Substituting the probability parameters obtained from the statistics, we get expressions (2) to (4). (2) (3) (4) Where H represents path entropy, P1 is the probability parameter corresponding to pulse width modulation mode, P2 is the probability parameter corresponding to pulse frequency modulation mode, and P3 is the probability parameter corresponding to sleep mode.

[0050] The physical meaning of path entropy lies in quantifying the uncertainty or randomness of the adaptive adjustment loop selection; in this example, the path entropy value is approximately 0.91 bits; if the adaptive chip ages or has potential defects, its decision may become unstable, and the mode switching under the same dynamic stimulus may become random (for example, the three modes appear with approximately equal probability); this will lead to a more uniform probability distribution, and the calculated path entropy value will increase significantly (approaching the theoretical maximum value log2(3)≈1.58 bits); conversely, a completely healthy and stable adaptive chip should have highly deterministic and repeatable path selection, a concentrated probability distribution, and a lower path entropy; therefore, as a dynamic reliability entropy, the magnitude and trend of path entropy directly and physically characterize the stability and consistency of decision-making in the adaptive adjustment loop, providing a quantifiable core indicator for reliability assessment.

[0051] More specifically, the behavioral reliability assessment module 130 also includes a data feedback unit, which generates an assessment report based on the dynamic reliability entropy and quantitative score, and dynamically adjusts the preset scenario scripts based on the assessment report. Specifically, after obtaining the quantitative score, the data feedback unit can also generate an assessment report based on the quantitative score, the sequence of dynamic reliability entropy, and abnormal time points, and feed the assessment report back to the dynamic stimulus generation module in real time, so as to dynamically adjust the stress intensity, change rate, or mode combination of subsequent preset scenario scripts to form a closed loop of reinforcement testing for the identified weak links.

[0052] In detail, the digital twin analysis module 140 includes: a simulation generation unit, which, driven by a preset scenario script, uses behavioral sub-models corresponding to each functional circuit to generate expected values ​​of measured parameters, including chip behavior data flow and dynamic reliability entropy; a deviation analysis unit, which determines the deviation data of each measured parameter according to the measured parameters and the corresponding expected values, and analyzes the deviation contribution of each functional circuit to the total deviation of the adaptive chip based on the deviation data; and a fault diagnosis unit, which performs fault identification on each deviation contribution based on preset fault mapping rules to generate reliability results. Specifically, the digital twin analysis module 140 includes a simulation generation unit, a deviation analysis unit, and a fault diagnosis unit. Driven by a preset scenario script, the simulation generation unit runs discretely modeled behavioral sub-models (i.e., sensing sub-model, decision sub-model, and execution sub-model) to generate expected values ​​corresponding to the chip behavior data flow (i.e., the expected output values ​​of each functional circuit) and the expected values ​​corresponding to the dynamic reliability entropy. The deviation analysis unit connects to the simulation generation unit and the behavioral reliability assessment module at its input. It calculates the deviation data between the output nodes of each functional circuit and their corresponding expected values, as well as the deviation data between the dynamic reliability entropy and its expected value. Based on these multiple deviation data, it calculates the deviation contribution of each functional circuit to the total deviation of the adaptive chip. The fault diagnosis unit identifies the deviation contribution according to preset fault mapping rules, determines the faulty components of the adaptive chip, and establishes reliability results including degradation trends.

[0053] More specifically, the deviation analysis unit includes: a relationship construction subunit, which constructs a sensitivity analysis model characterizing the sensitivity of each functional circuit to the total deviation based on the signal transmission relationships between multiple behavioral sub-models; and a deviation determination subunit, which inputs the deviation data into the sensitivity analysis model to determine the deviation contribution of each functional circuit. Specifically, the deviation analysis unit includes a relationship construction subunit and a deviation determination subunit. The relationship construction subunit constructs a sensitivity analysis model characterizing the sensitivity of the output of each functional circuit to the total deviation based on the signal transmission relationships between the discretely modeled behavioral sub-models. The sensitivity analysis model is either a Jacobian matrix or a sensitivity model. The Jacobian matrix is ​​suitable for accurate modeling when the analytical expression of the transfer function is known, while the sensitivity model is suitable for approximate analysis of complex nonlinearities. The deviation determination subunit inputs the deviation data into the sensitivity analysis model to calculate the deviation contribution of each functional circuit's responsibility.

[0054] For example, a simplified Jacobian matrix J is established based on multiple behavioral sub-models. At a certain operating moment, the total deviation of the test system (such as the output voltage error ΔV) can be approximately represented as the linear superposition of the deviations of each functional circuit. Each column of the Jacobian matrix J characterizes the sensitivity of the functional circuit parameters to the total deviation by small changes. For example, if the total deviation ΔV is -50mV, the contribution weights [c1, c2, c3] of each functional circuit can be calculated using the least squares method, such as [70%, 5%, 25%]. This quantifies the "responsibility" of each functional circuit for the current failure.

[0055] More specifically, the behavioral sub-model includes: a first behavioral sub-model that transmits and outputs the acquired data inside the adaptive chip; a second behavioral sub-model that determines the mode control signal based on the output of the first behavioral sub-model and a preset parameter threshold; and a third behavioral sub-model that calculates the target parameters based on the mode control signal and a preset variable function.

[0056] Specifically, the digital twin analysis module 140 is equipped with a discrete behavioral sub-model corresponding to the adaptive adjustment loop of the adaptive chip. Taking the adaptive power management chip as an example: the digital twin analysis module includes a sensing sub-model, a decision sub-model, and an execution sub-model. The sensing sub-model simulates the voltage and stable sampling chain inside the adaptive chip. Its core is the analog front-end transfer function containing gain, bias, and bandwidth parameters. The analog front-end transfer function is shown in expression (5): (5) in, It is the output of the sensor sub-model; K is the gain coefficient of the sensor sub-model (K>1 indicates amplification, K<1 indicates attenuation), and K is equal to 1 for an ideal sensor sub-model; For the actual physical quantity being measured, This is the inherent DC offset error in the sensor sub-model.

[0057] In the analog front-end transfer function, the gain coefficient K is determined by factors such as the operational amplifier gain and the voltage division ratio of the resistors.

[0058] The decision sub-model simulates the mode selection logic inside the adaptive chip and is implemented as a finite state machine. Its state transition conditions are based on the output of the sensing sub-model (such as "voltage is higher than threshold voltage Vth"), and the output is a specific mode control signal (such as "switch to PFM mode").

[0059] The dynamic response of the power stage is simulated by the sub-model, which is usually described by the transfer function of a controlled voltage source or current source and its output filter circuit (RLC network). The calculation expression of the transfer function is shown in (6): (6) in, The core control signal output by the decision sub-model. Let be a function with complex frequency s as the variable. The target parameters are output by the sub-model.

[0060] It is worth mentioning that, It is a value between 0 and 1 that determines the proportion of the power switch's on-time within one cycle, thereby enabling voltage regulation of the adaptive chip. It encapsulates the dynamic characteristics of all passive components (inductor L, capacitor C, parasitic resistance R) in the power stage; that is, the regulated voltage supplied to the chip core or other loads. Running expression (6), given a... At that time, the power stage will not output an ideal DC voltage instantaneously, but will have a voltage range determined by... The determined dynamic response process (such as rise, overshoot, oscillation) ultimately causes the execution sub-model to output the target parameter V. out .

[0061] More specifically, the fault diagnosis unit includes: a first diagnosis subunit, which determines that the adaptive chip has a first-line fault when the weight of the deviation contribution in the first-line sub-model exceeds a first preset threshold; a second diagnosis subunit, which determines that the adaptive chip has a second-line fault when the weight of the deviation contribution in the second-line sub-model exceeds a second preset threshold; and a third diagnosis subunit, which determines that the adaptive chip has a third-line fault when the weight of the deviation contribution in the third-line sub-model exceeds a third preset threshold.

[0062] Specifically, the fault diagnosis unit includes a first diagnostic subunit, a second diagnostic subunit, and a third diagnostic subunit. The first diagnostic subunit determines a first-order fault in the adaptive chip when the weight of the deviation contribution in the sensing function circuit consistently exceeds 65%, and the deviation timing exhibits slow unidirectional drift; that is, sensor circuit gain degradation. The second diagnostic subunit determines a second-order fault in the adaptive chip when the weight of the deviation contribution in the decision function circuit significantly increases, such as exceeding 30%, and the dynamic reliability entropy shows frequent, unexpected switching under specific conditions; that is, the decision function circuit is affected by noise interference or improper threshold settings. The third diagnostic subunit determines a third-order fault in the adaptive chip when the weight of the deviation contribution in the execution function circuit exceeds 80%, and high-frequency oscillation occurs; that is, the inductor or capacitor parameters of the power stage output filter in the execution function circuit degrade.

[0063] This invention proposes an adaptive chip electrical reliability testing system, comprising: a dynamic excitation generation module that generates dynamic excitation applied to the adaptive chip based on a preset scenario script; an internal signal monitoring module that collects node signals of multiple functional circuits of the adaptive chip in a distributed manner to obtain a chip behavior data stream; a behavior reliability assessment module that determines the dynamic reliability entropy based on the chip behavior data stream and the dynamic excitation, and assesses the quantitative score of the adaptive adjustment loop formed by different functional circuits based on the dynamic reliability entropy; and a digital twin analysis module that generates simulation data based on the preset scenario script, compares the simulation data with the chip behavior data stream and the dynamic reliability entropy respectively, determines the deviation contribution of the functional circuits, and then assesses the reliability result of the adaptive chip based on the deviation contribution. This invention monitors the adaptive adjustment loop inside the chip to achieve white-box operation and process visualization under dynamic excitation, transforming the test object from static functional results into dynamic behavioral processes. It can directly capture faults caused by various functional circuits, making up for the dynamic blind spots of traditional static testing. At the same time, it introduces dynamic reliability entropy to quantitatively characterize the adaptive adjustment behavior, elevating reliability assessment from qualitative analysis to quantitative analysis. In addition, through real-time comparison of measured data with high-fidelity models and analysis of deviation contribution, it can not only achieve early degradation warning, but also accurately locate the abnormal occurrence link.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An adaptive chip electrical reliability testing system, characterized in that, include: The dynamic stimulus generation module generates dynamic stimuli to be applied to the adaptive chip according to a preset scenario script. The dynamic stimulus includes at least one of port voltage, load current and clock frequency. An internal signal monitoring module, which is connected to the adaptive chip, performs distributed sampling of multiple functional circuits in the adaptive chip during the application of the dynamic excitation to obtain a time-synchronized chip behavior data stream; A behavior reliability assessment module, which is connected to the dynamic excitation generation module and the internal signal monitoring module respectively, determines the dynamic reliability entropy characterizing the deviation of the adaptive chip behavior features based on the chip behavior data stream and the dynamic excitation, and evaluates the quantitative score of the adaptive adjustment loop formed by different functional circuits in the adaptive chip based on the dynamic reliability entropy. The digital twin analysis module is connected to the internal signal monitoring module and the behavior reliability assessment module, respectively. It generates simulation data based on the preset scenario script, compares the chip behavior data stream and the dynamic reliability entropy with the corresponding simulation data to determine the deviation contribution of multiple functional circuits, and evaluates the reliability result of the adaptive chip based on the deviation contribution.

2. The adaptive chip electrical reliability testing system according to claim 1, characterized in that, The dynamic stimulus generation module includes: A programmable power sequence unit generates the port voltage according to the preset scenario script; The electronic load control unit generates the load current according to the preset scenario script; The frequency generation unit generates the clock frequency according to the preset scenario script; The excitation generation unit controls at least two of the programmable power sequence unit, the electronic load control unit, and the frequency generation unit to output synchronously, thereby forming a dynamic excitation with a predetermined timing relationship.

3. The adaptive chip electrical reliability testing system according to claim 1, characterized in that, The internal signal monitoring module includes: The signal acquisition unit acquires the data packets output by each of the aforementioned functional circuits. The timestamp marking unit adds a timestamp to each of the data packets according to the global reference clock; The data alignment unit reorders and aligns the data packets based on the timestamp to generate the chip behavior data stream.

4. The adaptive chip electrical reliability testing system according to claim 1, characterized in that, The behavioral reliability assessment module includes: The data preparation unit receives the dynamic stimulus and the chip behavior data stream, and performs time alignment. An entropy determination unit calculates at least one dynamic reliability entropy based on the time-aligned dynamic stimulus and the chip behavior data stream. The dynamic reliability entropy includes at least path entropy, which is used to characterize the randomness of the selection of the adaptive adjustment loop. The evaluation unit converts the dynamic reliability entropy into the quantitative score based on a preset scoring mapping relationship.

5. The adaptive chip electrical reliability testing system according to claim 4, characterized in that, The entropy determination unit includes: The path extraction subunit analyzes the adaptive adjustment loop activated in each dynamic excitation cycle based on the node signal output by the decision function circuit of the adaptive chip. The probability determination subunit, based on the repeatedly applied dynamic excitation, counts the activation frequency of each adaptive adjustment loop and determines the probability parameter based on the activation frequency; The entropy calculation subunit calculates the path entropy based on the probability parameter and the information entropy relationship.

6. The adaptive chip electrical reliability testing system according to claim 4, characterized in that, The behavioral reliability assessment module also includes: The data feedback unit generates an evaluation report based on the dynamic reliability entropy and the quantitative score, and dynamically adjusts the preset scenario script based on the evaluation report.

7. The adaptive chip electrical reliability testing system according to claim 1, characterized in that, The digital twin analysis module includes: The simulation generation unit, driven by the preset scenario script, uses the behavioral sub-models corresponding to each of the functional circuits to generate expected values ​​of the measured parameters, which include the chip behavior data stream and the dynamic reliability entropy. The deviation analysis unit determines the deviation data of each measured parameter according to the measured parameters and the corresponding expected values, and analyzes the deviation contribution of each functional circuit to the total deviation of the adaptive chip based on the deviation data. The fault diagnosis unit identifies faults based on preset fault mapping rules for each of the deviation contributions, in order to generate the reliability result.

8. The adaptive chip electrical reliability testing system according to claim 7, characterized in that, The deviation analysis unit includes: The relationship construction subunit constructs a sensitivity analysis model characterizing each functional circuit to the total deviation based on the signal transmission relationship between multiple behavioral sub-models. The deviation determination subunit inputs the deviation data into the sensitivity analysis model to determine the deviation contribution of each of the functional circuits.

9. The adaptive chip electrical reliability testing system according to claim 7, characterized in that, The behavioral sub-model includes: The first row is a sub-model that transmits and outputs the collected data inside the adaptive chip; The second row is a sub-model, which determines the mode control signal based on the output of the first row sub-model and a preset parameter threshold. The third row is a sub-model, which calculates the target parameters based on the mode control signal and the preset variable function.

10. The adaptive chip electrical reliability testing system according to claim 7, characterized in that, The fault diagnosis unit includes: The first diagnostic unit determines that the adaptive chip has a first behavior fault when the weight of the deviation contribution in the first behavior sub-model exceeds a first preset threshold. The second diagnostic unit determines that the adaptive chip has a second behavior fault when the weight of the deviation contribution in the second behavior sub-model exceeds a second preset threshold. The third diagnostic unit determines that the adaptive chip has a third-line fault when the weight of the deviation contribution in the third-line sub-model exceeds a third preset threshold.

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