A mask layout optimization method, device, medium, and program product

Abstract

This application discloses a mask layout optimization method, apparatus, medium, and program product, relating to the field of semiconductor manufacturing technology. The mask layout optimization method includes: dividing the mask layout according to the rule that blocks of the same level are not adjacent to each other, obtaining multiple blocks of varying levels from low to high, ensuring that blocks of the same level do not interfere with each other and avoiding conflicts caused by circular dependencies; pushing at least one lowest-level block into an optimization queue, and retrieving blocks according to the optimization queue for optimization; for each block with a level higher than the lowest-level block, after optimizing other adjacent blocks with a lower level, inserting that block at the head of the optimization queue, triggering the insertion of higher-level blocks by optimizing adjacent lower-level blocks, avoiding out-of-order optimization; after one or more highest-level blocks have been optimized, releasing the memory of optimized blocks that have no optimization relationship with other blocks, avoiding memory accumulation, thereby improving the stability of mask optimization.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and in particular relates to a mask layout optimization method, apparatus, medium and process product. Background Technology

[0002] With the increasing integration of chips, a single mask layout now integrates billions of graphics units, making it impossible for a single computer to meet the timeliness requirements of mask optimization.

[0003] Currently, the mask layout is generally divided into multiple blocks, and each block is distributed to different nodes in a computer cluster for parallel computation. After all blocks are computed, the computation results of each node are aggregated to output the mask optimization result. However, this method lacks a block memory management mechanism, which makes it impossible to release memory in a timely manner after the block computation is completed. The accumulation of memory usage causes the mask optimization process to be interrupted, resulting in poor stability of mask optimization. Summary of the Invention

[0004] This application provides a mask layout optimization method, device, medium, and program product that can release memory after block optimization is completed, thereby improving the stability of mask optimization.

[0005] A first aspect of this application provides a mask layout optimization method, including: The mask layout is divided according to the rule that blocks of the same level are not adjacent to each other, resulting in multiple blocks of different levels from low to high. Push at least one lowest-level block into the optimization queue; Extract blocks according to the optimized queue and optimize them accordingly; During the optimization of the extracted graphics within the blocks, for each block whose level is higher than the lowest level block, after optimizing the blocks adjacent to that block whose level is lower than that block, the block is inserted at the head of the optimization queue. After one or more top-level blocks have been optimized, release the memory of the optimized blocks that have no optimization relationship with other blocks.

[0006] A second aspect of this application provides a mask layout optimization apparatus, comprising: The partitioning module is used to divide the mask layout according to the rule that blocks of the same level are not adjacent to each other, so as to obtain multiple blocks of different levels from low to high. The queue building module is used to push at least one lowest-level block into an optimized queue; The queue reading module is used to retrieve blocks according to the optimized queue and perform optimization; The queue adjustment module is used to, during the process of optimizing the graphics within the extracted blocks, insert each block with a level higher than the lowest level block into the head of the optimization queue after optimizing the adjacent blocks with a level lower than the lowest level block. The memory release module is used to release the memory of optimized blocks that have no optimization relationship with other blocks after one or more top-level blocks have been optimized.

[0007] A third aspect of the embodiments of this application provides a computer device, the device comprising: a memory and a program or instructions stored in the memory and executable on a processor, wherein when the program or instructions are executed by the processor, they implement the mask layout optimization method provided in any of the embodiments of this application described above.

[0008] A fourth aspect of the embodiments of this application provides a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, implement the mask layout optimization method provided by any aspect of the embodiments of this application described above.

[0009] A fifth aspect of the embodiments of this application provides a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a mask layout optimization method as provided in any aspect of the embodiments of this application described above.

[0010] The technical solution provided in this application has at least the following beneficial effects: In a mask layout optimization method provided in this application embodiment, firstly, the mask layout is divided according to the rule that blocks of the same level are not adjacent to each other, resulting in multiple blocks of varying levels from low to high, ensuring that blocks of the same level do not interfere with each other and avoiding conflicts caused by circular dependencies; secondly, at least one lowest-level block is pushed into an optimization queue, and blocks are retrieved and optimized according to the optimization queue. Then, for each block with a level higher than the lowest-level block, after optimizing other blocks adjacent to the block with a lower level, the block is inserted at the head of the optimization queue. Optimizing adjacent low-level blocks triggers the insertion of high-level blocks, avoiding out-of-order optimization or missed optimization; finally, after one or more highest-level blocks have been optimized, the memory of optimized blocks that have no optimization relationship with other blocks is released to avoid memory accumulation, thereby improving the stability of mask optimization. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a mask layout optimization method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the block hierarchy provided in the embodiments of this application; Figure 3 This is a schematic diagram of the mask layout hierarchy provided in the embodiments of this application; Figure 4a This is a schematic diagram of the selection box for defining the region provided in an embodiment of this application; Figure 4b This is a schematic diagram of the optimized queue after the lowest level block is divided within the push area selection box provided in the embodiments of this application; Figure 4c This is a schematic diagram of the first-level block insertion into the queue head, as provided in an embodiment of this application, to optimize the queue; Figure 4d This is a schematic diagram of the second-level block insertion into the queue head, as provided in an embodiment of this application, to optimize the queue; Figure 4e This is a schematic diagram of the expanded region selection box provided in an embodiment of this application; Figure 4f This is a schematic diagram of the optimized queue after pushing a new frame into the lowest-level block, provided in an embodiment of this application; Figure 4g This is a schematic diagram illustrating the optimization of the queue after inserting the highest-level block into the queue head, as provided in the embodiments of this application. Figure 5a This is a schematic diagram illustrating the trend of memory occupancy released in batches according to block levels, as provided in an embodiment of this application. Figure 5b This is a schematic diagram illustrating the memory usage trend after each highest-level block has been optimized, as provided in an embodiment of this application. Figure 6 This is a schematic diagram of the structure of a mask layout optimization device provided in one embodiment of this application; Figure 7 This is a schematic diagram of a mask layout optimization device provided in one embodiment of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0016] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0017] Mask optimization is a process that uses algorithms to correct the pattern of a mask layout in order to counteract the optical proximity effect caused by light diffraction and interference during photolithography.

[0018] A patch refers to a graphic unit formed after dividing a mask layout.

[0019] A computer cluster is a computing system consisting of multiple independent computers connected by a network. These computers work together to complete large-scale, highly complex computing tasks that a single computer cannot handle.

[0020] The head of the queue is the starting position for optimization. The blocks in the queue are taken out and optimized in order from the head to the tail of the queue.

[0021] The optimization relationship is the scheduling relationship formed between different blocks in the mask layout due to the optical proximity effect correction requirements. That is, the optimization of one block needs to call the optimization result of another block.

[0022] With the increasing integration of chips, a single mask layout now integrates billions of graphics units, making it impossible for a single computer to meet the timeliness requirements of mask optimization.

[0023] Currently, the mask layout is generally divided into multiple blocks, and each block is distributed to different nodes in a computer cluster for parallel computation. After all blocks are computed, the computation results of each node are aggregated to output the mask optimization result. However, this method lacks a block memory management mechanism, which makes it impossible to release memory in a timely manner after the block computation is completed. The accumulation of memory usage causes the mask optimization process to be interrupted, resulting in poor stability of mask optimization.

[0024] To address the aforementioned technical problems, this application provides a mask layout optimization method, apparatus, medium, and computer program product. In the mask layout optimization method provided in this application, the mask layout is divided into multiple blocks according to the rule that blocks of the same level are not adjacent. Each block is then divided into multiple levels from low to high. Ordered optimization of the blocks is achieved through optimization queue scheduling: first, at least one lowest-level block is pushed into the optimization queue; then, blocks are sequentially retrieved and optimized according to the optimization queue. During the optimization process, for blocks with a level higher than the lowest level, after the optimization of adjacent blocks of even lower level is completed, the block is inserted at the head of the optimization queue. After optimizing one or more highest-level blocks, the memory of optimized blocks that have no optimization relationship with other blocks is released to avoid memory accumulation and improve the stability of mask optimization.

[0025] For example, the mask layout optimization method provided in this application embodiment can be applied to the production line of a semiconductor manufacturing enterprise for optimizing and scheduling mask layouts and managing memory. In practical applications, a mask optimization computing platform can be built based on a computer cluster, storing configuration information such as the mask layout to be processed, partitioning rules, and queue scheduling rules in a data storage device. Operators can set configuration information such as block size / number of blocks, partitioning rules, block level, and memory release trigger conditions through an operating interface or control terminal, and issue mask layout optimization task instructions to execute mask optimization of the mask layout.

[0026] It should be noted that the application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems. The mask layout optimization method provided by the embodiments of this application can be applied to various application scenarios involving optimized scheduling and memory management.

[0027] The mask layout optimization method provided in this application embodiment is described below. In practical applications, the execution subject of the mask layout optimization method in this application embodiment can be a terminal device, such as a desktop computer, laptop computer, etc., or a remote device like a server. Of course, this application embodiment can also adopt an execution subject in the form of software, such as a client or software program installed on a terminal device. The specific type of execution subject corresponding to the technical solution provided in this application embodiment is not strictly limited here, and can be flexibly selected according to the actual application scenario and actual needs.

[0028] The following describes specific embodiments of the mask layout optimization method, apparatus, electronic device, storage medium, and computer program product provided in this application. First, a mask layout optimization method is introduced.

[0029] Figure 1 This is a schematic flowchart illustrating a mask layout optimization method provided in an embodiment of this application. Figure 1 As shown, the method includes steps S100 to S104.

[0030] S100: Divide the mask layout according to the rule that blocks of the same level are not adjacent to each other, and obtain multiple blocks of different levels from low to high.

[0031] S101: Push at least one lowest-level block into the optimization queue.

[0032] S102: Take out blocks according to the optimized queue and optimize them.

[0033] S103: During the optimization of the extracted graphics within the blocks, for each block whose level is higher than the lowest level block, after optimizing the blocks adjacent to that block whose level is lower than that block, the block is inserted at the head of the optimization queue.

[0034] S104: After one or more top-level blocks have been optimized, release the memory of the optimized blocks that have no optimization relationship with other blocks.

[0035] In the aforementioned mask layout optimization method, this application divides the mask layout into multiple blocks of varying levels from low to high according to the rule that blocks of the same level are not adjacent to each other. At least one lowest-level block is pushed into the optimization queue. Blocks are then retrieved and optimized sequentially according to the optimization queue. During the optimization process, for blocks with a level higher than the lowest level, after the optimization of adjacent blocks of even lower level is completed, the block is inserted into the head of the optimization queue to ensure orderly optimization of blocks. After one or more highest-level blocks have been optimized, the memory of optimized blocks that have no optimization relationship with other blocks is released to avoid memory accumulation and improve the stability of mask layout optimization.

[0036] In step S100, in order to ensure that the optimization results of its adjacent low-level blocks can be scheduled when optimizing high-level blocks in the future, and to avoid calculation errors or memory waste caused by disordered block association, this application needs to divide the mask layout according to the rule that blocks of the same level are not adjacent to each other, so as to obtain multiple blocks marked as different levels.

[0037] It should be noted that adjacent blocks refer to blocks whose edge regions are adjacent. The core of mask optimization is to correct the optical proximity effect. Since the patterns of adjacent blocks are adjacent in the edge region, light diffraction during photolithography will cause mutual interference between adjacent patterns. Therefore, when correcting the optical proximity effect of a block, it is necessary to call the optimization results of its adjacent blocks in order to accurately reflect the real optical effects and complete the mask optimization. In other words, any two blocks with adjacent edge regions (adjacent blocks) have an inherent attribute of bidirectional physical dependence due to the need for optical proximity effect correction, which depends on the optimization results of each other. If such adjacent blocks with bidirectional physical dependence are set to the same level, they will fall into a circular waiting state of waiting for each other's optimization results due to the lack of optimization priority distinction, which will cause the optimization process to fail and form a scheduling deadlock. In order to avoid scheduling deadlock, this application sets a rule that blocks of the same level are not adjacent to each other. This rule ensures that two adjacent blocks must belong to different levels, cuts off the scheduling dependency of blocks of the same level, and ensures that each block only needs to call its adjacent lower-level blocks during optimization. Another way to express this rule is that blocks of different levels are neighbors to each other. This clarifies that when optimizing, higher-level blocks only depend on their adjacent lower-level blocks. The optimization result of each block is only used to satisfy the scheduling needs of its adjacent higher-level blocks. There is no redundant dependency across levels or across non-adjacent regions, thus forming a unidirectional hierarchical dependency optimization relationship in which adjacent lower-level blocks are optimized first and higher-level blocks are optimized later. This unidirectional hierarchical dependency optimization relationship ensures that each block optimization trigger has a clear scheduling requirement, ensuring the orderly scheduling of subsequent optimizations.

[0038] Based on the rule that blocks of the same level are not adjacent, once all adjacent higher-level blocks corresponding to a certain block have been optimized, the optimization result of that block will no longer be called by any subsequent blocks, allowing for safe release and preventing memory overflow that could lead to optimization interruption, thus improving the stability of mask layout optimization. This application does not limit the specific method of block division and level labeling; it can be set according to actual needs, such as using mesh partitioning, contour partitioning, or adaptive partitioning methods to divide the mask layout into blocks. For the level labeling of blocks, it can be customized based on optimization priority, graphics complexity, or optimization correlation, while ensuring that the labeling results satisfy the rule that blocks of the same level are not adjacent. This application does not limit the specific size of the number or size of blocks when dividing the mask layout; it can be set according to actual needs. For example, based on the complexity of the mask layout and the processing power of the computing cluster, the number or size of blocks can be adjusted while satisfying the rule that blocks of the same level are not adjacent. This application does not limit the number of levels and can set them according to actual needs, such as the configuration of computing resources, layout size, or optimization accuracy requirements. Among them, for the same mask layout and the same number of levels / block size, the larger the number of levels, the more blocks of the same level can be optimized in parallel, and the higher the optimization parallelism.

[0039] For example, a grid partitioning method using orthogonal horizontal and vertical lines can be used to divide the mask pattern into multiple matrix-arranged blocks, and these blocks can be labeled with four levels from low to high according to the rule that blocks of the same level are not adjacent to each other. Figure 2 As shown, this application divides the mask layout into multiple blocks and marks them as four levels from low to high according to the rule that blocks of the same level are not adjacent to each other and blocks of different levels are neighbors of each other, resulting in the lowest level block 201, the first level block 202, the second level block 203 and the highest level block 204.

[0040] If we take the corner points of the mask image as the origin and the graphic boundaries as the coordinate axes, and assign unique coordinates (row coordinates, column coordinates) to each block, then the level labeling of the blocks can be completed based on coordinate characteristics. For example... Figure 3 As shown, this application can take blocks with both even row and column coordinates as the lowest level blocks; blocks with odd row and even column coordinates as the first level blocks; blocks with even row and odd column coordinates as the second level blocks; and blocks with odd row and odd column coordinates as the highest level blocks.

[0041] In step S101, in order to ensure that the subsequent optimization scheduling satisfies the optimization association relationship of unidirectional level dependency, and to schedule the optimization results of its adjacent low-level blocks when optimizing high-level blocks, so as to avoid the situation where the optimization of high-level blocks is blocked due to the disorder of the execution sequence of low-level block optimization, this application needs to push at least one lowest-level block into the optimization queue as the starting node of the entire mask layout optimization process.

[0042] It should be noted that this application does not limit the specific method of pushing at least one lowest-level block into the optimization queue. It can be set according to actual needs, such as pushing all lowest-level blocks into the optimization queue; selecting the lowest-level blocks at corner positions, within corner regions, or within preset regions to push into the optimization queue, and then gradually pushing other lowest-level blocks into the queue through dynamic replenishment. Pushing at least one lowest-level block into the optimization queue serves as the starting point of the entire mask layout optimization process. Its purpose is to initiate the mask layout optimization process from the lowest-level blocks without any prior optimization relationships. Subsequently, the optimization queue is updated by replenishing the lowest-level blocks and inserting higher-level blocks, ensuring that each block is optimized according to a unidirectional level-dependent optimization relationship.

[0043] In step S102, to ensure the timely output of the optimization results of the lowest-level blocks, and to provide data support for subsequent optimization of higher-level blocks and insertion of higher-level blocks at the head of the queue, this application can sequentially retrieve each block from the optimization queue according to a first-in-first-out (FIFO) rule, and then perform serial optimization calculations on the blocks according to the retrieval order, or distribute them to different nodes of a computer cluster for parallel optimization calculations. This application does not limit the specific method of mask optimization; it can be set according to actual needs. For example, block optimization calculations may include lithographic mask optimization operations such as optical proximity effect correction, auxiliary pattern addition, and pattern edge fine-tuning.

[0044] In step S103, to shorten the memory usage time of low-level block optimization results and ensure that the optimization results of adjacent low-level blocks can be scheduled in a timely manner during high-level block optimization, this application monitors the optimization status of blocks in the optimization queue. For each block with a level higher than the lowest-level block, after optimizing adjacent blocks with a lower level, the block is inserted at the head of the optimization queue, enabling it to obtain the required optimization results in a timely manner, skipping other blocks to be optimized in the queue, and prioritizing their optimization.

[0045] In step S104, to avoid memory accumulation caused by the failure to release block memory in a timely manner, and to prevent mask optimization interruption caused by memory usage exceeding the physical limit of the computing node, this application can, after one or more highest-level blocks have been optimized, filter out the optimized blocks that have no optimization relationship with the blocks to be optimized, and release their graphics data and the memory space occupied by the optimization results.

[0046] It should be noted that since the highest-level block is the highest-level block, if a lower-level block that is adjacent to the highest-level block and has been optimized has no optimization relationship with the block to be optimized, it means that the optimization result of the lower-level block has no further call requirement. In this case, the memory of the lower-level block can be released to avoid invalid data occupying memory for a long time, thereby improving the system resource utilization and overall optimization efficiency.

[0047] Furthermore, in step S101, in order to improve the efficiency of mask layout optimization and refine the granularity of memory management, in one or more embodiments of this application, this application may adopt a region-based progressive optimization, as follows: First, this application allows you to define a selection area in the mask pattern.

[0048] It should be noted that this application does not limit the location or initial size of the selection area; these can be set according to actual needs, such as using the center area of ​​the mask layout or a specified target area as a reference to define the selection area. To facilitate the gradual expansion of the optimization area from the mask boundary, in one or more embodiments of this application, a region selection box is defined starting from any corner point of the mask layout, and the area within this selection box is the selection area. Figure 4a As shown, the dashed box 401 is the defined area selection box.

[0049] Secondly, the lowest-level blocks within the selected area are pushed into the optimization queue. For example... Figure 4b As shown in the previous example, when defining the region selection box, each lowest-level block 201 in the selected region is pushed into the optimization queue in sequence. The left figure shows the position distribution of the lowest-level blocks in the selected region in the local area of ​​the mask layout, and the right figure shows the current optimization queue.

[0050] Finally, during the optimization of the extracted graphics within the blocks, this application needs to perform the queue insertion operation of high-level blocks in step S103, and the queue addition operation of other lowest-level blocks besides the lowest-level blocks within the selected area during the delineation. Specifically, the queue addition operation involves expanding the selected area to include adjacent areas if the block to be pushed into the optimization queue is located at the boundary of the selected area and has an optimization relationship with adjacent blocks outside the selected area, and then pushing the newly expanded lowest-level block to the tail of the optimization queue. For example... Figure 4c As shown, the dashed arrows indicate the trend of the optimization queue. In the left-hand graph, the blocks corresponding to the strikethrough characters are optimized blocks, and the blocks corresponding to the unstrikethrough characters are blocks to be optimized in the optimization queue. Following the previous example, after the lowest-level blocks adjacent to the first-level blocks are optimized, the first-level blocks are inserted at the head of the queue. Figure 4dAs shown, following the example above, after optimizing the lowest-level block and the first-level block adjacent to the second-level block, the second-level block 203 is inserted into the head of the queue.

[0051] Continuing with the previous example, when the second second-level block is about to be executed, the selection region expansion is triggered, such as... Figure 4e As shown, the dashed box 402 represents the region selection box after the initial expansion. Figure 4f As shown, after triggering region expansion, the newly enclosed lowest-level block is pushed into the optimization queue. Then, the insertion operation of higher-level blocks continues until the optimization of the adjacent low-level blocks of the second second-level block 403 is completed, at which point the second second-level block is pushed in. Figure 4g As shown, after the optimization of the lowest-level block, the first-level block, and the second-level block adjacent to the highest-level block is completed, the highest-level block is inserted into the head of the queue, and the high-level block insertion operation continues.

[0052] It should be noted that the specific size of the expanded region is not limited in this application and can be set according to actual needs. To avoid distortion of optimization results due to region fragmentation and to ensure the continuity and data integrity of the optimized region, in one or more embodiments of this application, the region selection box can be expanded according to the initial size when the region selection box is defined, so as to include adjacent regions of the same size as the initial size. To make the region expansion size more adaptable to the computing power load of the computing cluster and to avoid overloading the computing pressure of a single node due to excessive region expansion or causing too much cross-regional scheduling due to excessive region expansion, in one or more embodiments of this application, the region expansion size can be determined according to the available computing resources of the computing node and the size of the mask layout. Among them, available computing resources include, but are not limited to, CPU computing power, memory capacity, parallel processing capability, etc.; of course, in this embodiment, the region can also be divided with reference to the graphic distribution density. For example, the graphic density of the mask layout can be detected first, and the graphic proportion, graphic edge density and lithography sensitive graphic distribution at different positions can be statistically analyzed. Smaller division sizes can be set for positions with high graphic density, and larger division sizes can be set for regions with low graphic density and sparse graphic distribution.

[0053] In step S101, in order to ensure the orderliness of mask optimization, in one or more embodiments of this application, the lowest level blocks in the mask layout can be pushed into the optimization queue in a preset processing order.

[0054] It should be noted that this application does not limit the specific content of the preset processing order, which can be set according to actual needs. For example, the preset processing order can be from left to right or from bottom to top. Continuing with the previous example, this application selects the smallest coordinate (bottom and leftmost) in the mask layout as the starting position, and pushes each lowest-level block in the mask layout / region selection box into the optimization queue in the preset processing order.

[0055] Furthermore, in one or more embodiments of this application, the mask layout can be divided into multiple block processing regions, and then the multiple block processing regions can be sorted according to a preset processing order to obtain a processing region sequence; according to the processing region sequence, the lowest-level blocks of each block processing region are pushed into an optimization queue; according to the optimization queue, the graphics within the blocks in the initial processing region are retrieved and optimized.

[0056] It should be noted that this application does not limit the way the processing area is divided into blocks. It can be set according to actual needs, such as dividing according to the functional modules of the mask layout; or dividing according to a fixed grid coordinate range; or dividing according to the difference in graphic density.

[0057] In step S103, in order to accurately trigger the priority scheduling of high-level blocks, in one or more embodiments of this application, when the blocks include the lowest-level blocks, the first-level blocks, the second-level blocks, and the highest-level blocks sorted from low to high, this application can construct an optimized triggering mechanism for high-level blocks, as follows: During the optimization of the extracted graphics within each block, after optimizing each lowest-level block, for each adjacent first-level block, if a block adjacent to the first-level block but with a lower level has already been optimized, the first-level block is inserted at the head of the queue. After optimizing each first-level block, for each adjacent second-level block, if a block adjacent to the second-level block but with a lower level has already been optimized, the second-level block is inserted at the head of the queue. After optimizing each second-level block, for each adjacent highest-level block, if a block adjacent to the highest-level block but with a lower level has already been optimized, the highest-level block is inserted at the head of the queue.

[0058] In this embodiment, in order to achieve accurate scheduling of high-level blocks, ensure the data support required for high-level block optimization, and avoid memory resource occupation caused by global waiting scheduling, this application shortens the waiting time of high-level blocks and improves the overall efficiency of mask optimization through a high-level block queue-jumping mechanism.

[0059] In step S104, in order to refine the granularity of memory release and realize the immediate reclamation of memory resources, in one or more embodiments of this application, this application can release the memory of the block that has an optimization relationship with the highest-level block but no optimization relationship with other blocks to be optimized, as well as the memory of the highest-level block, after each highest-level block optimization is completed.

[0060] It should be noted that this application does not limit the specific method of memory release, which can be set according to actual needs, such as batch release by block level, gradual release by region, and dynamic release triggered by computing node load. In one or more embodiments of this application, memory management can be achieved through block memory status marking and association verification, as follows: First, when each highest-level block is found to be optimized, its memory state is changed to be freeable. This application can pre-set the memory state of each block, initially setting it to be non-freeable. Second, each block with an optimization relationship to the highest-level block is traversed, and it is checked whether the block has an optimization relationship with other highest-level blocks. If not, the memory state of the block is changed to be freeable; otherwise, the memory state of the block remains non-freeable. Finally, the memory occupied by blocks with a freeable memory state is released.

[0061] In this embodiment, compared to the real-time memory release method of this application, the method of releasing memory in batches by block level has obvious drawbacks. Specifically, after all the lowest-level blocks have been optimized, the memory of the lowest-level blocks is released; then, after the first-level block has been optimized, the memory of the first-level block and the lowest-level blocks it depends on are released, and so on. Figure 5a As shown, the method of releasing memory in batches by block level only releases the lower-level blocks it depends on after the highest-level block has been executed. This results in a large backlog of optimized memory blocks that have no optimization relationship with other unoptimized blocks, leading to low memory resource reuse efficiency. This application adopts a real-time memory release method based on optimization relationships, that is, releasing optimized memory blocks that have no optimization relationship with the blocks to be optimized after one or more highest-level blocks have been optimized. Figure 5b As shown, this application achieves instant memory release and rapid reuse by finely identifying the optimized relationships between blocks, avoiding long-term memory accumulation and improving memory resource utilization.

[0062] Based on the above-described mask layout optimization method, this application also provides specific embodiments of a mask layout optimization apparatus.

[0063] like Figure 6 As shown in the figure, a mask layout optimization device 600 provided in this application embodiment includes a partitioning module 601, a queue construction module 602, a queue reading module 603, a queue adjustment module 604, and a memory release module 605.

[0064] The partitioning module 601 is used to partition the mask layout according to the rule that blocks of the same level are not adjacent to each other, so as to obtain multiple blocks of different levels from low to high. Queue building module 602 is used to push at least one lowest-level block into an optimized queue; The queue reading module 603 is used to retrieve blocks according to the optimized queue and perform optimization; The queue adjustment module 604 is used to, during the process of optimizing the graphics within the extracted blocks, insert each block with a level higher than the lowest level block into the head of the optimization queue after optimizing the adjacent blocks with a level lower than the lowest level block. The memory release module 605 is used to release the memory of optimized blocks that have no optimization relationship with other blocks after one or more highest-level blocks have been optimized.

[0065] In some embodiments, the queue construction module described above is specifically used for: defining a selection area in the mask layout; pushing each of the lowest-level blocks in the selection area into the optimization queue; after retrieving blocks according to the optimization queue and optimizing them, the method further includes: during the optimization of the graphics within the retrieved blocks, if the block to be pushed into the optimization queue is located at the boundary of the selection area and has the optimization association relationship with an adjacent block outside the selection area, then the selection area is expanded to add the adjacent area to the selection area, and the newly added lowest-level blocks in the expanded selection area are pushed into the tail of the optimization queue.

[0066] In some embodiments, the queue construction module described above can also be used to: delineate a region selection box starting from any corner of the mask layout, wherein the region within the region selection box is the selection region.

[0067] In some embodiments, the queue construction module described above can also be used to: expand the region selection box according to the initial size when the region selection box is defined, so as to frame adjacent regions of the size corresponding to the initial size.

[0068] In some embodiments, the queue construction module described above can also be used to: sequentially push each of the lowest-level blocks in the mask layout into the optimized queue according to a preset processing order.

[0069] In some embodiments, the queue adjustment module is specifically configured to: the blocks include the lowest-level blocks, first-level blocks, second-level blocks, and the highest-level blocks sorted from low to high; during the optimization of the extracted graphics within the blocks, after each lowest-level block is optimized, for the first-level blocks adjacent to the lowest-level block, if a block adjacent to the first-level block with a lower level has been optimized, then the first-level block is inserted at the head of the queue; after each first-level block is optimized, for the second-level blocks adjacent to the first-level block, if a block adjacent to the second-level block with a lower level has been optimized, then the second-level block is inserted at the head of the queue; after each second-level block is optimized, for the highest-level blocks adjacent to the second-level block, if a block adjacent to the highest-level block with a lower level has been optimized, then the highest-level block is inserted at the head of the queue.

[0070] In some embodiments, the memory release module described above is specifically used for: when it is detected that the optimization of each highest-level block is completed, changing the memory state of the highest-level block from its initial non-released state to releaseable state; traversing each block that has the optimization association with the highest-level block, querying whether the block has the optimization association with the block to be optimized; if not, changing the memory state of the block to releaseable state; if yes, keeping the memory state of the block as non-released state; and releasing the memory occupied by the block whose memory state is releaseable state.

[0071] Based on a mask layout optimization method, this application also provides a specific embodiment of a mask layout optimization device.

[0072] Figure 7 This illustration shows a schematic diagram of the hardware structure of a mask layout optimization device provided in an embodiment of this application.

[0073] The mask layout optimization device may include a processor 701 and a memory 702 storing computer program instructions.

[0074] Specifically, the processor 701 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0075] Memory 702 may include mass storage for data or instructions. For example, and not limitingly, memory 702 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 702 may include removable or non-removable (or fixed) media. Where appropriate, memory 702 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 702 is non-volatile solid-state memory.

[0076] The processor 701 reads and executes computer program instructions stored in the memory 702 to implement any of the mask layout optimization methods in the above embodiments.

[0077] In one example, the electronic device may also include a communication interface 703 and a bus 710. Wherein, as... Figure 7 As shown, the processor 701, memory 702, and communication interface 703 are connected through bus 710 and complete communication with each other.

[0078] The communication interface 703 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0079] Bus 710 includes hardware, software, or both, that couples the components of the electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 710 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0080] Furthermore, in conjunction with the mask layout optimization method described in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the mask layout optimization methods described in the above embodiments.

[0081] In addition, in conjunction with the mask layout optimization method in the above embodiments, this application embodiment can provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device performs a mask layout optimization method as provided in any aspect of the above embodiments of this application.

[0082] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0083] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0084] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0085] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0086] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A mask layout optimization method, characterized in that, include: The mask layout is divided according to the rule that blocks of the same level are not adjacent to each other, resulting in multiple blocks of different levels from low to high. Push at least one lowest-level block into the optimization queue; Extract blocks according to the optimized queue and optimize them accordingly; During the optimization of the extracted graphics within the blocks, for each block whose level is higher than the lowest level block, after optimizing the blocks adjacent to that block whose level is lower than that block, the block is inserted at the head of the optimization queue. After one or more top-level blocks have been optimized, release the memory of the optimized blocks that have no optimization relationship with the blocks to be optimized.

2. The method as described in claim 1, characterized in that, Push at least one lowest-level block into the optimization queue, including: Define a selection area in the mask layout; Divide each of the lowest-level blocks in the selected area and push them into the optimization queue; After retrieving and optimizing the blocks according to the optimized queue, the method further includes: During the optimization of the extracted block graphics, if the block to be pushed into the optimization queue is located at the boundary of the selected area and has the optimization association relationship with the adjacent block outside the selected area, then the selected area is expanded to add the adjacent area to the selected area, and the newly added lowest-level block in the expanded selected area is pushed into the tail of the optimization queue.

3. The method as described in claim 2, characterized in that, Defining a selection area in the mask layout includes: Starting from any corner of the mask pattern, a region selection box is defined, and the area within the region selection box is the selection area.

4. The method as described in claim 3, characterized in that, Expanding the selection area to include adjacent areas includes: Expand the region selection box according to its initial size when it was defined, so as to include adjacent regions of the same size as the initial size.

5. The method as described in claim 1, characterized in that, Push at least one lowest-level block into the optimization queue, including: According to the preset processing order, each of the lowest-level blocks in the mask layout is pushed into the optimization queue in sequence.

6. The method as described in claim 1, characterized in that, The blocks include the lowest-level blocks, the first-level blocks, the second-level blocks, and the highest-level blocks, sorted from low to high. During the optimization of the extracted graphics within a block, for each block with a level higher than the lowest-level block, after optimizing other adjacent blocks with a lower level, the block is inserted at the head of the optimization queue, including: During the process of optimizing the extracted graphics within the blocks, after each lowest-level block is optimized, for the first-level block adjacent to the lowest-level block, if a block adjacent to the first-level block and of a lower level has been optimized, then the first-level block is inserted at the head of the queue. After each first-level block is optimized, for the second-level block adjacent to the first-level block, if the block adjacent to the second-level block and of a lower level has been optimized, then the second-level block is inserted at the head of the queue. After each second-level block is optimized, for the highest-level block adjacent to that second-level block, if a block adjacent to the highest-level block but of a lower level has already been optimized, then the highest-level block is inserted at the head of the queue.

7. The method as described in claim 1, characterized in that, After one or more top-level blocks have been optimized, release the memory of optimized blocks that have no optimization relationship with the blocks to be optimized, including: When it is detected that the optimization of each of the highest-level blocks is completed, the memory state of the highest-level block is changed from the initial non-releasable state to releasable state; Iterate through each block that has the optimization relationship with the highest-level block, and query whether the block has the optimization relationship with the block to be optimized; If not, then the memory state of that block is changed to be freeable; If so, then the memory state of that block remains as non-releasable; Release the memory occupied by the block whose memory status is "releaseable".

8. A computer device, characterized in that, The computer device includes: a memory and a program or instructions stored in the memory and executable on a processor, wherein when the program or instructions are executed by the processor, they implement a mask layout optimization method as provided in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a processor, implement the mask layout optimization method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the mask layout optimization method as described in any one of claims 1-7.

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