Light color computing chip

Abstract

A light-color computation chip, belonging to the field of data computation technology, includes: an instruction scheduling unit, a decoding unit, an optical transmitting unit, an optical receiving unit, a register buffer unit, a pre-stored code library unit, and a computation result integration unit. The optical transmitting unit, optical receiving unit, register buffer unit, and pre-stored code library unit corresponding to the same data bit collectively constitute a single-data-bit computation unit. The instruction scheduling unit receives external instructions and distributes them to the decoding unit, and receives the final computation result and outputs it uniformly. The decoding unit converts the electrical signal instructions issued by the instruction scheduling unit into corresponding bit-specific light-color codes. The optical transmitting unit outputs data light signals of corresponding colors or wavelengths according to the light-color codes. Advantages: It adopts a novel architecture combining direct wavelength encoding and lookup table operations, achieving a simplified, low-latency, and modularly expandable direct computation architecture.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology, and specifically relates to a light and color processing chip. Background Technology

[0002] Current computers and conventional computing chips rely entirely on electrical signals for data transmission and computation. Their underlying mechanism is based on binary electrical signals, requiring repeated splitting, compilation, conversion, and step-by-step calculation through multiple logic gates to complete various computational tasks. In this computing mode, data must undergo continuous splitting, grouping, step-by-step carry-over, and frequent encoding conversions, resulting in cumbersome computational steps, high transmission latency, and severely limiting the chip's computing speed and overall performance.

[0003] Most existing optical computing technologies follow traditional circuit logic, still employing binary decomposition and step-by-step operation modes, failing to break out of the existing framework. Their computational functions are limited, their encoding methods are rigid, their system compatibility is poor, and their architecture is outdated, making it difficult to achieve simple, fast, integrated direct computation.

[0004] At the same time, conventional electrical signal operations require frequent adaptation to conversions and calculations between different number systems, involving repeated splitting and reassembly of data, resulting in high computing power consumption, high computational latency, and complex system structure.

[0005] For a long time, the industry has lacked a chip architecture that can directly represent data for synchronous computation without repeatedly splitting data or requiring multi-level compilation and conversion. To address this, the applicant has developed a useful design, and the technical solution described below arose from this context. Summary of the Invention

[0006] The purpose of this invention is to provide a light and color computing chip that abandons the old computing method of traditional electrical signal splitting and conversion, and adopts a brand-new architecture that combines direct wavelength encoding and lookup table operation to achieve a simple, low-latency, modularly expandable direct computing architecture.

[0007] The objective of this invention is achieved by providing a light-color arithmetic chip, comprising: an instruction scheduling unit, a decoding unit, a light transmitting unit, a light receiving unit, a register buffer unit, a pre-stored code library unit, and an arithmetic result integration unit; wherein, the light transmitting unit, light receiving unit, register buffer unit, and pre-stored code library unit corresponding to the same data bit collectively constitute a single data bit arithmetic unit. The instruction scheduling unit is used to receive external instructions and distribute them to the decoding unit, as well as to receive the final calculation results and output them uniformly. The decoding unit is used to convert the electrical signal command issued by the instruction scheduling unit into data optical color code for the corresponding bit. The light emitting unit is used to output a data light signal of a corresponding color or wavelength according to the data light color encoding; The optical receiving unit is used to receive at least two data optical signals of the same data bit, as well as carry or borrow optical color signals transmitted from the previous optical transmitting unit, and convert each data optical signal into a corresponding electrical signal. The register buffer unit is connected to the output of the optical receiving unit and is used to temporarily store the received signals. After the two local data signals and one carry or borrow signal are all received and aligned, they are then transmitted to the pre-stored code library unit. The pre-stored code library unit stores a lookup table for single data bits, which is used to look up the corresponding operation result and carry or borrow information according to the combination of electrical signals. The pre-stored code library unit receives two color information channels and carry or borrow signals. The three signals are used to perform lookup operations synchronously. When outputting the operation result of this bit, the operation result of this bit carries the address code of this bit and is transmitted to the operation result integration unit. At the same time, the newly generated carry or borrow light color signal is directly transmitted to the light receiving unit corresponding to the previous bit and participates in the operation of the previous bit without going through the instruction scheduling unit. The calculation result integration unit receives the single-bit calculation results output by each single-data-bit calculation unit, distinguishes different bit data by the address code it carries, splices and integrates them according to the preset bit order, and recombines the single-bit results into a standard digital data format according to the data bit width mode specified by the instruction scheduling unit, so as to output the results to external devices for interaction.

[0008] In a specific embodiment of the present invention, the operation lookup table includes an addition, subtraction, multiplication, and division operation lookup table, which is used to call the corresponding result code and carry or borrow information according to the operation type instruction.

[0009] In another specific embodiment of the present invention, the optical receiving unit supports expansion to more than two multi-channel signal processing.

[0010] In another specific embodiment of the present invention, each bit of each single data operation unit adopts the same light color encoding and lookup table rules, and is directly cascaded to the previous operation unit through carry or borrow light color signals to form multi-digit operations of arbitrary length and arbitrary number of bits.

[0011] In another specific embodiment of the present invention, the encoding rule of the single data bit is compatible with binary, octal, decimal, hexadecimal and any custom number system.

[0012] In another specific embodiment of the present invention, the decoding unit can convert multi-digit electrical signal instructions into corresponding state codes required for optical color operations; the decoding unit is also used to convert the operation results into standard electrical signals and send them back to the instruction scheduling unit; the decoding unit does not require clock and timing synchronization control, can adapt to code stream signals input in any way, autonomously complete equal grouping and splitting output, and each output is independently isolated from the others.

[0013] In a further specific embodiment of the present invention, each color of light or each specific wavelength of light output by the light emitting unit uniquely corresponds to a numerical code, realizing a one-to-one mapping between light color and numerical value.

[0014] In a further specific embodiment of the present invention, the optical receiving unit integrates photoelectric conversion function to directly convert multiple optical color signals into electrical signals that match the pre-stored code library unit.

[0015] In yet another specific embodiment of the present invention, the instruction scheduling unit can simultaneously interface with multiple decoding units to realize parallel instruction distribution and result aggregation of multiple computation paths.

[0016] In yet another specific embodiment of the present invention, before the local signal enters the code library to complete the lookup operation, the register buffer unit completes the temporary storage and timing alignment of each signal, and the lookup operation is triggered synchronously after all three signals arrive.

[0017] In subsequent specific embodiments of the present invention, the computational architecture of decoding, optical signal transmission, three-way signal buffer alignment, merge lookup, carry concatenation, and result integration can achieve the same logical computational functions through pure electrical signal encoding and transmission.

[0018] The present invention, by employing the above-described structure, has the following advantages compared to the prior art: Firstly, it uses light color as the data carrier to achieve direct computation: different light colors directly represent the corresponding data signals, and using light color as the data carrier eliminates the need to convert data into binary electrical signals. By uniformly matching, synchronously looking up tables, and performing integrated computation on light color signals, it completely eliminates the cumbersome steps of repeated bit splitting, step-by-step compilation, and back-and-forth base conversion in traditional schemes, and realizes direct computation at the light color level. Secondly, it is compatible with multiple number systems and has strong versatility: This invention is not limited to a fixed single number system, but can simultaneously support binary, hexadecimal, and other multi-number systems. Regardless of the number system format of the input data, it can be directly mapped to the corresponding light color for calculation without additional number system conversion, which significantly improves the versatility and adaptability of the chip. Third, the operation steps are simplified and the latency is extremely low: the overall operation steps are greatly simplified, the transportation path is short and the latency is extremely low. The operation performance is significantly better than that of electronic chips and ordinary optical computing structures, which can effectively meet the stringent requirements of real-time performance and throughput in high-performance computing scenarios. Fourthly, it has a simple structure and can be modularly expanded: the structure is simple and clear, not bound by the traditional circuit operation logic, and each operation unit can be modularly cascaded and expanded as needed to achieve flexible configuration of arbitrary bit width, with good scalability and integration convenience. Attached Figure Description

[0019] Figure 1 This is a structural block diagram of the present invention. Detailed Implementation

[0020] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, the description of the embodiments is not a limitation on the technical solution. Any formal but not substantive changes made based on the concept of the present invention should be considered within the scope of protection of the present invention.

[0021] In the following description, all directional (or orientational) concepts involving up, down, left, right, front, and back refer to the position of the figure being described, and are intended to facilitate public understanding. Therefore, they should not be construed as a special limitation on the technical solution provided by this invention.

[0022] The various modules, device selections, connection methods, data bit widths, packaging forms, and process dimensions described in this invention can be replaced, deleted, expanded, or modified according to actual application scenarios. Any implementation method based on the core concept of optical color coding mapping values, multi-channel signal combination lookup table operations, carry cascade expansion, and silicon-based optical transceiver integration falls within the protection scope of this invention.

[0023] See Figure 1 This chip is implemented using silicon-based photonics integration technology and mainly includes: an instruction scheduling unit, a decoding unit, an optical transmitting unit, an optical receiving unit, a register buffer unit, a pre-stored code library unit, an operation result integration unit, a power management unit, input / output interfaces, and a standard package structure. The optical transmitting unit, optical receiving unit, register buffer unit, and pre-stored code library unit corresponding to the same data bit together constitute a single data bit operation unit. Multiple single data bit operation units are cascaded through carry / borrow to form a complete operation architecture, enabling multi-digit operations of arbitrary length and number of bits.

[0024] The instruction scheduling unit is the core control part of the chip. It can be implemented using a programmable logic array, a dedicated control circuit, a microcontroller core, or other digital logic circuits with instruction parsing and scheduling capabilities. Its core function is to receive, parse, and distribute external instructions to the decoding unit, as well as receive the final calculation results and output them uniformly, providing precise and efficient control support for the parallel operation of the chip. The specific functions are described below.

[0025] Firstly, instruction reception. This unit receives digital instructions from external processors, host computers, or main control devices via parallel or serial high-speed interfaces. Simultaneously, it connects to external clock and synchronization signals. Through clock synchronization and signal verification mechanisms, it ensures the stability and reliability of the digital instruction reception process, preventing instruction loss and errors during transmission, and providing high-quality input signals for subsequent instruction parsing and scheduling. Furthermore, this instruction scheduling unit can simultaneously interface with multiple decoding units, enabling parallel instruction distribution and result aggregation across multiple computation paths, thus improving computational efficiency. Secondly, instruction parsing and decomposition. The received complete instruction is parsed in real time and decomposed into various sub-instructions and information required for operation control. Specifically, this includes: operation type instructions, which specify the type of operation the chip needs to perform, including four selectable types: addition, subtraction, multiplication, and division, providing a basis for the pre-stored code library unit to call the corresponding operation lookup table; data bit width instructions, which select the chip's operation data bit width working mode, specifically 16-bit, 32-bit, or 64-bit modes to adapt to different precision operation requirements; input data information to be operated on, which carries the input data required for chip operation, specifically the encoded information of two or more input data channels, providing the operation data source for the operation unit; and output target instructions, which specify the output location of the operation result (such as internal storage unit, external interface, etc.) and transmission path, ensuring that the operation result can be accurately transmitted to the target terminal.

[0026] Third, instruction scheduling and distribution. Based on the data bit width instruction obtained from instruction parsing, the corresponding processing channels (i.e., the corresponding number of single-data-bit processing units) are automatically allocated to achieve reasonable adaptation of processing resources. The specific channel allocation rules are as follows: When the chip operates in 64-bit mode, it enables 16 parallel processing units to achieve high-speed parallel processing. When the chip operates in 32-bit mode, it enables 8 parallel computing units to achieve a balance between computing speed and resource consumption. When the chip operates in 16-bit mode, it enables 4 sets of parallel computing units, which are suitable for low-precision and low-power computing scenarios.

[0027] After completing the allocation of computing channels, the parsed computing type instructions and the data information to be computed are synchronously distributed to the corresponding allocated computing channels. Through timing control logic, the working timing of the multi-channel parallel computing units is kept consistent to avoid errors in computing results due to timing deviations.

[0028] Fourth, modulation and mapping control. This unit pre-stores the mapping relationship between binary states and optical color codes. According to the preset mapping relationship, each 4-bit binary state combination is mapped to 16 different optical color codes, thereby realizing the accurate conversion of electrical signals to optical color signals. At the same time, the modulation module outputs the corresponding addressing control signal to the pre-stored code library unit inside the chip according to the operation type instruction obtained by instruction parsing. This is used to call the encoded data in the pre-stored code library that matches the current operation type, providing auxiliary support for the operation process. It should be noted that the specific circuit form, control logic details, interface type and parameters of the instruction scheduling unit described in this invention can be replaced or adjusted according to the actual application scenario, as long as it can achieve the above core functions, that is, it does not deviate from the core protection scope of this invention and does not affect the normal implementation of the core solution of this invention.

[0029] The core function of the decoding unit is to convert the electrical signal commands issued by the instruction scheduling unit into corresponding bit-specific optical color codes. Simultaneously, it can convert the calculation results into standard electrical signals and transmit them back to the instruction scheduling unit. Furthermore, this decoding unit can convert multi-bit electrical signal commands into corresponding state codes required for optical color calculations, ensuring accurate correspondence between electrical signals and optical color codes, thus laying the foundation for optical signal transmission. Moreover, the decoding unit is a purely hardware-based, fixed-wire structure, requiring no clock signal. Whether signals are input synchronously in batches or sequentially, it can autonomously complete equal grouping and splitting, with each line independently isolated, preventing issues such as code mixing, out-of-order delivery, or grouping errors. The specific circuit implementation of the decoding unit can utilize high-speed decoders, programmable logic devices, etc., as long as they can achieve the aforementioned electrical signal to optical color code conversion function; any such device can be flexibly replaced.

[0030] In this embodiment, the optical emitting unit employs a 128-micron band micro-optical emitting device to output data optical signals of corresponding colors or wavelengths according to the data optical color encoding. Each color light or each specific wavelength light output by the optical emitting unit uniquely corresponds to a numerical code, achieving a one-to-one mapping between light color and numerical value, ensuring the uniqueness and accuracy of the optical color encoding. The optical receiving unit employs a wavelength division multiplexing receiver, integrated vertically with the optical emitting device on a silicon-based chip, forming a vertically coupled structure. It integrates photoelectric conversion functionality to directly convert multiple optical color signals into electrical signals that match the pre-stored code library unit. Specifically, the optical receiving unit receives at least two data optical signals of the same data bit, as well as carry or borrow optical color signals from the previous optical emitting unit, and converts each data optical signal into a corresponding electrical signal. It also supports expansion to more than two multi-channel signal operations, adapting to multi-input operation scenarios.

[0031] The above-mentioned optoelectronic devices are merely examples and can be replaced with other wavelength and other types of light emitting and receiving devices, as long as they can achieve accurate transmission and photoelectric conversion of light and color signals.

[0032] The aforementioned register buffer unit is used to temporarily store various signals from the received optical transmitting unit (including two electrical signals of the same data bit and carry or borrow signals from the previous bit). Its core function is to temporarily store and align the timing of each signal. After the two local data signals and one carry or borrow signal are all received and aligned, they are then uniformly transmitted to the pre-stored code library unit to trigger subsequent table lookup operations. This avoids calculation errors caused by signal transmission timing deviations and ensures calculation accuracy. The register buffer unit can be implemented using on-chip registers, buffers, or other devices, and its buffer depth and read / write speed can be flexibly adjusted according to actual operational needs.

[0033] The pre-stored code library unit, as the core data support module for chip operation, can be implemented using on-chip read-only memory (ROM), programmable memory array (PROM / EPROM), or other non-volatile memory devices. It pre-stores a single-data-bit operation lookup table, which includes addition, subtraction, multiplication, and division operation lookup tables. It is used to call the corresponding result code and carry or borrow information according to the operation type instruction, which can be quickly called without real-time operation, greatly reducing the operation delay.

[0034] The pre-stored code library unit receives the electrical signals corresponding to the two color information transmitted by the register buffer unit, as well as the carry or borrow electrical signals. The three signals are simultaneously merged and lookup table operations are performed. When outputting the current operation result, the current operation result carries the current address code and is transmitted to the operation result integration unit. At the same time, the newly generated carry or borrow light color signal is directly transmitted to the light receiving unit corresponding to the previous bit to participate in the previous bit operation without going through the instruction scheduling unit. This direct cascading method improves the operation efficiency and simplifies the logic structure.

[0035] It should be noted that each bit of each single data operation unit adopts the same light color encoding and lookup table rules, and is directly cascaded to the previous operation unit through carry or borrow light color signals to form multi-digit operations of arbitrary length and number of bits; and the encoding rules of the single data bit are compatible with binary, octal, decimal, hexadecimal and arbitrary custom number base operations, adapting to the operation requirements of different number bases and improving the versatility of the chip.

[0036] The calculation result integration unit receives the single-bit calculation results output by each single-data-bit calculation unit, distinguishes different bits of data by the address code they carry, and concatenates and integrates them according to a preset bit order (from low bit to high bit or high bit to low bit). According to the data bit width mode specified by the instruction scheduling unit, the single-bit results are recombined into a standard 16-bit, 32-bit, or 64-bit digital data format for outputting the results to external devices for interaction. At the same time, the calculation result integration unit transmits the integrated complete calculation result to the instruction scheduling unit, which outputs it uniformly to complete the entire calculation process.

[0037] Furthermore, the computational architecture described in this invention, which includes decoding, optical signal transmission, three-way signal buffer alignment, merge lookup, carry concatenation, and result integration, can achieve the same logical computational functions through pure electrical signal encoding and transmission. The implementation method can be flexibly selected according to the actual application scenario (such as high-speed requirements or low-cost requirements), and all of these fall within the protection scope of this invention.

[0038] The chip is based on an instruction scheduling unit, and its overall operation process is as follows.

[0039] External signals are uniformly sent to the instruction scheduling unit, which then performs signal parsing, scheduling, and computational control.

[0040] After receiving the operation instruction, the instruction scheduling unit first determines the operation type: if it is a basic addition, subtraction, multiplication, or division operation, it directly issues the corresponding operation instruction and opens the dedicated operation channel; if it is a complex operation such as square root or trigonometric function, the instruction scheduling unit has a built-in complex operation decomposition module that automatically decomposes it into a combination of basic addition, subtraction, multiplication, and division operations, and then issues the basic operation instructions in sequence to open the corresponding channel.

[0041] After receiving the arithmetic instruction, the decoding unit immediately opens the matching dedicated arithmetic channel and waits for data input. Once the channel is open, the instruction scheduling unit sends every four bits of externally input electronic signal to the decoding unit, which converts them into corresponding optical color signals and transmits them to the optical transmitting unit. The optical transmitting unit outputs the corresponding optical color signal; it first transmits the first set of corresponding data optical signals, then the second set of corresponding data optical signals, and simultaneously emits the carry / borrow optical color signals. The three optical signals are simultaneously sent to the optical receiving unit of the corresponding single-data-bit arithmetic unit.

[0042] The optical receiving unit converts the received three optical color signals into electrical signals and transmits them to the register buffer unit. The register buffer unit performs temporary storage and timing alignment of the three signals. After all three signals arrive, they are synchronously transmitted to the pre-stored code library unit for table lookup and matching to obtain the local operation result.

[0043] After the lookup is completed, the result is output in two paths: one path generates a new carry / borrow optical color signal from the pre-stored code library unit and transmits it directly to the optical receiving unit corresponding to the previous bit to participate in the previous bit's calculation; the other path transmits the current bit result along with the address code to the calculation result integration unit. After the complex calculation is completed through multiple basic calculation cycles, the calculation result integration unit sorts and concatenates the results output by all single data bit calculation units using the address code to form a complete calculation result and transmits it to the instruction scheduling unit. The instruction scheduling unit then outputs the final complete calculation result, while the decoding unit converts the calculation result into a standard electrical signal and sends it back to the instruction scheduling unit for verification.

[0044] This invention is uniformly managed by the instruction scheduling unit. Complex operations are automatically broken down into basic addition, subtraction, multiplication, and division operations, reusing existing operation channels and lookup table logic. No new independent operation hardware is required. The chip has high integration and coherent operation logic, taking into account both basic and complex operations. It has high operation efficiency and can be flexibly cascaded to expand the number of bits. At the same time, the timing alignment function of the register cache unit further improves the operation accuracy and stability.

[0045] Furthermore, the chip incorporates an integrated power management module, which features voltage regulation, power consumption adjustment, and overcurrent protection. This module provides a stable and adaptable operating voltage based on the operational requirements of the internal photonic devices and digital circuits, preventing voltage fluctuations from affecting the chip's computational accuracy and signal transmission stability, and ensuring long-term stable operation of the chip.

[0046] The chip's input / output pins include a variety of general-purpose interfaces, including instruction input interface, data output interface, clock signal interface, reset interface, power interface, and ground interface. Each interface conforms to industry-standard specifications, enabling convenient connection with external processors, host computers, and main control devices to meet the needs of instruction transmission, data interaction, and device control.

[0047] The chip adopts standard integrated circuit packaging forms (such as QFP, LQFP, BGA, etc.), and the package size and pin layout conform to industry standards, making it directly compatible with existing mainstream processor systems and circuit board designs, thus reducing the application cost and integration difficulty of the chip. It should be noted that the specific package form, pin definition, and power supply method of the chip can be flexibly adjusted according to the needs of the actual application scenario without affecting the implementation of the core solution of this invention.

[0048] The following is an embodiment of the present invention, which focuses on 64-bit addition operations. Complex operations such as trigonometric functions and square roots are broken down by the instruction scheduling unit into basic addition, subtraction, multiplication, and division operations, and then executed according to the same process as in this embodiment. The execution process of this embodiment includes the following steps.

[0049] The first step is for the instruction scheduling unit to receive and schedule the execution of instructions.

[0050] The external device sends a 64-bit addition operation instruction, along with two complete 64-bit raw operation data channels A and B, to the instruction scheduling unit. Upon receiving the data, if the instruction scheduling unit identifies the operation type as addition, it activates the corresponding addition operation lookup channel and then directly sends both sets of 64-bit data (A and B) to the decoding unit. Simultaneously, the instruction scheduling unit reserves a result receiving port for subsequently receiving and forwarding the final operation result.

[0051] The second step involves the decoding unit performing data processing and optical signal conversion.

[0052] After receiving the 64-bit data from the instruction scheduling unit, the decoding unit divides the 64-bit data into 16 independent data segments of 4 bits each, with each segment corresponding to a numerical code from 0 to 15. In this embodiment, a uniform wavelength interval of 50nm is used to establish the optical color coding correspondence. An exemplary mapping is as follows: 400nm wavelength corresponds to the numerical value 0, 450nm wavelength corresponds to the numerical value 1, and so on, completing the matching and conversion between numerical values ​​and optical wavelengths. After the conversion is complete, the optical emission unit is driven to output an optical signal of the corresponding wavelength.

[0053] The third step is to arrange the signals of the optical receiving unit in a regular pattern.

[0054] The optical receiving unit receives each set of optical signals output by the optical transmitting unit and converts them into standard electrical signals sequentially: first, the A-channel optical signal is converted into a first set of 4-bit electrical signals, and then the B-channel optical signal is converted into a second set of 4-bit electrical signals. Both electrical signals are sent to the corresponding register buffer units, arranged in the order of the first 4 bits of A data and the last 4 bits of B data; the low-order carry signal is synchronously input into the register buffer unit. After the three sets of signals are aligned, they are sent together to the corresponding pre-stored code library unit.

[0055] The fourth step is to define the built-in computation code library specifications and the lookup table operation logic.

[0056] The pre-stored code library unit contains four dedicated code libraries for arithmetic operations. Each code library covers all arithmetic scenarios for 4-bit data. The specific specifications are as follows:

[0057] Taking addition as an example: The data in position A is 8, the data in position B is 9, the initial carry signal is 0, the three sets of signals enter the adder code library to look up the table at the same time. According to the operation rules, 8+9+0=17, the result in position A is 2, and a carry signal 1 is generated at the same time. This carry signal is directly passed to the adjacent previous operation unit to participate in the previous table lookup operation.

[0058] The fifth step is to align the address code with the data integration.

[0059] Each bit's result, along with its own unique address code, is transmitted to the result integration unit. This address code identifies the corresponding number of bits in the data, such as the units, tens, and hundreds digits, ensuring precise data positioning. Subsequent results from all operations are then transmitted with their corresponding address codes. The result integration unit precisely aligns all data according to these address codes, concatenates them to form a complete 64-bit operation data, and then removes all address codes to obtain the pure final result.

[0060] Step 6: Result feedback and final output.

[0061] The complete 64-bit operation result after removing the address code is sent back to the instruction scheduling unit. After verifying that the data is correct, the instruction scheduling unit sends the final operation result to the designated external receiving unit. At this point, the entire 64-bit addition operation process is completed.

[0062] The technical features described in this invention, including but not limited to: the specific implementation of the instruction scheduling unit, the selection of the 128-micron optical emitting device, the configuration of the wavelength division multiplexing receiver, the 16-color optical encoding scheme, the setting of 16 groups of parallel computing units, the combination of data bit widths, the storage type of the pre-stored code library unit, and the chip packaging structure, are all illustrative examples and are not the only implementation of this invention.

[0063] Without departing from the core concept of this invention, those skilled in the art can, according to actual application needs, implement the same technical solution as this embodiment by changing the device type (such as changing the model of the optical transmitter / receiver device or the type of the storage device), adjusting the number of optical color codes, changing the number of parallel processing units, modifying the instruction scheduling logic, adding or removing functional modules, optimizing the circuit structure, etc. All such modifications, substitutions, and extensions should fall within the protection scope of this invention.

Claims

1. A light and color calculation chip, characterized in that, include: The system includes an instruction scheduling unit, a decoding unit, an optical transmission unit, an optical reception unit, a register buffer unit, a pre-stored code library unit, and a result integration unit. The optical transmission unit, optical reception unit, register buffer unit, and pre-stored code library unit corresponding to the same data bit collectively constitute a single data bit arithmetic unit. The instruction scheduling unit is used to receive external instructions and distribute them to the decoding unit, as well as to receive the final calculation results and output them uniformly. The decoding unit is used to convert the electrical signal command issued by the instruction scheduling unit into data optical color code for the corresponding bit. The light emitting unit is used to output a data light signal of a corresponding color or wavelength according to the data light color encoding; The optical receiving unit is used to receive at least two data optical signals of the same data bit, as well as carry or borrow optical color signals transmitted from the previous optical transmitting unit, and convert each data optical signal into a corresponding electrical signal. The register buffer unit is connected to the output of the optical receiving unit and is used to temporarily store the received signals. After the two local data signals and one carry or borrow signal are all received and aligned, they are then transmitted to the pre-stored code library unit. The pre-stored code library unit stores a lookup table for single data bits, which is used to look up the corresponding operation result and carry or borrow information according to the combination of electrical signals. The pre-stored code library unit receives two color information channels and carry or borrow signals. The three signals are used to perform lookup operations synchronously. When outputting the operation result of this bit, the operation result of this bit carries the address code of this bit and is transmitted to the operation result integration unit. At the same time, the newly generated carry or borrow light color signal is directly transmitted to the light receiving unit corresponding to the previous bit and participates in the operation of the previous bit without going through the instruction scheduling unit. The calculation result integration unit receives the single-bit calculation results output by each single-data-bit calculation unit, distinguishes different bit data by the address code it carries, splices and integrates them according to the preset bit order, and recombines the single-bit results into a standard digital data format according to the data bit width mode specified by the instruction scheduling unit, so as to output the results to external devices for interaction.

2. The light and color calculation chip according to claim 1, characterized in that: The operation lookup table includes addition, subtraction, multiplication, and division operation lookup tables, which are used to call the corresponding result code and carry or borrow information according to the operation type instruction.

3. The light and color calculation chip according to claim 1, characterized in that, The optical receiving unit supports expansion to multiple signal processing for two or more channels.

4. The light and color calculation chip according to claim 1, characterized in that, Each bit of each single data processing unit uses the same light color encoding and lookup table rules, and is directly cascaded to the previous processing unit through carry or borrow light color signals to form multi-digit operations of arbitrary length and number of bits.

5. The light and color calculation chip according to claim 4, characterized in that, The encoding rules for a single data bit are compatible with binary, octal, decimal, hexadecimal, and any custom number base operations.

6. The light and color calculation chip according to claim 1, characterized in that, The decoding unit can convert multi-digit electrical signal instructions into corresponding state codes required for optical color operations; the decoding unit is also used to convert the operation results into standard electrical signals and send them back to the instruction scheduling unit; the decoding unit does not require clock and timing synchronization control, can adapt to code stream signals input in any way, and can autonomously complete equal grouping and splitting output, and each output is independent and isolated from each other.

7. The light and color calculation chip according to claim 1, characterized in that, Each color of light or each specific wavelength of light output by the light emitting unit has a unique numerical code, realizing a one-to-one mapping between light color and numerical value.

8. The light and color calculation chip according to claim 1, characterized in that, The optical receiving unit integrates photoelectric conversion function, which is used to directly convert multiple optical color signals into electrical signals that match the pre-stored code library unit.

9. The light and color calculation chip according to claim 1, characterized in that, The instruction scheduling unit can simultaneously interface with multiple decoding units to achieve parallel instruction distribution and result aggregation across multiple computation paths.

10. The light and color calculation chip according to claim 1, characterized in that, Before the local signal enters the code library to complete the lookup operation, the register buffer unit completes the temporary storage and timing alignment of each signal. After all three signals arrive, the lookup operation is triggered synchronously.

11. The light and color calculation chip according to claim 1, characterized in that: The computational architecture, which includes decoding, optical signal transmission, three-way signal buffer alignment, table lookup, carry concatenation, and result integration, can achieve the same logical computational functions through pure electrical signal encoding and transmission.

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