A configurable route distribution SSD master controller command processing method
By introducing the BXM module into the SSD controller for automatic command routing and distribution, the latency and performance bottlenecks of traditional SSD controller command processing methods are solved, achieving low-power, high-performance command processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU XINSHENG INTELLIGENT TECH CO LTD
- Filing Date
- 2026-06-02
- Publication Date
- 2026-06-30
AI Technical Summary
In high-performance, low-power scenarios, traditional SSD controller command processing methods suffer from latency overhead and performance bottlenecks, and increasing CPU resources leads to increased power consumption and cost.
The BXM module is used to implement automatic routing and distribution of master control commands. It includes an interface module, a two-layer routing table, a FIFO queue, and a cross switch. The NVMe controller generates data packets and queries the routing table to determine the target engine. After the target engine performs the operation, it returns to the BXM module, thus completing all operation processes.
It achieves improved performance while reducing power consumption, maintaining processing flexibility and efficiency, and reducing command processing latency.
Smart Images
Figure CN122308751A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a configurable route-distributed SSD controller command processing method. Background Technology
[0002] The traditional approach to sending commands from the host to the edge processor is to hand the commands over to the CPU, which then parses them and distributes them to the corresponding processing engine based on their attributes. This approach can meet the requirements when performance requirements are not high. However, for high-performance, low-power scenarios, the CPU, being the core of the processing, will introduce latency overhead and performance bottlenecks. Adding more CPUs to improve processing power will lead to increased power consumption and costs.
[0003] After receiving commands from the host, the SSD controller typically handles them in two ways. One is to report the command to the SSD software, which processes it, parses the relevant domains, and controls the next steps of other Masters (such as the DMA engine, DDR controller, NAND controller, and even other CPU cores) according to the algorithm. The second is for other Masters to process the received commands according to their algorithms, perform the necessary actions, and then distribute them to the next Master for further processing. In this process, the traditional integration of processing nodes into CPU cores and the connection methods between Masters can lead to significant processing latency and require substantial CPU resources. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a configurable route distribution SSD master control command processing method.
[0005] The objective of this invention is achieved through the following technical solution: a configurable route distribution SSD master control command processing method, comprising the following steps: A BXM module is configured in the SSD controller. The BXM module includes an interface module, a two-layer routing table, a FIFO queue, a processing node, and a cross switch, which are used to realize the automatic routing and distribution of controller commands. The NVMe controller receives the master control command issued by the host and generates a data packet after parsing the master control command. The data packet includes a header and a payload. The header contains an operation reference field and an operation step number field. The data packet is sent to the BXM module. The processing node of the BXM module queries the first layer of the two-layer routing table based on the operation reference field in the packet header to determine the operation index. It then queries the second layer of the routing table in conjunction with the operation step number field to determine the engine index and engine instruction index of the target engine. The BXM module routes data packets to the FIFO queue corresponding to the target engine via a crossbar switch and updates the operation step number field and engine instruction index in the packet header; The target engine executes the corresponding operation according to the engine instruction index, writes the processing result into the payload of the data packet, and then returns the data packet to the BXM module; The routing and processing steps are repeated until all operations are completed and the engine finally terminates processing, and data packets are no longer forwarded.
[0006] Preferably, the two-layer routing table includes: The first-level routing table is used to map to the operation index based on the operation reference field in the packet header; The second-level routing table is used to map the operation index and operation step number field to the engine index and engine instruction index; The last operation index in the second-layer routing table is configured as an error handling operation, and its engine index points to the firmware or CPU responsible for error handling.
[0007] Preferably, the interface module of the BXM module stores data packets through a FIFO queue; the processing node extracts data packets from the FIFO queue and determines the target address by querying a two-layer routing table; the cross switch uses a round-robin arbitration mechanism to route data packets to the target FIFO queue.
[0008] Preferably, the BXM module is integrated into the SSD host SOC and connected to the NVMe controller, buffer manager, FTL accelerator, buffer list controller, firmware service routine and NAND flash controller.
[0009] Preferably, the configuration method of the two-layer routing table includes: Load the two-level routing table directly via register interface; Alternatively, DMA can be triggered via the register interface to load / read the two-level routing table from storage space.
[0010] Preferably, during the routing process, the BXM module increments the operation step number field in the packet header each time it forwards the data packet, and inserts a new engine instruction index according to the two-layer routing table to drive the multi-step operation process.
[0011] Preferably, the BXM module includes 16 processing engines; the two-layer routing table includes 64 operations, each of which contains 32 steps.
[0012] The beneficial effects of this invention are: 1) This invention achieves automatic processing and distribution of host commands through the BXM module, instead of relying on SSD software to control various processes, thereby reducing power consumption, improving performance, and maintaining flexibility. Attached Figure Description
[0013] Figure 1 Here is a diagram of the BXM module architecture; Figure 2 A schematic diagram showing the BXM module integrated into an SSD controller SoC. Figure 3 This represents the intent of a two-layer routing scheme. Detailed Implementation
[0014] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0015] First, some terms in this invention are defined as follows: NVMe: Non-volatile memory host controller interface specification; BXM module: In this invention, it specifically refers to the control engine that performs route distribution; Packet header: The Head field in the routing data structure; FIFO: First-In-First-Out (FIFO) data structure; Routing table: Used to indicate which interface a data packet should be sent out from when it arrives at its destination from this device, and the address of the next hop; NAND: Non-volatile memory.
[0016] See Figures 1-3 This invention provides a technical solution: a configurable route distribution SSD master control command processing method, comprising the following steps: A BXM module is configured in the SSD controller. The BXM module includes an interface module, a two-layer routing table, a FIFO queue, a processing node, and a cross switch, which are used to realize the automatic routing and distribution of controller commands. The NVMe controller receives the master control command issued by the host and generates a data packet after parsing the master control command. The data packet includes a header and a payload. The header contains an operation reference field and an operation step number field. The data packet is sent to the BXM module. The processing node of the BXM module queries the first layer of the two-layer routing table based on the operation reference field in the packet header to determine the operation index. It then queries the second layer of the routing table in conjunction with the operation step number field to determine the engine index and engine instruction index of the target engine. The BXM module routes data packets to the FIFO queue corresponding to the target engine via a crossbar switch and updates the operation step number field and engine instruction index in the packet header; The target engine executes the corresponding operation according to the engine instruction index, writes the processing result into the payload of the data packet, and then returns the data packet to the BXM module; The routing and processing steps are repeated until all operations are completed and the engine finally terminates processing, and data packets are no longer forwarded.
[0017] In this embodiment, the present invention primarily utilizes commands to drive control flow processing within the SOC, based on business characteristics. Combined with software configuration, this allows for logic-based process management similar to that of SSD software, while simultaneously reducing power consumption, improving performance, and maintaining flexibility. Figure 1 As shown, the core of this invention is the BXM module, which automatically processes and distributes host commands, instead of relying on SSD software to control various processes. The BXM interface module is used to route data packets (also called descriptors) between engines. Similar to traditional switches, each data packet contains a header with information needed to query the routing table and engine operation instructions. The BXM interface module includes a two-layer routing table, a FIFO queue, processing nodes, and a crossbar switch. The two-layer routing table can be configured in two ways: directly programmed through the register interface, or loaded / read from storage space via DMA triggered by the register interface. The processing node extracts data packets from the FIFO queue and determines the destination address by querying the routing table. The crossbar switch uses a round-robin arbitration mechanism to ultimately route the data packet to the target FIFO queue. The BXM module of this invention is a command routing architecture that combines software processing flexibility with logical automatic distribution, greatly improving energy efficiency while reducing command processing latency.
[0018] In some embodiments, the two-layer routing table includes: The first-level routing table is used to map to the operation index based on the operation reference field in the packet header; The second-level routing table is used to map the operation index and operation step number field to the engine index and engine instruction index; The last operation index in the second-layer routing table is configured as an error handling operation, and its engine index points to the firmware or CPU responsible for error handling.
[0019] In this embodiment, the routing table has a two-layer structure. The processing node uses the OP_REF field in the packet header to identify the operation index from the first-layer routing table. Then, by combining the operation index and the step index, the engine index and engine instruction index are located. For example... Figure 3 As shown, the engine index eng_idx determines the route destination, while the engine instruction index eng_instr determines the operation performed by the engine. The engine instruction index is similar to the instruction sent to the engine.
[0020] The last operation index is used for error handling. In most applications, the firmware / CPU is responsible for the error handling process. In this case, the user only needs to program the engine index of all entries corresponding to the last operation index in the Layer 2 routing table to the index of the firmware / CPU responsible for error handling. For example, assuming the CPU responsible for error handling is assigned an engine index of 10, then all entries in the OP_N column of the Layer 2 routing table need to be programmed to 10.
[0021] In some embodiments, the interface module of the BXM module stores data packets through a FIFO queue; the processing node extracts data packets from the FIFO queue and determines the target address by querying a two-layer routing table; the cross switch uses a round-robin arbitration mechanism to route data packets to the target FIFO queue.
[0022] In this embodiment, the data structure of the data packet is shown in Table 1, and the packet header contains 6 main data fields: Table 1 Data Packet Structure Table
[0023] In some embodiments, the BXM module is integrated into the SSD host SOC and connected to the NVMe controller, buffer manager, FTL accelerator, buffer list controller, firmware service routine, and NAND flash controller.
[0024] In this embodiment, the workflow is as follows: 1. The NVMe controller receives NVMe commands from the host through the PCIe controller (i.e., the PCIe control module). After analyzing and parsing the command, the NVMe controller generates a data packet (with STEP=6'b0 in the header and the corresponding OP_REF[10:0] set), and then forwards the data packet to the BXM module.
[0025] 2. After receiving a data packet, the BXM module queries the routing table to determine the next processing engine, for example, assuming it is BM (Buffer Manager). The BXM module increments the STEP value in the packet header by 1, inserts the engine instruction index, and then forwards the data packet to BM.
[0026] 3. After receiving the data packet, BM begins executing the operation specified by the engine instruction index. Once the operation is complete, BM writes the necessary information into the data packet payload and then forwards the data packet back to the BXM module (with the packet header remaining unchanged).
[0027] 4. After receiving the data packet, the BXM module queries the routing table to determine the next processing engine, for example, the FTL accelerator. The BMX module increments the STEP value in the packet header by 1, inserts the engine instruction index, and then forwards the data packet to the FTL accelerator.
[0028] 5. After receiving the data packet, the FTL accelerator begins executing the operation specified by the engine instruction index. Once the operation is complete, it writes the necessary information into the data packet payload and then forwards the data packet back to the BXM module (with the packet header remaining unchanged).
[0029] 6. After receiving the data packet, the BXM module queries the routing table to determine that the next processing engine is the buffer list controller. The BXM module increments the STEP value in the packet header by 1, inserts the engine instruction index, and then forwards the data packet to the buffer list controller.
[0030] 7. After receiving the data packet, the buffer list controller begins executing the operation specified by the engine instruction index. Once the operation is complete, it writes the necessary information into the data packet payload and then forwards the data packet back to the BXM module (with the packet header remaining unchanged).
[0031] 8. After receiving the data packet, the BXM module queries the routing table to determine that the next processing engine is the firmware service routine. The BXM module increments the STEP value in the packet header by 1, inserts it into the engine instruction index, and then forwards the data packet to the firmware service routine.
[0032] 9. The firmware service routine sends a read command to the NAND flash memory controller to perform a read operation. If a read exception occurs, the firmware service routine must handle it accordingly.
[0033] 10. After the NAND flash controller completes the read operation, the firmware service routine sends a data packet with the configured payload back to the BXM module.
[0034] 11. After receiving the data packet, the BXM module queries the routing table to determine that the next processing engine is BM. The BXM module increments the STEP value in the packet header by 1, inserts the engine instruction index, and then forwards the data packet to BM.
[0035] 12. After receiving the data packet, BM begins executing the operation specified by the engine instruction index. Once the operation is complete, it writes the necessary information into the data packet payload and then forwards the data packet back to the BXM module (with the packet header remaining unchanged).
[0036] 13. After receiving the data packet, the BXM module queries the routing table to determine that the next processing engine is the NVMe controller. The BXM module increments the STEP value in the packet header by 1, inserts the engine instruction index, and then forwards the data packet to the NVMe controller.
[0037] 14. After receiving the data packet, the NVMe controller begins executing the operation specified by the engine instruction index. Once the operation is complete, the data packet terminates the process and is no longer forwarded.
[0038] In some embodiments, the configuration method of the two-layer routing table includes: Load the two-level routing table directly via register interface; Alternatively, DMA can be triggered via the register interface to load / read the two-level routing table from storage space.
[0039] In some embodiments, during the routing process, the BXM module increments the operation step number field in the packet header each time it forwards the data packet, and inserts a new engine instruction index according to the two-layer routing table to drive the multi-step operation process.
[0040] In some embodiments, the BXM module includes 16 processing engines; the two-layer routing table includes 64 operations, each containing 32 steps.
[0041] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A configurable route-distributed SSD master control command processing method, characterized in that: Includes the following steps: A BXM module is configured in the SSD controller. The BXM module includes an interface module, a two-layer routing table, a FIFO queue, a processing node, and a cross switch, which are used to realize the automatic routing and distribution of controller commands. The NVMe controller receives the master control command issued by the host and generates a data packet after parsing the master control command. The data packet includes a header and a payload. The header contains an operation reference field and an operation step number field. The data packet is sent to the BXM module. The processing node of the BXM module queries the first layer of the two-layer routing table based on the operation reference field in the packet header to determine the operation index. It then queries the second layer of the routing table in conjunction with the operation step number field to determine the engine index and engine instruction index of the target engine. The BXM module routes data packets to the FIFO queue corresponding to the target engine via a crossbar switch and updates the operation step number field and engine instruction index in the packet header; The target engine executes the corresponding operation according to the engine instruction index, writes the processing result into the payload of the data packet, and then returns the data packet to the BXM module; The routing and processing steps are repeated until all operations are completed and the engine finally terminates processing, and data packets are no longer forwarded.
2. The SSD master control command processing method with configurable route distribution according to claim 1, characterized in that: The two-layer routing table includes: The first-level routing table is used to map to the operation index based on the operation reference field in the packet header; The second-level routing table is used to map the operation index and operation step number field to the engine index and engine instruction index; The last operation index in the second-layer routing table is configured as an error handling operation, and its engine index points to the firmware or CPU responsible for error handling.
3. The SSD master control command processing method with configurable route distribution according to claim 1, characterized in that: The interface module of the BXM module stores data packets through a FIFO queue; the processing node extracts data packets from the FIFO queue and determines the target address by querying a two-layer routing table; the cross switch uses a round-robin arbitration mechanism to route data packets to the target FIFO queue.
4. The SSD master control command processing method with configurable route distribution according to claim 1, characterized in that: The BXM module is integrated into the SSD controller SoC and connects to the NVMe controller, buffer manager, FTL accelerator, buffer list controller, firmware service routines, and NAND flash controller.
5. The SSD master control command processing method with configurable route distribution according to claim 1, characterized in that: The configuration methods for the two-layer routing table include: Load the two-level routing table directly via register interface; Alternatively, DMA can be triggered via the register interface to load / read the two-level routing table from storage space.
6. The SSD master control command processing method with configurable route distribution according to claim 1, characterized in that: During the routing process, the BXM module increments the operation step number field in the packet header each time it forwards the data packet, and inserts a new engine instruction index according to the two-layer routing table to drive the multi-step operation process.
7. The SSD master control command processing method with configurable route distribution according to any one of claims 1-6, characterized in that: The BXM module includes 16 processing engines; the two-layer routing table includes 64 operations, each containing 32 steps.