Storage task scheduling method and device, storage medium and electronic device

Abstract

This application discloses a method and apparatus for scheduling storage tasks, a storage medium, and an electronic device, relating to the field of computers. The method includes: acquiring a sequence of storage tasks when the processor is in an idle state; detecting the target execution parameters of each storage task in the storage task sequence under the current target device state of the memory; extracting storage tasks from the storage task sequence based on the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a set of target tasks. The resource parameters may indicate the remaining free resources of the processor, and the expected consumption of free resources by the memory to execute the set of target tasks under the target device state is less than or equal to the remaining free resources indicated by the resource parameters; and controlling the memory to use the remaining free resources indicated by the resource parameters to execute the set of target tasks. This application solves the problem of increased system response latency due to insufficient flexibility in storage task scheduling in related technologies.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method and apparatus for scheduling storage tasks, a storage medium, and an electronic device. Background Technology

[0002] In related technologies, when a storage controller in a storage device performs background maintenance operations, it typically controls the memory to execute storage tasks such as garbage collection and cache refresh in a preset order when the device is idle. However, the above scheduling method only focuses on the timing and order of storage task control, and has limited ability to adjust the scheduling during task execution. Since some storage tasks are uninterruptible operations, once started, they must continue to execute until completion; otherwise, errors such as data inconsistency or physical block corruption may occur. When a high-priority request is received during the execution of the above uninterruptible tasks, it is usually necessary to wait for the current storage task to finish before responding, which can easily lead to priority inversion and business blocking issues, resulting in increased system response latency.

[0003] Therefore, no effective solution has yet been proposed to address the problem of insufficient flexibility in storage task scheduling leading to increased system response latency in related technologies. Summary of the Invention

[0004] This application provides a method and apparatus for scheduling storage tasks, a storage medium, and an electronic device to at least solve the problems in the related art, such as insufficient flexibility in storage task scheduling leading to increased system response latency.

[0005] According to one embodiment of this application, a method for scheduling storage tasks is provided, comprising: when the processor is in an idle state, acquiring a storage task sequence, wherein the storage task sequence includes multiple storage tasks having an execution order, the multiple storage tasks being tasks to be executed by a memory connected to the processor when the processor is in an idle state; detecting target execution parameters of each storage task in the storage task sequence under the current target device state of the memory, wherein the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory in executing the corresponding storage task; extracting storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set, wherein the resource parameters are used to indicate the remaining idle resources of the processor, and the idle resources expected to be consumed by the memory in the target device state in executing the target task set are less than or equal to the remaining idle resources indicated by the resource parameters; and controlling the memory to execute the target task set using the remaining idle resources indicated by the resource parameters.

[0006] In an exemplary embodiment, extracting storage tasks from a storage task sequence based on processor resource parameters and target execution parameters corresponding to each storage task to obtain a target task set includes: detecting whether the target execution parameters corresponding to each storage task are consistent; if the target execution parameters corresponding to each storage task are consistent, calculating a scale parameter based on the resource parameters and the target execution parameters corresponding to any storage task; extracting storage tasks matching the scale parameter from the storage task sequence to obtain a target task set, wherein the scale parameter is used to indicate the number of storage tasks that the remaining free resources of the processor allow the memory to execute; if the target execution parameters corresponding to each storage task are inconsistent, combining the storage tasks in the storage task sequence to obtain multiple reference task sets, wherein each reference task set includes at least one storage task; calculating a reference set parameter for each reference task set based on the target execution parameters corresponding to the storage tasks included in each reference task set, wherein the reference set parameter is used to indicate the processor's free resources expected to be consumed by the memory to execute the corresponding reference task set; and filtering from the multiple reference task sets to select a target task set whose free resources indicated by the reference set parameter are less than or equal to the remaining free resources indicated by the resource parameters.

[0007] In an exemplary embodiment, calculating the scale parameter based on resource parameters and target execution parameters corresponding to any storage task includes: obtaining a reference idle parameter and a candidate idle parameter of the processor, wherein the reference idle parameter is used to indicate the total idle resources of the processor, and the candidate idle parameter is used to indicate the idle resources consumed by the processor when it exits the idle state; calculating the parameter difference between the reference idle parameter and the candidate idle parameter to obtain the resource parameter; and calculating the scale parameter based on the resource parameter and the target execution parameter corresponding to any storage task.

[0008] In one exemplary embodiment, calculating the scale parameter based on the resource parameters and the target execution parameters corresponding to any storage task includes: calculating the scale parameter using the following formula: ;in, For resource parameters, For any storage task, the target execution parameters are... This is the ratio of resource parameters to the target execution parameters corresponding to any storage task. It is the largest integer less than or equal to the ratio of the parameters.

[0009] In an exemplary embodiment, detecting the target execution parameters of each storage task in the storage task sequence under the current target device state of the memory includes: obtaining reference execution parameters of each storage task when the memory is in a healthy state, and detecting the current device state of the memory based on the target operating parameters of the memory to obtain the target device state, wherein the target operating parameters are used to indicate the cumulative number of erase / write operations of the memory, and the higher the cumulative number of erase / write operations indicated by the target operating parameters, the lower the health level indicated by the target device state; and calculating the target execution parameters of each storage task based on the target device state and the reference execution parameters of each storage task.

[0010] In an exemplary embodiment, calculating the target execution parameters of each storage task based on the target device state and the reference execution parameters of each storage task includes: extracting the target attenuation parameter corresponding to the target device state from the corresponding device states and attenuation parameters, wherein the target attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state, and the lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the target attenuation parameter; and using the target attenuation parameter to correct the reference execution parameters of each storage task to obtain the target execution parameters of each storage task.

[0011] In an exemplary embodiment, after controlling the memory to execute the target task set using the remaining free resources indicated by the resource parameters, the method further includes: obtaining candidate set parameters of the target task set, and calculating target set parameters of the target task set according to the target execution parameters corresponding to the storage tasks included in the target task set, wherein the candidate set parameters are used to indicate the actual free resources of the processor consumed by the memory in executing the target task set, and the target set parameters are used to indicate the expected free resources of the processor consumed by the memory in executing the target task set; calculating a deviation parameter between the candidate set parameters and the target set parameters, wherein the deviation parameter is used to indicate the degree of deviation between the candidate set parameters and the target set parameters; and correcting the target attenuation parameter corresponding to the target device state according to the deviation parameter to obtain a target device state and candidate attenuation parameters with a corresponding relationship, wherein the candidate attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state, and the lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the candidate attenuation parameter.

[0012] According to another embodiment of the present application, a storage task scheduling device is also provided, comprising: a first acquisition module, configured to acquire a storage task sequence when the processor is in an idle state, wherein the storage task sequence includes multiple storage tasks having an execution order, and the multiple storage tasks are tasks to be executed by the memory connected to the processor when the processor is in an idle state; a detection module, configured to detect the target execution parameters of each storage task in the storage task sequence under the target device state of the memory, wherein the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory in executing the corresponding storage task; an extraction module, configured to extract storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set, wherein the resource parameters are used to indicate the remaining idle resources of the processor, and the idle resources expected to be consumed by the memory in the target device state in executing the target task set are less than or equal to the remaining idle resources indicated by the resource parameters; and a control module, configured to control the memory to execute the target task set using the remaining idle resources indicated by the resource parameters.

[0013] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to execute the scheduling method of the above-described storage task at runtime.

[0014] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above-mentioned scheduling method for the storage task through the computer program.

[0015] According to another aspect of the embodiments of this application, a computer program product is also provided, including a computer program, wherein the computer program is executed by a processor using the above-described storage task scheduling method.

[0016] In this embodiment, a dynamic scheduling method for storage tasks based on memory health status and available processor resources is adopted. By acquiring a sequence of storage tasks when the processor is idle, and detecting the target execution parameters of each storage task in the current target device state of the memory, the expected consumption of idle processor resources by each storage task can be accurately assessed based on the memory health level indicated by the target device state. Furthermore, by extracting storage tasks from the sequence based on the processor's resource parameters and the target execution parameters corresponding to each storage task, a target task set is obtained. The memory is then controlled to execute this target task set using the remaining idle resources indicated by the resource parameters, achieving a precise match between the storage task execution scale and the remaining idle processor resources. This method ensures that the expected consumption of idle resources by the memory to execute the target task set in the target device state is less than or equal to the remaining idle processor resources. This effectively prevents uninterruptible storage tasks from occupying more than the currently available idle resources, overcoming the shortcomings of related technologies where insufficient storage task scheduling flexibility leads to difficulty in responding to other requests in a timely manner. Ultimately, this achieves the technical effect of improving storage task scheduling flexibility and significantly reducing system response latency. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a hardware structure block diagram of a terminal device for a storage task scheduling method according to an embodiment of this application;

[0020] Figure 2 This is a flowchart of a storage task scheduling method according to an embodiment of this application;

[0021] Figure 3 This is a flowchart of a storage task scheduling method according to an optional embodiment of this application;

[0022] Figure 4 This is a structural block diagram of a storage task scheduling device according to an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] The methods and embodiments provided in this application can be run on terminal devices or computer terminals. Taking running on a terminal device as an example, Figure 1 This is a hardware structure block diagram of a terminal device for a storage task scheduling method according to an embodiment of this application. For example... Figure 1 As shown, the terminal device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a processing system such as a microprocessor unit (MPU), central processing unit (CPU), or programmable logic device (PLD)), a storage controller 104 for performing low-level storage management and control, and a memory 106 for storing data (such as a NAND flash memory chip array inside a universal flash storage (UFS) or embedded multi-media card (eMMC)). In one exemplary embodiment, the terminal device may further include a transmission device 108 for communication functions and an input / output device 110. Those skilled in the art will understand that... Figure 1The structure shown is for illustrative purposes only and does not limit the structure of the terminal device described above. For example, the terminal device may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The configurations shown are equivalent or different.

[0026] The read-only memory area or memory 106 inside the storage controller 104 can be used to store computer programs, such as firmware programs and modules of the Flash Translation Layer (FTL), such as the computer program corresponding to the storage task scheduling method in the embodiments of this application. The storage controller 104, as the hardware carrier and execution body of the FTL algorithm, runs the aforementioned computer program to trigger and run various background maintenance operations (such as garbage collection, cache refresh, and other storage tasks with execution order) when the processor 102 is in an idle state with no instructions issued, thus implementing the aforementioned scheduling method. During this process, the storage controller 104 obtains the resource parameters of the processor 102 and detects the health status of the memory 106, thereby accurately assessing the idle resources of the processor 102 expected to be consumed by the memory 106 in executing storage tasks under the current health status. Furthermore, the storage controller 104 elastically schedules and extracts storage tasks sent to the memory 106 based on available resources to ensure that when the terminal device generates high-priority data requests, the overall system will not experience response blockage due to the continuous execution of uninterrupted storage tasks at the underlying level.

[0027] This embodiment provides a method for scheduling storage tasks, applied in the aforementioned terminal device. Figure 2 This is a flowchart of a storage task scheduling method according to an embodiment of this application, the process including the following steps:

[0028] Step S202: When the processor is in an idle state, obtain a storage task sequence, wherein the storage task sequence includes multiple storage tasks with an execution order, and the multiple storage tasks are tasks that the memory connected to the processor is waiting to be executed when the processor is in an idle state.

[0029] Optionally, in this embodiment, the processor may be, but is not limited to, the main control chip of the terminal device; the storage controller may be, but is not limited to, the underlying control chip where the FTL resides; and the memory may be, but is not limited to, a physical medium composed of multiple NAND flash memory chips. The processor being in an idle state may be, but is not limited to, a state where the processor has not received read / write instructions from the host, or a state where the terminal device is in standby mode with the screen off. It should be noted that the idle state is not limited to the processor having no instructions or actions at all, but rather refers to the processor not currently processing high-priority or external business-level read / write requests, and having the conditions to process underlying background storage tasks.

[0030] Optionally, in this embodiment, the storage tasks included in the storage task sequence may be, but are not limited to, garbage collection tasks, wear leveling tasks, or cache refresh tasks. The storage controller can acquire the storage task sequence when the processor is in an idle state in several ways. For example, the storage controller receives a sleep level signal sent by the processor via a hardware interrupt pin to confirm that the processor has entered an idle state, and then scans the internal task scheduling queue to generate a storage task sequence according to a first-in-first-out principle. Another example is that the storage controller continuously listens on the communication bus; if it does not receive a host read / write command from the processor within a preset time threshold (e.g., 5 milliseconds), it determines that the processor is in an idle state, and then sorts the background maintenance operations according to the urgency score of the garbage collection algorithm to generate a storage task sequence with execution order. Yet another example is that the storage controller receives an idle hint instruction (IdleHint) issued by the processor via the general flash memory storage protocol, passively senses the idle state, and packages the background storage tasks to be processed to generate a storage task sequence.

[0031] Step S204: Detect the target execution parameters of each storage task in the storage task sequence under the current target device state of the memory. The target device state is used to indicate the health status of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory in executing the corresponding storage task.

[0032] Optionally, in this embodiment, the target device status can be, but is not limited to, a health rating determined based on erase / write cycles, usage duration, or bad block ratio. Target execution parameters and resource parameters can be, but are not limited to, occupied time, occupied clock cycles, or occupied bus bandwidth. It should be noted that resource "consumption" refers not only to the utilization of processor computing power, but also, in a storage architecture, to the consumption of time windows or bus data transfer bandwidth.

[0033] Optionally, in this embodiment, the process of the storage controller detecting the target execution parameters can be implemented in various ways. For example, the storage controller reads the usage duration and bad block ratio recorded in the underlying registers of the memory through the internal serial peripheral interface, comprehensively evaluates the health rating of the memory based on the above information, and determines the health rating as the target device state; then, based on the target device state, it calculates the estimated time (the unit can be, but is not limited to, microseconds) to execute each storage task, thus obtaining the target execution parameters. Another example is that the storage controller directly reads the wear leveling table maintained in the static random access memory, extracts the cumulative erase count of the current physical block, and evaluates the current health rating of the memory as the target device state based on the preset interval in which the cumulative erase count is located; then, the storage controller calls a preset aging penalty function to map the standard time of the storage task to the actual number of clock cycles corresponding to the current target device state, thus using this as the target execution parameter.

[0034] Step S206: Extract storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set. The resource parameters are used to indicate the remaining free resources of the processor. The free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters.

[0035] It is important to note that the total resources expected to be consumed by the target task set are strictly less than or equal to the remaining free resources, in order to prevent uninterruptible storage tasks at the underlying level from overstepping their limits and occupying the response time window of normal business operations.

[0036] Optionally, in this embodiment, the storage controller obtains the number of available clock cycles or time margin remaining in the processor's current idle state as a resource parameter. Extracting storage tasks from the storage task sequence can be achieved, but is not limited to, in the following ways: For example, comparing the resource parameters with each target execution parameter; sequentially extracting storage tasks from the storage task sequence according to their execution order until the total expected consumption of idle resources corresponding to the extracted storage tasks reaches the threshold boundary indicated by the resource parameters, and then forming a target task set from the extracted storage tasks.

[0037] Step S208: Control the memory to use the remaining free resources indicated by the resource parameters to execute the target task set.

[0038] Optionally, in this embodiment, the process of controlling the memory to execute the target task set can be implemented, but is not limited to, by the following means: the memory controller converts the target task set into a low-level instruction stream conforming to the physical layer interface protocol, and sends it to the memory via the data bus to complete physical erasure and write. After the task is completed, the memory controller can also, but is not limited to, update the logical-physical mapping table of the flash memory translation layer, and return a status report to the processor via the host interface, so that the processor can seamlessly connect to subsequent read and write operations when exiting the idle state.

[0039] The embodiments provided in this application, when the processor is in an idle state, acquire a sequence of storage tasks consisting of multiple storage tasks with an execution order; detect the target execution parameters of each storage task in the target device state indicating the health level of the memory; extract storage tasks based on resource parameters indicating the remaining idle resources of the processor and the aforementioned target execution parameters, obtaining a set of target tasks whose expected consumption of idle resources is less than or equal to the remaining idle resources; and control the memory to use the remaining idle resources to execute the set of target tasks. This scheduling mechanism can solve the technical problem in related technologies where insufficient flexibility in storage task scheduling leads to unexpected execution time of uninterrupted storage tasks, causing priority inversion and service blocking, resulting in increased system response latency; it achieves precise dynamic matching between the execution scale of storage tasks and the remaining available resources of the processor, ensuring that uninterrupted storage tasks can be safely and completely executed within the current idle period, improving the flexibility of underlying storage task scheduling, and thus significantly reducing the overall system response latency.

[0040] As an optional approach, the target execution parameters of each storage task in the storage task sequence are detected under the current target device state of the memory. This includes: obtaining reference execution parameters of each storage task when the memory is in a healthy state, and detecting the current device state of the memory based on the target running parameters of the memory to obtain the target device state. The target running parameters are used to indicate the cumulative number of erase / write cycles of the memory. The higher the cumulative number of erase / write cycles indicated by the target running parameters, the lower the health level indicated by the target device state. The target execution parameters of each storage task are calculated based on the target device state and the reference execution parameters of each storage task.

[0041] Optionally, in this embodiment, the reference execution parameters may be, but are not limited to, the baseline time or baseline duty cycle required for the memory to perform a standard storage task in its initial factory state, brand new state, or zero-erase / write state. The target operating parameters may be, but are not limited to, the cumulative block erase count or the number of programming and erasing cycles of the memory.

[0042] Optionally, in this embodiment, the storage controller may obtain the reference execution parameters and target operating parameters through, but is not limited to, the following methods. For example, the storage controller reads the factory-preset baseline physical page programming time (e.g., 500 microseconds) from the flash read-only memory area and uses it as the reference execution parameter indicating that the memory is in a healthy state; simultaneously, the storage controller reads the total number of times the physical block has been erased recorded in the flash translation layer mapping table and uses this total number as the target operating parameter (the unit may be, but is not limited to, times). As another example, during the system initialization phase, the storage controller obtains the basic read / write clock cycle of the memory at the current operating voltage and temperature as the reference execution parameter by sending a low-level query command, and obtains the recently updated block erase / write frequency index as the target operating parameter by querying the wear leveling log maintained internally by the firmware.

[0043] Optionally, in this embodiment, the storage controller can compare the target operating parameters with multiple preset wear thresholds to detect the current target device state of the storage. For example, if the target operating parameters are between 0 and 3000, the target device state is determined to be a first state with high health; if the target operating parameters are greater than 3000 and less than or equal to 5000, the target device state is determined to be a second state with medium health; if the parameters are greater than 5000, the target device state is determined to be a third state with low health. The storage controller can also input the target operating parameters into a preset health assessment algorithm within the firmware, outputting a health score between 0 and 100, and determining the interval level corresponding to this score as the target device state.

[0044] Optionally, in this embodiment, the storage controller can, based on the determined target device state, call the corresponding penalty weight or conversion coefficient to perform weighted calculation or mapping operation on the reference execution parameters, and output the calculation result as the target execution parameters. For example, when the target device state is the aforementioned low health level third state, the storage controller calls a penalty weight greater than 1 (such as 1.2) to multiply with the reference execution parameters (such as 500 microseconds) to obtain the increased value (600 microseconds), and determines this 600 microseconds as the final target execution parameter of the storage task.

[0045] It is important to note that the higher the cumulative number of erase / write cycles in the physical medium (such as a NAND flash memory array), the greater the wear and tear on the underlying physical structure, such as the insulating oxide layer. This leads to slower charge / discharge processes or a significantly increased probability of triggering internal retry mechanisms. Therefore, when the health level decreases, the time required for the memory to complete the same type of storage task will increase accordingly, or the bus time window occupied will increase. The embodiments provided in this application can solve the technical problem in related technologies where a fixed standard time is used to evaluate task time consumption, failing to consider the actual execution time extension caused by the physical aging of the storage medium, thus leading to scheduling timeouts and blocking of normal system services. This further improves the accuracy and reliability of resource evaluation during task scheduling.

[0046] As an optional approach, the target execution parameters of each storage task are calculated based on the target device state and the reference execution parameters of each storage task. This includes: extracting the target attenuation parameter corresponding to the target device state from the corresponding device states and attenuation parameters, wherein the target attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state. The lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the target attenuation parameter; and using the target attenuation parameter to correct the reference execution parameters of each storage task to obtain the target execution parameters of each storage task.

[0047] Optionally, in this embodiment, the attenuation parameter is used to characterize the performance degradation of the memory under different device states. The corresponding device states and attenuation parameters can be, but are not limited to, a one-dimensional lookup table, a correspondence curve, or key-value pairs stored in the static random access memory. The target attenuation parameter can be, but is not limited to, a dimensionless percentage coefficient or a multiplier coefficient used to characterize the increase in read / write latency. The higher the performance degradation, the greater the increase in latency indicated by the target attenuation parameter. It should be noted that the aforementioned corresponding lookup table or attenuation curve can be obtained by batch testing and calibration of memory chips in the same batch at different wear and aging stages at the time of manufacture.

[0048] Optionally, in this embodiment, the storage controller can extract the target attenuation parameter that matches the target device state in the following ways, but not limited to: For example, the storage controller uses the evaluated target device state (such as the third state) as the index address, performs memory addressing in a one-dimensional lookup table maintained within the firmware, and directly reads the corresponding target attenuation parameter (such as a constant value of 1.15 or a percentage of 115%).

[0049] Optionally, in this embodiment, when the attenuation parameter is a multiplier, the storage controller can use a hardware multiplier to multiply the reference execution parameter by the target attenuation parameter to obtain the target execution parameter (e.g., multiplying 500 microseconds by 1.15 to obtain 575 microseconds). When the attenuation parameter is an offset constant, the storage controller can use an addition instruction to add the offset to the reference execution parameter (e.g., adding 50 microseconds to 50 microseconds to obtain 550 microseconds).

[0050] The embodiments provided in this application can solve the technical problem in the related art where the nonlinear performance degradation of memory due to physical wear and tear leads to low accuracy of estimated execution time. By using table lookup or simple algebraic operations combined with the factory-calibrated attenuation parameters for rapid correction, not only is the computational overhead of the underlying controller greatly reduced, but the final calculated target execution parameters can also closely match the actual performance degradation of memory devices at different aging stages, further ensuring the timeliness of the scheduling system's response throughout the entire device lifecycle.

[0051] As an optional approach, storage tasks are extracted from the storage task sequence based on the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set. This includes: detecting whether the target execution parameters corresponding to each storage task are consistent; if the target execution parameters corresponding to each storage task are consistent, calculating a scale parameter based on the resource parameters and the target execution parameters corresponding to any storage task; extracting storage tasks matching the scale parameter from the storage task sequence to obtain a target task set, wherein the scale parameter indicates the number of storage tasks that the processor's remaining free resources allow the memory to execute; if the target execution parameters corresponding to each storage task are inconsistent, combining the storage tasks in the storage task sequence to obtain multiple reference task sets, wherein each reference task set includes at least one storage task; calculating a reference set parameter for each reference task set based on the target execution parameters corresponding to the storage tasks included in each reference task set, wherein the reference set parameter indicates the processor's free resources expected to be consumed by the memory to execute the corresponding reference task set; and selecting a target task set from the multiple reference task sets where the free resources indicated by the reference set parameter are less than or equal to the remaining free resources indicated by the resource parameters.

[0052] Optionally, in this embodiment, there are multiple ways to detect whether the execution parameters of each target are consistent. For example, the storage controller traverses the storage task sequence and calculates the variance of the target execution parameters of each storage task. If the variance is 0, the target execution parameters are considered consistent; otherwise, they are considered inconsistent. Another example is that the storage controller compares the maximum and minimum values ​​of the target execution parameters, and determines consistency when the difference is less than a preset tolerance range (e.g., 1 microsecond). The aforementioned situation of consistent target execution parameters typically occurs when the storage task sequence consists entirely of atomic operations of the same type, such as flash memory page read tasks of a fixed size (e.g., 4 kilobytes) or background erase tasks of the same block.

[0053] Optionally, in this embodiment, the scale parameter may be, but is not limited to, the number of tasks allowed to be executed, the number of data blocks, or the number of flash memory pages. When the target execution parameters are consistent, the extraction of the target task set can be achieved in various ways, but is not limited to. For example, the storage controller performs hardware division with the resource parameter as the dividend and the target execution parameter of any storage task as the divisor, rounding the quotient down to obtain the scale parameter. Subsequently, the storage controller extracts a corresponding number of storage tasks from the head of the storage task sequence according to the quantity indicated by the scale parameter to form the target task set. Another example is that the storage controller uses an iterative subtraction counting method, continuously subtracting the target execution parameter of any storage task from the resource parameter while simultaneously increasing the count value until the remaining resource parameter is less than the target execution parameter. The current count value is then determined as the scale parameter, and storage tasks are extracted sequentially from the sequence according to this count value.

[0054] Optionally, in this embodiment, when the target execution parameters are inconsistent, the reference task set may include, but is not limited to, at least one storage task. The reference set parameter may be the sum of the expected resource consumption of all storage tasks within the reference task set. The process of filtering the target task set may be implemented, but is not limited to, the following: the storage controller uses the resource parameters as the total capacity and the target execution parameters of each storage task as the item weight, and finds multiple combination schemes under the premise of not exceeding the total capacity by constructing a state transition equation to obtain multiple reference task sets. The target execution parameters in each set are then summed to obtain the reference set parameter. Subsequently, the reference task set that satisfies the condition that the reference set parameter is less than or equal to the resource parameter and has the highest resource utilization rate is directly selected as the target task set. For example, if the resource parameter is 100 microseconds, and the sequence contains three storage tasks with time consumption of 40 microseconds, 50 microseconds, and 70 microseconds respectively, the algorithm can combine them to obtain multiple reference task sets with a total time consumption (i.e., reference set parameter) of 40 microseconds, 50 microseconds, 70 microseconds, 90 microseconds, 110 microseconds, or 120 microseconds respectively. At this time, the algorithm will eliminate combinations that exceed the limit and select the reference task set with a total time consumption of 90 microseconds as the final target task set.

[0055] Optionally, in this embodiment, the process of filtering the target task set can also be implemented in the following ways, but not limited to: the storage controller slices the storage task sequence into segments of different lengths and randomly combines them, calculates the reference set parameters for each combination, and after removing combinations whose reference set parameters are greater than the resource parameters, selects a set from the remaining reference task set as the target task set according to the principle of the highest total task priority or the time consumption closest to the remaining idle resources.

[0056] The embodiments provided in this application, when extracting the target task set, firstly, detect whether the target execution parameters are consistent; if consistent, quickly extract a matching number of storage tasks by calculating the scale parameter; if inconsistent, combine tasks and calculate the reference set parameter to filter out the target task set that meets the resource constraints. This mechanism can solve the technical problem in related technologies where a single, rigid scheduling strategy easily leads to excessive computational overhead or low utilization of idle resources when facing complex and ever-changing background storage task queues; by using low-latency, fast batch deployment for homogeneous tasks and fine-grained combination filling for heterogeneous tasks, the resource utilization of the processor's idle time window is maximized while strictly ensuring that tasks do not time out, further improving the flexibility and execution efficiency of system scheduling.

[0057] As an optional approach, the scale parameter is calculated based on the resource parameters and the target execution parameters corresponding to any storage task, including: obtaining the processor's reference idle parameters and candidate idle parameters, wherein the reference idle parameters are used to indicate the processor's total idle resources, and the candidate idle parameters are used to indicate the idle resources consumed by the processor when it exits the idle state; calculating the parameter difference between the reference idle parameters and the candidate idle parameters to obtain the resource parameters; and calculating the scale parameter based on the resource parameters and the target execution parameters corresponding to any storage task.

[0058] Optionally, in this embodiment, the reference idle parameter may be, but is not limited to, the total available time window or the total number of available clock cycles of the processor within an idle state cycle. The candidate idle parameter may be, but is not limited to, the occupancy time or number of clock cycles that the processor must reserve to exit the idle state and return to the working state. The process by which the storage controller obtains the reference idle parameter and the candidate idle parameter may be, but is not limited to, the following: The storage controller captures the estimated total sleep time when the processor is about to enter the idle state through the operating system kernel interface (e.g., the CPUIdle governors module, i.e., the CPU idle manager); since the kernel prediction algorithm may have errors, the storage controller multiplies the estimated total sleep time by a preset prediction confidence factor (e.g., a coefficient ranging from 0.7 to 0.9), uses the prediction confidence factor to offset the error and reserve safety redundancy, and uses the resulting product as the reference idle parameter (e.g., 100 milliseconds). At the same time, the storage controller obtains the fixed buffer time reserved in the system configuration for the processor to perform context switching and preemption of high-priority services after waking up, and uses this wake-up reserve as the candidate idle parameter (e.g., 5 milliseconds).

[0059] It's important to note that the candidate idle parameter is introduced to ensure the system has sufficient free resources to safely exit the idle state and respond to potential high-priority requests. If the candidate idle parameter is not deducted and total free resources are used directly for scheduling, underlying storage tasks can easily finish just before the processor wakes up, potentially leading to bus response deadlocks or system wake-up delays.

[0060] Optionally, in this embodiment, the process of the storage controller calculating the parameter difference to obtain the resource parameter and further calculating the scale parameter can be implemented, but is not limited to, in the following way: The storage controller uses hardware subtraction logic to subtract the candidate idle parameter from the reference idle parameter to obtain the parameter difference, and assigns it to the resource parameter (e.g., 100 milliseconds minus 5 milliseconds equals 95 milliseconds). Then, the storage controller uses this resource parameter to perform a division operation with the target execution parameter corresponding to any storage task to obtain the scale parameter. For example, if the target execution parameter of a single storage task is 10 milliseconds, then the scale parameter obtained by dividing the resource parameter (95 milliseconds) by the target execution parameter and rounding down is 9.

[0061] The embodiments provided in this application solve the technical problem in the related art that the execution of storage tasks at the edge of the idle period time out due to the failure to consider the system overhead of processor state switching, thus hindering the normal wake-up of the system, and further improves the timeliness and stability of the system in responding to sudden high-priority services.

[0062] As an optional approach, the scale parameter is calculated based on the resource parameters and the target execution parameters corresponding to any storage task, including: calculating the scale parameter using the following formula:

[0063] ;

[0064] in, For resource parameters, For any storage task, the target execution parameters are... This is the ratio of resource parameters to the target execution parameters corresponding to any storage task. It is the largest integer less than or equal to the ratio of the parameters.

[0065] Optionally, in this embodiment, the storage controller extracts the resource parameters calculated above and records them as variables. The unit can be, but is not limited to, microseconds, milliseconds, or clock cycles; extract the target execution parameters corresponding to any stored task and denote them as variables. The unit of the parameter is consistent with the resource parameter. Next, the storage controller calls its internal division logic unit to divide the resource parameter by the target execution parameter corresponding to any storage task, obtaining the parameter ratio. This parameter ratio is then rounded down, i.e., the largest integer less than or equal to the parameter ratio is found, and this largest integer is determined as the number of tasks allowed to be executed by the memory, i.e., the scale parameter M.

[0066] Optionally, in this embodiment, the storage controller calls the internal division logic unit to divide the variable. (e.g., 95 microseconds) divided by the variable (e.g., 20 microseconds) to obtain the parameter ratio (e.g., 4.75). The storage controller performs a floor operation on this ratio, discarding the remainder by calling a hardware floor function instruction (Floor instruction) or an integer division instruction, to obtain the maximum integer (e.g., the value 4), which is then determined as the scale parameter M. It is important to note that this floor operation ensures that the resource consumption of the batch extraction tasks will never exceed the limit due to carry-over. For example, if the parameter ratio is 4.75, and the scale parameter is 5 using the rounding mechanism, then 5 storage tasks will consume 100 microseconds, directly exceeding the 95 microsecond resource parameter limit, thus triggering a scheduling timeout; however, by using floor operation to obtain 4, the total consumption is 80 microseconds, strictly ensuring that the total resource consumption of the batch extraction storage tasks during execution is absolutely less than or equal to the remaining idle resources of the processor, further strengthening the non-blocking guarantee mechanism of the system when exiting the idle state and executing high-priority business.

[0067] As an optional approach, after controlling the memory to use the remaining free resources indicated by the resource parameters to execute the target task set, the method further includes: obtaining candidate set parameters of the target task set, and calculating target set parameters of the target task set based on the target execution parameters corresponding to the memory tasks included in the target task set, wherein the candidate set parameters are used to indicate the actual processor free resources consumed by the memory in executing the target task set, and the target set parameters are used to indicate the expected processor free resources consumed by the memory in executing the target task set; calculating a deviation parameter between the candidate set parameters and the target set parameters, wherein the deviation parameter is used to indicate the degree of deviation between the candidate set parameters and the target set parameters; and correcting the target attenuation parameter corresponding to the target device state based on the deviation parameter to obtain a corresponding target device state and candidate attenuation parameter, wherein the candidate attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state, and the lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the candidate attenuation parameter.

[0068] Optionally, in this embodiment, the candidate set parameter may be, but is not limited to, the actual measured time consumed or the actual clock cycles occupied after the memory has completed the execution of the target task set. The target set parameter may be, but is not limited to, the total amount of idle resources expected to be consumed by the target task set before scheduling. The deviation parameter may be, but is not limited to, the absolute difference, ratio difference, or percentage difference between the actual consumed resources and the expected consumed resources.

[0069] Optionally, in this embodiment, the storage controller can obtain the candidate set parameters and the target set parameters in, but is not limited to, the following methods: For example, the storage controller starts a hardware timer when starting the target task set, and stops the timer when it receives an execution completion interrupt signal; the time value read is the candidate set parameter. Simultaneously, the storage controller simply sums the target execution parameters of all storage tasks within the target task set, and uses the sum as the target set parameter.

[0070] Optionally, in this embodiment, the storage controller calculates the difference between the candidate set parameters and the estimated target set parameters to obtain a deviation parameter. It then determines whether this deviation parameter is greater than a preset tolerance threshold. If the deviation parameter is greater than the tolerance threshold, it indicates that the current target attenuation parameter estimate is too optimistic (i.e., the actual execution is slower than expected). The storage controller then adds a compensation step size (e.g., 0.05) to the original target attenuation parameter (e.g., 1.15) to obtain a candidate attenuation parameter (e.g., 1.20). Alternatively, the storage controller calculates the difference between the candidate set parameters and the target set parameters, and divides this difference by the target set parameters to obtain the deviation parameter (i.e., the error percentage). If the error percentage exceeds a preset tolerance range (e.g., 10%), the storage controller multiplies the original target attenuation parameter by a penalty coefficient slightly greater than 1 (e.g., 1.02), and uses the multiplication result as the candidate attenuation parameter. Finally, the candidate attenuation parameter is overwritten into the index position of the corresponding target device state in the one-dimensional lookup table, completing the update of the correspondence.

[0071] It is important to note that as the operating environment of the equipment changes (such as drastic variations in chip temperature) or individual silicon wafer process differences emerge, the factory-calibrated attenuation parameters may gradually deviate from the actual physical conditions. By comparing the actual execution time of each task with the estimated execution time and dynamically adjusting the attenuation parameters, the machine can automatically compensate for resource assessment errors caused by the aforementioned environmental or individual differences.

[0072] To better understand the process of the above-mentioned storage task scheduling method, the following description of the storage task scheduling method flow is further illustrated with reference to optional embodiments, but it is not intended to limit the technical solutions of the embodiments of this application.

[0073] In related technologies, the scheduling method of the storage controller in the storage device is fixed when performing background maintenance operations. When the system receives a high-priority business request during the execution of an uninterruptible atomic operation, it must wait for the current task to finish. This can easily lead to priority inversion and business blocking, resulting in a significant increase in the overall system response latency.

[0074] Therefore, optional embodiments of this application propose a method for scheduling storage tasks. Figure 3This is a flowchart of a storage task scheduling method according to an optional embodiment of this application, such as... Figure 3 As shown, it includes the following steps:

[0075] Step S301: During system operation, it is determined in real time whether the processor (e.g., CPU) is ready to enter the idle state. If the CPU is not ready to enter the idle state, the operation continues; if the CPU is ready to enter the idle state, the sequence of background storage operations to be processed (i.e., the sequence of storage tasks) is obtained. The system captures sleep signals and extracts background storage tasks to be processed in real time by registering a processor idle notification chain.

[0076] Step S302: Capture the estimated sleep time. Obtain the available duration of the current idle window and determine the currently available schedulable effective idle resources (i.e., resource parameters) by combining the reserved overhead. Capture the estimated sleep time through the kernel interface and obtain the time reserved for system context switching, i.e., the wake-up reserved margin (i.e., candidate idle parameters). Combined with the prediction confidence factor, calculate the actual safe total time available for scheduling within the current idle window and determine it as the resource parameter.

[0077] Step S303: Establish a time-consumption baseline model: Obtain reference execution parameters for various storage tasks under different device states of the memory; determine the target device state based on the current target operating parameters of the memory, and correct the reference execution parameters based on the target device state to obtain the target execution parameters corresponding to each storage task. Measure and maintain the standard execution time of atomic operations (read, write, erase) of memory (such as Flash) at different wear stages, i.e., the baseline time (i.e., reference execution parameters). Simultaneously, based on the current number of erase / write wear cycles of the memory (i.e., target operating parameters), dynamically extract the corresponding environmental decay coefficient (i.e., target decay parameter). Use this environmental decay coefficient to compensate for the physical characteristics of increased atomic operation time after memory wear, thereby adjusting the expected time consumption to obtain the actual time expected to be consumed for each atomic operation (i.e., target execution parameter).

[0078] Step S304: Determine whether the types of each storage task are consistent.

[0079] For scenarios where all storage tasks are homogeneous atomic operations (e.g., all are single physical block erases) and their target execution parameters are consistent, the following steps are included:

[0080] Step S305A: Calculate the number M of executable storage tasks. Quantitatively segment the tasks using a specific mathematical model to calculate the maximum number of allowed task steps (scale parameter). Let M be the maximum number of NAND Flash atomic operation task steps allowed to execute within the current CPU idle window; This represents the total CPU sleep time predicted by the operating system kernel. A prediction confidence factor (usually taken as 0.7~0.9) is used to offset the error of the kernel prediction algorithm; Environmental degradation coefficient; The baseline time for a single atomic operation at the current wear stage; To allow for some leeway in waking up, the maximum number of task steps that can be executed in the currently idle window is calculated using the following formula:

[0081] ;

[0082] in, The floor sign is used to ensure that the calculated number of task steps M does not exceed [the floor number]. The integer. When the calculation result M < 1, it is determined that the current idle window is insufficient to complete at least one atomic operation. Therefore, no asynchronous data operations are triggered, and the processor is directly put into sleep mode to avoid unnecessary scheduling overhead. Example implementation scenario (…) =10ms =1ms, =0.8, =2ms, low wear level =1), and we calculate that M is 6.

[0083] Step S306A: Initialize the execution sequence number, set i=1, and execute the i-th stored task. The control memory uses the remaining free resources indicated by the resource parameters to execute the current task unit from the target task set.

[0084] In step S307A, after the i-th task unit is completed, the remaining sleep time is reread for a second check to determine if there is enough time to execute one more storage task. If there is enough time, i = i + 1, and the next task unit continues. If there is not enough time, execution stops and the thread is actively suspended. Even if there are still unprocessed tasks in the memory that need to be reclaimed, they will not continue to occupy the processor; the remaining tasks must wait for the next idle loop before execution. Subsequently, the processor enters sleep mode. When an external interrupt is received, the processor is awakened and returns to the top "System Business Running" state, without interfering with subsequent high-priority business operations.

[0085] For scenarios where storage tasks are not all homogeneous atomic operations (such as simultaneously including read, write, and erase operations of different sizes), i.e., where the types of storage tasks are inconsistent and the target execution parameters are inconsistent, the following steps are included:

[0086] For scenarios where storage tasks are not all homogeneous atomic operations (such as simultaneously including reads, writes, and erases of different sizes), and their target execution parameters are inconsistent, the following steps are included:

[0087] Step S305B: When the target execution parameters of each storage task are inconsistent, the storage task sequence is combined to obtain multiple reference task sets. For the task priority queue and the heterogeneous operations to be processed, since the time consumption of each storage task is inconsistent, the task steps cannot be directly calculated using a single formula. Therefore, different storage tasks in the sequence are combined to obtain multiple execution schemes (i.e., reference task sets).

[0088] Step S306B: Calculate the estimated consumption (i.e., reference set parameters) for each reference task set, and select task combinations whose estimated consumption is less than or equal to the resource parameters as the target task set. For each combination scheme, sum the target execution parameters of all internal tasks to calculate the total estimated time consumption of the scheme (i.e., reference set parameters), and select combination schemes from multiple reference task sets whose estimated total consumption is less than or equal to the total available safe time of the current window (i.e., resource parameters) and maximizes the utilization of the idle window as the actual load to be executed during this sleep period (i.e., target task set).

[0089] Step S307B: The control memory uses the remaining free resources indicated by the resource parameters to execute the selected set of target tasks. During execution, the remaining free resources are dynamically monitored. After each task unit is completed, the current remaining sleep time is reread for a secondary check to see if there is enough time to execute the next task unit. If there is enough time, execution continues; if there is not enough time, execution is stopped early and the thread is actively suspended, and the processor enters sleep mode. When an external interrupt is received, the processor is awakened and returns to the "system business running" state.

[0090] After the target task in any of the above scenarios is completed and the business operation status is returned, a closed-loop calibration is performed:

[0091] Step S308: After the target task set is completed, obtain the actual consumption (i.e., candidate set parameters) and compare it with the expected consumption (i.e., target set parameters) to obtain the deviation parameter. For example, if the actual measured total execution time of the task unit is 32ms (i.e., candidate set parameters), which is 1ms less than the expected value of 33ms (i.e., target set parameters), then calculate the difference between the actual consumption time and the expected value (i.e., deviation parameter).

[0092] Step S309: Correct the attenuation parameter corresponding to the target device state based on the deviation parameter to update the calculation results of the subsequent target execution parameters. Fine-tune the environmental attenuation coefficient for the next calculation based on the above deviation parameter (correcting to obtain candidate attenuation parameters) to further improve the accuracy of subsequent predictions, thereby ensuring that control can be safely returned before the processor wakes up in subsequent scheduling scenarios.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0094] Figure 4 This is a structural block diagram of a storage task scheduling device according to an embodiment of this application; as shown below. Figure 4 As shown, it includes:

[0095] The first acquisition module 42 is used to acquire a storage task sequence when the processor is in an idle state. The storage task sequence includes multiple storage tasks with an execution order. The multiple storage tasks are tasks that the memory connected to the processor is waiting to be executed when the processor is in an idle state.

[0096] The detection module 44 is used to detect the target execution parameters of each storage task in the storage task sequence under the current target device state of the memory. The target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory to execute the corresponding storage task.

[0097] Extraction module 46 is used to extract storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set. The resource parameters are used to indicate the remaining free resources of the processor. The free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters.

[0098] The control module 48 is used to control the memory to execute the target task set using the remaining free resources indicated by the resource parameters.

[0099] By employing the aforementioned apparatus, and acquiring a sequence of storage tasks while the processor is idle, and detecting the target execution parameters of each storage task in the sequence under the current target device state of the memory, the expected consumption of processor idle resources by each storage task can be accurately assessed based on the memory health level indicated by the target device state. Furthermore, by extracting storage tasks from the sequence based on the processor's resource parameters and the target execution parameters corresponding to each storage task, a target task set is obtained. The memory is then controlled to execute this target task set using the remaining idle resources indicated by the resource parameters, achieving a precise match between the storage task execution scale and the processor's remaining idle resources. This method ensures that the expected consumption of idle resources by the memory in executing the target task set under the target device state is less than or equal to the processor's remaining idle resources. It effectively prevents uninterruptible storage tasks from occupying more than the currently available idle resources, overcoming the shortcomings of related technologies where insufficient storage task scheduling flexibility leads to difficulty in responding to other requests in a timely manner. Ultimately, it achieves the technical effects of improving storage task scheduling flexibility and significantly reducing system response latency.

[0100] In one exemplary embodiment, the extraction module includes: a detection unit, configured to detect whether the target execution parameters corresponding to each storage task are consistent; a first calculation unit, configured to calculate a scale parameter based on resource parameters and the target execution parameters corresponding to any storage task when the target execution parameters corresponding to each storage task are consistent; an extraction unit, configured to extract storage tasks matching the scale parameter from the storage task sequence to obtain a target task set, wherein the scale parameter indicates the number of storage tasks that the remaining free resources of the processor allow the memory to execute; a combination unit, configured to combine the storage tasks in the storage task sequence to obtain multiple reference task sets when the target execution parameters corresponding to each storage task are inconsistent, wherein each reference task set includes at least one storage task; a second calculation unit, configured to calculate a reference set parameter for each reference task set based on the target execution parameters corresponding to the storage tasks included in each reference task set, wherein the reference set parameter indicates the processor's free resources expected to be consumed by the memory to execute the corresponding reference task set; and a filtering unit, configured to filter from the multiple reference task sets a target task set whose free resources indicated by the reference set parameter are less than or equal to the remaining free resources indicated by the resource parameter.

[0101] In an exemplary embodiment, the first computing unit is configured to: obtain a reference idle parameter and a candidate idle parameter of the processor, wherein the reference idle parameter is used to indicate the total idle resources of the processor, and the candidate idle parameter is used to indicate the idle resources consumed by the processor when exiting the idle state; calculate the parameter difference between the reference idle parameter and the candidate idle parameter to obtain resource parameters; and calculate scale parameters based on the resource parameters and the target execution parameters corresponding to any storage task.

[0102] In one exemplary embodiment, the first computing unit is further configured to: calculate the scale parameter using the following formula: ;in, For resource parameters, For any storage task, the target execution parameters are... This is the ratio of resource parameters to the target execution parameters corresponding to any storage task. It is the largest integer less than or equal to the ratio of the parameters.

[0103] In one exemplary embodiment, the detection module includes: an acquisition unit, configured to acquire reference execution parameters of each storage task when the memory is in a healthy state, and detect the current device state of the memory based on the target operating parameters of the memory to obtain a target device state, wherein the target operating parameters are used to indicate the cumulative number of erase / write operations of the memory, and the higher the cumulative number of erase / write operations indicated by the target operating parameters, the lower the health level indicated by the target device state; and a third calculation unit, configured to calculate the target execution parameters of each storage task based on the target device state and the reference execution parameters of each storage task.

[0104] In an exemplary embodiment, the third calculation unit is configured to: extract a target attenuation parameter corresponding to a target device state from device states and attenuation parameters that have a corresponding relationship, wherein the target attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state, and the lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the target attenuation parameter; and use the target attenuation parameter to correct the reference execution parameters of each memory task to obtain the target execution parameters of each memory task.

[0105] In one exemplary embodiment, the scheduling device further includes: a second acquisition module, configured to acquire candidate set parameters of the target task set after the control memory uses the remaining free resources indicated by the resource parameters to execute the target task set, and calculate target set parameters of the target task set according to the target execution parameters corresponding to the storage tasks included in the target task set, wherein the candidate set parameters are used to indicate the actual free resources of the processor consumed by the memory in executing the target task set, and the target set parameters are used to indicate the expected free resources of the processor consumed by the memory in executing the target task set; a calculation module, configured to calculate a deviation parameter between the candidate set parameters and the target set parameters, wherein the deviation parameter is used to indicate the degree of deviation between the candidate set parameters and the target set parameters; and a correction module, configured to correct the target attenuation parameter corresponding to the target device state according to the deviation parameter, to obtain a target device state and candidate attenuation parameters with a corresponding relationship, wherein the candidate attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state, and the lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the candidate attenuation parameter.

[0106] Embodiments of this application also provide a storage medium including a stored program, wherein the program executes any of the methods described above when it is run.

[0107] Optionally, in this embodiment, the storage medium may be configured to store program code for performing the following steps:

[0108] S1, when the processor is in an idle state, obtain a sequence of storage tasks, wherein the sequence of storage tasks includes multiple storage tasks with an execution order, and the multiple storage tasks are tasks that the processor is connected to and the memory is waiting to be executed when the processor is in an idle state.

[0109] S2, detect the target execution parameters of each storage task in the storage task sequence in the target device state of the memory, where the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory to execute the corresponding storage task.

[0110] S3. Extract storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set. The resource parameters are used to indicate the processor's remaining free resources. The free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters.

[0111] S4 controls the memory to use the remaining free resources indicated by the resource parameters to execute the target task set.

[0112] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0113] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0114] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0115] S1, when the processor is in an idle state, obtain a sequence of storage tasks, wherein the sequence of storage tasks includes multiple storage tasks with an execution order, and the multiple storage tasks are tasks that the processor is connected to and the memory is waiting to be executed when the processor is in an idle state.

[0116] S2, detect the target execution parameters of each storage task in the storage task sequence in the target device state of the memory, where the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory to execute the corresponding storage task.

[0117] S3. Extract storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set. The resource parameters are used to indicate the processor's remaining free resources. The free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters.

[0118] S4 controls the memory to use the remaining free resources indicated by the resource parameters to execute the target task set.

[0119] Embodiments of this application also provide a computer program product, including a computer program that is executed by a processor through the steps of any of the above method embodiments.

[0120] Optionally, in this embodiment, the above-mentioned computer program product can be executed by a processor using the following steps:

[0121] S1, when the processor is in an idle state, obtain a sequence of storage tasks, wherein the sequence of storage tasks includes multiple storage tasks with an execution order, and the multiple storage tasks are tasks that the processor is connected to and the memory is waiting to be executed when the processor is in an idle state.

[0122] S2, detect the target execution parameters of each storage task in the storage task sequence in the target device state of the memory, where the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory to execute the corresponding storage task.

[0123] S3. Extract storage tasks from the storage task sequence according to the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set. The resource parameters are used to indicate the processor's remaining free resources. The free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters.

[0124] S4 controls the memory to use the remaining free resources indicated by the resource parameters to execute the target task set.

[0125] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0126] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0127] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0128] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for scheduling storage tasks, characterized in that, include: When the processor is in an idle state, a storage task sequence is obtained, wherein the storage task sequence includes multiple storage tasks having an execution order, and the multiple storage tasks are tasks to be executed by the memory to which the processor is connected when the processor is in the idle state; The target execution parameters of each storage task in the storage task sequence are detected in the target device state of the memory, wherein the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory in executing the corresponding storage task; Based on the processor's resource parameters and the target execution parameters corresponding to each storage task, storage tasks are extracted from the storage task sequence to obtain a target task set. The resource parameters are used to indicate the processor's remaining free resources. The free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters. The memory is controlled to use the remaining free resources indicated by the resource parameters to execute the target task set.

2. The method according to claim 1, characterized in that, The step of extracting storage tasks from the storage task sequence based on the processor's resource parameters and the target execution parameters corresponding to each storage task to obtain a target task set includes: Check whether the target execution parameters corresponding to each storage task are consistent; When the target execution parameters corresponding to each storage task are consistent, a scale parameter is calculated based on the resource parameters and the target execution parameters corresponding to any storage task; storage tasks matching the scale parameter are extracted from the storage task sequence to obtain the target task set, wherein the scale parameter is used to indicate the number of storage tasks that the remaining free resources of the processor allow the memory to execute; When the target execution parameters corresponding to the various storage tasks are inconsistent, the storage tasks in the storage task sequence are combined to obtain multiple reference task sets, wherein each reference task set includes at least one storage task; a reference set parameter is calculated for each reference task set based on the target execution parameters corresponding to the storage tasks included in each reference task set, wherein the reference set parameter is used to indicate the idle resources of the processor expected to be consumed by the memory executing the corresponding reference task set; and a target task set is selected from the multiple reference task sets where the idle resources indicated by the reference set parameter are less than or equal to the remaining idle resources indicated by the resource parameter.

3. The method according to claim 2, characterized in that, The calculation of the scale parameter based on the resource parameters and the target execution parameters corresponding to any storage task includes: Obtain the reference idle parameter and candidate idle parameter of the processor, wherein the reference idle parameter is used to indicate the total idle resources of the processor, and the candidate idle parameter is used to indicate the idle resources consumed by the processor when it exits the idle state; The resource parameters are obtained by calculating the parameter difference between the reference idle parameter and the candidate idle parameter; The scale parameter is calculated based on the resource parameters and the target execution parameters corresponding to any storage task.

4. The method according to claim 3, characterized in that, The step of calculating the scale parameter based on the resource parameters and the target execution parameters corresponding to any storage task includes: The scale parameter is calculated using the following formula: ; in, For the resource parameters, The target execution parameters are those corresponding to any storage task. This is the ratio of the resource parameters divided by the target execution parameters corresponding to any storage task. It is the largest integer less than or equal to the ratio of the parameter.

5. The method according to claim 1, characterized in that, The detection of the target execution parameters of each storage task in the storage task sequence in the target device state of the memory currently includes: The reference execution parameters of each storage task are obtained when the memory is in a healthy state, and the target device state is obtained by detecting the current device state of the memory based on the target operating parameters of the memory. The target operating parameters are used to indicate the cumulative number of erase / write cycles of the memory. The higher the cumulative number of erase / write cycles indicated by the target operating parameters, the lower the health level indicated by the target device state. The target execution parameters for each storage task are calculated based on the target device state and the reference execution parameters for each storage task.

6. The method according to claim 5, characterized in that, The step of calculating the target execution parameters of each storage task based on the target device state and the reference execution parameters of each storage task includes: The target attenuation parameter corresponding to the target device state is extracted from the corresponding device states and attenuation parameters. The target attenuation parameter is used to indicate the degree of performance loss of the memory in the target device state. The lower the health level indicated by the target device state, the higher the degree of performance loss indicated by the target attenuation parameter. The target attenuation parameter is used to correct the reference execution parameters of each storage task to obtain the target execution parameters of each storage task.

7. The method according to claim 1, characterized in that, After controlling the memory to execute the target task set using the remaining free resources indicated by the resource parameters, the method further includes: Obtain candidate set parameters of the target task set, and calculate target set parameters of the target task set according to the target execution parameters corresponding to the storage tasks included in the target task set. The candidate set parameters are used to indicate the idle resources of the processor actually consumed by the memory in executing the target task set, and the target set parameters are used to indicate the idle resources of the processor expected to be consumed by the memory in executing the target task set. Calculate the deviation parameter between the candidate set parameters and the target set parameters, wherein the deviation parameter is used to indicate the degree of deviation between the candidate set parameters and the target set parameters; The target attenuation parameter corresponding to the target device state is corrected according to the deviation parameter to obtain the target device state and candidate attenuation parameter with corresponding relationship. The candidate attenuation parameter is used to indicate the performance loss degree of the memory in the target device state. The lower the health level indicated by the target device state, the higher the performance loss degree indicated by the candidate attenuation parameter.

8. A scheduling device for storage tasks, characterized in that, include: The first acquisition module is used to acquire a storage task sequence when the processor is in an idle state, wherein the storage task sequence includes multiple storage tasks having an execution order, and the multiple storage tasks are tasks to be executed by the memory connected to the processor when the processor is in the idle state. The detection module is used to detect the target execution parameters of each storage task in the storage task sequence in the target device state of the memory, wherein the target device state is used to indicate the health of the memory, and the target execution parameters are used to indicate the idle resources of the processor expected to be consumed by the memory in executing the corresponding storage task; An extraction module is used to extract storage tasks from the storage task sequence according to the resource parameters of the processor and the target execution parameters corresponding to each storage task to obtain a target task set, wherein the resource parameters are used to indicate the remaining free resources of the processor, and the free resources that the memory is expected to consume when executing the target task set in the target device state are less than or equal to the remaining free resources indicated by the resource parameters; A control module is used to control the memory to execute the target task set using the remaining free resources indicated by the resource parameters.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program, when executed, performs the method described in any one of claims 1 to 7.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method described in any one of claims 1 to 7 through the computer program.

Images