A method for recovering from abnormal reset of a DSP under electrostatic interference of an audio system

Abstract

This invention provides a method for recovering a DSP from electrostatic interference in an audio system, belonging to the field of automotive electronics technology. The audio system includes a main control chip and a digital signal processor (DSP). The method is executed by the main control chip and includes: monitoring the operating status of the DSP and generating an abnormality flag when an abnormality is detected due to electrostatic interference; in response to the abnormality flag, backing up the current operating parameters of the DSP and generating a reset command; in response to the reset command, controlling the DSP to perform a reset operation to clear its abnormal state; and after confirming that the DSP has been reset, reconfiguring the backed-up operating parameters to the DSP to restore it to its operating state before the abnormality occurred.

Description

Technical Field

[0001] This invention belongs to the field of automotive electronics technology, and specifically relates to a method for recovering abnormal DSP reset under electrostatic interference in audio systems. Background Technology

[0002] Currently, the automotive industry is rapidly developing towards intelligence, and in-vehicle entertainment systems are becoming increasingly feature-rich, with audio-visual and music entertainment becoming a daily necessity for users. Cars are frequently affected by static electricity under various operating conditions. For example, in dry winter air, friction between seats, seatbelts, door metal parts and clothing, friction between the car body and dry air, and poor grounding due to improper wiring harness layout can all generate static electricity. This static electricity can enter the audio circuit through direct contact or air coupling, and then be conducted to the amplifier or speakers via ground wires, signal lines, or power supplies. This can cause momentary noise or, in severe cases, lead to abnormal audio system operation and complete vehicle silence, seriously affecting the user's driving experience. Summary of the Invention

[0003] In view of the technical defects and drawbacks existing in the prior art, the present invention provides a method for DSP abnormal reset recovery under electrostatic interference in audio systems to overcome the above problems or at least partially solve the above problems. The specific solution is as follows;

[0004] As a first aspect of the present invention, a method for DSP abnormal reset recovery under electrostatic interference in an audio system is provided, the audio system including a main control chip and a digital signal processor, the method being executed by the main control chip, and including the following steps:

[0005] Monitor the operating status of the digital signal processor and generate an anomaly flag when an anomaly is detected due to electrostatic interference.

[0006] In response to the anomaly flag, the current operating parameters of the digital signal processor are backed up, and a reset command is generated;

[0007] In response to the reset command, the digital signal processor is controlled to perform a reset operation to clear its abnormal state;

[0008] After confirming that the digital signal processor has been reset, the backed-up operating parameters are reconfigured to the digital signal processor to restore it to its working state before the anomaly occurred.

[0009] In some embodiments, the main control chip monitors the operating status of the digital signal processor and generates the abnormal flag in the following manner:

[0010] A monitoring thread is created and started in the operating system kernel layer of the main control chip;

[0011] The monitoring thread reads the value of the status register of the digital signal processor through the communication interface according to a preset polling cycle;

[0012] The value of the read status register is compared with the preset anomaly detection conditions;

[0013] When the value of the status register meets the anomaly determination condition, the digital signal processor is determined to have an anomaly, and the anomaly flag is generated.

[0014] In some embodiments, the main control chip generates parameter backup and reset instructions by executing a middleware layer in its software architecture, specifically including:

[0015] The kernel layer of the main control chip reports the exception flag to the middleware layer;

[0016] Upon receiving the exception flag, the middleware layer performs the following operations:

[0017] Read the current operating parameters of the digital signal processor and back them up to the storage area of ​​the main control chip;

[0018] Generate a reset instruction;

[0019] The reset command is sent to the kernel layer to trigger subsequent reset operations.

[0020] In some embodiments,

[0021] Upon receiving the exception flag, the middleware layer also sends an exception notification to the application layer; in response to the exception notification, the application layer outputs a prompt message indicating that the system is processing the exception on the user interface.

[0022] Furthermore, after confirming that the digital signal processor has been reset, the middleware layer sends a recovery notification to the application layer; in response to the recovery notification, the application layer outputs a message indicating that the reset was successful on the user interface.

[0023] In some embodiments, the hardware architecture of the audio system includes an entertainment domain and an instrumentation domain, with the main control chip located in the entertainment domain, and the initialization function of the digital signal processor being handled by the kernel layer of the instrumentation domain; the step of controlling the digital signal processor to perform a reset operation in response to the reset instruction specifically includes:

[0024] After receiving the reset command, the kernel layer of the entertainment domain sends a reset request to the kernel layer of the instrumentation domain through shared memory.

[0025] In response to the reset request, the kernel layer of the instrument domain performs a reset initialization operation on the digital signal processor, including loading initialization data from the storage area of ​​the main control chip and writing it to the digital signal processor through a serial communication interface.

[0026] After confirming that the digital signal processor has completed the reset, the kernel layer of the instrumentation domain sends a reset completion signal to the kernel layer of the entertainment domain through the shared memory.

[0027] In some embodiments, the step of reconfiguring the backed-up operating parameters to the digital signal processor after confirming that the digital signal processor has been reset specifically includes:

[0028] After receiving the reset completion signal, the kernel layer of the entertainment domain sends a parameter recovery notification to the middleware layer of the entertainment domain.

[0029] In response to the parameter recovery notification, the middleware layer of the entertainment domain sends the backed-up running parameters to the kernel layer of the entertainment domain.

[0030] The kernel layer of the entertainment domain configures the operating parameters to the corresponding registers of the digital signal processor;

[0031] After the parameters are configured, the audio processing link of the digital signal processor is reactivated to restore the normal transmission of the audio stream.

[0032] In some embodiments, when the kernel layer of the instrument domain performs the reset initialization operation, it writes initialization data to the digital signal processor through a serial communication interface, and after the writing is completed, verifies whether the digital signal processor has been successfully initialized.

[0033] In some embodiments, the entertainment domain and the instrumentation domain communicate via shared memory, specifically including:

[0034] A shared memory area is partitioned in the memory of the main control chip, and both the kernel layer of the entertainment domain and the kernel layer of the instrument domain can access this shared memory area.

[0035] The kernel layer of the entertainment domain sends the reset request to the kernel layer of the instrumentation domain by writing the reset request to a first predetermined address in the shared memory area;

[0036] The kernel layer of the instrument domain obtains the reset request by periodically reading the first predetermined address;

[0037] The kernel layer of the instrument domain sends the reset completion signal to the kernel layer of the entertainment domain by writing the reset completion signal to a second predetermined address in the shared memory area;

[0038] The kernel layer of the entertainment domain obtains the reset completion signal by periodically reading the second predetermined address.

[0039] In some embodiments, the operating parameters include at least one of equalizer settings, volume level, channel balance, crossover point parameters, and dynamic range compression parameters.

[0040] In some embodiments, during the reset operation of the digital signal processor in response to the reset command, the main control chip suspends sending audio data to the digital signal processor; after the digital signal processor returns to normal operation, the main control chip resumes sending audio data to the digital signal processor.

[0041] The present invention has the following beneficial effects:

[0042] 1. This invention can avoid the problems of noise and silence caused by static electricity during daily use of automobiles, thus improving the robustness of the system.

[0043] 2. When the system detects that the DSP is in an abnormal state due to electrostatic discharge, the user does not need to manually restart the system. This method can automatically reset the DSP, improving user convenience.

[0044] 3. This invention only resets the DSP and does not restart the entire vehicle system, thereby minimizing the impact of the reset on the user.

[0045] 4. This invention automatically saves the audio parameters before electrostatic interference. After the DSP is reset, the previously saved audio parameters are sent to the DSP to keep the state of the DSP consistent before and after the reset. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating a method for recovering from DSP abnormal reset under electrostatic interference in an audio system, provided by an embodiment of the present invention.

[0047] Figure 2 A flowchart illustrating the process of monitoring the working status of the digital signal processor and generating the abnormal flag, provided for an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of the architecture of the instrumentation domain and entertainment domain provided in an embodiment of the present invention;

[0049] Figure 4 A schematic diagram illustrating the audio data flow provided in an embodiment of the present invention;

[0050] Figure 5 A schematic flowchart of the reset operation provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the process for restoring operating parameters provided in an embodiment of the present invention. Detailed Implementation

[0052] To enable those skilled in the art to better understand the technical solutions of the present invention, exemplary embodiments of the present invention are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0053] Where there is no conflict, the various embodiments of the present invention and the features thereof may be combined with each other.

[0054] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0057] In the technical solution of this invention, the collection, storage, use, processing, transmission, provision, and disclosure of user personal information all comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations (e.g., the "Information Security Technology - Personal Information Security Specification"). For example: appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identity targeting is eliminated when using personal information to avoid precisely locating a specific individual.

[0058] To address at least one of the technical problems existing in the aforementioned related technologies, the present invention provides a method for DSP abnormal reset recovery under electrostatic interference in audio systems. Figure 1 This is a flowchart illustrating a method for recovering from DSP abnormal reset under electrostatic interference in an audio system, provided by an embodiment of the present invention. The audio system includes a main control chip and a digital signal processor (DSP chip). The method is executed by the main control chip and includes the following steps:

[0059] S1. Monitor the working status of the digital signal processor, and generate an abnormality flag when an abnormality is detected due to electrostatic interference.

[0060] S2. In response to the abnormal flag, back up the current operating parameters of the digital signal processor and generate a reset command;

[0061] S3. In response to the reset command, control the digital signal processor to perform a reset operation to clear its abnormal state;

[0062] S4. After confirming that the digital signal processor has been reset, the backed-up operating parameters are reconfigured to the digital signal processor to restore it to its working state before the abnormality occurred.

[0063] This invention provides a complete automatic recovery process for DSP abnormal states. Through monitoring, backup, isolation reset, and parameter restoration, it fundamentally solves the problem of requiring users to manually restart the vehicle's infotainment system after DSP malfunctions caused by electrostatic interference. Specifically, this method can automatically detect abnormalities, automatically trigger the recovery process, and automatically restore the user's previous audio settings after reset, achieving a seamless and rapid recovery that improves user experience and system reliability. Furthermore, because it only resets the DSP, it avoids restarting the entire infotainment system, ensuring the continuous operation of other functions such as navigation and air conditioning, thus enhancing driving safety.

[0064] See Figure 2As shown, in some embodiments, in step S1, the main control chip monitors the operating status of the digital signal processor and generates the abnormal flag in the following manner:

[0065] S11. Create and start a monitoring thread in the operating system kernel layer of the main control chip;

[0066] S12. The monitoring thread reads the value of the status register of the digital signal processor through the communication interface according to a preset polling cycle;

[0067] S13. Compare the value of the read status register with the preset exception judgment conditions;

[0068] S14. When the value of the status register meets the abnormality determination condition, the digital signal processor is determined to have an abnormality, and the abnormality flag is generated.

[0069] In the above embodiments, by creating an independent monitoring thread at the kernel layer of the main control chip's operating system and periodically polling the DSP status register, real-time, proactive, and low-overhead monitoring of the DSP's operating status is achieved. This software-level monitoring mechanism requires no additional hardware costs, yet can promptly and accurately capture abnormal jumps in the DSP registers caused by electrostatic interference, providing reliable and timely triggering conditions for the subsequent automatic recovery process, ensuring the speed and accuracy of the entire method's response.

[0070] Optionally, the "preset anomaly determination conditions" can be implemented through one or more combinations of the following:

[0071] Register value range error:

[0072] Judgment condition: Read the DSP's status register A (address 0x0001). When the register is working normally, the value of its bits [15:8] (i.e., the high 8 bits) is preset to 0x5A (a fixed magic number) by the DSP firmware. At the same time, bits [7:0] (the low 8 bits) are used to represent the DSP core load rate, which is normally in the range of 0x00 to 0x64 (i.e., 0% to 100%).

[0073] Anomaly detection: If the monitoring thread reads that the value of bit[15:8] is not equal to 0x5A, or the value of bit[7:0] is greater than 0x64, then the register value range is determined to be abnormal.

[0074] Critical register bit status abnormal:

[0075] Judgment condition: Read the DSP's error status register B (address 0x0002). Bit 0 of this register is the "clock lock flag" (1=locked, 0=unlocked), and bit 1 is the "algorithm overflow flag" (1=overflow, 0=normal).

[0076] Anomaly detection: If the monitoring thread reads that bit0 is 0 (indicating clock lockout) or bit1 is 1 (indicating algorithm overflow), then it is determined that the critical status bit is abnormal.

[0077] Communication response timeout exception:

[0078] Judgment criteria: After reading the DSP registers, the monitoring thread checks the CRC8 checksum returned by the DSP via the SPI bus. Simultaneously, a timeout timer (e.g., 10ms) is set.

[0079] Anomaly detection: If no response data is received from the DSP within 10ms, or if the CRC check of the received data fails, it is determined to be a communication response timeout anomaly.

[0080] In some embodiments, in step S2, the main control chip generates parameter backup and reset instructions by executing the middleware layer in its software architecture, specifically including:

[0081] The kernel layer of the main control chip reports the exception flag to the middleware layer;

[0082] Upon receiving the exception flag, the middleware layer performs the following operations:

[0083] Read the current operating parameters of the digital signal processor and back them up to the storage area of ​​the main control chip;

[0084] Generate a reset instruction;

[0085] The reset command is sent to the kernel layer to trigger subsequent reset operations.

[0086] The above embodiment achieves reliable preservation of user settings by backing up runtime parameters through the middleware layer responding to exception flags in the kernel layer. This architecture separates exception handling logic (kernel layer) from business data management (middleware layer), resulting in a clear and robust system architecture. The middleware layer acts as a bridge, ensuring that even during DSP hardware reset, the user's critical audio parameters are securely retained in the main control chip SOC, laying a solid foundation for restoring state consistency after reset.

[0087] In some embodiments, the hardware architecture of the audio system includes an entertainment domain and an instrumentation domain. The main control chip is located in the entertainment domain, and the initialization function of the digital signal processor is handled by the kernel layer of the instrumentation domain. The architecture of the entertainment domain and the instrumentation domain is as follows: Figure 3 As shown;

[0088] See Figure 4 As shown, the audio system consists of a main control SOC chip, a DSP chip, and a PA chip. When playing audio, the audio data flows through the SOC chip, DSP chip, PA chip, and vehicle speaker. When the vehicle system is affected by static electricity, the DSP chip and kernel layer often become abnormal, leading to noise and silence problems.

[0089] See Figure 5 As shown, step S3 includes:

[0090] S31. After receiving the reset instruction, the kernel layer of the entertainment domain sends a reset request to the kernel layer of the instrument domain through shared memory.

[0091] S32. In response to the reset request, the kernel layer of the instrument domain performs a reset initialization operation on the digital signal processor, including loading initialization data from the storage area of ​​the main control chip and writing it to the digital signal processor through a serial communication interface.

[0092] S33. After confirming that the digital signal processor has completed the reset, the kernel layer of the instrument domain sends a reset completion signal to the kernel layer of the entertainment domain through the shared memory.

[0093] The above embodiments leverage the hardware architecture advantages of the instrumentation domain and the entertainment domain. By having the kernel layer of the instrumentation domain specifically handle the DSP's reset and initialization operations, the isolation and hardening of critical hardware control functions are achieved. The instrumentation domain typically offers higher real-time performance and reliability guarantees; its execution of the reset ensures stable and reliable operation. Cross-domain communication via shared memory allows the entertainment domain to safely and efficiently trigger the instrumentation domain's reset action, achieving functional decoupling while ensuring real-time performance of collaborative work and improving the determinism of the entire recovery process.

[0094] See Figure 6 As shown, in some embodiments, step S4 includes:

[0095] S41. After receiving the reset completion signal, the kernel layer of the entertainment domain sends a parameter recovery notification to the middleware layer of the entertainment domain.

[0096] S42. In response to the parameter recovery notification, the middleware layer of the entertainment domain sends the backed-up running parameters to the kernel layer of the entertainment domain.

[0097] S43. The kernel layer of the entertainment domain configures the operating parameters to the corresponding registers of the digital signal processor;

[0098] S44. After the parameters are configured, the audio processing link of the digital signal processor is reactivated to restore the normal transmission of the audio stream.

[0099] In the above embodiments, after the DSP reset, the kernel layer and middleware layer of the entertainment domain collaboratively reconfigure the backed-up operating parameters to the DSP, ensuring complete consistency of the audio processing state of the DSP before and after the reset. Users do not need to perform any manual operations; the audio system can automatically restore the sound effect settings (such as equalizer, volume, etc.) to what they were before the anomaly occurred. This completely eliminates the problem of user settings being lost due to reset in traditional solutions, achieving true "seamless" recovery and significantly improving user satisfaction.

[0100] The following is a specific embodiment of the DSP anomaly recovery implementation based on a domain isolation architecture provided by the present invention. This embodiment takes a certain model of in-vehicle infotainment system as the implementation object. The hardware platform adopts a main control chip (located in the entertainment domain) and a microcontroller (located in the instrument domain), and the digital signal processor adopts an audio DSP chip. The system runs the QNX operating system (entertainment domain) and the AUTOSAR operating system (instrument domain).

[0101] (1) The hardware architecture and initial configuration are as follows:

[0102] 1. Shared memory region partitioning:

[0103] A 4KB shared memory area is allocated in the DDR memory of the main control chip (entertainment domain), with a physical address range of 0x80000000-0x80000FFF. This area is mapped to the kernel address spaces of both the entertainment and instrumentation domains, allowing access from both sides via memory mapping. The first 256 bytes of the shared memory area are used for cross-domain communication protocol definition.

[0104] 2. Communication protocol definition:

[0105] Define the following communication fields in the shared memory area (each field occupies 4 bytes, 32-bit aligned):

[0106] Reset request field: Address 0x80000000, write 0xAA55AA55 to the entertainment field to indicate a reset request, and the instrument field reads this value and then performs the reset operation;

[0107] Reset completion signal field: Address 0x80000004. Writing 0x55AA55AA to the instrument field indicates that the reset is complete. Reading this value in the entertainment field triggers the subsequent process.

[0108] Status confirmation field: Address 0x80000008, used for handshake confirmation (optional);

[0109] Reserved fields: Addresses 0x8000000C-0x800000FF, used for extensions;

[0110] 3. DSP initialization data preparation:

[0111] The DSP initialization firmware (bin file format) is pre-stored in the eMMC storage of the entertainment domain main control chip. The file path is / system / etc / dsp_firmware.bin, and the file size is approximately 128KB. This firmware contains initialization data such as DSP register configuration and algorithm parameters.

[0112] 4. Communication Interface Configuration

[0113] The DSP connects to the main control chip via an SPI bus, with the SPI clock frequency configured at 12.5MHz and mode 0 (CPOL=0, CPHA=0). The instrumentation domain connects to the DSP via another SPI bus for performing reset and initialization operations.

[0114] (2) The abnormal recovery process is executed as follows:

[0115] 1. Reset request sent:

[0116] When the kernel layer of the entertainment domain receives a reset command, it performs the following operations:

[0117] The reset request field (address 0x80000000) is written to the value 0xAA55AA55 using memory mapping.

[0118] Simultaneously set a timeout counter to wait for the instrument domain response (timeout time set to 500ms);

[0119] 2. Perform reset initialization on the instrument domain:

[0120] The kernel layer of the instrumentation domain reads the reset request field of the shared memory area through periodic polling (every 10ms):

[0121] When the reset request field value is detected as 0xAA55AA55, the reset process begins.

[0122] First, the DSP's reset pin is pulled low via the GPIO pin (held low for 100ms) to complete the hardware reset;

[0123] Then, the DSP initialization firmware is read from the eMMC of the entertainment domain master control chip (through the cross-domain file access mechanism).

[0124] Initialization data is written byte by byte to the DSP's configuration register via the SPI bus (write rate is approximately 100KB / s, and the entire write process takes approximately 1.3 seconds).

[0125] After writing is complete, read the DSP's status register (address 0x4000) to verify whether the initialization was successful: if the return value is 0x0001, it means the initialization was successful; otherwise, it means it failed.

[0126] After successful confirmation, write the value 0x55AA55AA to the reset completion signal field (address 0x80000004);

[0127] 3. Parameter restoration execution:

[0128] The kernel layer of the entertainment domain reads the reset completion signal field through periodic polling (every 20ms):

[0129] When the detected value is 0x55AA55AA, a parameter recovery notification is sent to the middleware layer (via inter-process communication mechanism).

[0130] After the middleware layer responds to the notification, it reads the previously backed-up running parameters from the backup storage area (located in the DDR memory of the main control chip, address 0x90000000);

[0131] The operating parameter data structure includes: equalizer settings (10-band equalizer, gain value of -12dB to +12dB per band, step 0.5dB), volume level (0-100), channel balance (gain difference between left and right channels -12dB to +12dB), crossover parameters (high-pass / low-pass filter frequency points, range 20Hz-20kHz), and dynamic range compression parameters (threshold, ratio, start time, release time).

[0132] The middleware layer passes parameter data to the kernel layer via shared memory or message queues;

[0133] The kernel layer configures parameters item by item to the corresponding register address of the DSP via the SPI bus:

[0134] Equalizer settings: Register addresses 0x2000-0x2028;

[0135] Volume level: Register address 0x3000;

[0136] Channel balance: Register address 0x3004;

[0137] Frequency division point parameters: Register address 0x4000-0x4010;

[0138] Dynamic range compression parameters: register addresses 0x5000-0x5010;

[0139] After the parameters are configured (which takes about 200ms), the kernel layer sends an activation command to the DSP (writes to register 0x6000, value 0x01) to reactivate the audio processing link.

[0140] 4. Confirmation of recovery completion:

[0141] The kernel layer reads the DSP's status register (address 0x4000) and confirms a return value of 0x0002 (indicating the audio link is active), thus completing the entire recovery process. The entertainment domain resumes sending audio data streams to the DSP, and the audio system returns to normal operation.

[0142] In some embodiments, the entertainment domain and the instrumentation domain communicate via shared memory, specifically including:

[0143] A shared memory area is partitioned in the memory of the main control chip, and both the kernel layer of the entertainment domain and the kernel layer of the instrument domain can access this shared memory area.

[0144] The kernel layer of the entertainment domain sends the reset request to the kernel layer of the instrumentation domain by writing the reset request to a first predetermined address in the shared memory area;

[0145] The kernel layer of the instrument domain obtains the reset request by periodically reading the first predetermined address;

[0146] The kernel layer of the instrument domain sends the reset completion signal to the kernel layer of the entertainment domain by writing the reset completion signal to a second predetermined address in the shared memory area;

[0147] The kernel layer of the entertainment domain obtains the reset completion signal by periodically reading the second predetermined address.

[0148] The above embodiments detail the shared memory communication mechanism, providing an efficient and reliable cross-domain communication implementation scheme. Specifically, by writing to predetermined addresses in the shared memory area and periodically reading from them, accurate transmission of reset requests and completion signals between the entertainment domain and the instrumentation domain is achieved. This method reduces communication latency, avoids complex protocol parsing overhead, ensures the real-time nature and determinism of cross-domain control, and provides underlying communication guarantees for the smooth execution of the entire automatic recovery process.

[0149] The following are specific embodiments of shared memory communication with timeout and acknowledgment mechanisms provided by the present invention:

[0150] The timeout retransmission mechanism of the sender (such as the entertainment domain kernel layer) is as follows:

[0151] After the entertainment domain kernel layer writes a reset request (e.g., value 0xAA55AA55) to the first predetermined address, it starts a retransmission timer (e.g., timeout of 100ms).

[0152] Within 100ms, the sender will periodically (e.g., every 10ms) check the second predetermined address, waiting for the response signal written by the receiver (instrument domain kernel layer).

[0153] Normal procedure: If the sender reads the “acknowledgment received” signal (e.g., value 0xACEDACED) written by the receiver within 100ms, the timer is cleared, and the request is considered to have been sent successfully.

[0154] Error handling: If no response is received after a 100ms timeout, the sender will rewrite the reset request value to the first predetermined address and restart the retransmission timer. This retransmission operation can be set with an upper limit (e.g., a maximum of 3 retransmissions). If no response is received after 3 retransmissions, the cross-domain communication is considered a failure, and the issue will be handled through other means (such as reporting to the system error log).

[0155] The reception confirmation mechanism for the receiver (such as the instrument domain kernel layer) is as follows:

[0156] After the receiver periodically reads the reset request at the first predetermined address, in addition to performing subsequent operations, it must immediately write a "received acknowledgment" signal (0xACEDACED) to a third predetermined address agreed upon by both parties.

[0157] This operation is intended to inform the sender, "I have received your request and am processing it," thus preventing the sender from mistakenly judging it as a timeout due to communication delays.

[0158] A simple verification of communication data is as follows:

[0159] When sending a write request signal, the sender can simultaneously write a simple XOR checksum to an adjacent address.

[0160] When reading a request signal, the receiver can calculate the checksum of the signal and compare it with the checksum written by the sender. If they do not match, the request is discarded to avoid erroneous operations due to occasional memory errors.

[0161] In some embodiments, when the kernel layer of the instrument domain performs the reset initialization operation, it writes initialization data to the digital signal processor through a serial communication interface, and after the writing is completed, verifies whether the digital signal processor has been successfully initialized.

[0162] The above embodiments clarify that initialization data is written and initialization success is verified through a serial (such as SPI bus) communication interface, ensuring that firmware or configuration data can be reliably and accurately loaded into the DSP. This is the technical basis for the DSP to recover normal operation from abnormal state.

[0163] In some embodiments, the operating parameters include at least one of equalizer settings, volume level, channel balance, crossover point parameters, and dynamic range compression parameters.

[0164] The above embodiments clarify that the parameters that need to be backed up and restored cover core audio processing parameters that directly affect the user's listening experience, such as equalizer settings, volume levels, and channel balance. This ensures that automatic restoration is not only a functional restoration but also a precise restoration of the user experience. After experiencing a DSP abnormal reset, the system can automatically restore the user to their preferred listening experience without needing to readjust the sound.

[0165] In some embodiments,

[0166] Upon receiving the exception flag, the middleware layer also sends an exception notification to the application layer; in response to the exception notification, the application layer outputs a prompt message indicating that the system is processing the exception on the user interface.

[0167] Furthermore, in step S4, the middleware layer also sends a recovery notification to the application layer; in response to the recovery notification, the application layer outputs a message indicating that the reset was successful on the user interface.

[0168] The above embodiments add a user prompt function. By providing clear prompts on the user interface through the application layer when an anomaly occurs and after recovery, the system's automatic processing status is transparently communicated to the user. This eliminates the confusion and anxiety caused by hearing background noise or silence, improving the user-friendliness of human-computer interaction. The prompt function lets users know that the system is resolving the problem and has successfully done so, enhancing users' trust in the system's reliability and is an important part of improving the overall user experience.

[0169] In some embodiments, during step S3, the main control chip pauses sending audio data to the digital signal processor; after the digital signal processor resumes normal operation, the main control chip resumes sending audio data to the digital signal processor.

[0170] In the above embodiments, by pausing the transmission of audio data during DSP reset and retransmitting it after it recovers, the problem of secondary failures, data loss, or more serious noise that may occur when transmitting audio data to the DSP when the DSP is in an abnormal state or is being initialized is effectively prevented.

[0171] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for recovering from DSP abnormal reset under electrostatic interference in an audio system, the audio system comprising a main control chip and a digital signal processor, characterized in that, The method is executed by the main control chip and includes the following steps: Monitor the operating status of the digital signal processor and generate an anomaly flag when an anomaly is detected due to electrostatic interference. In response to the anomaly flag, the current operating parameters of the digital signal processor are backed up, and a reset command is generated; In response to the reset command, the digital signal processor is controlled to perform a reset operation to clear its abnormal state; After confirming that the digital signal processor has been reset, the backed-up operating parameters are reconfigured to the digital signal processor to restore it to its working state before the anomaly occurred.

2. The method according to claim 1, characterized in that, The main control chip monitors the operating status of the digital signal processor and generates the abnormal flag in the following manner: A monitoring thread is created and started in the operating system kernel layer of the main control chip; The monitoring thread reads the value of the status register of the digital signal processor through the communication interface according to a preset polling cycle; The value of the read status register is compared with the preset anomaly detection conditions; When the value of the status register meets the anomaly determination condition, the digital signal processor is determined to have an anomaly, and the anomaly flag is generated.

3. The method according to claim 2, characterized in that, The main control chip generates parameter backup and reset instructions by executing them through the middleware layer in its software architecture, specifically including: The kernel layer of the main control chip reports the exception flag to the middleware layer; Upon receiving the exception flag, the middleware layer performs the following operations: Read the current operating parameters of the digital signal processor and back them up to the storage area of ​​the main control chip; Generate a reset instruction; The reset command is sent to the kernel layer to trigger subsequent reset operations.

4. The method according to claim 3, characterized in that, Upon receiving the exception flag, the middleware layer also sends an exception notification to the application layer; in response to the exception notification, the application layer outputs a prompt message indicating that the system is processing the exception on the user interface. Furthermore, after confirming that the digital signal processor has been reset, the middleware layer sends a recovery notification to the application layer; in response to the recovery notification, the application layer outputs a message indicating that the reset was successful on the user interface.

5. The method according to claim 3, characterized in that, The hardware architecture of the audio system includes an entertainment domain and an instrumentation domain. The main control chip is located in the entertainment domain, and the initialization function of the digital signal processor is handled by the kernel layer of the instrumentation domain. The step of controlling the digital signal processor to perform a reset operation in response to the reset command specifically includes: After receiving the reset command, the kernel layer of the entertainment domain sends a reset request to the kernel layer of the instrumentation domain through shared memory. In response to the reset request, the kernel layer of the instrument domain performs a reset initialization operation on the digital signal processor, including loading initialization data from the storage area of ​​the main control chip and writing it to the digital signal processor through a serial communication interface. After confirming that the digital signal processor has completed the reset, the kernel layer of the instrumentation domain sends a reset completion signal to the kernel layer of the entertainment domain through the shared memory.

6. The method according to claim 5, characterized in that, The step of reconfiguring the backed-up operating parameters to the digital signal processor after confirming that the digital signal processor has been reset specifically includes: After receiving the reset completion signal, the kernel layer of the entertainment domain sends a parameter recovery notification to the middleware layer of the entertainment domain. In response to the parameter recovery notification, the middleware layer of the entertainment domain sends the backed-up running parameters to the kernel layer of the entertainment domain. The kernel layer of the entertainment domain configures the operating parameters to the corresponding registers of the digital signal processor; After the parameters are configured, the audio processing link of the digital signal processor is reactivated to restore the normal transmission of the audio stream.

7. The method according to claim 5, characterized in that, When the kernel layer of the instrument domain performs the reset initialization operation, it writes the initialization data to the digital signal processor through the serial communication interface, and after the writing is completed, it verifies whether the digital signal processor has been successfully initialized.

8. The method according to claim 5, characterized in that, The entertainment domain and the instrumentation domain communicate via shared memory, specifically including: A shared memory area is partitioned in the memory of the main control chip, and both the kernel layer of the entertainment domain and the kernel layer of the instrument domain can access this shared memory area; The kernel layer of the entertainment domain sends the reset request to the kernel layer of the instrumentation domain by writing the reset request to a first predetermined address in the shared memory area; The kernel layer of the instrument domain obtains the reset request by periodically reading the first predetermined address; The kernel layer of the instrument domain sends the reset completion signal to the kernel layer of the entertainment domain by writing the reset completion signal to a second predetermined address in the shared memory area; The kernel layer of the entertainment domain obtains the reset completion signal by periodically reading the second predetermined address.

9. The method according to claim 1, characterized in that, The operating parameters include at least one of the following: equalizer settings, volume level, channel balance, crossover point parameters, and dynamic range compression parameters.

10. The method according to claim 1, characterized in that, In response to the reset command, during the reset operation of the digital signal processor, the main control chip suspends sending audio data to the digital signal processor; after the digital signal processor returns to normal operation, the main control chip resumes sending audio data to the digital signal processor.

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