Methods for adjusting memory operating parameters and memory modules

Abstract

This application proposes a method for adjusting memory operating parameters and a memory module, relating to the field of memory control technology. The method includes: performing at least one correction amount acquisition process on the memory module, and fitting all obtained single correction amounts to obtain a final correction amount, which is written to the storage medium associated with the memory module during the production phase, so as to be superimposed with the first operating parameters obtained from each initialization training during the runtime phase to determine the final operating parameters. The correction amount acquisition process includes: performing initialization training when the memory module is powered on to obtain a second operating parameter; testing the memory module with training code simulating target operating conditions to obtain error distribution information, and determining a third operating parameter accordingly; and determining the single correction amount based on the difference between the third operating parameter and the second operating parameter. This scheme can effectively obtain memory operating parameters with a larger operating margin during actual operation of the memory module without reducing memory startup efficiency.

Description

Technical Field

[0001] This application relates to the field of memory control technology, and more specifically, to a method for adjusting memory operating parameters and a memory module. Background Technology

[0002] Double Data Rate (DDR) memory is a core component of computer systems, used for temporary storage of data and instructions required by the processor. To ensure the reliability of high-speed data transmission, modern memory systems typically perform memory training during the initialization phase. This is done by sending specific, finite-length command and data burst sequences to the DDR memory, thereby establishing an eye diagram matrix and determining the optimal timing parameters and reference voltage values ​​for each data channel.

[0003] In existing technologies, memory training processes typically rely on standardized, relatively short training modes, with data volume and command sequence complexity limited by training time and protocol specifications. In implementing this application, the inventors discovered that the timing parameters and reference voltage values ​​determined based on the memory training process often suffer from insufficient working margins in practical applications, particularly failing to cover signal integrity requirements in high-error-rate regions or extreme business scenarios. Further analysis revealed that to improve DDR memory startup efficiency, standardized memory training processes inevitably employ short data volumes and training times, thus failing to simulate the complex and variable read / write loads of real-world business operations, leading to a risk of insufficient working margins in the determined parameters.

[0004] Therefore, how to effectively obtain memory operating parameters with a larger working margin without reducing the startup efficiency of DDR memory, so as to cover high bit error rate areas or extreme business scenarios, has become an urgent technical problem to be solved. Summary of the Invention

[0005] The purpose of this application is to provide a method for adjusting memory operating parameters and a memory module, which can effectively obtain memory operating parameters with a larger working margin without reducing memory startup efficiency during actual operation of the memory module.

[0006] This application is implemented as follows: In a first aspect, this application provides a method for adjusting memory operating parameters, comprising the following steps: performing at least one correction amount acquisition process on the memory module to obtain the corresponding single correction amount; fitting all single correction amounts to obtain a final correction amount, wherein the final correction amount is used to write into the storage medium associated with the memory module during the production stage, so that during the operation stage, it is superimposed with the first operating parameters obtained from each initialization training to determine the final operating parameters controlling the memory module.

[0007] The correction amount acquisition process includes: responding to the power-on startup of the memory module, performing initialization training to obtain the second operating parameters; testing the memory module using training codes used to simulate the target operating conditions to obtain error distribution information characterizing signal quality; determining the third operating parameter based on the error distribution information; and determining the corresponding single correction amount based on the difference between the third operating parameter and the second operating parameter.

[0008] Secondly, this application provides a memory module including a storage medium storing a final correction value, wherein the final correction value is generated and written using the adjustment method described in any one of the first aspects. The memory module is configured to: perform initialization training upon each power-on startup to obtain first operating parameters; read the final correction value from the storage medium; superimpose the first operating parameters and the final correction value to generate final operating parameters; and configure internal timing control circuitry and voltage regulation circuitry according to the final operating parameters.

[0009] Compared with the prior art, this application has at least the following advantages or beneficial effects: This application proposes a method for adjusting memory operating parameters. By introducing a final correction value and specifically acquiring this value during the production phase, it is written into the storage medium associated with the memory module. Thus, during the memory module's operation, the correction value is superimposed with the initial operating parameters obtained during each initialization training, allowing for the rapid and accurate determination of the final operating parameters with a high operating margin.

[0010] Since the final correction amount is pre-calculated and stored during the production phase, the user equipment only needs to perform standard initialization training and one addition operation each time it starts up, without repeating complex testing processes during the runtime phase. Therefore, it does not affect the startup efficiency of the memory module at all. Furthermore, this application uses training codes specifically designed to simulate the target operating conditions during the production phase, and through multiple tests and fitting processes, it can obtain a final correction amount closer to the true optimal value. This results in the superimposed final operating parameters having a larger operating margin, effectively covering high bit error rate regions and extreme business scenarios. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of an embodiment of a method for adjusting memory operating parameters according to this application; Figure 2 This is a flowchart illustrating the steps of determining a third working parameter based on error distribution information in one embodiment of this application. Figure 3 This is a schematic diagram of a two-dimensional eye diagram matrix in one embodiment of this application; Figure 4 This is a flowchart illustrating the steps for determining the largest connected region consisting of consecutive correct cells in a two-dimensional eye diagram matrix in one embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0014] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0015] To facilitate understanding of the technical solutions provided in this application, some concepts will be introduced below.

[0016] 1. Initialize training Initialization training, also known as memory training, is a standardized parameter calibration process performed after the memory module powers on. Its purpose is to compensate for differences in physical wiring, signal integrity issues, and environmental variations (such as voltage, temperature, and process deviations). Specifically, the memory controller sends specific commands and data burst sequences to the memory module. At the receiving end, signal quality is sampled and analyzed to establish a two-dimensional eye diagram matrix for each data channel. By analyzing this eye diagram matrix, optimal timing parameters and reference voltage values ​​are determined, and these parameters are written to corresponding registers to control subsequent memory module operation, ensuring stable and reliable data reading and writing at a specified data transfer rate. This training process follows the memory protocol specifications defined by the Joint Electron Device Engineering Council (JEDEC). Its characteristics include a limited test sequence length and short execution time, aiming to establish a basic signal read / write window for the memory module while ensuring startup efficiency.

[0017] In developing this application, the inventors discovered that the timing parameters and reference voltage values ​​determined during the memory training process often suffer from insufficient working margin in practical applications, particularly failing to cover signal integrity requirements in high-error-rate regions or extreme business scenarios. Further analysis revealed that this insufficient working margin is due to the fact that, to improve DDR memory startup efficiency, the standardized memory training process inevitably employs a short data volume and training time. The training modes used have limited data volume and relatively fixed patterns, making it impossible to simulate the complex and variable read / write loads in actual business operations. This means that, using the existing method, a trade-off must be struck between "startup efficiency" and "working margin," making it difficult to achieve both simultaneously.

[0018] Based on the above analysis, this application proposes a method for adjusting memory operating parameters. This method introduces a "correction amount," which is specifically acquired before the memory module leaves the factory and written into the storage medium associated with the memory module. During the memory module's operation, the correction amount is superimposed with the first operating parameters obtained during each initialization training, quickly and accurately determining the final operating parameters with a high operating margin. It can be seen that the acquisition of this "correction amount" is completed during the production stage, which neither affects the startup efficiency of the memory module at the user end nor prevents the acquisition of final operating parameters with a larger operating margin through simple superposition processing.

[0019] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0020] Please see Figure 1 The method for adjusting these memory operating parameters includes the following steps: Step S110: Perform the correction amount acquisition process at least once on the memory module to obtain the corresponding single correction amount.

[0021] In step S110, the memory module is processed one or more times to obtain correction values, with each correction value acquisition process generating a single correction value independently. These single correction values ​​reflect the differences between the initial training results and the actual optimal working parameters under multiple tests under the same test conditions or under multiple tests under different test conditions. That is, by executing at least one correction value acquisition process, at least one sample of data can be accumulated, providing a statistical basis for subsequent fitting, and executing it multiple times can further avoid random errors that may be caused by a single measurement.

[0022] For example, in some implementations of this application, the step of performing at least one correction value acquisition process on the memory module includes: performing multiple correction value acquisition processes on the same memory module, wherein the memory module is powered on and restarted in each correction value acquisition process. This means that each test starts from a complete hardware reset state, simulating the cold start scenario of the memory module in actual use. In this way, by powering on and restarting multiple times and repeating the test, parameter fluctuations that may occur under different startup conditions can be captured. After subsequent fitting processing, these multiple single correction values ​​can effectively eliminate random errors in single measurements, making the final correction value more representative and stable.

[0023] Step S120: Fit all single correction values ​​to obtain the final correction value. This final correction value is written into the storage medium associated with the memory module during the production phase, so that it can be superimposed with the first operating parameters obtained from each initialization training during the runtime phase to determine the final operating parameters controlling the memory module. Thus, for different combinations of dual in-line memory modules, motherboards, and central processing units, the corresponding offsets can be obtained through the diagnostic tests in steps S110-S120, and the final operating parameters can be corrected based on the diagnostic results.

[0024] When step S110 is executed multiple times, generating multiple single correction values, step S120 performs mathematical fitting on these single correction values. The purpose of fitting is to extract the most representative and stable final correction value from multiple samples that may exhibit fluctuations. This final correction value is used to write to the storage medium associated with the memory module during the production stage. That is, fitting can eliminate random noise and accidental errors in single measurements, making the final correction value more accurate and reliable.

[0025] In other words, through the processing steps S110-S120, this application can pre-store the final correction amount in the storage medium associated with the memory module after obtaining the final correction amount through multiple tests in the production stage, thereby achieving superposition with the initial training results during the user's runtime phase. In this way, the startup efficiency of the memory module can be maintained while obtaining final operating parameters with a larger working margin.

[0026] It should be noted that during the operational phase, when the memory module is in normal use in the user equipment, the system will still perform standard memory initialization training after each power-on to obtain the initial operating parameters. At this time, the system directly reads the pre-stored final correction value from the storage medium, and adds the initial operating parameters to the final correction value to determine the final operating parameters controlling the memory module. Since the final correction value is obtained through multiple tests and fitting during the production phase, the user equipment does not need to repeat the complex testing process every time it starts up, which ensures both startup efficiency and obtains final operating parameters with a larger operating margin.

[0027] In some implementations of this application, after obtaining the final correction amount, it can be written into the storage medium associated with the memory module, and then the memory module can be tested with training code simulating the target working condition to verify whether the working margin has been improved.

[0028] For further information, please refer to [link / reference]. Figure 1 The specific process for obtaining the correction amount in step S110 includes the following steps: Step S111: In response to the power-on startup of the memory module, perform initialization training to obtain the second working parameters.

[0029] For the correction amount acquisition process, each iteration is triggered by a power-on startup of the memory module. After power-on, a standardized initialization training is first performed, following industry-standard training protocols to generate a set of basic operating parameters, which this application refers to as the second operating parameters. These second operating parameters typically include timing parameters and reference voltage (Vref) values. This ensures that each correction amount acquisition process starts from the same standardized starting point, making subsequent calculations of differences comparable.

[0030] It should be noted that the first, second, and third operating parameters in this application contain the same parameter items. Furthermore, both the first and second operating parameters are obtained through standardized initialization training performed on the memory module, and the acquisition methods are identical. The terms "first" and "second" are used here only to distinguish between the two stages: the second operating parameter is obtained through initialization training performed during the correction amount acquisition process in the production stage, while the first operating parameter is obtained through initialization training performed each time the device is powered on during actual operation.

[0031] Step S112: Test the memory module using the training code used to simulate the target working condition to obtain error distribution information characterizing the signal quality.

[0032] After completing the initialization training and obtaining the second operating parameters, step S112 tests the memory module using specially constructed training code. This training code is not the short pattern used in standard training, but is designed to simulate challenging target conditions in real-world business scenarios, such as high-frequency data flipping or long consecutive identical data bits. During testing, sampling is performed under different combinations of timing offsets and reference voltages, recording which combinations result in data read errors, thereby generating error distribution information. In this way, the training code can expose the signal integrity weaknesses of the memory module under extreme operating conditions, making the error distribution information more valuable than standard training results.

[0033] Step S113: Determine the third working parameter based on the error distribution information.

[0034] The error distribution information records the correct or incorrect performance of the memory module under different timing offsets and reference voltage combinations. By analyzing this information, an operating parameter point with a larger operating margin can be located, which this application refers to as the third operating parameter. Compared to the second operating parameter, the third operating parameter is usually located in a more central area of ​​the error distribution map, with a larger timing and voltage safety boundary around it. That is, the third operating parameter represents a better configuration for this specific memory module under simulated target operating conditions.

[0035] Step S114: Determine the corresponding single correction amount based on the difference between the third working parameter and the second working parameter.

[0036] After obtaining the second and third operating parameters, step S114 calculates the difference between them. This difference can be a multi-dimensional vector, such as a timing difference component and a reference voltage difference component. This difference is the single correction amount corresponding to this correction amount acquisition process. This single correction amount exists in the form of a difference, and its value is usually small, making it easy to store and calculate later, while retaining complete information on the adjustment from standardized parameters to optimized parameters.

[0037] In summary, this application obtains and pre-stores the correction amount during the generation stage using a specific correction amount acquisition process, so that it can be superimposed on the initial training results when used, thereby achieving the goal of obtaining better working parameters without affecting the startup efficiency (the user equipment only needs to perform one more addition operation when completing the standardized startup process).

[0038] Based on the aforementioned scheme, in some implementations of this application, the training code includes a first code pattern and a second code pattern. The first code pattern is a sequence in which logic levels flip in each clock cycle within a continuous clock cycle, used to simulate synchronous switching noise, ground bounce, power supply noise, or crosstalk interference. The second code pattern includes alternating first and second sub-code patterns, used to simulate inter-symbol interference and reference voltage noise; wherein, the first sub-code pattern is a sequence of consecutive bits of a first logic level interspersed with a single second logic level, and the second sub-code pattern is a sequence of consecutive bits of a second logic level interspersed with a single first logic level.

[0039] Understandably, this implementation constructs two specialized training codes to simulate different extreme physical interferences, thereby more comprehensively exposing the signal integrity weaknesses of the memory module under real harsh operating conditions.

[0040] Specifically, the first code pattern can be used to test the stability of the memory module under power fluctuations, while the second code pattern contains both long consecutive identical bits and single bit flips, which can effectively induce inter-symbol interference and reference voltage noise. By using the above two training codes for testing, more comprehensive error distribution information can be obtained than that of standard memory training, thus providing a more reliable data foundation for subsequently determining the third operating parameter with a larger operating margin.

[0041] For ease of understanding, let's take the first and second 32-bit (binary) code patterns as examples. Assuming the first and second code patterns are stored in their respective registers in the memory module, the value of the first code pattern in the register is 0x55555555, and the value of the second code pattern is 0xFDF8103F. Converting to bit patterns, the first code pattern is: 010101010101010101010101010101, and the second code pattern is: 11111101111110000001000000111111. From this, we can see that the first code pattern uses the highest frequency of continuous switching between 0 and 1 to obtain the worst-case synchronous switching noise / ground bounce / power supply noise / crosstalk interference. The second code pattern includes the strongest inter-symbol interference type: consecutive 0s with a 1 in between, and consecutive 1s with a 0 in between; as well as the strongest reference voltage noise: the switching between consecutive 1s and consecutive 0s. This example uses the constructed 32-bit first and second code patterns. In practical applications, the bit length can also be customized according to the size of the register space.

[0042] Based on the aforementioned scheme, in some implementations of this application, the number of data bits of the first code pattern and the second code pattern is greater than or equal to a first threshold, and the first threshold is greater than the number of data bits used for initial training. The step of testing the memory module using training codes to simulate target operating conditions to obtain error distribution information characterizing signal quality includes: Step S1121: Testing the memory module using the first code pattern and recording the timing position and reference voltage position of the error during the test to generate first error distribution information; Step S1122: Testing the memory module using the second code pattern and recording the timing position and reference voltage position of the error during the test to generate second error distribution information; Step S1123: Merging the first error distribution information and the second error distribution information to obtain error distribution information characterizing signal quality.

[0043] Understandably, this implementation uses a significantly larger amount of data than the initial training data for testing and merges the test results of the two code types to obtain more comprehensive and reliable error distribution information. This is because testing with a larger number of data bits can capture sporadic errors that only occur during long-term operation or under specific data patterns, making the final error distribution information closer to real-world business scenarios and providing more sufficient data support for subsequently determining a third working parameter with greater working margin.

[0044] Because initial training has time constraints, the number of bits used for initial training is typically only 1024. However, in this implementation, the first threshold generally requires at least 1e6 bits (1 million data bits). Assuming the first threshold is 1e6 bits and the first and second code patterns are 32 bits each, then the first and second code patterns need to be repeated at least 31250 times.

[0045] It should be noted that the execution order of steps S1121 and S1122 is not limited. Step S1121 can be executed first, followed by step S1122, or step S1122 can be executed first, followed by step S1121.

[0046] Based on the aforementioned solution, please refer to Figure 2 In some implementations of this application, the step of determining the third working parameter based on the error distribution information includes: Step S210: Constructing a two-dimensional eye diagram matrix based on the error distribution information (e.g., ... Figure 3 As shown), each cell of the two-dimensional eye diagram matrix represents the sampling result under a specific time offset and a specific reference voltage combination, indicating that the sampling result is correct. Figure 3 00 in the middle) or error ( Figure 3(Results that are not 00, such as ff, 01, 10, etc. in the two-dimensional eye diagram matrix); Step S220: Determine the largest connected region in the two-dimensional eye diagram matrix consisting of consecutive correct cells; Step S230: Calculate the center point of the largest connected region as the timing value and reference voltage value of the third working parameter.

[0047] Understandably, this implementation transforms error distribution information into a two-dimensional eye diagram matrix and locates the center of the largest continuous correct region within it, thereby finding the optimal operating point with the maximum operating margin. For example... Figure 3 As shown, the optimal operating point found in the end is B, while the point found during the initial training is A. Obviously, point B will have a larger timing and voltage margin compared to point A.

[0048] Specifically, in this implementation, a two-dimensional eye diagram matrix is ​​first constructed based on the error distribution information. Each cell in this matrix corresponds to a specific combination of timing offset and reference voltage, and the cell value represents whether the result is correct or incorrect under that sampling condition. In actual testing, the correct region typically appears as a continuous connected region. Subsequently, the largest connected region consisting of continuous correct cells is identified from this matrix. This region represents the range with the largest safety margin in both timing and voltage dimensions. Finally, the geometric center point of this largest connected region is calculated and used as the timing value and reference voltage value of the third operating parameter.

[0049] In other words, through the processing in steps S210-S230, the third operating parameter found from the error distribution information is located at the center of the most stable region, rather than at the edge. This means that there is the largest timing and voltage fault tolerance margin around this parameter point, which can effectively cope with environmental interference such as temperature changes and voltage fluctuations, thereby significantly improving the stability and reliability of the memory module in actual operation.

[0050] It should be noted that, in Figure 3 In the two-dimensional eye diagram matrix shown, the timing offset is the horizontal axis (row direction) and the reference voltage is the vertical axis (column direction). The connected regions formed by the correct cells represent the sampling window that can correctly read data under this timing and voltage combination.

[0051] Timing margin 1 and timing margin 2 represent the distances that the maximum connected region can be offset to the right and left in the timing direction, respectively. In other words, they are the spans from the center point to the right and left boundaries of the region, respectively. These two values ​​reflect the tolerance in the timing dimension; the larger the values, the more ample the adjustment space in the timing aspect. Voltage margin 1 and voltage margin 2 represent the distances that the maximum connected region can be offset upwards and downwards in the voltage direction, respectively. In other words, they are the spans from the center point to the upper and lower boundaries of the region, respectively. These two values ​​reflect the tolerance in the voltage dimension; the larger the values, the smaller the impact of voltage fluctuations on the correct sampling of the signal.

[0052] In summary, these four margins collectively define the safe operating range around the center point. In this application, by selecting a center point with a larger margin as the third operating parameter, it can be ensured that the memory module can still operate stably when faced with environmental disturbances such as temperature changes and voltage fluctuations.

[0053] Based on the aforementioned solution, please refer to Figure 4 In some implementations of this application, the step of determining the maximum connected region composed of consecutive correct cells in the two-dimensional eye diagram matrix includes: Step S221: Counting the number of consecutive correct cells from top to bottom in each column of the two-dimensional eye diagram matrix to obtain the continuous depth value of each column; Step S222: Among the continuous depth values ​​in each column, searching for segments composed of consecutive non-zero depth values, and selecting the column index set corresponding to the segment with the longest consecutive segment length as the continuous valid column set; Step S223: Counting the number of consecutive correct cells from left to right in each row of the two-dimensional eye diagram matrix to obtain the continuous depth value of each row; Step S224: Among the continuous depth values ​​in each row, searching for segments composed of consecutive non-zero depth values, and selecting the row index set corresponding to the segment with the longest consecutive segment length as the continuous valid row set; Step S225: Determining the maximum connected region based on the rectangular region defined by the continuous valid column set and the continuous valid row set.

[0054] Understandably, this implementation locates the largest rectangular connected region by statistically analyzing the distribution of consecutive correct cells in the column and row directions of the two-dimensional eye diagram matrix.

[0055] It should be noted that this implementation does not impose any restrictions on the execution order of steps S221 and S223. In practice, step S221 can be executed first and then step S223, or step S223 can be executed first and then step S221, or both steps can be executed simultaneously; all of these methods can achieve the technical solution of this implementation.

[0056] For ease of explanation, assuming step S221 is executed before step S223, in this implementation, the number of consecutive correct cells in each column of the 2D eye diagram matrix is ​​first counted from top to bottom, obtaining the continuous depth value for each column. Then, in these continuous depth value sequences, segments consisting of consecutive non-zero depth values ​​are searched, and the segment with the longest consecutive segment is selected; the set of column indices corresponding to this segment is the set of consecutive valid columns. Similarly, the number of consecutive correct cells in each row from left to right is counted, obtaining the continuous depth value for each row; segments consisting of consecutive non-zero depth values ​​are searched, and the set of row indices corresponding to the segment with the longest consecutive segment is selected as the set of consecutive valid rows. Finally, the set of consecutive valid columns and the set of consecutive valid rows together define a rectangular region, which is the maximum connected region. In this way, stable regions with the maximum continuous span in both the temporal and voltage directions can be quickly and accurately filtered from the 2D eye diagram matrix, providing a reliable range constraint for subsequent calculation of the center point.

[0057] To facilitate understanding, the process of determining the largest connected component will be illustrated below with a specific example: First, in the column direction, statistically analyze the two-dimensional eye diagram matrix (e.g. Figure 3 The continuous depth value of each column is obtained by counting the number of consecutive correct cells from top to bottom in each column (as shown). Then, in these consecutive depth value sequences, the segment consisting of consecutive non-zero depth values ​​is found, and the segment with the longest consecutive segment is selected. The set of column indices corresponding to this segment is the set of consecutive valid columns. For example, suppose the consecutive depth values ​​of each column are 0, 0, 4, 4, 4, 4, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0. There are two consecutive non-zero segments: the first segment is four consecutive 4s, and the second segment is thirteen consecutive 4s. Since the second segment is longer, the column corresponding to this segment is taken as the consecutive valid column.

[0058] Similarly, in the row direction, count the number of consecutive correct cells from left to right in each row of the 2D eye diagram matrix to obtain the continuous depth value of each row. Find the segment formed by consecutive non-zero depth values, and select the segment with the longest consecutive segment. The set of row indices corresponding to this segment is the set of consecutive valid rows. For example, suppose the consecutive depth values ​​of each row are 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 5, 5, 5, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0. There are two consecutive non-zero segments: the first segment is four consecutive 1s, and the second segment is six consecutive 5s. Since the second segment is longer, the row corresponding to this segment is taken as the consecutive valid row.

[0059] Based on the aforementioned scheme, in some implementations of this application, the step of calculating the center point of the maximum connected region includes: within the maximum connected region, taking a weighted average of the values ​​in the last row with the square of the number of consecutive correct cells in each column as the weight, to obtain the target column index; within the maximum connected region, taking a weighted average of the values ​​in the first column with the square of the number of consecutive correct cells in each row as the weight, to obtain the target row index; and determining the position of the center point based on the target column index and the target row index.

[0060] Understandably, this implementation calculates the center point of the largest connected region using a weighted average, where the weights are the square of the number of consecutive correct cells, making more stable columns or rows have a greater impact on the center position. Specifically, the target column index can be determined first, followed by the target row index, or vice versa, or both can be determined simultaneously. Finally, the center point's position is determined based on both the target column and row indices.

[0061] It should be noted that the values ​​in the last row and the first column are in hexadecimal format. In actual calculations, they need to be converted to decimal before being included in the weighted average. Due to the use of squared weights, columns or rows with more consecutive correct cells (i.e., more stable) will receive higher weights in the center point determination process. This results in the final determined center point being more biased towards an area with a larger margin, ensuring that the third working parameter has better robustness.

[0062] In other words, when calculating the target column index, the following operations can be performed on each column within the area defined by the set of consecutive valid columns: multiply the square of the number of consecutive correct cells (00) in that column by the value of the last row in the two-dimensional eye diagram matrix in that column, where the value is in hexadecimal format and needs to be converted to decimal; sum the products obtained from all columns to obtain the first weighted sum 'a'. Simultaneously, sum the squares of the number of consecutive correct cells in each column within that area to obtain the first sum of squares 'b'. Divide the first weighted sum 'a' by the first sum of squares 'b', round the quotient to one decimal place, and obtain the target column index 'new_col'. That is, 'new_col' = a divided by b, rounded to one decimal place.

[0063] Similarly, when calculating the target row index, the following operations can be performed on each row within the region defined by the set of consecutive valid rows: Multiply the square of the number of consecutive correct cells in that row by the value in the first column of the two-dimensional eye diagram matrix for that row. This value is also in hexadecimal format and needs to be converted to decimal. Sum the products obtained from all rows to obtain the second weighted sum c. Simultaneously, sum the squares of the number of consecutive correct cells in each row within this region to obtain the second sum of squares d. Divide the second weighted sum c by the second sum of squares d, round the quotient to one decimal place, and obtain the target row index new_row. That is, new_row = c divided by d, rounded to one decimal place.

[0064] Based on the aforementioned scheme, in some implementations of this application, the step of fitting all single correction values ​​to obtain the final correction value includes: using a statistical algorithm to estimate the parameters of all single correction values ​​to obtain the final correction value; or, using all single correction values ​​as training samples to input into a machine learning model, so as to use the prediction output of the machine learning model as the final correction value; or, using a filtering algorithm to smooth all single correction values, so as to use the smoothed result as the final correction value.

[0065] It should be noted that since random noise or measurement errors are inevitably introduced in each correction acquisition process, directly using a single correction value may not be stable enough. By using corresponding mathematical methods to comprehensively process the single correction values ​​obtained from multiple measurements, random errors can be effectively eliminated, making the final correction value closer to the true optimal offset value, thus providing more reliable operating parameters in practical use.

[0066] Specifically, three different fitting methods can be adopted: The first is a statistical algorithm, which estimates the parameters of all single correction values. For example, the final correction value can be obtained by calculating the mean or fitting a distribution curve. Another example is using an "unbiased estimation (corrected maximum likelihood)" method to fit a Gaussian distribution. There are many methods for fitting a Gaussian distribution, such as least squares and Bayesian estimation, which are not specifically limited in this application. The second method is to use all single correction values ​​as training samples and input them into a machine learning model, using the model's predicted output as the final correction value. This method can learn the underlying patterns between single correction values. The third method is to use a filtering algorithm to smooth all single correction values, such as using a moving average filter, and using the smoothed result as the final correction value, which can effectively suppress random fluctuations in single measurements.

[0067] Based on the foregoing scheme, in some implementations of this application, the storage medium is a non-volatile register, and the non-volatile register is set in at least one of the following: the memory module, the memory controller coupled to the memory module, or the motherboard firmware chip coupled to the memory module.

[0068] Understandably, because this implementation stores the final correction value in a non-volatile register, it ensures that the stored final correction value is retained even after the memory module is powered off, regardless of its location within the memory module, the memory controller coupled to the memory module, or the motherboard firmware chip coupled to the memory module. The specific location of this setting can be selected based on different hardware architectures.

[0069] This application embodiment also provides a memory module, which includes a storage medium storing a final correction value. The final correction value is generated and written using the memory operating parameter adjustment method described in any of the foregoing implementations. The memory module is configured to: perform initialization training upon each power-on startup to obtain first operating parameters; read the final correction value from the storage medium; superimpose the first operating parameters and the final correction value to generate final operating parameters; and configure internal timing control circuitry and voltage regulation circuitry according to the final operating parameters.

[0070] It is understood that this implementation provides a memory module with built-in correction parameters. This memory module pre-stores the final correction parameters in its internal storage during the production phase, and can automatically perform parameter overlay during use. In this way, the memory module does not need to rely on an external system for parameter correction; it automatically loads and configures the optimized parameters after each startup, ensuring both startup efficiency and greater operational margin. The specific implementation process for adjusting the memory operating parameters of the aforementioned memory module is described in the above embodiment as a method for adjusting memory operating parameters, and will not be repeated here.

[0071] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for adjusting memory operating parameters, characterized in that, The adjustment method includes: Perform the correction amount acquisition process at least once on the memory module to obtain the corresponding single correction amount; All individual correction values ​​are fitted to obtain a final correction value, which is used to write to the storage medium associated with the memory module during the production phase so that it can be superimposed with the first operating parameters obtained from each initialization training during the runtime phase to determine the final operating parameters controlling the memory module. The correction amount acquisition process includes: In response to the power-on startup of the memory module, initialization training is performed to obtain the second working parameters; The memory module was tested using training code to simulate the target working condition, and error distribution information characterizing signal quality was obtained. Based on the error distribution information, determine the third operating parameter; The corresponding single correction amount is determined based on the difference between the third working parameter and the second working parameter.

2. The adjustment method according to claim 1, characterized in that, The training code includes a first code type and a second code type; The first code pattern is a sequence in which the logic level flips in each clock cycle within a continuous clock cycle, used to simulate synchronous switch noise, ground bounce, power supply noise or crosstalk interference conditions. The second code pattern includes an alternating first sub-code pattern and a second sub-code pattern, used to simulate inter-symbol interference and reference voltage noise conditions; wherein, the first sub-code pattern is a sequence of consecutive bits of a first logic level interspersed with a single second logic level, and the second sub-code pattern is a sequence of consecutive bits of a second logic level interspersed with a single first logic level.

3. The adjustment method according to claim 2, characterized in that, The number of data bits of the first code pattern and the second code pattern is greater than or equal to a first threshold, and the first threshold is greater than the number of data bits used for initial training. The step of testing the memory module using training code to simulate the target operating condition and obtaining error distribution information characterizing signal quality includes: The memory module is tested using the first code pattern, and the timing position and reference voltage position of the error during the test are recorded to generate the first error distribution information; The memory module is tested using the second code pattern, and the timing position and reference voltage position of the error during the test are recorded to generate second error distribution information; By merging the first error distribution information and the second error distribution information, we obtain the error distribution information that characterizes the signal quality.

4. The adjustment method according to claim 1, characterized in that, The step of determining the third operating parameter based on the error distribution information includes: A two-dimensional eye diagram matrix is ​​constructed based on the error distribution information. Each cell of the two-dimensional eye diagram matrix represents whether the sampling result under a specific time offset and a specific reference voltage combination is correct or incorrect. Determine the largest connected region in the two-dimensional eye diagram matrix consisting of consecutive correct cells; The center point of the largest connected region is calculated and used as the timing value and reference voltage value of the third operating parameter.

5. The adjustment method according to claim 4, characterized in that, The steps for determining the largest connected region consisting of consecutive correct cells in the two-dimensional eye diagram matrix include: The number of consecutive correct cells in each column of the two-dimensional eye diagram matrix from top to bottom is counted to obtain the continuous depth value of each column; In each column of continuous depth values, find the segment formed by consecutive non-zero depth values, and select the column index set corresponding to the segment with the longest consecutive segment length as the continuous valid column set; The number of consecutive correct cells in each row of the two-dimensional eye diagram matrix from left to right is counted to obtain the consecutive depth value of each row; In each row of consecutive depth values, find the segment formed by consecutive non-zero depth values, and select the row index set corresponding to the segment with the longest consecutive segment length as the consecutive valid row set; The maximum connected region is determined based on the rectangular region defined by the set of consecutive valid columns and the set of consecutive valid rows.

6. The adjustment method according to claim 4 or 5, characterized in that, The steps for calculating the center point of the largest connected region include: Within the largest connected region, the values ​​in the last row are weighted and averaged using the square of the number of consecutive correct cells in each column as the weight, to obtain the target column index; Within the largest connected region, the values ​​in the first column are weighted and averaged using the square of the number of consecutive correct cells in each row as the weight, to obtain the target row index; The location of the center point is determined based on the target column index and the target row index.

7. The adjustment method according to claim 1, characterized in that, The step of fitting all individual correction values ​​to obtain the final correction value includes: Statistical algorithms are used to estimate the parameters of all individual corrections to obtain the final correction amount; Alternatively, all single correction values ​​can be used as training samples and input into a machine learning model to use the prediction output of the machine learning model as the final correction value. Alternatively, a filtering algorithm can be used to smooth all single correction values, and the smoothed result can be used as the final correction value.

8. The adjustment method according to claim 1, characterized in that, The step of performing at least one correction amount acquisition process on the memory module includes: performing multiple correction amount acquisition processes on the same memory module, wherein the memory module is powered on and restarted in each correction amount acquisition process.

9. The adjustment method according to claim 1, characterized in that, The storage medium is a non-volatile register, which is configured in at least one of the following: the memory module, a memory controller coupled to the memory module, or a motherboard firmware chip coupled to the memory module.

10. A memory module, characterized in that, include: A storage medium storing a final correction amount, wherein the final correction amount is generated and written by the adjustment method as described in any one of claims 1 to 9; The memory module is configured as follows: Initialization training is performed after each power-on startup to obtain the first working parameters; Read the final correction amount from the storage medium; The first working parameter is superimposed with the final correction amount to generate the final working parameter; Configure the internal timing control circuit and voltage regulation circuit according to the final operating parameters.

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