A multi-master IIC bus control system and its dynamic arbitration method

Abstract

This invention relates to the field of communication bus technology, and more particularly to a multi-master IIC bus control system and its dynamic arbitration method, including a parameter configuration unit, a dynamic arbitration unit, a dynamic role switching unit, and a slave data synchronization unit. Dynamic arbitration is achieved through a wired-AND mechanism and a readback detection mechanism: the master node determines the arbitration status by comparing its output level with the bus readback level, and switches to slave upon failure; the slave node switches to master upon detecting a bus idle timeout. The slave data synchronization unit captures bus timing data in real time to ensure zero-delay takeover during master-slave switching. During the power-on initialization phase, master and slave roles are allocated through contention timing. This invention solves the problems of bus conflict, switching delay, and data loss in multi-master scenarios, significantly improving system reliability and real-time performance, and is suitable for redundant control and high-reliability equipment.

Description

Technical Field

[0001] This invention relates to the field of communication bus technology, and in particular to a multi-master IIC bus control system and its dynamic arbitration method. Background Technology

[0002] The IIC (Inter-Integrated Circuit) bus is a widely used synchronous serial communication protocol with multi-slave support capabilities, but its native design only allows a single master to control the bus. In practical industrial scenarios (such as redundant control systems and high-reliability equipment), multiple masters often need to work together to improve system fault tolerance. However, traditional solutions have the following drawbacks: 1) Static master-slave allocation: When the master node fails, the slave node cannot take over automatically, causing the system to crash. The master node is the host node, and the slave node is the slave node. 2) Arbitration conflict: When two hosts initiate transmissions simultaneously, the lack of an efficient arbitration mechanism can easily lead to data conflicts or loss. 3) Switching delay: The master-slave switching process requires re-initializing the bus state, causing communication interruption and disrupting data continuity.

[0003] Existing improvement solutions (such as priority-based hardware arbitration or time-slice polling) rely on additional control chips or complex scheduling algorithms, which increases system complexity and latency, making it difficult to meet the requirements of high real-time scenarios.

[0004] In summary, the realization of a multi-master IIC bus control system capable of dynamic arbitration is of great significance for the pursuit of redundant control systems and high-reliability equipment. Summary of the Invention

[0005] This invention provides a multi-master IIC bus control system and its dynamic arbitration method, which can guarantee data continuity with low latency and high reliability, solve the problems of bus conflict, switching delay and data loss in multi-master scenarios, significantly improve the reliability and real-time performance of the system, and is suitable for redundant control and high reliability equipment.

[0006] To achieve the above objectives, the present invention employs the following technical solution: A multi-master IIC bus control system includes a parameter configuration unit, a dynamic arbitration unit, a dynamic role switching unit, and a slave data synchronization unit; The parameter configuration unit calculates the number of arbitration filter points based on the system clock and IIC baud rate, and sends the generated number of arbitration filter points to the dynamic arbitration unit. The dynamic arbitration unit arbitrates the wired-AND mechanism and readback detection mechanism of the physical layer under multi-master nodes. The wired-AND mechanism of the physical layer utilizes the open-drain output characteristics of the IIC bus and follows the low-level priority preemption principle. The readback detection mechanism includes a readback detection mechanism in master mode and a bus idle detection mechanism in slave mode. The readback detection mechanism in master mode compares the node output level with the bus readback level in real time. When the detected node output level is inconsistent with the bus readback level, the arbitration counter is started. When the counter value exceeds the number of arbitration filter points, the arbitration is determined to have failed. The bus idle detection mechanism in slave mode triggers a mode switch if there is no SCL transition for 1 consecutive second. The dynamic role switching unit, based on the wired-AND mechanism and readback detection mechanism of the dynamic arbitration unit, is responsible for the initial allocation of host and slave roles when the system starts up and the execution of role switching during operation. The slave data synchronization unit captures the complete timing data of the SCL / SDA bus in real time in slave mode and seamlessly takes over bus control when switching to master mode.

[0007] Furthermore, the multiple host nodes are redundant FPGA chip A and FPGA chip B.

[0008] Furthermore, the number of arbitration filter points is dynamically generated by the following formula: ; Among them, K is the fault tolerance coefficient.

[0009] Furthermore, during the power-on initialization phase, the dynamic role switching unit initiates an initialization count, and automatically enters master mode after completing a 1-second count, taking over IIC bus control. Simultaneously, when another master node detects an SCL transition, it actively enters slave mode. During the operation phase, the master node in master mode switches from master mode to slave mode based on the arbitration result of the bus arbitration failure, releasing bus control. Meanwhile, the master node in slave mode switches from slave mode to master mode based on the real-time detected SCL bus status, and if there is no SCL transition after a 1-second bus idle timeout, it switches from slave mode to master mode, thereby completing the control of the bus.

[0010] Furthermore, when the slave data synchronization unit switches to master mode, it directly reads the latest cached bus timing data and performs zero-latency bus takeover.

[0011] A dynamic arbitration method for a multi-master IIC bus includes the following steps: S101. The parameter configuration unit calculates the number of arbitration filter points of the dynamic arbitration unit and sends the number of arbitration filter points to the dynamic arbitration unit. S102. The dynamic arbitration unit compares the output level with the bus readback level in real time in master mode. If they are inconsistent, the arbitration count is started. When the count exceeds the number of arbitration filter points, the arbitration is determined to be unsuccessful and the unit switches to slave mode. In slave mode, if there is no SCL transition within 1 second, the unit switches to master mode. S103. The dynamic role switching unit selects and switches roles based on the power-on status and the arbitration result of the dynamic arbitration unit. During power-on initialization, the FPGA chip node that completes the 1-second count first becomes the master, and other nodes become slaves after detecting the SCL transition. During operation, master-slave switching is triggered based on arbitration failure or bus idle timeout. S104. According to the role allocation result of the dynamic role switching unit, the FPGA chip in slave mode continuously captures and caches the complete timing data of the SCL / SDA bus; when switching to master mode, it seamlessly takes over bus control based on the cached data.

[0012] Furthermore, in the master mode, after switching to slave mode, the master immediately releases bus control and enters data listening state.

[0013] Compared with the prior art, the beneficial effects of the present invention are: This invention employs a three-pronged approach—dynamic role allocation and switching, quantized threshold arbitration filtering, and uninterrupted data synchronization at the slave end—to efficiently and reliably resolve contention issues arising when multiple masters simultaneously operate the IIC bus. This system significantly improves the reliability and robustness of bus access, ensures the integrity and continuity of data transmission, and effectively reduces the risk of data loss and communication delays caused by arbitration failures or switching. Attached Figure Description

[0014] Figure 1 This is a structural topology diagram of the system described in this invention.

[0015] Figure 2 This is a diagram of the internal structure of the IIC bus interface of the present invention.

[0016] Figure 3 This is a schematic diagram of the three-state IObuf structure of the present invention.

[0017] Figure 4 This is a schematic diagram of the arbitration timing principle of the present invention.

[0018] Figure 5 This is the arbitration judgment flowchart of the present invention.

[0019] Figure 6 This is a flowchart of the dynamic role switching state of the present invention. Detailed Implementation

[0020] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings: This invention provides a multi-master IIC bus control system and its dynamic arbitration method, including a parameter configuration unit, a dynamic arbitration unit, a dynamic role switching unit, and a slave data synchronization unit.

[0021] The parameter configuration unit calculates the number of arbitration filter points based on the system clock and IIC baud rate, and sends the generated number of arbitration filter points to the dynamic arbitration unit. The dynamic arbitration unit arbitrates the wired-AND mechanism and readback detection mechanism of the physical layer under multiple host nodes; the dynamic arbitration unit adopts the wired-AND mechanism and the readback detection mechanism.

[0022] like Figure 1 and Figure 2 As shown, the system topology diagram and internal structure diagram of the IIC bus interface of this invention clearly demonstrate the physical layer arbitration mechanism under multiple master nodes; the wired-AND mechanism (physical basis) utilizes the open-drain output characteristics of the IIC bus standard, and its core rule is that the bus only behaves as a high level when all master nodes output a high level; if any master node outputs a low level, the bus is pulled low, i.e., the "low-level priority preemption" principle; the master node is implemented by FPGA hardware, and its open-drain output circuit ( Figure 2 This provides the physical basis for lines and mechanisms.

[0023] like Figure 3 As shown, the FPGA of this invention is a schematic diagram of a tri-state IObuf (SDA bus port) structure, which illustrates that when the output is enabled, T=1 and the readback bus signal is port O.

[0024] The readback detection mechanism, in master mode, compares the output level with the bus readback level in real time. If the output level and readback level match, master mode is maintained; otherwise, an arbitration counter is activated. When the accumulated value of the arbitration counter exceeds a preset threshold (number of arbitration filter points N), the current IIC bus arbitration is deemed to have failed, and the node exits master mode and switches to slave mode. Figure 4 As shown in the timing diagram of the present invention, when the SCL and SDA buses are set as output gates (out_en=1), when the SDA output is high (SDA_OUT=1) and the SDA bus readback (SDA_IN) is low, the arbitration counter arb_cnt is started. When arb_cnt>N (N is set according to the baud rate and clock frequency), the local arbitration is determined to have failed.

[0025] like Figure 5As shown in the flowchart of the arbitration judgment process for the master and slave devices of this invention, the master node continuously compares the output level with the bus readback level in master mode. When the output level and readback level are consistent, it indicates that the IIC bus is normal, and the master node maintains master mode. When the output level and readback level are inconsistent, the arbitration counter is started. When the cumulative value of the arbitration counter exceeds a preset threshold N for a certain period of time, it indicates that the current IIC bus communication is abnormal. The master node determines that the current IIC bus arbitration has failed, exits master mode, switches to slave mode, and releases bus control. In slave mode, the master node continuously monitors the transition state of the SCL bus. When no transition is detected on the SCL bus for 1 second, the master node is considered to be malfunctioning. At this time, the node automatically switches from slave mode to master mode and takes over bus control.

[0026] The dynamic role switching unit, based on the wired-AND mechanism and readback detection mechanism of the dynamic arbitration unit, is responsible for the initial allocation of master and slave roles at system startup and the execution of role switching during operation; such as Figure 6 As shown in the flowchart of the dynamic role switching state of the present invention, after multiple master nodes (FPGA chips) are powered on, they start initialization counting, and the first to complete 1 second of counting automatically enters the master mode and takes over the IIC bus control. At the same time, when another master node detects an SCL transition, it actively enters the slave mode. During the operation phase, the master node in master mode determines to switch from master mode to slave mode based on the arbitration result of the bus. If the arbitration fails, it releases the bus control. Alternatively, if the bus is idle for 1 second without an SCL transition, it determines to switch from slave mode to master mode, thereby completing the control of the bus. The slave data synchronization unit needs to continuously and accurately monitor the status changes of the SCL and SDA buses, synchronously capture all operation instructions and data (including addresses, read / write commands, data bytes, ACK / NACK, etc.) issued by the master, and store them in the cache. When switching to master, it immediately reads the latest bus status from the cache to achieve seamless takeover with zero delay, ensure data continuity, and achieve uninterrupted data following. It ensures that even at the moment of role switching (slave to master), the new master can fully grasp the latest status and historical data of the bus, thereby achieving zero-loss switching and ensuring data continuity.

[0027] The following embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the following embodiments. Unless otherwise specified, the methods used in the following embodiments are conventional methods.

Claims

1. A multi-master I2C bus control system, characterized by, It includes a parameter configuration unit, a dynamic arbitration unit, a dynamic role switching unit, and a slave data synchronization unit; The parameter configuration unit calculates the number of arbitration filter points based on the system clock and IIC baud rate, and sends the generated number of arbitration filter points to the dynamic arbitration unit. The dynamic arbitration unit arbitrates the wired-AND mechanism and readback detection mechanism of the physical layer under multi-master nodes. The wired-AND mechanism of the physical layer utilizes the open-drain output characteristics of the IIC bus and follows the low-level priority preemption principle. The readback detection mechanism includes a readback detection mechanism in master mode and a bus idle detection mechanism in slave mode. The readback detection mechanism in master mode compares the node output level with the bus readback level in real time. When the detected node output level is inconsistent with the bus readback level, the arbitration counter is started. When the counter value exceeds the number of arbitration filter points, the arbitration is determined to have failed. In the slave mode, if there is no SCL transition for 1 consecutive second, the mode switch is triggered. The dynamic role switching unit, based on the wired-AND mechanism and readback detection mechanism of the dynamic arbitration unit, is responsible for the initial allocation of host and slave roles when the system starts up and the execution of role switching during operation. The slave data synchronization unit captures the complete timing data of the SCL / SDA bus in real time in slave mode and seamlessly takes over bus control when switching to master mode.

2. A multi-master IIC bus control system according to claim 1, wherein, The multiple host nodes are FPGA chip A and FPGA chip B, which are redundant with each other.

3. A multi-master IIC bus control system according to claim 1, wherein, The number of arbitration filter points is dynamically generated by the following formula: ； Among them, K is the fault tolerance coefficient.

4. A multi-master IIC bus control system according to claim 1, wherein, During the power-on initialization phase, the dynamic role switching unit starts the initialization count, and automatically enters the master mode after completing the 1-second count, taking over the IIC bus control. At the same time, when another master node detects a change in SCL, it actively enters the slave mode. During operation, the master node in master mode switches from master mode to slave mode and releases bus control if the arbitration fails, based on the arbitration result of the bus. In slave mode, the master node determines the switch from slave mode to master mode based on the real-time detection of the SCL bus status. If there is no SCL transition after 1 second of bus idle timeout, the master node can then control the bus.

5. A multi-master IIC bus control system according to claim 1, wherein, When the slave data synchronization unit switches to master mode, it directly reads the latest cached bus timing data and performs zero-latency bus takeover.

6. A multi-master IIC bus dynamic arbitration method using the system according to any one of claims 1 to 5, characterized in that, Includes the following steps: S101. The parameter configuration unit calculates the number of arbitration filter points of the dynamic arbitration unit and sends the number of arbitration filter points to the dynamic arbitration unit. S102. The dynamic arbitration unit compares the output level with the bus readback level in real time in master mode. If they are inconsistent, the arbitration count is started. When the count exceeds the number of arbitration filter points, the arbitration is determined to be unsuccessful and the unit switches to slave mode. In slave mode, if there is no SCL transition within 1 second, the unit switches to master mode. S103, The dynamic role switching unit selects and switches roles based on the power-on status and the arbitration result of the dynamic arbitration unit; During power-on initialization, the FPGA chip node that completes the 1-second count first becomes the master, and other nodes become slaves after detecting the SCL transition. During operation, a master-slave switch is triggered based on arbitration failure or bus idle timeout. S104. According to the role allocation result of the dynamic role switching unit, the FPGA chip in slave mode continuously captures and caches the complete timing data of the SCL / SDA bus. When switching to the host, bus control is seamlessly taken over based on cached data.

7. A multi-master IIC bus dynamic arbitration method according to claim 8, characterized in that, After switching from master mode to slave mode, the master immediately releases bus control and enters data listening state.

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