Electronic devices and motherboards

Abstract

This application discloses an electronic device and a motherboard, relating to the field of electronic technology. The electronic device includes a connector, a path switching switch, and a processor chip. This application incorporates a path switching switch within the electronic device. The path switching switch has a second data transmission pin coupled to a first data transmission pin of the connector, and third and fourth data transmission pins coupled to different interfaces of the processor chip, respectively. Furthermore, the selection pin of the path switching switch is coupled to a power supply pin of the connector when the electronic device is not in host mode. This allows power to be supplied to the internal components of the electronic device via the power supply pin when it is not in host mode, providing a control signal for switching data paths to the path switching switch.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an electronic device and a motherboard. Background Technology

[0002] Typically, a processor chip includes different interfaces, such as functional interfaces for implementing its design tasks (e.g., communication, data processing, peripheral control, etc.) and debug interfaces for technicians to debug the chip.

[0003] In related technologies, after the processor chip is assembled into an electronic device, the connector in the electronic device used for external interaction is connected to the functional interface of the processor chip, thereby facilitating the use of the functional interface.

[0004] However, in the above scheme, due to the limited number of pins inside the connector, the debugging interface used by technicians is usually not connected to the connector again, which makes it inconvenient to use the debugging interface. Summary of the Invention

[0005] This application provides an electronic device and a motherboard. The technical solution provided by this application is as follows: According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including a connector, a path switching switch and a processor chip; The connector includes a power supply pin and a first data transmission pin; the path switching switch includes a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a selection pin; and the processor chip includes a first interface and a second interface. The first data transmission pin and the second data transmission pin are coupled; When the electronic device is not in host mode, the power supply pin and the selection pin are coupled. The third data transmission pin is coupled to the first interface, and the fourth data transmission pin is coupled to the second interface.

[0006] According to one aspect of the embodiments of this application, a motherboard is provided, the motherboard including a connector and a path switching switch; The connector includes a power supply pin and a first data transmission pin, and the path switching switch includes a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a selection pin; The first data transmission pin and the second data transmission pin are coupled; When the motherboard is not in host mode, the power supply pin and the selection pin are coupled, and the first data transmission pin and the second data transmission pin are coupled. The third data transmission pin is used to couple with the first interface of the processor chip, and the fourth data transmission pin is used to couple with the second interface of the processor chip.

[0007] The technical solutions provided in this application have at least the following beneficial effects: By incorporating a path switching switch within the electronic device, which has a second data transmission pin coupled to a first data transmission pin of the connector, and third and fourth data transmission pins coupled to different interfaces of the processor chip respectively, and by configuring the selection pin of the path switching switch to be coupled to the power supply pin of the connector when the electronic device is not in host mode, power can be supplied to the internal components of the electronic device via the power supply pin even when it is not in host mode, providing the path switching switch with the control signal for switching data paths. In summary, the above hardware design supports switching data paths from the first data transmission pin of the connector to different interfaces of the processor chip based on the operating mode of the electronic device, thereby facilitating the use of different interfaces of the processor chip. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the host mode and slave device mode provided in one embodiment of this application; Figure 2 This is a schematic diagram of an electronic device provided in one embodiment of this application; Figure 3 This is a schematic diagram of an electronic device provided in another embodiment of this application; Figure 4 This is a schematic diagram of an electronic device provided in another embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0010] On current electronic devices, debugging interfaces such as UART (Universal Asynchronous Receiver / Transmitter) interfaces and firmware loading interfaces are generally easy to debug in the single-board stage, as they can be connected via jumper wires or dedicated sockets. However, once the single boards are assembled into a complete device, the number of exposed interfaces is usually limited, and due to industrial design and other reasons, it is generally inconvenient to provide debugging interfaces on the casing. This makes it difficult to use debugging interfaces after the single boards are assembled into a complete device.

[0011] Please refer to Figure 1In a link containing electronic device 100 and external device 200, when electronic device 100 is working normally, it is usually in master mode, and the external device 200 connected to it is in slave mode. In this case, electronic device 100 is responsible for supplying power to external device 200 and actively initiating communication. When using external device 200 to debug electronic device 100, electronic device 100 is usually in slave mode, and external device 200 used for debugging is in master mode. In this case, external device 200 is responsible for supplying power to electronic device 100 and actively initiating communication.

[0012] To address the inconvenience of using the aforementioned debugging interface, this application improves the interface circuit of the electronic device 100, enabling the electronic device 100 to automatically switch its internal data path to the processor chip's debugging interface based on the voltage supplied by the external device 200 to the power supply pin of the connector when it is not in host mode. This will be explained in more detail in the following embodiments.

[0013] Please refer to Figure 2 The diagram illustrates an electronic device 100 provided in one embodiment of this application. The electronic device 100 includes a connector 10, a path switching switch 20, and a processor chip 30.

[0014] Connector 10 is a device for direct connection to external devices. For example, connector 10 can be a USB Type-C (Universal Serial Bus Type-C) interface connector.

[0015] The path switching switch 20 is used to switch the data path inside the electronic device 100. For its specific function, please refer to the following embodiment, which will not be repeated here.

[0016] The processor chip 30 can be any type of processor chip, such as a SoC (System on Chip), a CPU (Central Processing Unit) chip, or a GPU (Graphics Processing Unit) chip, etc. This application does not limit it in this regard.

[0017] Connector 10 includes a power supply pin 11 and a first data transmission pin 12; the path switching switch 20 includes a second data transmission pin 21, a third data transmission pin 22, a fourth data transmission pin 23 and a selection pin 24; and the processor chip 30 includes a first interface 31 and a second interface 32.

[0018] Power supply pin 11 is used for power supply. For example, when the electronic device 100 is in host mode, power supply pin 11 is used to transmit the voltage supplied by the electronic device 100 to an external device. When the electronic device 100 is in slave mode or charging state, power supply pin 11 is used to transmit the voltage provided by the external device to the internal components of the electronic device. For example, power supply pin 11 is a USB VBUS pin.

[0019] Select pin 24 as the pin used to control the path switching switch 20 to switch the data path.

[0020] The first interface 31 and the second interface 32 are different interfaces of the processor chip 30. For example, the first interface 31 belongs to the debugging interface described above, and the second interface 32 belongs to the functional interface described above.

[0021] Optionally, the first interface 31 can be a debugging interface such as a UART interface or a firmware loading interface. The UART interface transmits data serially via TX (transmit) and RX (receive) signal lines. The firmware loading interface is used to download or update firmware for the processor chip 30.

[0022] Optionally, the second interface 32 is a data transmission interface that supports the transmission of differential signals. For example, the second interface is a DP (Data Positive) / DM (Data Minus) interface, which transmits differential signals to transmit data through a pair of differential signal lines, namely the DP signal line and the DM signal line. Of course, the second interface 32 can also be any other interface related to the function of the processor chip.

[0023] In this embodiment, when the electronic device is in host mode, the DP / DM and other functional interfaces of the processor chip can be selected normally. When the electronic device is not in host mode, the selected chip interface can be switched to debugging interfaces such as UART interface or firmware loading interface. This makes it easier to perform debugging work such as data testing and firmware download and update while ensuring the execution of the processor chip's design tasks.

[0024] The first data transmission pin 12 and the second data transmission pin 21 are coupled. Optionally, the first data transmission pin 12 and the second data transmission pin 21 are connected.

[0025] When the electronic device 100 is not in host mode, the power supply pin 11 and the selection pin 24 are coupled.

[0026] The host mode mentioned above refers to the working mode that is responsible for supplying power to external devices and actively initiating communication. For example, USBhost (USB host) mode.

[0027] In some embodiments, the electronic device 100 not being in host mode may include the following situations: the electronic device 100 is in slave mode or the electronic device 100 is in a charging state.

[0028] The aforementioned slave device mode refers to the working mode of being the power recipient and the responder to communication requests, such as the USB device mode.

[0029] The electronic device 100 is in a charging state, that is, the external device connected to the connector 10 of the electronic device 100 is a charger or power adapter that does not support data interaction and only provides charging function.

[0030] The third data transmission pin 22 is coupled to the first interface 31, and the fourth data transmission pin 23 is coupled to the second interface 32.

[0031] Optionally, the third data transmission pin 22 is connected to the first interface 31, and the fourth data transmission pin 23 is connected to the second interface 32.

[0032] Additionally, it should be noted that the "coupling" relationship described in this application refers to the relationship between different objects to achieve functions such as information transmission, energy transmission, or signal control. That is to say, it can include direct physical connection or indirect energy (such as voltage) and signal connection achieved through circuit design. This application does not limit this relationship.

[0033] For example, a first data transmission pin 12 and a second data transmission pin 21 are coupled, and data transmission is supported between the first data transmission pin 12 and the second data transmission pin 21. When the electronic device 100 is not in host mode, a power supply pin 11 and a selection pin 24 are coupled, and the voltage at the selection pin 24 is generated based on the voltage at the power supply pin 11. For example, the voltage at the selection pin 24 is obtained by stepping down the voltage at the power supply pin 11 through multiple devices. A third data transmission pin 22 is coupled to a first interface 31, and data transmission is supported between the third data transmission pin 22 and the first interface 31. A fourth data transmission pin 23 is coupled to a second interface 32, and data transmission is supported between the fourth data transmission pin 23 and the second interface 32.

[0034] For example, when the electronic device 100 is in host mode, the power supply pin 11 and the select pin 24 are not coupled, and the voltage at the select pin 24 is a fixed level, such as 0 level, which is independent of the voltage at the power supply pin 11.

[0035] In some embodiments, the path switching switch 20 is used to select an enabled data path from a first data path and a second data path based on the voltage at the selection pin 24.

[0036] The first data path is the data path between the second data transmission pin 21 and the third data transmission pin 22, and the second data path is the data path between the second data transmission pin 21 and the fourth data transmission pin 23.

[0037] In some embodiments, the path switching switch 20 is configured to enable a first data path when the voltage at the selection pin 24 meets a first condition, and to enable a second data path when the voltage at the selection pin 24 meets a second condition.

[0038] The first and second conditions are different voltage conditions, which can be set by a technician as needed. For example, the first condition is that the voltage at select pin 24 is level 1, and the second condition is that the voltage at select pin 24 is level 0. Alternatively, the first condition may be that the voltage at select pin 24 belongs to one voltage range, and the second condition may be that the voltage at select pin 24 belongs to another voltage range. This application does not limit this.

[0039] Please refer to Figure 1 Because the first data transmission pin 12 is coupled to the second data transmission pin 21, the third data transmission pin 22 is coupled to the first interface 31, and the fourth data transmission pin 23 is coupled to the second interface 32, when the path switching switch 20 enables the first data path, the first data transmission pin 12 will be coupled to the first interface 31, thereby establishing a data path from the first interface 31 to an external device. When the path switching switch 20 enables the second data path, the second data transmission pin 21 will be coupled to the second interface 32, thereby establishing a data path from the second interface 32 to an external device. Therefore, by adopting the above scheme, only one path switching switch 20 is needed to switch the data paths between the internal pins, enabling selective use of different interfaces of the processor chip 30, resulting in low implementation complexity. Furthermore, in operating modes other than host mode, the voltage at the selection pin 24 of the path switching switch 20 is provided by the power supply pin 11, thereby enabling the switching of data paths by utilizing the characteristic of external devices supplying power to electronic device 100 in non-host mode. The logic is simple and does not require complex control devices such as EC (Embedded Controller) or other MCU (Microcontroller Unit) devices.

[0040] The technical solution provided in this application embodiment includes a path switching switch in the electronic device. This switch has a second data transmission pin coupled to a first data transmission pin of the connector, and third and fourth data transmission pins coupled to different interfaces of the processor chip, respectively. Furthermore, the selection pin of the path switching switch is coupled to the power supply pin of the connector when the electronic device is not in host mode. This allows power to be supplied to the internal components of the electronic device via the power supply pin when it is not in host mode, providing a control signal for switching the data path to the path switching switch. In summary, the above hardware design supports switching the data path from the first data transmission pin of the connector to different interfaces of the processor chip according to the operating mode of the electronic device, thereby facilitating the use of different interfaces of the processor chip.

[0041] Optionally, this application uses an over-voltage protection (OVP) circuit to control whether the power supply pin and the selection pin are coupled, which will be described in the following embodiments.

[0042] In some embodiments, please refer to Figure 3 The electronic device 100 also includes an overvoltage protection circuit 40, which includes a first voltage input pin 41 and a first voltage output pin 42.

[0043] The power supply pin 11 is coupled to the first voltage input pin 41, and the first voltage output pin 42 is coupled to the selection pin 24.

[0044] Optionally, power supply pin 11 is connected to the first voltage input pin 41, and the first voltage output pin 42 is connected to the selection pin 24. Optionally, the electronic device 100 also includes a step-down circuit. Figure 3 (not shown in the image) The first voltage output pin 42 is connected to one end of the buck circuit, and the other end of the buck circuit is connected to the selection pin 24. The buck circuit is used to achieve the function of bucking down the voltage.

[0045] The overvoltage protection circuit 40 is used to transfer the voltage at the first voltage input pin 41 to the first voltage output pin 42 when the electronic device 100 is not in host mode and the voltage at the first voltage input pin 41 is less than or equal to a first set threshold.

[0046] For example, if the first set threshold is 5V or 5.5V, the overvoltage protection circuit 40 will transfer the 5V voltage to the first voltage output pin 42 when the electronic device 100 is not in host mode and the voltage at the first voltage input pin 41 is 5V.

[0047] Optionally, when an external device supplies power to the electronic device 100 through the power supply pin of connector 10, and the voltage at the first voltage input pin 41 is less than or equal to the first set threshold, after the overvoltage protection circuit 40 transmits the voltage at the first voltage input pin 41 to the first voltage output pin 42, the voltage at the first voltage output pin 42 is stepped down by the aforementioned step-down circuit, so that a voltage satisfying the first condition is generated at the selection pin 24.

[0048] In some embodiments, when the electronic device 100 is not in host mode, the overvoltage protection circuit 40 can implement overvoltage protection through either Scheme 1 or Scheme 2 as follows: Option 1: If the voltage at the first voltage input pin 41 is greater than the first set threshold, disconnect the electrical path between the first voltage input pin 41 and the first voltage output pin 42.

[0049] Option 2: If the voltage at the first voltage input pin 41 is greater than the first set threshold, the voltage is reduced to a level less than the first set threshold at the first voltage output pin 42.

[0050] The aforementioned first threshold value is set by technical personnel as needed. Optional, please refer to... Figure 4 The overvoltage protection circuit 40 also includes a first OVLO (Overvoltage Lockout) pin 44, and the aforementioned electronic device 100 also includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is coupled to ground, and the other end of the first resistor R1 is coupled to both the first OVLO pin 44 and one end of the second resistor R2. The other end of the second resistor R2 is coupled to the first voltage input pin 41. A technician can set a first preset threshold by configuring the resistance values ​​of the first resistor R1 and the second resistor R2.

[0051] In some embodiments, when the electronic device 100 is in host mode, the overvoltage protection circuit 40 is inactive, meaning the electrical path between the first voltage input pin 41 and the first voltage output pin 42 is directly shut off. Therefore, the voltage at the selection pin 24 is unaffected by the voltage at the power supply pin 11 and remains at a fixed level (e.g., 0 level), consistently satisfying the second condition.

[0052] In the above embodiment, when the electronic device 100 is not in host mode, the overvoltage protection circuit 40 will limit the voltage at the first voltage output pin 42 to be less than the first set threshold, thereby ensuring that the voltage provided by the first voltage output pin 42 to the downstream device is within a safe range, and avoiding damage to the downstream device caused by the original voltage output by the power supply pin 11.

[0053] In some embodiments, please refer to Figure 4The electronic device 100 also includes a debugging circuit 50, which includes a fifth data transmission pin 51 and a sixth data transmission pin 52.

[0054] The first data transmission pin 12, the second data transmission pin 21, the third data transmission pin 22, the fourth data transmission pin 23, the fifth data transmission pin 51, and the second interface 32 support the transmission of data in the first format, while the sixth data transmission pin 52 and the first interface 31 support the transmission of data in the second format.

[0055] The first and second formats mentioned above are different data transmission formats.

[0056] For example, if the first data transmission pin 12, the second data transmission pin 21, the third data transmission pin 22, the fourth data transmission pin 23, and the fifth data transmission pin 51 all belong to the DP / DM pin, the second interface 32 is the DP / DM interface, the sixth data transmission pin 52 belongs to the UART pin, and the first interface 31 is the UART interface, then the first format is a differential signal format transmitted through differential signal lines, and the second format is a serial signal format transmitted through a single TX / RX signal line.

[0057] The third data transmission pin 22 is coupled to the fifth data transmission pin 51, and the sixth data transmission pin 52 is coupled to the first interface 31.

[0058] Optionally, the third data transmission pin 22 and the fifth data transmission pin 51 are connected, and the sixth data transmission pin 52 is connected to the first interface 31.

[0059] The debugging circuit 50 is used to convert the data received by the fifth data transmission pin 51 from the first format to the second format and then output it from the sixth data transmission pin 52; or, to convert the data received by the sixth data transmission pin 52 from the second format to the first format and then output it from the fifth data transmission pin 51.

[0060] In the above embodiment, when the data format transmitted by the first interface 31 is inconsistent with the data format transmitted by the second interface 32, the electronic device 100 will set up a debugging circuit 50 to perform format conversion. In this way, when the interface of the processor chip connected to the data path is switched from the second interface 32 to the first interface 31, it is ensured that each interface will not receive an unprocessable data format during data transmission. Thus, when the first interface 31 is a debugging interface, it is ensured that the debugging data is delivered and output smoothly.

[0061] Additionally, it should be noted that the aforementioned debugging circuit 50 can be selectively configured according to the type of the first interface 31. That is to say, if the data format supported by the first interface 31 is consistent with the data format supported by the second interface 32 and the first data transmission pin 12, then there is no need to configure the debugging circuit 50 for performing format conversion.

[0062] In some embodiments, please refer to Figure 4 The debugging circuit 50 also includes a first voltage pin 53 and a second voltage pin 54.

[0063] The first voltage output pin 42 is coupled to the first voltage pin 53, and the second voltage pin 54 is coupled to the select pin 24.

[0064] Optionally, the first voltage output pin 42 and the first voltage pin 53 are connected, and the second voltage pin 54 is connected to the select pin 24.

[0065] The voltage at the second voltage pin 54 is related to the voltage at the first voltage pin 53. Optionally, the voltage at the second voltage pin 54 is derived from the voltage at the first voltage pin 53.

[0066] In some embodiments, the first voltage pin 53 is a power input pin of the debugging circuit 50 for supplying power to its internal regulator; it is used to receive external voltage. For example, the first voltage pin 53 may be the VREGIN pin. The second voltage pin 54 is the operating voltage pin of the debugging circuit 50, which is used to provide a stable operating voltage converted from the internal regulator.

[0067] Optionally, when an external device supplies power to the electronic device 100 through the power supply pin of connector 10, and the voltage at the first voltage input pin 41 is less than or equal to the first set threshold, after the overvoltage protection circuit 40 transmits the voltage at the first voltage input pin 41 to the first voltage output pin 42, the debugging circuit 50 converts the voltage at the first voltage pin 53 into a working voltage output from the second voltage pin 54, which causes the selection pin 24 to generate a voltage that satisfies the first condition.

[0068] Optionally, the electronic device 100 further includes a third resistor R3. One end of the third resistor R3 is connected to the second voltage pin 54, and the other end is connected to the selection pin 24. After the operating voltage is stepped down by the third resistor R3, a voltage satisfying the first condition is generated at the selection pin 24.

[0069] In the above embodiment, the voltage at the first voltage output pin 42 is not directly transmitted to the selection pin 24, but is processed by the debugging circuit 50 before being transmitted to the selection pin 24. On the one hand, the voltage provided by an external device through the power supply pin 11 can be used to power the debugging circuit 50, eliminating the need for a separate power supply for the debugging circuit 50. On the other hand, the function of the debugging circuit 50 in processing the external voltage into the operating voltage can be fully utilized, simplifying subsequent voltage drop or voltage regulation design.

[0070] In addition, this application supports the control of multiple devices inside the electronic device 100 by reusing a single power supply controller, which will be described in detail in the following embodiments.

[0071] In some embodiments, please refer to Figure 4 The electronic device 100 also includes a power supply controller 60, which includes a first enable signal transmitting pin 61, and the overvoltage protection circuit 40 also includes a first enable signal receiving pin 43.

[0072] The first enable signal transmitting pin 61 and the first enable signal receiving pin 43 are coupled.

[0073] Optionally, the first enable signal transmitting pin 61 and the first enable signal receiving pin 43 are connected.

[0074] The power supply controller 60 is used to output a first enable signal via a first enable signal transmission pin 61 when the electronic device 100 is in host mode.

[0075] The overvoltage protection circuit 40 is used to disconnect the electrical path between the first voltage input pin 41 and the first voltage output pin 42 when a first enable signal is received.

[0076] The overvoltage protection circuit 40 is also used to transfer the voltage at the first voltage input pin 41 to the first voltage output pin 42 when no first enable signal is received and the voltage at the first voltage input pin 41 is less than or equal to the first set threshold.

[0077] In other words, the first enable signal is used to turn off, or to activate, the overvoltage protection circuit 40.

[0078] In some embodiments, the power controller 60 is a USB PD (Power Delivery) controller chip.

[0079] In some embodiments, the power supply controller 60 further includes control pins ( Figure 4 (Not shown in the image), connector 10 also includes a CC (Configuration Channel) pin ( Figure 4(Not shown in the image) The power supply controller 60 confirms the operating mode (master mode, slave mode, or charging state) of the electronic device 100 by receiving information transmitted from the CC pin at the monitoring control pin. Of course, technicians can also inform the power supply controller 60 of the operating mode through other settings in the electronic device 100 as needed, and this application does not limit this.

[0080] In the above embodiment, the power supply controller 60 will actively shut down the overvoltage protection circuit 40 when the electronic device 100 is in host mode, thereby preventing the data path from the first data transmission pin 12 to the first interface 31 from being incorrectly opened because the electronic device 100 supplies power to external devices through the power supply pin 11 in host mode.

[0081] In some embodiments, please refer to Figure 4 The power supply controller 60 also includes a second enable signal transmitting pin 62, and the electronic device 100 also includes a first load switch 70 and a voltage conversion circuit 80. The first load switch 70 includes a second voltage input pin 71, a second voltage output pin 72, and a second enable signal receiving pin 73.

[0082] The second enable signal transmitting pin 62 is coupled to the second enable signal receiving pin 73, the power supply pin 11 is coupled to the second voltage input pin 71, and the second voltage output pin 72 is coupled to the input terminal 81 of the voltage conversion circuit 80.

[0083] Optionally, the second enable signal transmitting pin 62 and the second enable signal receiving pin 73 are connected, the power supply pin 11 and the second voltage input pin 71 are connected, and the second voltage output pin 72 is connected to the input terminal 81 of the voltage conversion circuit 80.

[0084] The power supply controller 60 is also configured to output a second enable signal via the second enable signal transmission pin 62 when the electronic device 100 is in slave mode.

[0085] Optionally, the power supply controller 60 is also configured to output a second enable signal via the second enable signal transmission pin 62 when the electronic device 100 is in a charging state.

[0086] The first load switch 70 is used to transmit the voltage at the second voltage input pin 71 to the second voltage output pin 72 when a second enable signal is received and the voltage at the second voltage input pin 71 is within a first set range.

[0087] The first load switch 70 is a switch used to control the on / off of the power supply path from external devices to electronic device 100. For example, the first load switch 70 is a VBUS Sink load switch.

[0088] In some embodiments, the first load switch 70 is in a closed or inactive state and does not perform voltage transmission when it does not receive the second enable signal. That is to say, the second enable signal is an enable signal used to activate the first load switch 70.

[0089] The first set range is a safe voltage range configured by a technician for transmission to the voltage conversion circuit 80, which is not limited in this application.

[0090] For example, the first load switch 70 is used to disconnect the electrical path between the second voltage input pin 71 and the second voltage output pin 72 when a second enable signal is received and the voltage at the second voltage input pin 71 is not within the first set range.

[0091] For example, the first load switch 70 is used to output a voltage within the first set range at the second voltage output pin 72 when a second enable signal is received and the voltage at the second voltage input pin 71 is not within the first set range.

[0092] In some embodiments, the first load switch 70 further includes a second OVLO pin 74, which is grounded to maintain the use of a first set range configured inside the first load switch 70.

[0093] The voltage conversion circuit 80 is used to convert the voltage at the input terminal 81 into a set voltage, which is used to power the set device. Optionally, the voltage conversion circuit 80 can be a buck circuit, such as a BUCK circuit.

[0094] Based on the design requirements of the technicians, the device can be set to any device inside the electronic device 100 based on the design of the hardware connection relationship, such as an energy storage device for storing electrical energy, a logic device for performing logical behavior, etc. This application does not limit it.

[0095] In the above embodiment, the power supply controller 60 is also used to activate the first load switch 70 by sending a second enable signal, thereby ensuring that the electronic device 100 can normally rely on external devices for power supply when it is in slave device mode.

[0096] In some embodiments, please refer to Figure 4 The electronic device 100 also includes a second load switch 90, which includes a third voltage output pin 91 and a third enable signal receiving pin 92.

[0097] The first enable signal transmitting pin 61 is coupled to the third enable signal receiving pin 92, and the power supply pin 11 is coupled to the third voltage output pin 91.

[0098] Optionally, the first enable signal transmitting pin 61 and the third enable signal receiving pin 92 are connected, and the power supply pin 11 and the third voltage output pin 91 are connected.

[0099] The second load switch 90 is used to provide a voltage within a second set range via the third voltage output pin 91 when a first enable signal is received.

[0100] The second load switch 90 is a switch used to control the on / off of the power supply path from the electronic device 100 to external devices. For example, the second load switch 90 is a VBUS Source load switch.

[0101] In some embodiments, the second load switch 70 is in a closed or inactive state when it does not receive the first enable signal, and does not supply voltage to the power supply pin 11. That is to say, the first enable signal is both an enable signal for turning off the overvoltage protection circuit 40 and an enable signal for activating the second load switch 90.

[0102] The second setting range is a safe voltage range configured by a technician to be transmitted to the power supply pin 11, which is not limited in this application.

[0103] In some embodiments, the second load switch 90 generates a voltage within a second preset range via its internal power supply. In other embodiments, the electronic device 100 further includes a power supply connected to the second load switch 90, which converts the voltage supplied by that power supply into a voltage within the second preset range.

[0104] In the above embodiment, the enable signal (i.e. the first enable signal) of the second load switch 90 controlled by the power supply controller 60 is used to turn off the overvoltage protection circuit 40. This avoids the incorrect use of the first interface 31 in host mode, and eliminates the need to introduce additional control devices, resulting in lower implementation costs.

[0105] In some embodiments, the power supply controller 60 further includes a regulator output pin 63, and the path switching switch 20 further includes a third voltage pin 25.

[0106] Optionally, regulator output pin 63 is an LDO3V3 pin used to output a stable 3.3V voltage, and third voltage pin 25 is the operating voltage pin of the path switching switch 20, such as the VDD pin.

[0107] The regulator output pin 63 is coupled to the third voltage pin 25.

[0108] Optionally, the regulator output pin 63 and the third voltage pin 25 are connected.

[0109] The power supply controller 60 is also used to provide operating voltage to the path switching switch 20 via the regulator output pin 63.

[0110] In the above embodiment, the power supply controller 60 is also used to provide a stable operating voltage for the path switching switch 20, thereby making fuller use of the function of the power supply controller 60 and further saving hardware costs.

[0111] In some embodiments, please refer to Figure 4 The path switching switch 20 also includes an OE (Output Enable) pin 26, which controls whether the path switching switch 20 performs an output. Optionally, the OE pin 26 is grounded to keep the path switching switch 20 in the working state.

[0112] In summary, the technical solution provided by the embodiments of this application does not rely on MCU devices such as ECs. Through pure hardware design, it is possible to conveniently use different interfaces of the processor chip (such as functional interfaces and debugging interfaces) according to different usage scenarios. In the following embodiments, based on Figure 4 The electronic device 100 shown is illustrated by way of example in different cases.

[0113] Case 1: Electronic device 100 is connected to the host computer and is in a debugging state.

[0114] In this situation, the electronic device 100 is in slave mode, and the power supply pin 11 of the connector 10 receives a 5V voltage output from the host computer. This 5V voltage is less than the first set threshold of 5.5V. Therefore, the electrical path between the first voltage input pin 41 and the first voltage output pin 42 of the overvoltage protection circuit 40 is opened, and the 5V voltage is transmitted to the first voltage pin 53 of the debugging circuit 50. After obtaining a stable 5V power supply, the debugging circuit 50 generates a voltage at the second voltage pin 54, so that the selection pin of the path switching switch 20 obtains a voltage that meets the first condition (such as a 1 level), thereby controlling the path switching switch 20 to enable the data path between the second data transmission pin 21 and the third data transmission pin 22. Since the debugging circuit 50 can realize data format conversion, the host computer can use the first interface 31 through the first data transmission pin 12 of the connector 10 to realize the debugging of the processor chip 30.

[0115] Furthermore, in this case, the power supply controller 60 sends a second enable signal to the first load switch 70 through the second enable signal transmission pin 62, so the first load switch 70 supports the transmission of 5V voltage to the subsequent voltage conversion circuit 80 to generate the set voltage for powering the electronic device 100.

[0116] Scenario 2: Electronic device 100 is connected to a charger or power adapter and is in a charging state.

[0117] In this case, the power supply controller 60 sends a second enable signal to the first load switch 70 through the second enable signal transmission pin 62. Therefore, the first load switch 70 supports the transmission of the voltage obtained from the power supply pin 11 to the subsequent voltage conversion circuit 80 within a safe range to generate the set voltage for powering the electronic device 100.

[0118] Furthermore, it should be noted that in this case, if the voltage obtained by the power supply pin 11 is greater than the first set threshold, the overvoltage protection function of the overvoltage protection circuit 40 will be triggered, and the voltage at the first voltage input pin 41 will not be transmitted to the subsequent stage, thereby preventing damage to the subsequent stage devices due to overvoltage. When the voltage obtained by the power supply pin 11 is less than or equal to the first set threshold, referring to case 1, the path switching switch 20 will enable the data path between the second data transmission pin 21 and the third data transmission pin 22. However, since the charger or power adapter itself will not initiate any data transmission, the data path inside the electronic device will not have any effect or impact at this time.

[0119] Scenario 3: Electronic device 100 is being used normally by the user and connected to other USB devices.

[0120] In this case, the electronic device 100 is in host mode, and the power supply controller 60 sends a first enable signal to the second load switch 90 through the first enable signal sending pin 61. Therefore, the second load switch 90 supports supplying a voltage within a safe range to the power supply pin 11 to power the USB device.

[0121] Furthermore, since the first enable signal is also sent to the overvoltage protection circuit 40, the overvoltage protection circuit 40 will be turned off. The voltage supplied by the second load switch 90 to the power supply pin 11 will not affect the voltage at the selection pin 24. The selection pin 24 will obtain a constant voltage that meets the second condition (such as 0 level), thereby enabling the path switching switch 20 to maintain the data path between the second data transmission pin 21 and the fourth data transmission pin 23. Therefore, the electronic device 100 can normally use the second interface 32 of the processor chip 30 to interact with the USB device.

[0122] It should be noted that the structure of the electronic device 100 shown in the accompanying drawings of this application does not constitute a limitation on the components of the electronic device 100. Those skilled in the art should understand that, except... Figures 2 to 4 In addition to the components shown, the electronic device 100 may include more components, which are not limited in this application.

[0123] Optionally, the electronic device 100 may be an electronic device such as a mobile phone, tablet computer, multimedia playback device, PC (Personal Computer), wearable device, vehicle terminal device, VR (Virtual Reality) device, AR (Augmented Reality) device, MR (Mixed Reality) device, micro embedded device, etc., and this application does not limit it.

[0124] One embodiment of this application also provides a motherboard, which includes a connector and a path switching switch.

[0125] The connector includes a power supply pin and a first data transmission pin, and the path switching switch includes a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a selection pin.

[0126] The first data transmission pin and the second data transmission pin are coupled.

[0127] When the motherboard is not in host mode, the power supply pin and the selection pin are coupled, and the first data transmission pin and the second data transmission pin are coupled.

[0128] It should be noted that, in this embodiment of the application, the host mode and slave mode mentioned for the motherboard are similar to the host mode and slave mode mentioned for electronic devices above. The host mode refers to the working mode that is responsible for supplying power to external devices and supporting active communication initiated through the coupled processor chip. The slave mode refers to the working mode that acts as the powered party and supports the coupled processor chip as the responder to communication requests.

[0129] The third data transmission pin is used to couple with the first interface of the processor chip, and the fourth data transmission pin is used to couple with the second interface of the processor chip.

[0130] In some embodiments, the path switching switch is used to select an enabled data path from a first data path and a second data path based on the voltage at the selection pin.

[0131] The first data path is the data path between the second data transmission pin and the third data transmission pin, and the second data path is the data path between the second data transmission pin and the fourth data transmission pin.

[0132] In some embodiments, the motherboard further includes an overvoltage protection circuit, which includes a first voltage input pin and a first voltage output pin.

[0133] The power supply pin is coupled to the first voltage input pin, and the first voltage output pin is coupled to the selection pin.

[0134] The overvoltage protection circuit is used to transfer the voltage at the first voltage input pin to the first voltage output pin when the motherboard is not in the host mode and the voltage at the first voltage input pin is less than or equal to a first set threshold.

[0135] In some embodiments, the motherboard further includes a power supply controller, the power supply controller including a first enable signal transmitting pin, and the overvoltage protection circuit further including a first enable signal receiving pin; the first enable signal transmitting pin and the first enable signal receiving pin are coupled; the power supply controller is configured to output a first enable signal through the first enable signal transmitting pin when the motherboard is in the host mode; the overvoltage protection circuit is configured to disconnect the electrical path between the first voltage input pin and the first voltage output pin when the first enable signal is received.

[0136] In some embodiments, the power supply controller further includes a second enable signal transmitting pin, and the motherboard further includes a first load switch and a voltage conversion circuit. The first load switch includes a second voltage input pin, a second voltage output pin, and a second enable signal receiving pin. The second enable signal transmitting pin and the second enable signal receiving pin are coupled, the power supply pin is coupled to the second voltage input pin, and the second voltage output pin is coupled to the input terminal of the voltage conversion circuit. The power supply controller is further configured to output a second enable signal through the second enable signal pin when the motherboard is in slave mode. The first load switch is configured to transmit the voltage at the second voltage input pin to the second voltage output pin when it receives the second enable signal and the voltage at the second voltage input pin is within a first set range. The voltage conversion circuit is configured to convert the voltage at the input terminal into a set voltage, which is used to power a set device.

[0137] In some embodiments, the motherboard further includes a second load switch, the second load switch including a third voltage output pin and a third enable signal receiving pin; the first enable signal sending pin and the third enable signal receiving pin are coupled, and the power supply pin and the third voltage output pin are coupled; the second load switch is used to provide a voltage within a second set range through the third voltage output pin when the first enable signal is received.

[0138] In some embodiments, the power supply controller further includes a regulator output pin, and the path switching switch further includes a third voltage pin; the regulator output pin and the third voltage pin are coupled; the power supply controller is also configured to provide an operating voltage to the path switching switch through the regulator output pin.

[0139] In some embodiments, the motherboard further includes a debugging circuit, which includes a fifth data transmission pin and a sixth data transmission pin. The first data transmission pin, the second data transmission pin, the third data transmission pin, the fourth data transmission pin, the fifth data transmission pin, and the second interface support the transmission of data in a first format, and the sixth data transmission pin and the first interface support the transmission of data in a second format.

[0140] The third data transmission pin is coupled to the fifth data transmission pin, and the sixth data transmission pin is used to couple with the first interface.

[0141] The debugging circuit is used to convert the data received by the fifth data transmission pin from the first format to the second format and then output it from the sixth data transmission pin; or, to convert the data received by the sixth data transmission pin from the second format to the first format and then output it from the fifth data transmission pin.

[0142] In some embodiments, the motherboard further includes an overvoltage protection circuit, which includes a first voltage input pin and a first voltage output pin. The debugging circuit further includes a first voltage pin and a second voltage pin. The power supply pin is coupled to the first voltage input pin, the first voltage output pin is coupled to the first voltage pin, and the second voltage pin is coupled to the selection pin. The voltage at the second voltage pin is related to the voltage at the first voltage pin.

[0143] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0144] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. An electronic device, comprising: The electronic device includes a connector, a path switching switch, and a processor chip; The connector includes a power supply pin and a first data transmission pin; the path switching switch includes a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a selection pin; and the processor chip includes a first interface and a second interface. The first data transmission pin and the second data transmission pin are coupled; When the electronic device is not in host mode, the power supply pin and the selection pin are coupled. The third data transmission pin is coupled to the first interface, and the fourth data transmission pin is coupled to the second interface.

2. The electronic device according to claim 1, characterized in that, The path switching switch is used to select the enabled data path from the first data path and the second data path according to the voltage at the selection pin; The first data path is the data path between the second data transmission pin and the third data transmission pin, and the second data path is the data path between the second data transmission pin and the fourth data transmission pin.

3. The electronic device of claim 1, wherein, The electronic device further includes an overvoltage protection circuit, which includes a first voltage input pin and a first voltage output pin. The power supply pin is coupled to the first voltage input pin, and the first voltage output pin is coupled to the selection pin; The overvoltage protection circuit is used to transfer the voltage at the first voltage input pin to the first voltage output pin when the electronic device is not in the host mode and the voltage at the first voltage input pin is less than or equal to a first set threshold.

4. The electronic device of claim 3, wherein, The electronic device further includes a power supply controller, which includes a first enable signal transmitting pin, and the overvoltage protection circuit further includes a first enable signal receiving pin. The first enable signal transmitting pin and the first enable signal receiving pin are coupled; The power supply controller is configured to output a first enable signal via the first enable signal transmission pin when the electronic device is in the host mode. The overvoltage protection circuit is used to disconnect the electrical path between the first voltage input pin and the first voltage output pin when the first enable signal is received.

5. The electronic device of claim 4, wherein, The power supply controller further includes a second enable signal transmitting pin, and the electronic device further includes a first load switch and a voltage conversion circuit. The first load switch includes a second voltage input pin, a second voltage output pin, and a second enable signal receiving pin. The second enable signal transmitting pin is coupled to the second enable signal receiving pin, the power supply pin is coupled to the second voltage input pin, and the second voltage output pin is coupled to the input terminal of the voltage conversion circuit; The power supply controller is further configured to output a second enable signal via the second enable signal pin when the electronic device is in slave mode; The first load switch is used to transmit the voltage at the second voltage input pin to the second voltage output pin when the second enable signal is received and the voltage at the second voltage input pin is within a first set range; The voltage conversion circuit is used to convert the input voltage into a set voltage, which is used to power a set device.

6. The electronic device of claim 4, wherein, The electronic device further includes a second load switch, which includes a third voltage output pin and a third enable signal receiving pin. The first enable signal transmitting pin is coupled to the third enable signal receiving pin, and the power supply pin is coupled to the third voltage output pin; The second load switch is used to provide a voltage within a second set range through the third voltage output pin when the first enable signal is received.

7. The electronic device of claim 4, wherein, The power supply controller also includes a voltage regulator output pin, and the path switching switch also includes a third voltage pin; The regulator output pin is coupled to the third voltage pin; The power supply controller is also used to provide operating voltage to the path switching switch through the output pin of the voltage regulator.

8. The electronic device of claim 1, wherein, The electronic device further includes a debugging circuit, which includes a fifth data transmission pin and a sixth data transmission pin. The first data transmission pin, the second data transmission pin, the third data transmission pin, the fourth data transmission pin, the fifth data transmission pin, and the second interface support the transmission of data in a first format, while the sixth data transmission pin and the first interface support the transmission of data in a second format. The third data transmission pin is coupled to the fifth data transmission pin, and the sixth data transmission pin is coupled to the first interface; The debugging circuit is used to convert the data received by the fifth data transmission pin from the first format to the second format and then output it from the sixth data transmission pin; or, to convert the data received by the sixth data transmission pin from the second format to the first format and then output it from the fifth data transmission pin.

9. The electronic device according to claim 8, characterized in that, The electronic device further includes an overvoltage protection circuit, which includes a first voltage input pin and a first voltage output pin. The debugging circuit further includes a first voltage pin and a second voltage pin. The power supply pin is coupled to the first voltage input pin, the first voltage output pin is coupled to the first voltage pin, and the second voltage pin is coupled to the selection pin; The voltage at the second voltage pin is related to the voltage at the first voltage pin.

10. The electronic device according to any one of claims 1 to 9, characterized in that, The first interface is a Universal Asynchronous Receiver / Transmitter (UART) interface or a firmware loading interface, and the second interface is a data transmission interface that supports the transmission of differential signals.

11. A motherboard, characterized in that, The motherboard includes a connector and a path switching switch; The connector includes a power supply pin and a first data transmission pin, and the path switching switch includes a second data transmission pin, a third data transmission pin, a fourth data transmission pin, and a selection pin; The first data transmission pin and the second data transmission pin are coupled; When the motherboard is not in host mode, the power supply pin and the selection pin are coupled, and the first data transmission pin and the second data transmission pin are coupled. The third data transmission pin is used to couple with the first interface of the processor chip, and the fourth data transmission pin is used to couple with the second interface of the processor chip.

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