A device and method for expanding multiple nodes using a high-speed parallel bus.

Abstract

This invention relates to the field of power electronics control technology, and more particularly to a device and method for expanding multiple nodes via a high-speed parallel bus. The device includes a chassis, a power board, a main control board, function boards, a backplane, and a backplane. The chassis is a standard 6U chassis, and the power board, main control board, function boards, backplane, and backplane are all housed within the chassis. The backplane has 17 slots, in which the main control board and function boards are located. Slots 1-6 of the backplane form the first physical segment, slots 7-11 form the second physical segment, and slots 12-17 form the third physical segment. The power board employs a dual-board redundancy structure, located at the power supply position within the chassis and positioned on the far left and far right of the backplane. The backplane can be positioned between the various physical segments of the backplane. This invention realizes a device for expanding multiple nodes via a high-speed parallel bus, applicable to control fields requiring high speed, flexibility, high performance, and strong scalability.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, and in particular to a device and method for expanding multiple nodes via a high-speed parallel bus. Background Technology

[0002] With the rise of the power electronics industry, high-voltage, high-capacity power electronic equipment is being used more and more widely, which also places higher demands on the equipment. To better reflect the superior performance of the equipment, a flexible, interface-rich, high-speed, stable, high-precision, and highly expandable control device is needed to meet the control requirements of high voltage, high capacity, and high performance.

[0003] Traditional control system devices typically limit a single device chassis to a maximum of 10 nodes, and the parallel communication frequency is generally no more than 100MHz, requiring an additional synchronization signal bus, which greatly restricts their flexibility and scalability. Therefore, there is an urgent need for a device and method for expanding multiple nodes using a high-speed parallel bus. A control device that is flexible, high-speed, has complete interfaces, high control precision, and strong scalability is of great significance to meeting the requirements of increasingly advanced power electronic equipment. Summary of the Invention

[0004] This invention provides a device and method for expanding a high-speed parallel bus to multiple nodes, realizing high-speed parallel bus communication. The backplane bus adopts a segmented structure, and the segments are bridged by backplane connectors, which solves the problem of insufficient parallel bus driving capability. The device can support up to 17 nodes, and the device chassis also has chassis expansion capability, which greatly improves the expansion capability of nodes. Each bus segment of a single device chassis is independent and can be flexibly configured to meet the application needs of various control scenarios.

[0005] To achieve the above objectives, the present invention employs the following technical solution: A high-speed parallel bus expansion multi-node device includes a device chassis, a power board, a main control board, function boards, a backplane, and a back panel. The device chassis is a standard 6U chassis, which provides physical support for the power board, main control board, function boards and backplane. The power board, main control board, function boards, backplane and back panel are all installed inside the device chassis. The backplane has 17 slots, and the main control board and function boards are installed in the slots of the backplane. The backplane serves as a connection channel between the power board, the main control board, and the function boards. Slots 1 to 6 of the backplane are the first physical segment, slots 7 to 11 are the second physical segment, and slots 12 to 17 are the third physical segment. The power board adopts a dual-board redundant structure, and is respectively located in the power supply position inside the device chassis and is located on the far left and far right of the back panel. It is connected to the back panel and is used to power the entire device. The main control board serves as the master node and is the core of the entire device's communication. It is connected to the backplane and can be installed in slots 3, 8, and 13 of the device chassis. The functional board acts as a slave node, providing various functional interfaces and is connected to the backplane. The functional board can be set in any slot of the backplane. The backplate can be positioned between the physical segments of the backplate, connecting the backplate segment parallel bus, and can be inserted into the 2nd, 7th, 9th, and 14th slots of the backplate from the back.

[0006] Furthermore, the main control board adopts a DSP+FPGA control architecture. The DSP provides data processing computing power to the entire device, and the FPGA is configured to realize high-speed parallel differential bus (Buslvds) communication and control and synchronize each slave node in the system. At least one main control board is set in the device chassis.

[0007] Furthermore, the functional board uses an FPGA as the control core and interacts with the master node via a high-speed differential bus (Buslvds). The functional board is equipped with one or more of the following: a high-speed fiber optic communication expansion interface, a data acquisition interface, an analog acquisition interface, an analog output interface, an FT3 communication interface, an Ethernet communication interface, a CAN communication interface, an RS485 communication interface, and a GPS time synchronization interface.

[0008] Furthermore, the backplane provides a physical channel for high-speed parallel Buslvds communication. The backplane adopts a dual-bus redundant structure and provides a shared clock for each node.

[0009] Furthermore, the backplane serves as a bridging module between the various physical segments of the backplane, enhancing the parallel bus driving capability and enabling backplane data flow switching. A method for expanding multiple nodes using a high-speed parallel bus includes the following steps: S1. The main control board acts as the master node, and completes the packaging, distribution, unpacking and repacking of data through the DSP chip. The FPGA communicates with the DSP through the rapidio interface and is responsible for the high-speed parallel Buslvds bus data control, distribution and receiving of data from each slave node. The communication frequency is 100MHz to 150MHz and the data bit width is 16bit or 32bit. S2. The functional board acts as a slave node, controlling the high-speed parallel Buslvds bus data through the FPGA to summarize the high-speed fiber optic extended data, the collected analog data, digital data, Ethernet data, CAN bus data, and RS485 bus data, and finally send them to the master node through the Buslvds bus. S3. The backplane serves as the communication channel for the Buslvds bus, with dual buses and dual clock sources. It defines 17 slots, which are divided into three physical segments: slots 1-6 are the first physical segment, slots 7-11 are the second physical segment, and slots 12-17 are the third physical segment. The backplane bridges the physical segments, and the connection between the different physical segments of the backplane enables the master node to access all slave nodes, thereby maximizing the expansion of nodes. S4. The back panel uses FPGA as the control core to realize high-speed parallel bus data switching and bus drive enhancement; bridging relay is completed through at least two back panels, so that the number of nodes in a single device chassis can be expanded to 17.

[0010] Furthermore, the backplane is configured with physical and logical segments, with each logical segment independently forming a subsystem containing master and slave nodes, specifically including the following scenarios: 1) In the first scenario, there is no back panel connected between the three physical segments, and the three physical segments are three logical segments; 2) The second scenario involves connecting a back panel. A back panel is connected between the first physical segment and the second physical segment, but not between the second physical segment and the third physical segment. Alternatively, a back panel is not connected between the first physical segment and the second physical segment, but is connected between the second physical segment and the third physical segment, thus dividing the three physical segments into two logical segments. 3) The third scenario involves connecting two backplanes. One backplane is inserted between the first physical segment and the second physical segment, and another backplane is inserted between the second physical segment and the third physical segment. The three physical segments are combined into a logical segment, and the entire chassis is treated as a whole.

[0011] Furthermore, the device chassis has expansion capabilities, with the main chassis and slave chassis connected via high-speed optical fiber to form a large-scale control system with multiple chassis cascaded.

[0012] Compared with the prior art, the beneficial effects of the present invention are: This invention relates to a high-speed parallel bus expansion device for multiple nodes. It employs a master-slave bus topology, using an FPGA as the core communication device to achieve high-speed parallel bus communication. Each slave node synchronizes data with the master node, and all nodes share a backplane clock. By adjusting the sampling clock phase, the bus bandwidth reaches a 125MHz main frequency and a 32-bit data width. The backplane bus adopts a segmented structure, with segments bridged by backplane connectors, solving the problem of insufficient parallel bus driving capability. The device can support up to 17 nodes, and the chassis also has expansion capabilities, greatly improving node scalability. Each bus segment in a single chassis is independent and flexibly configurable to meet various control applications. This invention provides a high-speed parallel bus expansion method for multiple nodes, offering flexibility, high speed, comprehensive interfaces, high control precision, and strong scalability, which is of great significance in meeting the requirements of increasingly sophisticated power electronic equipment. Attached Figure Description

[0013] Figure 1 This is a structural block diagram of the device described in an embodiment of the present invention.

[0014] Figure 2 This is a functional block diagram of the main control board and function boards described in the embodiments of the present invention.

[0015] Figure 3 This is a functional block diagram of the back panel described in an embodiment of the present invention.

[0016] Figure 4 This is an example diagram of high-speed backplane parallel bus segmentation as described in an embodiment of the present invention. Detailed Implementation

[0017] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings: See Figure 1 This is a structural block diagram of the device described in this invention. The present invention provides a high-speed parallel bus expansion multi-node device, comprising a device chassis, a power board, a main control board, function boards, a backplane, and a back panel.

[0018] The device chassis provides physical support for the power board, main control board, function boards, and backplane, and fixes each board. The device chassis has expansion capabilities. The main chassis and multiple device slave chassis are connected through high-speed optical fiber, sampling high-speed SERDE serial communication, with a communication rate of up to 5Gbps.

[0019] The power board is connected to the backplate and fixed on both sides of the device chassis. The two are redundant and provide power to the device. If one power board fails, the other power board can still ensure that the system works normally.

[0020] See Figures 1-2The main control board is connected to the backplane and fixed in slots 3, 8, and 13 of the backplane. The main control board is the master node of the control system and can provide synchronization for each slave node. The main control board uses DSP+FPGA as the core control chip. The DSP is responsible for the implementation of the control algorithm, while the FPGA is responsible for the implementation of high-speed parallel Buslvds communication. The DSP and FPGA communicate through a high-speed rapidio interface, and the main control board communicates with the function boards through a high-speed parallel Buslvds bus. By adjusting the sampling clock phase, the bus communication bandwidth reaches a main frequency of 125MHz, a data bit width of 32 bits, and a total bandwidth of 4Gbps. The main control board also has a data recording function, giving full play to the advantages of the DSP and FPGA chips and maximizing the performance of the system.

[0021] The backplane is the pathway connecting the master node and each slave node. It has 17 slots. The main control board and function boards are located in the slots of the backplane. The backplane serves as the connection channel between the power board, the main control board, and the function boards. It adopts a segmented high-speed Bus lvds parallel bus and provides a common clock for each node. It has a fast communication rate, high bandwidth, and can be expanded to multiple nodes.

[0022] The functional boards are connected to the backplane and can be fixed in any slot from 1 to 17 of the device chassis. They serve as slave nodes of the control system, using an FPGA as the core control chip. They communicate and interact with the master node at high speed via the Buslvds bus, providing the desired functions according to user needs. Each functional board is independent and can provide interfaces for high-speed fiber optic communication expansion, data acquisition, analog acquisition, analog output, FT3 communication, Ethernet communication, CAN communication, RS485 communication, GPS time synchronization, etc., possessing powerful interface expansion capabilities.

[0023] See Figure 3 The backplane can be inserted into slots 2, 7, 9, and 14 of the backplane from the back. The backplane serves as a bridge connecting the segmented bus of the backplane, providing a powerful driving capability for the parallel bus, increasing the scalability of nodes, and simultaneously enabling the switching control of data flow direction for each node. Using an FPGA chip as the control core, it greatly improves the scalability of nodes and switches the high-speed parallel bus data flow, enabling the master node and segmented slave nodes to perform high-speed parallel Buslvds communication, which is an important link in expanding multi-node capabilities.

[0024] See Figure 4 The physical and logical segmentation of the backplane bus greatly increases the application flexibility of the device. Each logical segment can be regarded as an independent device, and can have its own master node and slave node. Using this feature, a device can be divided into three independent devices, including the following situations: 1) Scenario 1: In scenario 1, there is no back panel between the three physical segments. The three physical segments are three logical segments, which are logical segments in the form of "6+5+6" slots. That is, the first six slots, the middle five slots, and the last six slots form a combination of three physical segments. Each small segment is independent. This can be used to form an application such as "polar control system + valve control system + merging unit" of a small flexible DC transmission modular multilevel converter. One device chassis can be used for three application scenarios. 2) Second scenario: Insert a back panel into slots 2 and 7 to bridge physical segment 1 and physical segment 2, forming an "11+6" configuration. That is, the first 11 slots and the last 6 slots form a combination of two physical segments, which is a combination of a large logic segment + a small logic segment. This can be used in applications such as the "valve control system + merging unit" of small flexible DC transmission modular multilevel converter. 3) The third scenario: Insert a back panel into slots 9 and 14 to bridge physical segment 2 and physical segment 3, forming a combination of "6+11" slot logic segments. That is, the first six slots and the last 11 slots form a combination of two physical segments, thus forming a small logic segment + a large logic segment. 4) In the fourth scenario, insert a backplate from slots 2, 7, 9, and 14 on the back of the backplate to bridge physical segments 1, 2, and 3, forming a “17” configuration. This means that the three physical segments are combined into one, thus creating a super-large logic segment. This can be used to construct independent “valve control systems” or “merging units” for applications such as medium-sized flexible DC transmission modular multilevel converters.

[0025] The device chassis also has a chassis expansion function. The same chassis can be expanded through the high-speed optical ports of the function boards. The function boards can be freely defined. The device chassis are connected by optical fiber, and multiple chassis can be expanded to form a super-large control system, such as the overall valve control system of the flexible DC transmission system.

[0026] This invention proposes a method and apparatus for expanding multiple nodes using a high-speed parallel bus. It employs a high-speed back-mounted module bridging approach to address the insufficient driving capability of the parallel bus. A segmented structure allows for the combination of three types of devices. Furthermore, the device chassis can be expanded to include multiple slave chassis, greatly improving the flexibility of device applications. The sampling FPGA serves as the core device for bus communication, with each node sharing a backplane clock. By adjusting the sampling clock phase, the bus communication bandwidth reaches a 125MHz main frequency and a 32-bit data width, significantly improving the performance of the control system.

[0027] The above embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the above embodiments. Unless otherwise specified, the methods used in the above embodiments are conventional methods.

Claims

1. A device for expanding multiple nodes via a high-speed parallel bus, characterized in that, This includes the device chassis, power supply board, main control board, function boards, backplane, and back panel. The device chassis is a standard 6U chassis, which provides physical support for the power board, main control board, function boards and backplane. The power board, main control board, function boards, backplane and back panel are all installed inside the device chassis. The backplane has 17 slots, and the main control board and function boards are installed in the slots of the backplane. The backplane serves as a connection channel between the power board, the main control board, and the function boards. Slots 1 to 6 of the backplane are the first physical segment, slots 7 to 11 are the second physical segment, and slots 12 to 17 are the third physical segment. The power board adopts a dual-board redundant structure, and is respectively located in the power supply position inside the device chassis and is located on the far left and far right of the back panel. It is connected to the back panel and is used to power the entire device. The main control board serves as the master node and is the core of the entire device's communication. It is connected to the backplane and can be installed in slots 3, 8, and 13 of the device chassis. The functional board acts as a slave node, providing various functional interfaces and is connected to the backplane. The functional board can be set in any slot of the backplane. The backplate can be positioned between the physical segments of the backplate, connecting the backplate segment parallel bus, and can be inserted into the 2nd, 7th, 9th, and 14th slots of the backplate from the back.

2. The device for expanding multiple nodes via a high-speed parallel bus according to claim 1, characterized in that, The main control board adopts a DSP+FPGA control architecture. The DSP provides data processing computing power to the entire device, and the FPGA is configured to realize high-speed parallel differential bus Buslvds communication and control and synchronize each slave node in the system. At least one main control board is set in the device chassis.

3. The device for expanding multiple nodes via a high-speed parallel bus according to claim 1, characterized in that, The functional board uses an FPGA as the control core and interacts with the master node via a high-speed differential bus (Buslvds). The functional board is equipped with one or more of the following: a high-speed fiber optic communication expansion interface, a data acquisition interface, an analog acquisition interface, an analog output interface, an FT3 communication interface, an Ethernet communication interface, a CAN communication interface, an RS485 communication interface, and a GPS time synchronization interface.

4. The device for expanding multiple nodes via a high-speed parallel bus according to claim 1, characterized in that, The backplane provides a physical channel for high-speed parallel Buslvds communication. The backplane adopts a dual-bus redundant structure and provides a shared clock for each node.

5. The device for expanding multiple nodes via a high-speed parallel bus according to claim 4, characterized in that, The backplane is a bridging module between the physical segments of the backplane, used to enhance the parallel bus driving capability and realize the switching of backplane data flow direction.

6. A method for expanding multiple nodes using a high-speed parallel bus, applied to the apparatus according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. The main control board acts as the master node, and completes the packaging, distribution, unpacking and repacking of data through the DSP chip. The FPGA communicates with the DSP through the rapidio interface and is responsible for the high-speed parallel Buslvds bus data control, distribution and receiving of data from each slave node. The communication frequency is 100MHz to 150MHz and the data bit width is 16bit or 32bit. S2. The functional board acts as a slave node, controlling the high-speed parallel Buslvds bus data through the FPGA to summarize the high-speed fiber optic extended data, the collected analog data, digital data, Ethernet data, CAN bus data, and RS485 bus data, and finally send them to the master node through the Buslvds bus. S3. The backplane serves as the communication channel for the Buslvds bus, with dual buses and dual clock sources. It defines 17 slots, which are divided into three physical segments: slots 1-6 are the first physical segment, slots 7-11 are the second physical segment, and slots 12-17 are the third physical segment. The backplane bridges the physical segments, and the connection between the different physical segments of the backplane enables the master node to access all slave nodes, thereby maximizing the expansion of nodes. S4. The back panel uses FPGA as the control core to realize high-speed parallel bus data switching and bus drive enhancement; bridging relay is completed through at least two back panels, so that the number of nodes in a single device chassis can be expanded to 17.

7. The method for expanding multiple nodes on a high-speed parallel bus according to claim 6, characterized in that, The backplane is configured with physical and logical segments. Each logical segment independently constitutes a subsystem containing master and slave nodes, specifically including the following scenarios: 1) In the first scenario, there is no back panel connected between the three physical segments, and the three physical segments are three logical segments; 2) The second scenario involves connecting a back panel. A back panel is connected between the first physical segment and the second physical segment, but not between the second physical segment and the third physical segment. Alternatively, a back panel is not connected between the first physical segment and the second physical segment, but is connected between the second physical segment and the third physical segment, thus dividing the three physical segments into two logical segments. 3) The third scenario involves connecting two backplanes. One backplane is inserted between the first physical segment and the second physical segment, and another backplane is inserted between the second physical segment and the third physical segment. The three physical segments are combined into a logical segment, and the entire chassis is treated as a whole.

8. The method for expanding multiple nodes on a high-speed parallel bus according to claim 6, characterized in that, The device chassis has expansion capabilities, and the main chassis and slave chassis of the device chassis are connected through high-speed optical fiber to form a large-scale control system with multiple chassis cascaded.

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