Integrated circuit (IC) packages with additional metal pads for metal interconnects that reduce the die-to-substrate gap.

Abstract

An integrated circuit package and related manufacturing method are disclosed, comprising an additional metal pad with a reduced area for metal interconnects to reduce the die-to-substrate gap. The IC package includes a die interconnect with a first metal pad coupled to a metallization layer of the substrate to provide support and signal routing paths. To reduce the gap between the die and the substrate, and thus the height of the IC package, a second additional metal pad having a smaller cross-sectional area than the first metal pad is coupled to the first metal pad. Solder is used to couple the second additional metal pad to the die interconnect to couple the die to the substrate. When the solder is heated to form a solder joint, the solder flows along the reduced cross-sectional area of ​​the second additional metal pad.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 531,423, filed December 6, 2023, entitled “INTEGRATED CIRCUIT (IC) PACKAGE HAVING A SUBSTRATE EMPLOYING REDUCED AREA, ADDED METAL PAD(S) TO METAL INTERCONNECT(S) TO REDUCE DIE-SUBSTRATE CLEARANCE,” the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] This disclosure relates to integrated circuit (IC) packages, and more specifically to the design and manufacture of substrates within IC packages to meet thinning requirements.

[0005] II. Background Technology

[0006] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as “semiconductor packages” or “chip packages.” An IC package includes one or more semiconductor dies that serve as the IC, mounted on and electrically coupled to a package substrate to provide physical support and electrical interfaces for the dies. The dies are electrically connected to metal interconnects (e.g., metal traces) exposed in the top layer of the package substrate. The package substrate also includes one or more metallization layers comprising metal interconnects (e.g., metal traces, metal lines), wherein vertical interconnect channels (vias) couple the metal interconnects between adjacent metallization layers together to provide electrical interfaces between the dies. The package substrate also includes a bottom outer metallization layer comprising metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide external interfaces between the dies in the IC package. External metal interconnects can also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and electrically interconnect its die with the PCB's circuitry. Dies can be mounted to the top layer of the package substrate via die interconnects. Other dies can also be mounted to a bottom outer metallization layer, which includes metal interconnects between BGA interconnects, using die interconnects. Summary of the Invention

[0007] The aspects disclosed in the detailed description include an integrated circuit (IC) package having additional metal pads with reduced area for metal interconnects to reduce the die-substrate gap. The IC package includes a die having die interconnects with first metal pads coupled to corresponding metal interconnects of a metallization layer of the substrate (e.g., a package substrate) to provide support and signal routing paths. As an example, to facilitate a reduction in the gap between the die and the substrate, and thus a reduction in the height of the IC package, a second additional metal pad having a smaller cross-sectional area than the first metal pad is coupled to the first metal pad. Solder joints are used to couple the second additional metal pad to the die interconnects of the die to couple the die to the substrate. In this way, as an example, when the solder is heated to form the solder joint between the die interconnect and the second additional metal pad, the solder advantageously flows along the reduced cross-sectional area of ​​the second additional metal pad, allowing the designer to control the gap between the die and the substrate by using less solder, using shorter lengths of the corresponding die interconnect, or a combination of both.

[0008] In one aspect, an integrated circuit (IC) package includes a die, a substrate, and solder joints. The die includes a plurality of die interconnects. The substrate includes a lower metallization layer extending in a first direction, the lower metallization layer including a plurality of metal interconnects. The plurality of metal interconnects includes a first pad having a first surface and a second surface opposite to the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction; and a second pad coupled to the first surface, the second pad having a second cross-sectional area extending in the first direction that is smaller than the first cross-sectional area. The solder joints are coupled to the second pad and the first die interconnect of the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction and smaller than the first cross-sectional area, the second cross-sectional area being at least equal to the third cross-sectional area.

[0009] In another aspect, a method for manufacturing a substrate is disclosed. The method includes forming a die comprising a plurality of die interconnects, and forming a substrate comprising a lower metallization layer extending in a first direction, the lower metallization layer comprising a plurality of metal interconnects. The plurality of metal interconnects includes a first pad having a first surface and a second surface opposite to the first surface in a second direction orthogonal to the first direction. The first pad has a first cross-sectional area extending in the first direction. The method further includes forming a second pad coupled to the first surface, the second pad having a second cross-sectional area extending in the first direction smaller than the first cross-sectional area. The method further includes coupling solder joints to the second pad and the first die interconnects among the plurality of die interconnects, the first die interconnects having a third cross-sectional area extending in the first direction smaller than the first cross-sectional area, the second cross-sectional area being at least equal to the third cross-sectional area. Attached Figure Description

[0010] Figure 1 This is a side view of an exemplary three-dimensional (3D) integrated circuit (IC) (3DIC) package that includes additional metal pads with reduced area for metal interconnects to reduce die-to-substrate gap; Figure 2A yes Figure 1 The side view of an exemplary substrate embodiment shown is provided, in which additional metal pads with reduced area are used for metal interconnects between dicing lines A1 and A2 to reduce the die-substrate gap. Figure 2B yes Figure 1 The side view of another substrate embodiment of an exemplary substrate shown, in which additional metal pads with reduced area are used for metal interconnects between dicing lines A1 and A2 to reduce the die-substrate gap.

[0011] Figure 3 yes Figure 2A The substrate in the positive Z direction begins Figure 2A Perspective view of cutting line B1 in the diagram; Figure 4 This illustrates a substrate (such as) used in the manufacture of IC packages. Figure 1 , Figure 2A and Figure 2B A flowchart of an exemplary manufacturing process for the substrate described herein, including but not limited to... Figure 1 , Figure 2A and Figure 2B The substrate in the middle uses additional metal pads with reduced area for metal interconnects to reduce the die-substrate gap; Figures 5A to 5C This is a flowchart illustrating another exemplary manufacturing process for manufacturing a substrate for IC packages, including but not limited to... Figure 1, Figure 2A and Figure 2B The substrate in the middle uses additional metal pads with reduced area for metal interconnects to reduce the die-substrate gap; Figures 6A to 6H It is based on Figures 5A to 5C An exemplary manufacturing stage during the manufacturing of a substrate in the manufacturing process; Figure 7 This is a block diagram of an exemplary processor-based system that may include components deployed in an IC package, wherein the IC package includes a substrate with reduced-area additional metal pads for metal interconnects to reduce die-to-substrate gaps, the substrate including but not limited to... Figure 1 , Figure 2A and Figure 2B And according to Figure 4 and Figures 5A to 5C The substrate of the exemplary manufacturing process in the example; and Figure 8 This is a block diagram of an exemplary wireless communication device, which includes radio frequency (RF) components deployed in an IC package, wherein the IC package includes a substrate with additional metal pads of reduced area used for metal interconnects to reduce the die-to-substrate gap, the substrate including but not limited to... Figure 1 , Figure 2A and Figure 2B and according to Figure 4 and Figures 5A to 5C The substrate is an example of a manufacturing process described above. Detailed Implementation

[0012] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects. Unless otherwise specifically stated, the term “adjacent” as used herein means spatially adjacent but not necessarily adjacent to something, as shown in the accompanying drawings.

[0013] The aspects disclosed in the detailed description include an integrated circuit (IC) package having additional metal pads with reduced area for metal interconnects to reduce the die-substrate gap. The IC package includes a die having die interconnects with first metal pads coupled to corresponding metal interconnects of a metallization layer of the substrate (e.g., a package substrate) to provide support and signal routing paths. As an example, to facilitate a reduction in the gap between the die and the substrate, and thus a reduction in the height of the IC package, a second additional metal pad having a smaller cross-sectional area than the first metal pad is coupled to the first metal pad. Solder joints are used to couple the second additional metal pad to the die interconnects of the die to couple the die to the substrate. In this way, as an example, when the solder is heated to form the solder joint between the die interconnect and the second additional metal pad, the solder advantageously flows along the reduced cross-sectional area of ​​the second additional metal pad, allowing the designer to control the gap between the die and the substrate by using less solder, using shorter lengths of the corresponding die interconnect, or a combination of both.

[0014] In this regard, Figure 1 This is a side view of an exemplary IC package 100, which in this example is a three-dimensional (3D) IC (3DIC) package 100. The IC package 100 includes a package substrate 102 and an interposer substrate 104. The package substrate 102 and the interposer substrate 104 share a common route for signals and power, and for convenience, both may be simply referred to as substrate 106.

[0015] In this example, IC package 100 includes a first die 108(1) and a second die 108(2), which are included in corresponding first die package 112(1) and second die package 112(2), which are stacked on top of each other in the vertical direction (Z-axis direction). The first die package 112(1) of IC package 100 includes the first die 108(1) coupled to package substrate 102. In this example, package substrate 102 includes a first upper metallization layer 114. The first upper metallization layer 114 provides an electrical interface for signal routing to the first die 108(1). The first die 108(1) is coupled to a die interconnect 118 (e.g., raised metal bumps, pillars), which is electrically coupled to a metal interconnect 120 in the first upper metallization layer 114. Metal interconnects 120 in the first upper metallization layer 114 are coupled to metal vias 122 (not visible) in the package substrate 102, which in turn are coupled to metal interconnects 124 in the second bottom metallization layer 116. In this manner, the package substrate 102 provides interconnects between its first metallization layer 114 and second metallization layer 116 to provide signal routing to the first die 108(1). External interconnects 126 (e.g., ball grid array (BGA) interconnects) are coupled to the metal interconnects 124 in the second bottom metallization layer 116 to provide interconnects through the package substrate 102 to the first die 108(1) via die interconnects 118. In this example, the first active side 128(1) of the first die 108(1) is adjacent to and coupled to the package substrate 102, and more specifically, adjacent to and coupled to the first upper metallization layer 114 of the package substrate 102.

[0016] Third die 108(3) and fourth die 108(4) are attached to the bottom side of first die package 112(1). Third die 108(3) and fourth die 108(4) can be any silicon arsenide or gallium arsenide electronic device with a grindable back side. The general width of third die 108(3) and fourth die 108(4) in the z-direction is approximately 100 micrometers. Third die 108(3) and fourth die 108(4) include die connectors (not shown) coupled to metal interconnects 124 in the second bottom metallization layer 116 and via additional metal pads (not shown) with reduced area to reduce the die-substrate gap. Figure 1 The effect of this gap is that the height h1 of the bare dies 108(3) and 108(4) is smaller than the height h2 of the external interconnect 126. The reduced area of ​​the additional metal pads will bond... Figures 2A to 2B and Figure 3 Further discussion.

[0017] exist Figure 1In the exemplary IC package 100, an additional optional second die package 112(2) is provided and coupled to the first die package 112(1) to support a plurality of dies. For example, the first die 108(1) in the first die package 112(1) may include an application processor, and the second die 108(2) may be a memory die, such as a dynamic random access memory (DRAM) die that provides memory support for the application processor. In this respect, in this example, the first die package 112(1) also includes an interposer substrate 104 disposed on a package mold 130 covering the first die 108(1) and adjacent to a second non-functional side 128(2) of the first die 108(1). The interposer substrate 104 also includes one or more metallization layers 132, each metallization layer including a metal interconnect 134 to provide interconnection to the second die 108(2) in the second die package 112(2). The second die package 112(2) is physically coupled and electrically coupled to the first die package 112(1) by means of external interconnects 136 (e.g., solder bumps, BGA interconnects) coupled to the interposer substrate 104. The external interconnects 136 are coupled to metal interconnects 134 in the interposer substrate 104 through metal vias 138 (not visible). The first die package 112(1) includes vertical interconnects 140 to couple the second die 108(2) to the external interconnects 126 and to the first die 108(1) through the package substrate 102.

[0018] Figure 2A yes Figure 1 The image shows a side view of an embodiment of an exemplary substrate 106 in which additional metal pads with reduced area are used for metal interconnects between dicing lines A1 and A2 to reduce the die-substrate gap. The substrate 200 includes an upper metallization layer 114 and a bottom metallization layer 116, each metallization layer extending in a first horizontal direction (X-axis direction, Y-axis direction).

[0019] The bottom metallization layer 116 includes metal interconnects 202. The metal interconnects 202 are also first pads 204(A), which have a first surface 206(A) and a second surface 206(B) opposite to the first surface 206(A) in a second direction (Z-axis direction) orthogonal to the first direction. The first pad 204(A) has a first cross-sectional area extending in a first horizontal direction (X-axis direction, Y-axis direction). The first pads 204(A) to 204(F) are formed in the last metal layer of the substrate 200. An additional second pad 208(A) is coupled to the first surface 206(A) and has a second cross-sectional area extending in the first horizontal direction (X-axis direction, Y-axis direction). The second cross-sectional area is smaller than the first cross-sectional area. The second pad 208(A) has a height of 10 micrometers (μm) in a second vertical direction (Z-axis direction). The height of the second pad 208(A) may be larger depending on the desired gap level target.

[0020] The die 108(4) includes die interconnects 210(A) to 210(F) and solder joints 212(A) to 212(F). Solder joint 212(A) is coupled to a second pad 208(A) and the die interconnect 210(A). Solder joint 212(A) has a height of less than 30 μm in a second vertical direction (Z-axis direction). Die interconnect 210(A) has a height decreasing from 37 μm to 12 μm in the second vertical direction (Z-axis direction). Die interconnect 210(A) has a third cross-sectional area extending in a first horizontal direction (X-axis direction, Y-axis direction). The third cross-sectional area is smaller than the first cross-sectional area. The second cross-sectional area is at least equal to the third cross-sectional area. Specifically, the second cross-sectional area may be larger than the third cross-sectional area by a certain amount to ensure alignment between the solder joint 212(A) and the second pad 208(A) during assembly of the IC package 100. Die-substrate coupling (such as die couplings 211(A) to 211(F)) refers to a combination of die interconnects 210, solder joints 212, second pads 208, and first pads 204 in the second vertical direction (Z-axis direction), such as die interconnects 210(A), solder joints 212(A), second pads 208(A), and first pads 204(A). Furthermore, molding compound 217 fills the space between die-substrate couplings 211(A) to 211(F).

[0021] The substrate layout and design can impose different design rule constraints on the minimum cross-sectional area of ​​the corresponding first pads 204(A) to 204(F), and will combine Figure 3 discuss.

[0022] Figure 2B yes Figure 1The side view shown is of another substrate embodiment of an exemplary substrate 106 in which additional metal pads with reduced area are used for metal interconnects between dicing lines A1 and A2 to reduce the die-substrate gap. In addition to the upper metallization layer 114 in substrate 218 containing additional second pads (such as second pads 220(A) and 220(B)), substrate 218 and... Figure 2A The substrates 200 are the same, including the same die-substrate couplings 211(A) to 211(F).

[0023] The upper metallization layer 114 in substrate 218 includes metal interconnects 222. The metal interconnects 222, also referred to as first pads 224, have a first surface 226(A) and a second surface 226(B) opposite the first surface in a second direction (Z-axis direction) orthogonal to the first direction. The first pad 224 has a fourth cross-sectional area extending in a first horizontal direction (X-axis direction, Y-axis direction). A second pad 220(A) is coupled to the first surface 226(A) and has a fifth cross-sectional area extending in the first horizontal direction (X-axis direction, Y-axis direction). The fifth cross-sectional area of ​​the second pad 220(A) is smaller than the fourth cross-sectional area of ​​the first pad 224. Although not shown, the second pad 220(A) can receive solder to couple another die, such as die 108(1), through one die interconnect of die interconnects 118. The exemplary cross-sectional areas mentioned above will be combined with... Figure 3 Further discussion. Figure 2A and Figure 2B This shows the solder mask layer that was removed during manufacturing. The solder mask layer will be adjacent to the bottom metallization layer 116.

[0024] Figure 3 yes Figure 2A The substrate 200 in the positive Z direction begins Figure 2A A perspective view of cut line B1 in the diagram. Substrate configuration and design can impose minimum dimensional constraints, including cross-sectional area constraints, on the first pads 204(A) to 204(F). For example, the first pad 204(A) is coupled to via 214 (see...). Figure 2A The width of this via in the X and Y directions limits the cross-sectional area of ​​the first pad 204(A). Therefore, the first pad 204(A) has a diameter d1 of 90 μm and thus a first cross-sectional area A1 = π(.5d1). 2 or 45πµm 2 To limit unwanted solder flow, the second pad 208(A) has a diameter d2 of 60 μm and therefore a second cross-sectional area A2 or 30πµm. 2 The bare die interconnect 210(A) and solder joint 212(A) have a diameter of 50 μm, and therefore have a third cross-sectional area A3 or 25πµm. 2 .

[0025] As another example, the first pads 204(B) and 204(C) have minimum dimensions imposed by the substrate configuration and design. Therefore, the first pads 204(B) and 204(C) have a diameter d1 of 80 μm, and thus a first cross-sectional area A1 = π(.5d1). 2 or 40πµm 2 To limit unwanted solder flow, the second pads 208(B) and 208(C) have a diameter d2 of 50 μm and therefore a second cross-sectional area A2 or 25πµm. 2 The die interconnects 210(B) and 210(C) and solder joints 212(B) and 212(C) have a diameter of 50 μm and therefore have a third cross-sectional area A3 or 25πµm. 2 .

[0026] As another example, first pads 204(D) and 204(E) are coupled in a first horizontal direction (X-axis direction, Y-axis direction) to form a plane 216 that can be connected to ground when the IC package 100 is deployed in a device. Plane 216 is coupled to a plurality of second pads including second pads 208(D) and 208(E), and has a cross-sectional area different from that of the first pad 204(A). The second pads 208(D) and 208(E) have a diameter d2 of 55 μm, and therefore have a second cross-sectional area A2 or 27.5πµm. 2 The die interconnects 210(D) and 210(E) and the solder joints 212(D) and 212(E) have a diameter of 50 μm and therefore have a third cross-sectional area A3 or 25πµm. 2 By providing a second pad whose cross-sectional area is smaller than that of the corresponding first pad and equal to or slightly larger than that of the corresponding die interconnect / solder joint, the substrate designer can control the gap between the die and the substrate by using less solder, using shorter lengths of the corresponding die interconnect, or a combination of both. For example, by adding a second pad whose height is 10µm in the second vertical direction (Z-axis direction), the die interconnect has been reduced from 37µm to 12µm, thereby reducing the gap between the substrate and the die by 15µm (37µm – (12µm + 10µm)).

[0027] Please note Figure 3 The die-substrate coupling is illustrated as concentric circles. However, depending on the manufacturing tools, these cross-sectional areas can be of any shape, including squares, rectangles, quadrilaterals, ellipses, and so on.

[0028] Substrates that use additional metal pads with reduced area for metal interconnects to reduce die-to-substrate gaps (including but not limited to) Figure 1In the relevant IC package 100 Figure 1 , Figure 2A and Figure 2B The substrates 106, 200 and 218 in the middle can be manufactured by different manufacturing processes. Figure 4 This illustrates a substrate (such as) used in the manufacture of IC packages. Figure 1 , Figure 2A and Figure 2B A flowchart of an exemplary manufacturing process 400 for the substrate described herein, including but not limited to... Figure 1 , Figure 2A and Figure 2B The substrate in the middle uses additional metal pads with reduced area for metal interconnects to reduce the die-substrate gap.

[0029] In this regard, Figure 4 A first exemplary step in the manufacturing process 400 may include forming a die 108 comprising a plurality of die interconnects 118, 210(A) to 210(F). Figure 4 (See frame 402 in the text). A next step in the manufacturing process 400 may include forming a substrate 106 comprising metallization layers 114, 116 extending in a first direction, the metallization layers 114, 116 including a plurality of metal interconnects 202. The metal interconnects 202 include first pads 204(A) to 204(F), 224 having first surfaces 206(A), 226(A) and second surfaces 206(B), 226(B) opposite to the first surfaces 206(A), 226(A) in a second direction orthogonal to the first direction, the first pads 204(A) to 204(F), 224 having a first cross-sectional area A1 (…). Figure 4 (See box 404 in the text). A next step in manufacturing process 400 may include forming second pads 208(A) to 208(F), 220(A) coupled to the first surfaces 206(A), 226(A), the second pads 208(A) to 208(F), 220(A) having a second cross-sectional area A2 smaller than the first cross-sectional area A1 in a first direction. Figure 4 (See box 406 in the text). A next step in the manufacturing process 400 may include coupling solder joints 212(A) to 212(F) to second pads 208(A) to 208(F) and first die interconnects 210(A) to 210(F) of a plurality of die interconnects, the first die interconnects 210(A) to 210(F) having a third cross-sectional area A3 smaller than the corresponding first cross-sectional area A1, and the corresponding second cross-sectional area A2 being at least equal to the third cross-sectional area A3. Figure 4 (Box 406 in the middle).

[0030] Other manufacturing processes can also be used to produce substrates with reduced-area additional metal pads for metal interconnects to reduce die-substrate gaps (including but not limited to...). Figure 1 In the relevant IC package 100 Figure 1 , Figure 2A and Figure 2B (Substrates 106, 200, and 218 in the example). In this regard... Figures 5A to 5C This is a flowchart illustrating another exemplary manufacturing process for manufacturing a substrate for IC packages, including but not limited to... Figure 1 , Figure 2A and Figure 2B The substrate in the middle uses additional metal pads with reduced area for metal interconnects to reduce the die-substrate gap. Figures 6A to 6H It is based on Figures 5A to 5C An exemplary manufacturing stage during the fabrication of a substrate in a manufacturing process. For example... Figures 6A to 6H The manufacturing process 500 shown in manufacturing stages 600A to 600H refers to the substrate 200 in Figure 2 and Figure 1 The relevant IC package 100 in the reference, and therefore will be referenced Figure 1 and Figure 2A The substrate 200 and related IC package 100 are discussed.

[0031] In this regard, such as Figure 6A As shown in manufacturing stage 600A, an exemplary step in manufacturing process 500 is to apply solder resist layers 602 and 604 onto substrate 200. Figure 5A (See box 502 in the figure). As shown, a substrate 200 has been manufactured using conventional techniques, having multiple metallization layers including metallization layers 114 and 116, metal interconnects (such as first pads 204(A) to 204(F)), and wiring paths including vias 214 from the top surface 606 of the substrate 200 to the bottom surface 608 of the substrate 200. Figure 6B As shown in manufacturing stage 600B, the next step in manufacturing process 500 may include exposing the first pads 204(A) to 204(F) through solder mask by passing ultraviolet light through a mask. Figure 5A (Box 504 in the middle). Figure 6C As shown in manufacturing stage 600C, the next step in manufacturing process 500 may include applying a seed layer 610 of metal (e.g., copper (Cu)) onto the bottom surface 608 of substrate 200. Figure 5A (Box 506 in the middle). Figure 6D As shown in manufacturing stage 600D, the next step in manufacturing process 500 may include laminating a photoimageable material 612 (such as a dry film) onto the top surface 606 and bottom surface 608 of substrate 200. Figure 5B (Box 508 in the middle). Figure 6E As shown in manufacturing stage 600E, the next step in manufacturing process 500 may include exposing the cross-sectional area A2 on the first pads 204(A) to 204(F) to be transparent to the light-imageable material 612. Figure 5B (See box 510 in the image). Note that cross-sectional area A2 refers to the final cross-sectional area of ​​the corresponding second pad and can vary depending on which first pads 204(A) to 204(F) are exposed. Figure 6F As shown in manufacturing stage 600F, the next step in manufacturing process 500 may include electroplating metal (e.g., Cu) onto the cross-sectional area A2 of the first pads 204(A) to 204(F) to form second pads 208(A) to 208(F). Figure 5B (Box 512 in the middle). Figure 6G As shown in manufacturing stage 600G, the next step in manufacturing process 500 may include peeling the photoimageable material 612 from the bottom layer of substrate 200. Figure 5C (Box 514 in the middle). Figure 6H As shown in manufacturing stage 600H, the next step in manufacturing process 500 may include removing the seed layer 610 using chemical etching. Figure 5C (See box 516 in the diagram). After the manufacturing process 500 is completed, the substrate 200 can be assembled with a die to form die-substrate couplings 211(A) to 211(F).

[0032] Electronic devices including IC packages can be provided in or integrated into any processor-based device, wherein the IC package includes a substrate with reduced-area additional metal pads for metal interconnects to reduce die-to-substrate gaps, the substrate including but not limited to... Figure 1 , Figure 2A and Figure 2B In and according to Figure 4 and Figures 5A to 5C The exemplary manufacturing processes described herein and the substrates disclosed in any aspect thereof. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, and multirotor aircraft.

[0033] In this regard, Figure 7 This is a block diagram of an exemplary processor-based system that may include components deployed in an IC package, wherein the IC package includes a substrate with reduced-area additional metal pads for metal interconnects to reduce die-to-substrate gaps, the substrate including but not limited to... Figure 1 , Figure 2A and Figure 2B In and according to Figure 4 and Figures 5A to 5C The exemplary manufacturing process and substrate disclosed herein are as follows. In this example, the processor-based system 700 may be formed as an IC package 702 utilizing substrates 200, 218, or a combination of two substrates, such as Figure 1 The IC package 100 is included. The processor-based system 700 includes a central processing unit (CPU) 708, which includes one or more processors 710, which may also be referred to as a CPU core or processor core. The CPU 708 may have a cache memory 712 coupled to the CPU 708 for fast access to temporarily stored data. The CPU 708 is coupled to a system bus 714 and may be coupled to master and slave devices included in the processor-based system 700. As is well known, the CPU 708 communicates with these other devices by exchanging address, control, and data information via the system bus 714. For example, the CPU 708 may communicate a bus transaction request to a memory controller 716, which is an example of a slave device. Although in Figure 7 Not illustrated, but multiple system buses 714 may be provided, each of which constitutes a different texture.

[0034] Other master and slave devices can be connected to system bus 714. For example... Figure 7As illustrated, these devices may include a memory system 720, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728, the memory system including a memory controller 716 and a memory array 718. Each of the memory system 720, one or more input devices 722, one or more output devices 724, one or more network interface devices 726, and one or more display controllers 728 may be located in the same or different electronic devices. Input devices 722 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 724 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 726 may be any device configured to allow the exchange of data to and from network 730. Network 730 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™ Networks and the Internet. The network interface device 726 can be configured to support any type of communication protocol desired.

[0035] CPU 708 can also be configured to access display controller 728 via system bus 714 to control information transmitted to one or more displays 732. Display controller 728 transmits information to be displayed to display 732 via one or more video processors 734, which process the information to be displayed into a format suitable for use by display 732. As an example, display controller 728 and video processor 734 can be included as ICs in the same or different electronic devices, and in the same or different electronic devices containing CPU 708. Display 732 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0036] Figure 8 An exemplary wireless communication device 800 is illustrated, the wireless communication device including a radio frequency (RF) component formed of one or more ICs 802, wherein any IC 802 may be deployed in an IC package 803, wherein the IC package 803 includes a substrate with additional metal pads of reduced area used for metal interconnects to reduce die-to-substrate gaps, the substrate including but not limited to Figure 1 , Figure 2A and Figure 2B In and according to Figure 4 and Figures 5A to 5CThe exemplary manufacturing process and the substrate according to any exemplary aspect disclosed herein. As an example, wireless communication device 800 may include any of the devices mentioned above or be provided in any of the devices mentioned above. Figure 8 As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. Generally, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0037] The transmitter 808 or receiver 810 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, it is converted from RF to intermediate frequency (IF) in one stage of receiver 810, and subsequently from IF to baseband in another stage of the same receiver. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 8 In the wireless communication device 800, the transmitter 808 and receiver 810 are implemented using a direct frequency conversion architecture.

[0038] In the transmission path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) to convert the digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0039] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 upconverts the I and Q baseband signals using mixers 820(1) and 820(2) from the transmit (TX) local oscillator (LO) signal generator 822 to provide upconverted signal 824. Filter 826 filters the upconverted signal 824 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through the duplexer or switch 830 and transmitted via the antenna 832.

[0040] In the receiving path, antenna 832 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 830 and provided to low-noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Downconversion mixers 838(1) and 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 842(1) and 842(2) and further filtered by low-pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1) and 846(2) to convert analog input signals into digital signals to be further processed by the data processor 806.

[0041] exist Figure 8In the wireless communication device 800, a TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, while an RX LO signal generator 840 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. Similarly, an RXILL circuit 850 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0042] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0043] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0044] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0045] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0046] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0047] Specific implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: A bare die, the bare die including a plurality of bare die interconnects; and A substrate, the substrate including a lower metallization layer extending in a first direction, the lower metallization layer including a plurality of metal interconnects, the plurality of metal interconnects including: A first pad, the first pad having a first surface and a second surface opposite to the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction; and A second pad, coupled to the first surface, having a second cross-sectional area smaller than the first cross-sectional area extending in the first direction; and The solder joint is coupled to the second pad and a first die interconnect among the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction that is smaller than the first cross-sectional area, the second cross-sectional area being at least equal to the third cross-sectional area.

[0048] 2. The IC package as described in Clause 1, The substrate further includes: An upper metallization layer extending in the first direction, the upper metallization layer including a second plurality of metal interconnects, the second plurality of metal interconnects including: The second first pad has a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and The IC package further includes: A second pad extends in the first direction and is adjacent to the third surface, the second pad having a fifth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area; and The second solder joint is coupled to the second second pad and the second die interconnect in the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area, the sixth cross-sectional area being less than or equal to the fifth cross-sectional area.

[0049] 3. The IC package as described in Clause 1, wherein: The plurality of metal interconnects also include: The second first pad has a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and The IC package also includes: A second pad extending in the first direction and adjacent to the third surface, the second pad having a fifth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area; and The second solder joint is coupled to the second second pad and the second die interconnect in the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction that is smaller than the fourth cross-sectional area, the sixth cross-sectional area being less than or equal to the fifth cross-sectional area.

[0050] 4. The IC package according to Clause 2 or 3, wherein the first cross-sectional area is equal to the fourth cross-sectional area, the second cross-sectional area is equal to the fifth cross-sectional area, and the third cross-sectional area is equal to the sixth cross-sectional area.

[0051] 5. The IC package according to Clause 3, wherein the first pad and the second first pad are coupled in the first direction to form a plane.

[0052] 6. The IC package according to Clause 1, wherein the second cross-sectional area is equal to or less than 30π square micrometers (µm) 2 ).

[0053] 7. The IC package according to Clause 1, wherein the first die interconnect of the plurality of die interconnects has a first height of less than 37 micrometers (μm).

[0054] 8. The IC package according to Clause 6, wherein the solder joint has a second height of less than 30 μm.

[0055] 9. The IC package according to Clause 7, wherein the second pad has a third height of at least 10 μm.

[0056] 10. An IC package according to any one of Clauses 1 and 3 to 9, said IC package being integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet devices; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; and multirotor aircraft.

[0057] 11. A method for manufacturing a substrate, the method comprising: Forming a die that includes multiple die interconnects; A substrate comprising a lower metallization layer extending in a first direction, the lower metallization layer comprising a plurality of metal interconnects, the plurality of metal interconnects comprising: A first pad, the first pad having a first surface and a second surface opposite to the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction; A second pad is formed coupled to the first surface, the second pad having a second cross-sectional area smaller than the first cross-sectional area extending in the first direction; and A first die interconnect is coupled to the solder joint to the second pad and the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction that is smaller than the first cross-sectional area, the second cross-sectional area being at least equal to the third cross-sectional area.

[0058] 12. The method according to Clause 11, wherein the second cross-sectional area is larger than the third cross-sectional area by a certain amount to ensure alignment between the solder joint and the second pad.

[0059] 13. The method according to Clause 11, wherein: The plurality of metal interconnects also include: The second first pad has a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and The method further includes: A second pad is formed extending in the first direction and adjacent to the third surface, the second pad having a fifth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area; and The second solder joint is coupled to the second second pad and the second die interconnect in the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area that extends in the first direction and is smaller than the fourth cross-sectional area, the sixth cross-sectional area matching the fifth cross-sectional area.

[0060] 14. The method according to Clause 13, wherein the first cross-sectional area is equal to the fourth cross-sectional area, the second cross-sectional area is equal to the fifth cross-sectional area, and the third cross-sectional area is equal to the sixth cross-sectional area.

[0061] 15. The method according to Clause 13, wherein the first pad and the second first pad are coupled in the first direction to form a plane.

[0062] 16. The method according to any one of clauses 11 to 15, wherein the second cross-sectional area is equal to or less than 30π square micrometers (µm)2 ).

[0063] 17. The method according to any one of clauses 11 to 16, wherein the first die interconnect of the plurality of die interconnects has a first height of less than 37 micrometers (μm).

[0064] 18. The method according to any one of clauses 11 to 17, wherein the solder joint has a second height of less than 30 μm.

[0065] 19. The method according to any one of clauses 11 to 18, wherein the second pad has a third height of at least 10 μm.

Claims

1. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: A bare die, the bare die comprising a plurality of bare die interconnects; and A substrate, the substrate including a lower metallization layer extending in a first direction, the lower metallization layer including a plurality of metal interconnects, the plurality of metal interconnects including: A first pad, the first pad having a first surface and a second surface opposite to the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction; and A second pad, coupled to the first surface, having a second cross-sectional area smaller than the first cross-sectional area extending in the first direction; and The solder joint is coupled to the second pad and a first die interconnect among the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction that is smaller than the first cross-sectional area, the second cross-sectional area being at least equal to the third cross-sectional area.

2. The IC package according to claim 1, The substrate further includes: An upper metallization layer extending in the first direction, the upper metallization layer including a second plurality of metal interconnects, the second plurality of metal interconnects including: The second first pad has a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and The IC package further includes: A second pad extends in the first direction and is adjacent to the third surface, the second pad having a fifth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area; and The second solder joint is coupled to the second second pad and the second die interconnect in the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area, the sixth cross-sectional area being less than or equal to the fifth cross-sectional area.

3. The IC package according to claim 1, wherein: The plurality of metal interconnects also include: The second first pad has a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and The IC package also includes: A second pad extending in the first direction and adjacent to the third surface, the second pad having a fifth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area; and The second solder joint is coupled to the second second pad and the second die interconnect in the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction that is smaller than the fourth cross-sectional area, the sixth cross-sectional area being less than or equal to the fifth cross-sectional area.

4. The IC package of claim 3, wherein the first cross-sectional area is equal to the fourth cross-sectional area, the second cross-sectional area is equal to the fifth cross-sectional area, and the third cross-sectional area is equal to the sixth cross-sectional area.

5. The IC package of claim 3, wherein the first pad and the second first pad are coupled in the first direction to form a plane.

6. The IC package of claim 1, wherein the second cross-sectional area is equal to or less than 30π square micrometers (pm 2 ).

7. The IC package of claim 1, wherein the first die interconnect of the plurality of die interconnects has a first height of less than 37 micrometers (μm).

8. The IC package of claim 6, wherein the solder joint has a second height of less than 30 μm.

9. The IC package of claim 7, wherein the second pad has a third height of at least 10 μm.

10. The IC package of claim 1, wherein the IC package is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet devices; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; and multirotor aircraft.

11. A method for manufacturing a substrate, the method comprising: Forming a die that includes multiple die interconnects; A substrate comprising a lower metallization layer extending in a first direction, the lower metallization layer comprising a plurality of metal interconnects, the plurality of metal interconnects comprising: A first pad, the first pad having a first surface and a second surface opposite to the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction; A second pad is formed coupled to the first surface, the second pad having a second cross-sectional area smaller than the first cross-sectional area extending in the first direction; and A first die interconnect is coupled to the solder joint to the second pad and the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction that is smaller than the first cross-sectional area, the second cross-sectional area being at least equal to the third cross-sectional area.

12. The method of claim 11, wherein the second cross-sectional area is larger than the third cross-sectional area by a certain amount to ensure alignment between the solder joint and the second pad.

13. The method according to claim 11, wherein: The plurality of metal interconnects also include: The second first pad has a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction; and The method further includes: A second pad is formed extending in the first direction and adjacent to the third surface, the second pad having a fifth cross-sectional area extending in the first direction and smaller than the fourth cross-sectional area; and The second solder joint is coupled to the second second pad and the second die interconnect in the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area that extends in the first direction and is smaller than the fourth cross-sectional area, the sixth cross-sectional area matching the fifth cross-sectional area.

14. The method of claim 13, wherein the first cross-sectional area is equal to the fourth cross-sectional area, the second cross-sectional area is equal to the fifth cross-sectional area, and the third cross-sectional area is equal to the sixth cross-sectional area.

15. The method of claim 13, wherein the first pad and the second first pad are coupled in the first direction to form a plane.

16. The method of claim 11, wherein the second cross-sectional area is equal to or less than 30π square micrometers (pm 2 ).

17. The method of claim 11, wherein the first die interconnect of the plurality of die interconnects has a first height of less than 37 micrometers (μm).

18. The method of claim 16, wherein the solder joint has a second height of less than 30 μm.

19. The method of claim 17, wherein the second pad has a third height of at least 10 μm.

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