Methods, apparatus, electronic devices and storage media for instruction fusion in processors

Abstract

This application proposes a method, apparatus, electronic device, and storage medium for instruction fusion in a processor, relating to the field of processor technology. The method includes: acquiring an instruction set in the processor; performing a fusion judgment on any at least two instructions in the instruction set, wherein the fusion judgment is used to determine whether the overall function of the fused at least two instructions can correspond to the function of an existing single instruction in the processor; and, in response to the overall function corresponding to the function of an existing single instruction in the processor, performing instruction fusion on the at least two instructions corresponding to the overall function, which can effectively reduce processor resource consumption and improve instruction execution efficiency and processor performance.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a method, apparatus, electronic device, and storage medium for instruction fusion in a processor. Background Technology

[0002] Improving processor resource utilization efficiency and instruction execution efficiency are key factors in enhancing processor performance and are currently important research topics of widespread concern. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, the first objective of this application is to propose a method for instruction fusion in a processor to improve processor performance.

[0005] The second objective of this application is to provide an apparatus for instruction fusion in a processor.

[0006] The third objective of this application is to propose an electronic device.

[0007] The fourth objective of this application is to provide a computer-readable storage medium.

[0008] The fifth objective of this application is to provide a computer program product.

[0009] To achieve the above objectives, a first aspect of this application provides a method for instruction fusion in a processor, comprising:

[0010] Get the instruction set in the processor; A fusion judgment is performed on any at least two instructions in the instruction set, wherein the fusion judgment is used to determine whether the overall function of the fused at least two instructions can correspond to the function of an existing single instruction in the processor; In response to the fact that the overall function can correspond to a single instruction already existing in the processor, instruction fusion is performed on the at least two instructions corresponding to the overall function.

[0011] To achieve the above objectives, a second aspect of this application provides an apparatus for instruction fusion in a processor, comprising: The acquisition module is used to acquire the instruction set in the processor; The judgment module is used to perform a fusion judgment on any at least two instructions in the instruction set, wherein the fusion judgment is used to determine whether the overall function after the at least two instructions are fused can correspond to the function of a single instruction already existing in the processor. The fusion module is used to perform instruction fusion on at least two instructions corresponding to the overall function in response to the function that can correspond to a single instruction already existing in the processor.

[0012] To achieve the above objectives, a third aspect of this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method described in the first aspect embodiment.

[0013] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method described in the first aspect embodiment.

[0014] To achieve the above objectives, a fifth aspect of this application provides a computer program product including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0015] The method, apparatus, electronic device, and storage medium for instruction fusion in a processor provided in this application determine the fusion of at least two instructions in the instruction set of the processor. When the overall function of the fused at least two instructions corresponds to the function of an existing single instruction in the processor, the at least two instructions are fused to obtain a fused instruction. Multiple instructions are fused into a single fused instruction for execution, which can effectively reduce the processor's resource consumption and improve instruction execution efficiency and processor performance.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A flowchart illustrating a method for instruction fusion in a processor provided in an embodiment of this application; Figure 2 A flowchart illustrating another method for instruction fusion in a processor provided in an embodiment of this application; Figure 3 A logical schematic diagram of a method for instruction fusion in a processor provided in an embodiment of this application; Figure 4This is a structural block diagram of an instruction fusion apparatus in a processor provided in an embodiment of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0019] In a processor, if two or more instructions can be combined into one instruction and processed as a whole in the pipeline, then the two or more instructions only need to occupy one valuable processor resource such as various queues, thus improving the utilization efficiency of each queue.

[0020] If two or more instructions can be merged into one instruction, and the execution phase is also performed as a single instruction, it can not only improve the efficiency of processor resource utilization but also speed up instruction execution. For example, if two instructions originally required two clock cycles to complete, they can be completed in just one clock cycle after merging. Merging instructions with high execution frequency will have a more significant effect on improving processor performance.

[0021] The following description, with reference to the accompanying drawings, describes a method, apparatus, electronic device, and storage medium for instruction fusion in a processor according to embodiments of this application.

[0022] Figure 1 This is a flowchart illustrating a method for instruction fusion in a processor, as provided in an embodiment of this application. Figure 1 As shown, the method includes the following steps: S101, retrieve the instruction set from the processor.

[0023] The instruction set in this embodiment is the Reduced Instruction Set Computer-Five (RISC-V) instruction set, which is a standard language that the chip can understand.

[0024] In some embodiments, the RISC-V instruction set includes integer arithmetic operation instructions, logical operation instructions, control transfer instructions, load and store instructions, and system call instructions.

[0025] S102, perform a fusion judgment on any at least two instructions in the instruction set.

[0026] The fusion judgment is used to determine whether the overall function of at least two fused instructions can correspond to the function of an existing single instruction in the processor.

[0027] In some embodiments, if the overall function of the fused instruction A and instruction B in the instruction set can be implemented by an existing instruction C in the processor, then it is determined that the overall function of the fused instruction A and instruction B can correspond to the function of a single existing instruction C in the processor.

[0028] In some embodiments, if the overall function of the fused instruction A and instruction B in the instruction set can be implemented by the functional unit of the existing instruction C in the processor, except that the output logic and the number of write-back ports of the functional unit are different, then it is determined that the overall function of the fused instruction A and instruction B can correspond to the function of the existing single instruction C in the processor.

[0029] In some embodiments, if the overall function of the fused instruction A and instruction B in the instruction set can be implemented by the functional unit of the existing instruction C in the processor, only the number of input ports and input logic of the functional unit are different, then it is determined that the overall function of the fused instruction A and instruction B can correspond to the function of the existing single instruction C in the processor.

[0030] It is understandable that output logic refers to the logical rules or data path control method followed by the output of the result after the functional unit completes the instruction; the number of write-back ports refers to the number of physical ports that the functional unit can simultaneously write the result back to the register file; the number of input ports refers to the number of physical channels that the functional unit can simultaneously receive external data input; and input logic refers to the control rules or data path configuration followed by the combination, gating, or processing of input signals within the functional unit.

[0031] S103, in response to the fact that the overall function can correspond to a single instruction already existing in the processor, performs instruction fusion on at least two instructions corresponding to the overall function.

[0032] For example, if the overall function of the fused instruction A and instruction B can correspond to the function of a single instruction C already existing in the processor, then instruction A and instruction B are fused to obtain a fused instruction for execution, thereby reducing the processor's resource consumption.

[0033] In this embodiment, for the instruction set in the processor, at least two instructions in the instruction set are fused and judged. If the overall function of the fused at least two instructions can correspond to the function of an existing single instruction in the processor, then the at least two instructions are fused to obtain a fused instruction. Executing the fused instruction can effectively reduce the processor's resource consumption and improve instruction execution efficiency and processor performance.

[0034] Based on the above embodiments, Figure 2 This is a flowchart illustrating another method for instruction fusion in a processor provided in an embodiment of this application. Figure 2As shown, the method includes the following steps: S201, retrieve the instruction set from the processor.

[0035] In this application embodiment, the implementation method of step S201 can be implemented in any of the various embodiments of this disclosure, and no limitation is made here, nor will it be described in detail.

[0036] S202 performs a fusion judgment on any two instructions in the instruction set.

[0037] In this application embodiment, the implementation method of step S202 can be implemented in any of the various embodiments of this disclosure, and no limitation is made here, nor will it be described in detail.

[0038] S203, in response to the fact that the overall function of at least two instructions fused together is the same as the function of a single instruction already existing in the processor, determines that the overall function of at least two instructions fused together can correspond to the function of a single instruction already existing in the processor.

[0039] It is understandable that if the overall function of the fused instruction A and instruction B is the same as the function of a single instruction C already existing in the processor, then it is determined that the overall function of the fused instruction A and instruction B can correspond to the function of a single instruction C already existing in the processor.

[0040] In this embodiment, instruction combinations that satisfy the requirement that the overall function of the fused instruction A and instruction B is the same as the function of instruction C include, but are not limited to: Command A1 "slli r1, r0, 32", Command B1 "srli r1, r1, 32", Command C1 "add.uw r1, r0,zero"; Instruction A2 "slli r1, r0, 48", instruction B2 "srli r1, r1, 48", instruction C2 "zext.h r1,r0"; Command A3 "slliw r1, r0, 16", command B3 "srliw r1, r1, 16", command C3 "zext.h r1,r0"; Instruction A4 "slliw, r1, r0, 16", instruction B4 "sraiw r1, r1, 16", instruction C4 "sext.h r1,r0"; Command A5 "slli r1, r0, 1", Command B5 "add r1, r1, r2", Command C5 "sh1add r1, r0,r2"; Command A6 "slli r1, r0, 2", command B6 "add r1, r1, r2", command C6 "sh2add r1, r0,r2"; Command A7 "slli r1, r0, 3", Command B7 "add r1, r1, r2", Command C7 "sh3add r1, r0,r2".

[0041] (1) For instruction A1 “slli r1, r0, 32”, instruction B1 “srli r1, r1, 32”, instruction C1 “add.uwr1, r0, zero”.

[0042] The RISC-V shift instruction is used to perform a shift operation on a register or an immediate value and store the result in another register. The shift operation moves each bit of an operand to the left or right by a certain number of bits to obtain a new number.

[0043] In some embodiments, the shift instructions in the RISC-V instruction set include ShiftLeft Logical Immediate (slli) and ShiftRight Logical Immediate (srli), which are used to perform logical left or logical right shift operations on the values ​​in the register.

[0044] It is understandable that an immediate logical left shift (slli) shifts the value in a register to the left by an immediate number of bits and fills the empty bits with 0; an immediate logical right shift (srli) shifts the value in a register to the right by an immediate number of bits and fills the empty bits with 0.

[0045] Instruction A1 is “slli r1, r0,32”, where r1 represents the destination register, r0 represents the source register, and 32 is the immediate value, which is the number of bits to shift. Instruction A1 means to logically shift the 64-bit register r0 left by 32 bits, fill the empty bits with 0, and then store it in r1.

[0046] Instruction B1 is “srli r1, r1, 32”, where the first r1 represents the destination register, the second r1 represents the source register, and 32 represents the immediate value, which is the number of bits to shift. Instruction B means to logically shift the 64-bit register r1 to the right by 32 bits, fill the empty bits with 0, and then store them in r1.

[0047] For the instructions A1 "slli r1, r0, 32" and B1 "srli r1, r1, 32", after logically shifting slli left by 32 bits and then logically shifting srli right by 32 bits, it is equivalent to placing the lower 32 bits of register r0 into the lower bits of register r1, while the higher 32 bits of register r1 are all 0. In the RISC-V instruction set, the function of combining instructions A1 and B1 can be converted into a single instruction C1, which is "add.uw r1, r0, zero".

[0048] In the instruction C1 “add.uw r1, r0, zero”, add represents the addition operation, which adds two numbers; uw represents unsigned integer addition, that is, the operands are processed in unsigned integer form, and w represents 32-bit word operation; r1 is the destination register, which stores the addition result; r0 is the first source register, which provides the first value for the addition operation; zero is the second source register, and the value of zero is 0, which is the zero register x0.

[0049] It is understandable that the instruction C1 "add.uw r1, r0, zero" adds the value of register r0 to 0 and stores the result in register r1. Since zero represents zero, i.e. x0, this operation essentially takes the lower 32 bits of the value of r0 and assigns the upper 32 bits to r1 with an unsigned extension of 0. This also achieves the function of placing the lower 32 bits of register r0 in the lower bits of register r1, and the upper 32 bits of register r1 being all 0. Therefore, the combination of instructions A1 "slli r1, r0, 32" and instructions B1 "srli r1, r1, 32" has the same function as instruction C1 "add.uw r1, r0, zero". It is confirmed that the overall function of the fused instructions A1 and B1 corresponds to the function of the existing instruction C1 in the processor.

[0050] (2) For instruction A2 “slli r1, r0, 48”, instruction B2 “srli r1, r1, 48”, instruction C2 “zext.hr1, r0”.

[0051] Instruction A2 is "slli r1, r0, 48", which means shifting register r0 left by 48 bits and placing it into register r1. This is equivalent to placing the lower 16 bits of register r0 into the higher 16 bits of register r1, leaving the lower 48 bits of register r1 as 0.

[0052] Instruction B2 is "srli r1, r1, 48", which means shifting the r1 register to the right by 48 bits. This is equivalent to placing the high 16 bits of the r1 register into the low 16 bits of the r1 register, and the high 48 bits of the r1 register are 0.

[0053] The result of the instructions A2 "slli r1, r0, 48" and B2 "srli r1, r1, 48" is to place the lower 16 bits of register r0 into the lower 16 bits of register r1, and set the higher 48 bits of register r1 to 0. In the RISC-V instruction set, the combined function of these two instructions can be converted into a single instruction C2, which is "zext.h r1, r0".

[0054] The `zext.h` instruction expands a 16-bit value to a 64-bit value using zeros. `zext.h` is an extension instruction in the RISC-V instruction set, belonging to one of the RISC-V extension functions. In the RISC-V extension standard, there is the address generation instruction extension Zba (Bit Manipulation Extension). Instruction C2 "zext.h r1, r0" retrieves a 16-bit (half-word) value from register r0, expands it to 64 bits using zeros, and stores the result in register r1. This instruction performs the function of placing the lower 16 bits of register r0 into the lower 16 bits of register r1, leaving the higher 48 bits of register r1 as 0. Therefore, the combination of instructions A2 "slli r1, r0, 48" and instruction B2 "srli r1, r1, 48" has the same function as instruction C2 "zext.h r1, r0", confirming that the overall function of the merged instructions A2 and B2 corresponds to the function of the existing instruction C2 in the processor.

[0055] (3) Instruction A3 “slliw r1, r0, 16”, instruction B3 “srliw r1, r1, 16”, instruction C3 “zext.hr1, r0”.

[0056] In some embodiments, the 64-bit Integer Base Instruction Set (RV64I) is the foundation of all RISC-V processors, containing basic arithmetic, logic, control flow, and memory access instructions. RV64I is a superset of the 32-bit Integer Base Instruction Set RV32I, and RV32I is a subset of RV64I. Although RV64I has 64-bit addresses and a default data size of 64 bits, 32-bit words are still a valid data type in programs, so RV64I needs to support words. More specifically, because registers are 64-bit wide, RV64I includes word versions of shift instructions to obtain 32-bit shift results instead of 64-bit shift results.

[0057] The Shift Left Logical Immediate Word (slliw) performs a logical left shift on the lower 32 bits of the source register (filling the high bits with 0). The number of bits to shift is specified by the immediate value, and the result is sign-extended to 64 bits and written to the destination register.

[0058] The Shift Right Logical Immediate Word (srliw) performs a logical right shift on the lower 32 bits of the source register (filling the high bits with 0). The number of bits to shift is specified by the immediate value, and the result is sign-extended to 64 bits and stored in the destination register.

[0059] Instruction A3 is "slliw r1, r0, 16" and instruction B3 is "srliw r1, r1, 16". The result of instructions A3 and B3 is that after logically shifting left by 16 bits by slliw, logically shifting right by 16 bits by srliw, it is equivalent to putting the lower 16 bits of register r0 into the lower 16 bits of register r1, and the higher 48 bits of register r1 are 0.

[0060] In the RISC-V instruction set, the function of instruction A3 and the combined function of instruction B3 can be converted into the function of an existing instruction C3. Instruction C3 is "zext.h r1, r0", which means to fetch a 16-bit (half-word) value from register r0, extend it to 64 bits, and store the result in register r1. The function of this instruction is to put the lower 16 bits of register r0 into the lower 16 bits of register r1, and the higher 48 bits of register r1 are 0. Therefore, the combination of instruction A3 "slliw r1, r0, 16" and instruction B3 "srliw r1, r1, 16" has the same function as instruction C3 "zext.h r1, r0", which confirms that the overall function of instruction A3 and instruction B3 after fusion can correspond to the function of instruction C3 in the processor.

[0061] (4) Instruction A4 “slliw, r1, r0, 16”, instruction B4 “sraiw r1, r1, 16”, instruction C4 “sext.hr1, r0”.

[0062] In some embodiments of the RISC-V instruction set, the Sign Extension (SEXT) operation is used to expand a shorter-width immediate value into a longer-width data value. Sign Extension is used when processing immediate values ​​of different widths (e.g., expanding a 12-bit immediate value to 32 bits). SEXT retains the sign bit (most significant bit) of the original data and copies it to fill the higher bits of the target width. SEXT expands the shorter-width data to the target width by copying the sign bit (most significant bit); for example, when expanding a 12-bit immediate value to 32 bits, if the original most significant bit is 1, the higher 20 bits are filled with 1s; if it is 0, it is filled with 0s.

[0063] Instruction A4 is "slliw, r1, r0, 16", and instruction B4 is "sraiw r1, r1, 16". Instruction A4 shifts the logic left of register r0 by 16 bits into r1, meaning the lowest 16 bits of r1 are 0, the highest 32 bits are 0, and bits 16 to 31 are the lowest 16 bits of r0. Then, instruction B4 shifts bits 16 to 31 of r1 into the lowest 16 bits of r1, and bits 16 to 63 are for sign bit extension. Finally, the lowest 16 bits of r0 are placed into the lowest 16 bits of r1, and the highest 48 bits of register r1 are for sign bit extension.

[0064] The combined function of instructions A4 "slliw, r1, r0, 16" and B4 "sraiw r1, r1, 16" can be converted into the function of an existing instruction C4, "sext.h r1, r0". Instruction C4 fills the high bits of r0 with the sign bit until the bit width is equal to the bit width of r1, that is, puts the lowest 16 bits of r0 into the lowest 16 bits of r1, and the high 48 bits of the r1 register are for sign bit extension. Therefore, the combined function of instructions A4 "slliw, r1, r0, 16" and B4 "sraiw r1, r1, 16" is consistent with the function of instruction C4 "sext.h r1, r0", confirming that the overall function of the combined instruction A4 and instruction B4 corresponds to the function of the existing instruction C4 in the processor.

[0065] (5) Instruction A5 “slli r1, r0, 1”, instruction B5 “add r1, r1, r2”, instruction C5 “sh1add r1,r0, r2”.

[0066] The instruction A5 "slli r1, r0, 1" means shifting the value of the source register r0 one bit to the left (arithmetic shift, retaining the sign bit) and placing it in r1.

[0067] The instruction B5 "add r1, r1, r2" means adding r1 and r2 and storing the result in r1.

[0068] In instruction C5 "sh1add r1, r0, r2", "sh1add" means left shift by 1 bit and add (Shift Left One and Add, sh1add); rd is the destination register, which stores the calculation result; rs1 is the source register to be left shifted by one bit; rs2 is the source register to be added; this instruction C5 is used to left shift the value of source register r0 by one bit (arithmetic shift, retaining the sign bit) and add it to the value of source register r2, and store the result in the destination register r1.

[0069] The combined function of instruction A5 "slli r1, r0, 1" and instruction B5 "add r1, r1, r2" is consistent with the function of instruction C5 "sh1add r1, r0, r2", confirming that the overall function of instruction A5 and instruction B5 after merging can correspond to the function of instruction C5 already in the processor.

[0070] (6) Instruction A6 “slli r1, r0, 2”, instruction B6 “add r1, r1, r2”, instruction C6 “sh2add r1,r0, r2”.

[0071] `sh2add` is an extension instruction in the RISC-V instruction set, belonging to the instruction type that combines bitwise operations and arithmetic operations. It is primarily used for efficient shift and addition operations. Its core function is to shift the value of source register `rs1` left by 2 bits and add it to the value of `rs2`, storing the result in the destination register `rd`. The instruction format is: `sh2add rd, rs1, rs2`; where `rd` is the destination register storing the calculation result; `rs1` is the source register to be shifted left by 2 bits; and `rs2` is the source register to be added. The execution formula is: `rd = (rs1 << 2) + rs2`, where the shift is a logical left shift (filling the least significant bit with zeros).

[0072] The instruction A6 "slli r1, r0, 2" means shifting the value of the source register r0 left by 2 bits (arithmetic shift, retaining the sign bit) and placing it in r1.

[0073] The instruction B6 "add r1, r1, r2" means adding r1 and r2 and storing the result in r1.

[0074] In the instruction C6 “sh2add r1, r0, r2”, “sh2add” means left shift by 2 bits and add. Here, rd is the destination register, which stores the calculation result; rs1 is the source register to be left shifted by 2 bits; and rs2 is the source register to be added. Instruction C6 is used to left shift the value of source register r0 by 2 bits (arithmetic shift, retaining the sign bit) and add it to the value of source register r2, and store the result in the destination register r1.

[0075] The combined function of instruction A6 “slli r1, r0, 2” and instruction B6 “add r1, r1, r2” is consistent with the function of C6 “sh2addr1, r0, r2”, confirming that the overall function of instruction A6 and instruction B6 after fusion can correspond to the function of instruction C6 already in the processor.

[0076] (7) Instruction A7 “slli r1, r0, 3”, instruction B7 “add r1, r1, r2”, instruction C7 “sh3add r1,r0, r2”.

[0077] In the RISC-V architecture, the SH3ADD (Shift Left Three and Add) instruction is used to shift the value of source register rs1 left by 3 bits and add it to the value of another source register rs2, storing the result in the destination register rd. This instruction is an arithmetic shift operation, suitable for efficiently implementing multiplication by 8 and addition. The instruction format is: sh3add rd, rs1, rs2, where rd is the destination register that stores the calculation result; rs1 is the source register to be shifted left by 3 bits; and rs2 is the source register to be added.

[0078] The instruction A7 "slli r1, r0, 3" means shifting the value of the source register r0 left by 3 bits (arithmetic shift, retaining the sign bit) and placing it in r1.

[0079] The instruction B7 "add r1, r1, r2" means adding r1 and r2 and storing the result in r1.

[0080] In instruction C7 “sh3add r1, r0, r2”, rd is the destination register that stores the calculation result; rs1 is the source register that is shifted left by 3 bits; and rs2 is the source register that is added. Instruction C7 is used to shift the value of source register r0 left by 3 bits (arithmetic shift, retaining the sign bit) and add it to the value of source register r2, and store the result in destination register r1.

[0081] The combined function of instruction A7 "slli r1, r0, 3" and instruction B7 "add r1, r1, r2" is consistent with the function of instruction C7 "sh3add r1, r0, r2", confirming that the overall function of the fused instruction A7 and instruction B7 corresponds to the function of the existing instruction C7 in the processor.

[0082] S204, based on the overall function of at least two instructions fused together, matches the first functional unit with the same function in the processor.

[0083] The first functional unit is the unit that implements the function of any single instruction.

[0084] Understandably, functional units with the same function can be obtained by matching within the processor based on the overall function of at least two fused instructions.

[0085] S205, in response to matching a first functional unit with the same function, and realizing the overall function only requires adjusting the output logic and the number of write-back ports of the first functional unit, determine that the overall function after the fusion of at least two instructions can correspond to the function of an existing single instruction in the processor.

[0086] For example, suppose that the function of the combined instruction A and instruction B can be implemented by functional unit D, but the output logic and the number of write-back ports of the functional unit are different. Then the overall function of the combined instruction A and instruction B can correspond to the function of a single instruction that already exists in the processor.

[0087] For example, instruction A8 is "addiw r1,r0, imm", which adds the result of register r0 and the immediate value imm1 into register r1. Then, ANDi r1, r1, imm2 performs an immediate AND operation, which is equivalent to using imm2 plus a mask to select the output. It is equivalent to using the functional unit of addiw r1, r0, imm1, that is, the opcode of the functional unit addiw, and the output is using the immediate value imm2 plus a mask.

[0088] All function unit instructions, including addition, subtraction, multiplication, division, XOR, etc., followed by instruction B8 "andi r1, r1,255", can be combined into a single function unit instruction. When outputting, a mask can be added to select the output. Therefore, for all function unit instructions followed by instruction B8 "andi r1, r1, 255", they can be combined into the same function unit instruction operation, and a mask can be added after the result is output.

[0089] It is understood that in this embodiment, the instructions A8 "addiw r1,r0, imm" and B8 "andi r1, r1,255" are combined into a functional unit: the Arithmetic Logic Unit (ALU) performs an immediate word operation (addiw op), and adds a mask after marking the output result; the ALU is a core hardware module specifically designed to perform operations such as addition, subtraction, AND, OR, NOT, shifting, addition concatenation, and mask selection.

[0090] In this embodiment, after ALU addition, concatenation is performed, and the addition output position is connected to a multiplexer to select the required data according to the byte.

[0091] S206, based on the overall function of at least two instructions fused together, matches a second functional unit with the same function in the processor.

[0092] The second functional component is the component that implements the function of any single instruction.

[0093] S207, in response to matching a second functional unit with the same function, and realizing the overall function only requires adjusting the number of input ports and input logic of the second functional unit, it is determined that the overall function after the fusion of at least two instructions can correspond to the function of an existing single instruction in the processor.

[0094] For example, instruction A9 is "slli r1, r0, 4" and instruction B9 is "add r1, r1, r2". Instruction A9 performs a logical left shift of register r0 by 4 bits into register r1. Then instruction B9 performs an addition operation, which is equivalent to first concatenating bits 0 to 59 of the input register into bits 4 to 63, and then performing the addition. It is equivalent to using the functional unit add r1, r1, r2, i.e., the opcode of the functional unit add, where the input is first concatenated and then the addition is performed.

[0095] All instructions that begin with a shift instruction (including logical and arithmetic left and right shifts, etc.) and are followed by a function unit instruction (including addition, subtraction, multiplication, division, etc.) can be combined into a single function unit instruction by performing a bitwise concatenation operation at the input terminal before inputting the data.

[0096] In this embodiment, the instructions A9 "slli r1, r0, 4" and B9 "add r1, r1, r2" are combined into an addition operation "add op" of the functional unit ALU, and a multiplexer is added to the input terminal of the functional unit add. That is, the instructions A9 "sllir1, r0, 4" and B9 "add r1, r1, r2" are added after concatenating the input positions.

[0097] S208, in response to the overall function being able to correspond to a single instruction already existing in the processor, performs instruction fusion on at least two instructions corresponding to the overall function.

[0098] It is understandable that at least two instructions corresponding to the overall function are fused, that is, at least two instructions are merged into one fused instruction. In this embodiment, the fused instruction is also marked according to the implementation method of the overall function. The mark is used to indicate whether the fused instruction needs to perform data preprocessing operation on the input end of the functional component or data postprocessing operation on the output end.

[0099] Optionally, before the fusion instruction is executed, in response to the flag indicating that the input of the functional unit needs to be preprocessed, a concatenation operation is performed on the data input to the functional unit, such as the fusion of instruction A9 and instruction B9.

[0100] Optionally, after the fusion instruction is executed, in response to the flag indicating that the output of the functional unit needs to be processed, a mask selection operation is performed on the data output by the functional unit, such as the fusion of instruction A8 and instruction A9.

[0101] In this embodiment, for the instruction set in the processor, at least two instructions in the instruction set are fused and judged. The overall function of the fused two instructions is consistent with the function of the existing instructions, and the overall function of the fused two instructions can be implemented by the functional unit. Only the output logic, write-back port number or input port and input logic of the functional unit need to be adjusted. Multiple basic instructions can be merged into a single fused instruction, which greatly reduces the overhead of instruction decoding, scheduling, instruction fetching and pipeline execution stages. By reusing existing mature functional units, there is no need to reconstruct the processor hardware architecture on a large scale. This effectively reduces the instruction execution cycle, reduces processor power consumption and resource consumption, and improves instruction execution efficiency and processor performance.

[0102] Figure 3 This is a logical diagram illustrating a method for instruction fusion in a processor, provided as an embodiment of this application. Figure 3 As shown, in the instruction decoding stage, it is determined whether two instructions meet the conditions for merging instructions. If they do, they are merged into one instruction, and it is marked whether the instruction needs to be operated at the input or output end of the functional unit. At the input end of the functional unit, if the merged instruction is marked to be operated at the input end of the functional unit, the corresponding operation is executed. In the functional unit execution stage, the instruction is executed. At the output end of the functional unit, if the merged instruction is marked to be operated at the output end of the functional unit, the corresponding operation is executed.

[0103] To implement the above embodiments, this application also proposes an apparatus for instruction fusion in a processor.

[0104] Figure 4 This is a schematic diagram of a device for instruction fusion in a processor, provided as an embodiment of this application. Figure 4 As shown, the instruction fusion device 400 in the processor includes: Acquisition module 401 is used to acquire the instruction set in the processor; The judgment module 402 is used to perform a fusion judgment on any at least two instructions in the instruction set, wherein the fusion judgment is used to determine whether the overall function after the fusion of at least two instructions can correspond to the function of a single instruction already existing in the processor. The fusion module 403 is used to perform instruction fusion on at least two instructions corresponding to the overall function in response to the function that can correspond to a single instruction already existing in the processor.

[0105] Furthermore, in one possible implementation of this application embodiment, the determination module 402 is used for: In response to the fact that the overall function of the fusion of at least two instructions is the same as the function of a single instruction already existing in the processor, it is determined that the overall function of the fusion of at least two instructions corresponds to the function of a single instruction already existing in the processor.

[0106] Furthermore, in one possible implementation of this application embodiment, the determination module 402 is further configured to: Based on the overall function after the fusion of at least two instructions, a first functional unit with the same function is matched in the processor. The first functional unit is a unit that implements the function of any single instruction. In response to a first functional unit with the same function being matched, and the implementation of the overall function only requires adjusting the output logic and the number of write-back ports of the first functional unit, it is determined that the overall function after the fusion of at least two instructions can correspond to the function of an existing single instruction in the processor.

[0107] Furthermore, in one possible implementation of this application embodiment, the determination module 402 is further configured to: Based on the overall function of at least two instructions fused together, a second functional unit with the same function is matched in the processor. The second functional unit is a unit that implements the function of any single instruction. In response to the matching of a second functional unit with the same function, and the realization of the overall function only requires adjusting the number of input ports and input logic of the second functional unit, it is determined that the overall function after the fusion of at least two instructions can correspond to the function of an existing single instruction in the processor.

[0108] Furthermore, in one possible implementation of this application embodiment, the fusion module 403 is used for: At least two instructions are merged into one fusion instruction, and the fusion instruction is marked according to the overall function implementation method. The mark is used to indicate whether the fusion instruction needs to perform data preprocessing operation on the input end of the functional unit or data postprocessing operation on the output end.

[0109] Furthermore, in one possible implementation of this application embodiment, the fusion module 403 is further configured to: Before the fusion instruction is executed, in response to the flag indicating that the fusion instruction needs to perform data preprocessing operations on the input end of the functional unit, the data input to the functional unit is concatenated.

[0110] Furthermore, in one possible implementation of this application embodiment, the fusion module 403 is further configured to: After the fusion instruction is executed, in response to the flag indicating that the fusion instruction needs to perform data post-processing operations on the output of the functional unit, a mask selection operation is performed on the data output by the functional unit.

[0111] It should be noted that the foregoing explanation of the method embodiment for instruction fusion in a processor also applies to the apparatus for instruction fusion in a processor in this embodiment, and will not be repeated here.

[0112] In this embodiment, for the instruction set in the processor, at least two instructions in the instruction set are fused and judged. The overall function of the fused two instructions is consistent with the function of the existing instructions, and the overall function of the fused two instructions can be implemented by the functional unit. Only the output logic, write-back port number or input port and input logic of the functional unit need to be adjusted. Multiple basic instructions can be merged into a single fused instruction, which greatly reduces the overhead of instruction decoding, scheduling, instruction fetching and pipeline execution stages. By reusing existing mature functional units, there is no need to reconstruct the processor hardware architecture on a large scale. This effectively reduces the instruction execution cycle, reduces processor power consumption and resource consumption, and improves instruction execution efficiency and processor performance.

[0113] To implement the above embodiments, this application also proposes an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0114] To implement the above embodiments, this application also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided in the foregoing embodiments.

[0115] To implement the above embodiments, this application also proposes a computer program product, including a computer program that, when executed by a processor, implements the methods provided in the foregoing embodiments.

[0116] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in this application all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0117] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0118] This application is intended to provide an implementation scheme for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0119] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0120] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0121] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0122] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0123] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0124] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0125] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0126] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method of instruction fusion in a processor, the method comprising: The method includes: Get the instruction set in the processor; A fusion judgment is performed on any at least two instructions in the instruction set, wherein the fusion judgment is used to determine whether the overall function of the fused at least two instructions can correspond to the function of a single instruction already existing in the processor; In response to the fact that the overall function can correspond to a single instruction already existing in the processor, instruction fusion is performed on the at least two instructions corresponding to the overall function.

2. The method of claim 1, wherein, Determining whether the overall function of the fused at least two instructions corresponds to the function of a single instruction already existing in the processor includes: In response to the fact that the overall function of the fusion of the at least two instructions is the same as the function of a single instruction already existing in the processor, it is determined that the overall function of the fusion of the at least two instructions can correspond to the function of a single instruction already existing in the processor.

3. The method of claim 1, wherein, The step of determining whether the overall function of the fused at least two instructions can correspond to the function of a single instruction already existing in the processor further includes: Based on the overall function of the fusion of the at least two instructions, a first functional unit with the same function is matched in the processor, wherein the first functional unit is a unit that implements the function of any single instruction; In response to a first functional component with the same function being matched, and the implementation of the overall function only requires adjusting the output logic and the number of write-back ports of the first functional component, it is determined that the overall function after the fusion of the at least two instructions can correspond to the function of an existing single instruction in the processor.

4. The method of claim 1, wherein, The step of determining whether the overall function of the fused at least two instructions can correspond to the function of a single instruction already existing in the processor further includes: Based on the overall function of the fusion of the at least two instructions, a second functional unit with the same function is matched in the processor. The second functional unit is a unit that implements the function of any single instruction. In response to the matching of a second functional component with the same function, and the realization of the overall function only requires adjusting the number of input ports and input logic of the second functional component, it is determined that the overall function after the fusion of the at least two instructions can correspond to the function of an existing single instruction in the processor.

5. The method according to claim 3 or 4, characterized in that, The instruction fusion of the at least two instructions corresponding to the overall function includes: The at least two instructions are merged into one fusion instruction, and the fusion instruction is marked according to the implementation method of the overall function. The mark is used to indicate whether the fusion instruction needs to perform data preprocessing operation on the input end of the functional component or data postprocessing operation on the output end.

6. The method of claim 5, wherein, The method further includes: Before the fusion instruction is executed, in response to the flag indicating that the fusion instruction needs to perform data preprocessing operation on the input terminal of the functional component, a concatenation operation is performed on the data input to the functional component.

7. The method of claim 5, wherein, The method further includes: After the fusion instruction is executed, in response to the flag indicating that the fusion instruction needs to perform data post-processing operation on the output of the functional component, a mask selection operation is performed on the data output by the functional component.

8. An apparatus for instruction fusion in a processor, the apparatus comprising: include: The acquisition module is used to acquire the instruction set in the processor; The judgment module is used to perform a fusion judgment on any at least two instructions in the instruction set, wherein the fusion judgment is used to determine whether the overall function after the fusion of the at least two instructions can correspond to the function of a single instruction already existing in the processor. The fusion module is used to perform instruction fusion on at least two instructions corresponding to the overall function in response to the function that can correspond to a single instruction already existing in the processor.

9. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-7.

11. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-7.

Images