Mapping method and apparatus for logical lanes and physical lanes of a chip

Abstract

This application provides a method and apparatus for mapping logic channels and physical channels of a chip, relating to the field of chip testing technology. The method includes: obtaining an initial mapping table for the target chip, the initial mapping table including mapping relationships between multiple logic channels and multiple physical channels of the target chip, the mapping relationships including multiple sequential values; during the final testing stage of the chip, when a faulty physical channel is identified, re-establishing a one-to-one correspondence between the logic channels starting from the logic channel corresponding to the first faulty physical channel in the sequence and the sequential values ​​corresponding to the normal physical channels following the first faulty physical channel in the sequence, obtaining a final mapping table; and writing the final mapping table into a programmable memory unit of the target chip to complete the mapping of the logic channels and physical channels of the target chip. This solution can improve chip yield and reduce the development cost of chip and software adaptation.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, specifically to a method and apparatus for mapping logical channels and physical channels of a chip. Background Technology

[0002] The BeiDou navigation chip tracking engine has multiple physical channels. If any physical channel fails during mass production, the chip will be directly identified as defective, resulting in low yield. Although some manufacturers classify faulty chips (Class I / II / III), the differences in fault channels among different chips mean that user software needs to be adapted separately, leading to poor compatibility and high development costs. Therefore, a technical solution is needed to improve chip yield and reduce the development costs of chip and software adaptation. Summary of the Invention

[0003] The purpose of this application is to provide a method and apparatus for mapping logic channels and physical channels of a chip.

[0004] To achieve the above objectives, the first aspect of this application provides a method for mapping logic channels and physical channels in a chip, comprising: Obtain the initial mapping table of the target chip, wherein the initial mapping table includes the mapping relationship between multiple logical channels and multiple physical channels of the target chip, the mapping relationship includes multiple sequential values, the multiple sequential values ​​correspond one-to-one with the multiple physical channels, and the multiple logical channels correspond one-to-one with the multiple sequential values; During the final chip testing phase, when a faulty physical channel is identified, the logical channels from the first faulty physical channel at the top of the list are sequentially re-established with the order values ​​of the normal physical channels that follow the first faulty physical channel in the list, thus obtaining the final mapping table. The final mapping table is written into the programmable memory cell of the target chip to complete the mapping between the logical channels and physical channels of the target chip.

[0005] In this embodiment, during the final chip testing phase, when a faulty physical channel is identified, the logical channels, starting from the logical channel corresponding to the first faulty physical channel, are sequentially re-established with the order values ​​corresponding to the normal physical channels following the first faulty physical channel to obtain the final mapping table. This includes: during the final chip testing phase, the order values ​​of the detected faulty physical channels are determined as invalid order values, and the order values ​​of the detected normal physical channels are determined as valid order values; starting from the invalid order value corresponding to the first faulty physical channel, for each invalid order value, the invalid order value is swapped with a valid order value following the invalid order value until no valid order value follows the invalid order value, at which point the swapping stops; if the swapping stops, the faulty physical channel is masked according to the invalid order values ​​present in the initial mapping table to obtain the final mapping table.

[0006] In this embodiment, determining the sequence value of the detected faulty physical channel as an invalid sequence value and the sequence value of the detected normal physical channel as a valid sequence value includes: during the final chip testing stage, each physical channel is tested according to a preset order, where the preset order is the default order of multiple logic channels; if the currently detected physical channel is a faulty physical channel, the sequence value of the faulty physical channel is replaced with an invalid sequence value; if the currently detected physical channel is a normal physical channel, the sequence value of the normal physical channel is retained as a valid sequence value; starting from the invalid sequence value corresponding to the first faulty physical channel at the top of the sort, for each invalid sequence value, the invalid sequence value is swapped with a valid sequence value following the invalid sequence value, until the swapping is terminated when there is no valid sequence value after the invalid sequence value, which includes: starting from the invalid sequence value corresponding to the first faulty physical channel at the top of the sort, if the currently detected physical channel is a normal physical channel and there is an invalid sequence value before the valid sequence value corresponding to the normal physical channel, the invalid sequence value and the valid sequence value are swapped, until all physical channels have been tested, and the swapping is terminated.

[0007] In this embodiment of the application, swapping an invalid sequence value with a valid sequence value that follows the invalid sequence value includes: multiplying the invalid sequence value by multiple fault masks in a traversal manner until the result of multiplying the invalid sequence value with the fault mask is a valid sequence value that follows the invalid sequence value; replacing the invalid sequence value with a valid sequence value, and replacing the valid sequence value that follows the invalid sequence value with an invalid sequence value.

[0008] In this embodiment of the application, masking the faulty physical channel based on the invalid sequence value existing in the initial mapping table includes: rewriting the invalid sequence value into a masking code to mask the faulty physical channel.

[0009] In this embodiment, invalid sequence values ​​are represented by masking codes; masking faulty physical channels based on invalid sequence values ​​existing in the initial mapping table includes masking faulty physical channels based on masking codes existing in the initial mapping table.

[0010] In this embodiment, the programmable memory unit is the efuse memory of the target chip.

[0011] The second aspect of this application provides a method for loading a mapping relationship between logical channels and physical channels of a chip. The mapping relationship loading method includes: chip initialization; reading a final mapping table in a one-time programmable memory cell, wherein the final mapping table is obtained according to the mapping method for logical channels and physical channels of a chip provided in the first aspect of this application; writing the parsing result of the final mapping table into a channel mapping buffer; and determining the corresponding physical channel based on the parsing result of the final mapping table in the mapping buffer when the user specifies the use of a logical channel.

[0012] A third aspect of this application provides a mapping apparatus for logic channels and physical channels of a chip, comprising: an interface unit connected to a target chip; and a processor configured to execute the mapping method for logic channels and physical channels of a chip provided in the first aspect of this application.

[0013] A fourth aspect of this application provides a machine-readable storage medium storing instructions that, when executed by a processor, cause the processor to execute the mapping method for logical and physical channels of a chip provided in the first aspect of this application.

[0014] Through the above technical solution, a correspondence can be established between the logical channels that are prioritized and the normal physical channels. When the user uses the target chip and continuously calls the logical channels based on the software, the user can successfully call the logical channels and their physical channels that are prioritized. This prevents the software from failing or reporting errors due to the presence of faulty physical channels when continuously calling logical channels. As a result, the target chip can still be used by the user even when there are physical channel failures, thereby improving the chip yield. Furthermore, the mapping method for logical channels and physical channels of the chip based on the embodiments of this application can achieve the effect of flexibly adjusting the channel usage strategy based on physical channel failures. The user software can directly call the logical channels continuously based on the final mapping table of the target chip and use the normal physical channels and shield the faulty physical channels, thereby reducing the adaptation and development cost of the chip and software.

[0015] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings: Figure 1 The illustration shows a flowchart of a mapping method for logic channels and physical channels of a chip according to an embodiment of this application; Figure 2 The schematic diagram illustrates a flowchart of another method for mapping logic channels and physical channels for a chip according to an embodiment of this application; Figure 3 The schematic diagram illustrates a flowchart of another mapping method for logic channels and physical channels of a chip according to an embodiment of this application; Figure 4 The diagram illustrates the internal structure of a computer device according to an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0019] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0020] The acquisition, transmission, storage, use, and processing of data in this application comply with relevant laws and regulations. Furthermore, it should be noted that existing industry solutions such as software, components, and models may be mentioned in the embodiments of this application. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that such solutions have been or necessarily used.

[0021] The Beidou navigation chip tracking engine has multiple physical channels. If any physical channel fails during mass production, the chip will be directly identified as defective, resulting in low yield. To improve chip yield and allow chips with some damaged physical channels to continue to be used, this application provides a mapping method for chip logic channels and physical channels. This method can reconfigure the mapping relationship between physical and logical channels based on the detection results of physical channels during the final chip testing stage. This allows the chip's physical channels to be effectively utilized by users, improving chip mass production yield and providing users with a unified logic channel interface, reducing user software adaptation costs.

[0022] Figure 1 A schematic flowchart illustrating a mapping method for logic channels and physical channels of a chip according to an embodiment of this application is shown. Figure 1 As shown in one embodiment of this application, a mapping method for logic channels and physical channels of a chip is provided. This embodiment mainly illustrates the application of this method to a chip final testing device, including the following steps: S102. Obtain the initial mapping table of the target chip, wherein the initial mapping table includes the mapping relationship between multiple logical channels and multiple physical channels of the target chip, the mapping relationship includes multiple sequential values, the multiple sequential values ​​correspond one-to-one with the multiple physical channels, and the multiple logical channels correspond one-to-one with the multiple sequential values. S104. During the final chip testing phase, when a faulty physical channel is identified, the logical channels from the first faulty physical channel at the top of the sorting are sequentially re-established with the order values ​​of the normal physical channels that are after the first faulty physical channel in the sorting, to obtain the final mapping table. S106. Write the final mapping table into the programmable memory cell of the target chip to complete the mapping between the logical channels and physical channels of the target chip.

[0023] The initial mapping table of the target chip includes mapping relationships between multiple logical channels and multiple physical channels. If all physical channels of the target chip can function normally, then when the user uses the target chip based on software and continuously calls logical channels, the physical channel corresponding to the logical channel can be successfully determined and used based on the initial mapping table. However, during the final chip testing stage, if the target chip is found to have faulty physical channels, and the user still uses the target chip based on software and continuously calls logical channels, the presence of the faulty physical channels will cause errors in the continuous calls to logical channels, and the software will fail to run or report errors. The mapping method for logical channels and physical channels of a chip provided in this application, after obtaining the initial mapping table of the target chip, can, during the final chip testing stage, during the detection of each physical channel, re-establish a one-to-one correspondence between the logical channels starting from the logical channel corresponding to the first faulty physical channel in the sorting order and the sequence values ​​corresponding to the normal physical channels that are located after the first faulty physical channel in the sorting order, thus obtaining the final mapping table. This establishes a correspondence between the first-order logical channels and the normal physical channels. When users utilize the target chip via software and continuously call logical channels, they can successfully call the first-order logical channel and its corresponding physical channel. This prevents software malfunctions or errors caused by faulty physical channels during continuous logical channel calls. Consequently, the target chip remains usable even with physical channel failures, improving chip yield. Furthermore, the mapping method for logical and physical channels in this application allows for flexible adjustment of channel usage strategies based on physical channel failures. User software can directly call logical channels continuously based on the target chip's final mapping table, using both normal and disabled physical channels, thereby reducing the development costs associated with chip and software compatibility.

[0024] As an example, assuming the target chip has 8 physical channels and 8 logical channels, the initial mapping table of the target chip can be, for example, [0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000]. In the initial mapping table, 0001 represents the first sequential value, that is, the mapping relationship between the first logical channel and the first physical channel; 0010 represents the second sequential value, that is, the mapping relationship between the second logical channel and the second physical channel; and so on, the initial mapping table has a total of 8 mapping relationships, and 1000 represents the eighth sequential value, that is, the mapping relationship between the eighth logical channel and the eighth physical channel.

[0025] Assuming only the second physical channel is detected as a faulty physical channel, the mapping method for logic channels and physical channels of a chip provided in this application can identify the second physical channel as the first faulty physical channel in the order of priority, and the second logical channel as the logical channel corresponding to the first faulty physical channel in the order of priority. Therefore, it is necessary to establish a one-to-one correspondence between each logical channel starting from the second logical channel and each physical channel following the second physical channel to obtain the final mapping table.

[0026] The final mapping table can be, for example, [0001, 0011, 0100, 0101, 0110, 0111, 1000, 0010]. In the final mapping table, 0001 represents the first sequential value, i.e., the mapping relationship between the first logical channel and the first physical channel; 0011 represents the third sequential value, which represents the mapping relationship between the second logical channel and the third physical channel; 0100 represents the fourth sequential value, which represents the mapping relationship between the third logical channel and the fourth physical channel, and so on. That is, the multiple sequential values ​​in the final mapping table correspond to the first logical channel, the second logical channel, and so on, up to eight logical channels. The last one, 0010, represents the second sequential value, which represents the mapping relationship between the eighth logical channel and the second physical channel. Therefore, the mapping method for logical channels and physical channels of a chip based on the embodiments of this application can achieve the effect of flexibly adjusting the channel usage strategy based on physical channel failure, so that the logical channels that are ranked first can be associated with normal physical channels. When the user uses the target chip based on software and calls the logical channels one after another, the logical channels and their physical channels that are ranked first can be successfully called. This prevents the software from failing to run or reporting errors due to the presence of faulty physical channels when calling the logical channels one after another.

[0027] In some embodiments of this application, see Figure 2 Step S104 may include: S202. During the final chip testing phase, the sequence values ​​of the detected faulty physical channels are determined as invalid sequence values, and the sequence values ​​of the detected normal physical channels are determined as valid sequence values. S204. Starting from the invalid sequence value corresponding to the first faulty physical channel at the top of the sequence, for each invalid sequence value, swap the invalid sequence value with the valid sequence value that follows the invalid sequence value, until there is no valid sequence value after the invalid sequence value, then terminate the swapping. S206. In the case of termination of the swap, the faulty physical channel is masked according to the invalid sequence value existing in the initial mapping table to obtain the final mapping table.

[0028] There can be multiple faulty physical channels. Based on the above steps, the invalid sequence values ​​corresponding to multiple first faulty physical channels can be placed at the end of the final mapping table, so that the logical channels that are sorted first can be associated with normal physical channels. Furthermore, the faulty physical channels can be blocked based on the invalid sequence values, thereby preventing the software from calling the logical channels that are sorted later and correspond to the faulty physical channels.

[0029] In some embodiments of this application, see Figure 3 Step S202 may include: S302. During the final chip testing phase, each physical channel is tested according to a preset order, which is the default order of multiple logical channels. If the currently tested physical channel is a faulty physical channel, the order value of the faulty physical channel is replaced with an invalid order value. If the currently tested physical channel is a normal physical channel, the order value of the normal physical channel is retained as a valid order value.

[0030] Specifically, the default order of multiple logical channels can be seen in the example above. For example, it can be the order in which the user software reads the final mapping table in the programmable memory unit, i.e., in a final mapping table: [0001, 0011, 0100, 0101, 0110, 0111, 1000, 0010]. The order in which the user software reads the final mapping table in the programmable memory unit and the default order of multiple logical channels are the order of the final mapping table from left to right.

[0031] Step S204 may include: S304. Starting from the invalid sequence value corresponding to the first faulty physical channel at the top of the sequence, if the currently detected physical channel is a normal physical channel and there is an invalid sequence value before the valid sequence value corresponding to the normal physical channel, the invalid sequence value and the valid sequence value are swapped until all physical channels have been detected, and then the swapping is terminated.

[0032] To achieve the swapping of invalid sequence values ​​and valid sequence values ​​that follow the invalid sequence value, the above embodiment detects subsequent physical channels after determining the existence of an invalid sequence value. If a normal physical channel is detected, and an invalid sequence value precedes the valid sequence value corresponding to the normal physical channel, the invalid and valid sequence values ​​are swapped until all physical channels have been detected, at which point the swapping ends. This places the valid sequence value corresponding to the normal physical channel at the front. In this process, regardless of how many invalid sequence values ​​precede the valid sequence value, the above steps allow for the placement of the valid sequence value at the front and the placement of all existing invalid sequence values ​​at the back during the physical channel detection process.

[0033] In some embodiments of this application, step S304, which involves swapping an invalid sequence value with a valid sequence value that follows the invalid sequence value, may include: multiplying the invalid sequence value by multiple fault masks in a traversal manner until the result of multiplying the invalid sequence value with the fault mask is a valid sequence value that follows the invalid sequence value; replacing the invalid sequence value with a valid sequence value, and replacing the valid sequence value that follows the invalid sequence value with an invalid sequence value.

[0034] In some embodiments of this application, step S206, which involves masking the faulty physical channel based on invalid sequence values ​​present in the initial mapping table, may include: rewriting the invalid sequence values ​​into masking codes to mask the faulty physical channel. Specifically, the masking code may be, for example, a preset masking code such as ffff, indicating that the physical channel is inaccessible due to failure.

[0035] In some embodiments of this application, the programmable memory unit may be a one-time programmable memory unit. A one-time programmable memory unit may be, for example, an efuse memory.

[0036] This application embodiment also provides a method for loading the mapping relationship between logical channels and physical channels of a chip, including: chip initialization, reading the final mapping table in a one-time programmable memory unit, wherein the final mapping table is obtained according to the mapping method for logical channels and physical channels of a chip provided in this application embodiment; writing the parsing result of the final mapping table into a channel mapping buffer; and determining the corresponding physical channel based on the parsing result of the final mapping table in the mapping buffer when the user specifies the use of a logical channel.

[0037] In summary, the mapping method for logical and physical channels of a chip provided in this application establishes a correspondence between the first-order logical channels and the normal physical channels. This allows user software to successfully call the first-order logical channel and its corresponding physical channel when using the target chip and continuously calling logical channels. This prevents software malfunctions or errors caused by faulty physical channels during continuous logical channel calls, ensuring the target chip can still be used even with physical channel failures, thus improving chip yield. Furthermore, the mapping method for logical and physical channels of a chip based on this application allows for flexible adjustment of channel usage strategies based on physical channel failures. User software can directly call logical channels continuously based on the final mapping table of the target chip and use both normal and disabled physical channels, thereby reducing the development cost of chip and software adaptation.

[0038] It should be understood that while the steps in the flowchart of this application embodiment are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0039] This application also provides a mapping device for logic channels and physical channels of a chip. The device includes: an interface unit connected to a target chip; and a processor configured to execute the mapping method for logic channels and physical channels of a chip according to embodiments of this application. The mapping device for logic channels and physical channels of a chip may be, for example, a chip final testing device.

[0040] This application also provides a machine-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform a mapping method for logical and physical channels of a chip according to embodiments of this application.

[0041] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown in the figure, the computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05, and a memory (not shown) connected via a system bus. The processor A01 provides computing and control capabilities. The memory includes internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 stored in the non-volatile storage medium A06. The network interface A02 is used for communication with external terminals via a network connection. When the computer program is executed by the processor A01, it implements a mapping method for logical and physical channels of a chip. The display screen A04 can be a liquid crystal display (LCD) or an e-ink display. The input device A05 can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0042] Those skilled in the art will understand that Figure 4The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0043] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0044] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0045] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0046] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0047] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0048] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0049] Computer-readable media include both permanent and non-permanent, removable and non-removable media, which can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0050] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0051] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for mapping logical lanes and physical lanes of a chip, characterized in that, The mapping method includes: Obtain the initial mapping table of the target chip, wherein the initial mapping table includes the mapping relationship between multiple logical channels and multiple physical channels of the target chip, the mapping relationship includes multiple sequence values, the multiple sequence values ​​correspond one-to-one with the multiple physical channels, and the multiple logical channels correspond one-to-one with the multiple sequence values; During the final chip testing phase, when a faulty physical channel is identified, the logical channels from the first faulty physical channel at the top of the sorting are sequentially re-established with the order values ​​corresponding to the normal physical channels that are located after the first faulty physical channel in the sorting, thus obtaining the final mapping table. The final mapping table is written into the programmable memory cell of the target chip to complete the mapping of the logical channels and physical channels of the target chip.

2. The mapping method of claim 1, wherein, During the final chip testing phase, when detecting each physical channel, if a faulty physical channel is identified, the logical channels from the first faulty physical channel at the top of the sequence are sequentially re-established with the order values ​​corresponding to the normal physical channels following the first faulty physical channel in the sequence, resulting in a final mapping table including: During the final chip testing phase, the sequence values ​​of the detected faulty physical channels are determined as invalid sequence values, and the sequence values ​​of the detected normal physical channels are determined as valid sequence values. Starting from the invalid sequence value corresponding to the first faulty physical channel at the top of the sort, for each invalid sequence value, the invalid sequence value is swapped with the valid sequence value that follows the invalid sequence value, until there are no valid sequence values ​​after the invalid sequence value, and the swapping ends. In the case of termination of the swap, the faulty physical channel is masked according to the invalid sequence value existing in the initial mapping table to obtain the final mapping table.

3. The mapping method of claim 2, wherein, The step of determining the sequence value of the detected faulty physical channel as an invalid sequence value and the sequence value of the detected normal physical channel as a valid sequence value includes: During the final chip testing phase, each physical channel is tested according to a preset order, where the preset order is the default order of the plurality of logical channels; If the currently detected physical channel is a faulty physical channel, replace the sequence value of the faulty physical channel with an invalid sequence value; If the currently detected physical channel is a normal physical channel, the order value of the normal physical channel is retained as a valid order value; Starting from the invalid sequence value corresponding to the first faulty physical channel in the sorting, for each invalid sequence value, the invalid sequence value is swapped with a valid sequence value that follows the invalid sequence value, until the swapping terminates when there are no valid sequence values ​​following the invalid sequence value. This includes: Starting from the invalid sequence value corresponding to the first faulty physical channel in the sorting, if the currently detected physical channel is a normal physical channel and there is an invalid sequence value before the valid sequence value corresponding to the normal physical channel, the invalid sequence value and the valid sequence value are swapped until all physical channels have been detected, and then the swapping is terminated.

4. The mapping method of claim 2, wherein, The step of swapping the invalid order value with a valid order value that follows the invalid order value includes: The invalid sequence value is multiplied by multiple fault masks in a traversal process until the result of multiplying the invalid sequence value by the fault mask is a valid sequence value following the invalid sequence value. Replace the invalid order value with the valid order value, and replace the valid order value following the invalid order value with the invalid order value.

5. The mapping method of claim 2, wherein, The physical channels that mask faults based on invalid sequence values ​​present in the initial mapping table include: The invalid sequence value is rewritten as a mask code to mask the faulty physical channel.

6. The mapping method according to claim 2, characterized in that, The invalid sequence value is represented by a mask code; The physical channels that mask faults based on invalid sequence values ​​present in the initial mapping table include: The physical channel of the fault is blocked according to the masking code present in the initial mapping table.

7. The mapping method according to claim 1, characterized in that, The programmable memory unit is the efuse memory of the target chip.

8. A method for loading the mapping relationship between logic channels and physical channels of a chip, characterized in that, The mapping relationship loading method includes: Chip initialization involves reading the final mapping table from a one-time programmable memory cell, wherein the final mapping table is obtained using the mapping method for logic channels and physical channels of a chip according to any one of claims 1-7; Write the parsing result of the final mapping table into the channel mapping buffer; When the user specifies the use of a logical channel, the corresponding physical channel is determined based on the parsing result of the final mapping table of the mapping buffer.

9. A mapping device for logic channels and physical channels of a chip, characterized in that, The mapping device includes: The interface unit connects to the target chip; The processor is configured to execute the mapping method for logical and physical channels of a chip according to any one of claims 1 to 7.

10. A machine-readable storage medium storing instructions thereon, characterized in that, When executed by a processor, this instruction causes the processor to be configured to perform the mapping method for logical and physical channels of a chip according to any one of claims 1 to 7.

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