Lvds adaptive frame synchronization system

Abstract

This application discloses an LVDS adaptive frame synchronization system, comprising: a transmitting end: a clock generation module providing multi-rate clocks; a data parallel-to-serial conversion module converting parallel data into a high-speed serial bit stream under clock control; a multi-functional auxiliary channel parallel-to-serial conversion module interleaving and encoding auxiliary control information and synchronization information into a composite bit stream; and an LVDS driver group converting signals into differential signals for transmission. The receiving end: an LVDS receiver group converts differential signals into single-ended signals, including multiple data signals, one auxiliary channel signal, and one half-rate clock signal. A serial-to-parallel conversion and synchronization control module uses a half-rate clock to perform DDR sampling of the data and auxiliary channel signals. Synchronization information is extracted by sampling on the falling edge of the auxiliary channel signal, and auxiliary control information is extracted by sampling on the rising edge. A synchronization detection unit obtains the capture sequence from the synchronization information, and a numerically controlled delay unit calculates the delay correction amount based on the mapping relationship between the capture sequence and the correction signal to delay the data, thereby achieving adaptive frame synchronization.

Description

Technical Field

[0001] This application relates to the field of mixed-signal integrated circuits, specifically to physical layer data recovery technology for high-speed serial communication interfaces. In particular, it relates to an LVDS adaptive frame synchronization system based on a high-speed LVDS interface, employing a multi-functional out-of-band auxiliary channel and DDR sampling technology. Background Technology

[0002] Before the advent of LVDS technology, in the early 1990s, electronic systems primarily relied on TTL / CMOS parallel buses for on-board data transmission. This architecture was effective at lower frequencies, but as system demands for data rates and bandwidth increased dramatically, its fundamental shortcomings in high-speed scenarios became apparent. Early parallel buses suffered from the following main deficiencies: 1. Timing synchronization difficulties: When operating at high frequencies, the slight length difference between the hundreds of parallel data lines connecting chips can cause severe timing skew, preventing data from arriving simultaneously and thus limiting the effective operating frequency of the bus to the order of hundreds of megahertz.

[0003] 2. Deterioration of signal integrity: Dense parallel lines can cause serious electromagnetic interference and crosstalk between signals.

[0004] 3. High physical implementation cost: To drive hundreds of data lines, hundreds of chip I / O ports are required, which puts a huge pressure on chip area; at the same time, the large number of interfaces and wiring also consumes a lot of PCB area and connector space, which not only increases costs but also seriously restricts the miniaturization of the device.

[0005] The aforementioned systemic bottlenecks make it difficult for parallel buses to meet the demands of high-speed data transmission, and the industry urgently needs a new physical layer interface technology.

[0006] In 1994, National Semiconductor introduced LVDS technology, whose core design concept was to solve the aforementioned problems using "differential signaling" and "low voltage swing." LVDS uses a constant current source of approximately 3.5mA to drive a pair of differential lines, generating a tiny voltage swing of only about 350mV across the 100Ω matching resistor at the receiving end. This method inherently possesses extremely strong common-mode noise immunity, thus achieving low power consumption, low noise, and low electromagnetic interference. In addition, its current-mode drive is simple and reliable, with good signal quality, supporting transmission rates of hundreds of Mbps and even Gbps. Subsequently, core standards such as ANSI / TIA / EIA-644 (November 1995) and IEEE 1596.3 (March 1996) were established, providing specifications for the electrical characteristics and protocol layer coding of LVDS, laying the foundation for its widespread application.

[0007] From the mid-1990s to the 2010s, after its standard was established, LVDS quickly gained dominance in the field of on-screen interfaces for notebook computers and LCD monitors due to its superior performance. This application required the reliable transmission of high-speed image data generated by the motherboard to the screen. LVDS's high speed, low noise, and low power consumption, along with its serializer / deserializer architecture, significantly reduced the number of connecting cables, perfectly meeting the needs for thinner and lighter devices and interference resistance, making it the de facto standard interface in the LCD panel industry for over fifteen years. During this period, its physical layer performance continued to improve with technological advancements, with speeds moving from the standard-recommended 655Mbps to higher theoretical values. Engineers also recognized LVDS as an excellent universal high-speed point-to-point serial transmission solution, and its applications rapidly expanded to fields requiring high-speed and reliable data transmission, such as industrial cameras, automotive electronics, medical equipment, and communication base stations.

[0008] Since the 2010s, technology has continued to evolve. Faced with the exponential bandwidth growth brought by 4K / 8K video, LVDS has gradually been replaced by interfaces such as eDP, which have higher bandwidth and more advanced protocols, in the consumer display field. However, in industrial and professional fields with extremely high requirements for cost, reliability, and anti-interference, LVDS still maintains strong vitality due to its maturity, stability, and ease of implementation. As the LVDS interface evolves to higher speeds of Gbps, the challenges faced by the system have shifted from "whether the physical layer can transmit" to "whether the link layer can reliably synchronize and recover." Specifically: first, there is the clock recovery problem. At GHz speeds, dedicated clock channels are susceptible to interference and have stringent wiring requirements; second, there is the data alignment (i.e., frame synchronization) problem, which is how to accurately lock the starting boundary of bytes or data frames when performing serial-to-parallel conversion at the receiving end to avoid data misalignment caused by clock skew or jitter accumulation.

[0009] In existing technologies, solutions for achieving data synchronization at the receiving end can be mainly divided into two categories: The first type is a synchronization scheme based on data content recognition. This type of scheme does not occupy additional physical channels; instead, it periodically inserts specific training sequences into the effective data stream or relies on predetermined coding rules. The receiving end needs to continuously search and match this specific code pattern in the serial bit stream to determine the boundaries of the data frames. Its disadvantages are: complex synchronization recognition circuitry; in high-speed or high-error-rate environments, the training sequence itself is easily distorted by interference, leading to synchronization loss and system lockout; and the synchronization establishment and recovery process is time-consuming.

[0010] The second type is the protocol layer synchronization scheme based on an independent control channel, represented by the mechanism defined for the Scalable Consistency Interface in the IEEE 1596.3 standard. This scheme uses a dedicated LVDS physical channel to transmit a "flag signal," whose level transitions are used to identify the start and end boundaries of data packets at the data link layer. Although it avoids data content interference with synchronization through a dedicated channel, its design and implementation serve the frame encapsulation and parsing of upper-layer protocols, rather than the lower-level bit synchronization and word alignment. The receiving end needs to use a complex protocol state machine to parse the flag signal, resulting in deep coupling between the synchronization logic and the specific protocol, which is still redundant in pure data stream transmission scenarios that pursue extreme simplicity, high speed, and low latency.

[0011] In summary, existing data content-based synchronization schemes have limited reliability, while independent channel-based schemes (such as IEEE 1596.3) focus on the protocol layer and fail to directly address the fundamental bit synchronization and word alignment challenges during high-speed serial-to-parallel conversion. Therefore, a more direct, reliable, and independent physical layer synchronization scheme is urgently needed. Summary of the Invention

[0012] In view of this, embodiments of this application provide a high-speed serial data bit synchronization and frame alignment scheme based on an innovative system architecture. This scheme does not rely on complex protocols and aims to achieve higher reliability with simplified circuitry.

[0013] This application discloses an LVDS adaptive frame synchronization system, comprising: a transmitter for transmitting data; and a receiver for receiving and recovering data from the transmitter. The transmitter includes: a clock generation module for generating multiple clock signals at different rates; a data parallel-to-serial conversion module connected to the clock generation module, including multiple data channels, for converting each input multi-bit parallel data stream into a high-speed serial bitstream under the control of the clock signals; a multi-function auxiliary channel parallel-to-serial conversion module connected to the clock generation module, including an auxiliary channel, for interleaving and encoding input auxiliary control information and synchronization information to generate a composite bitstream; and an LVDS driver group connected to the outputs of the clock generation module, the data parallel-to-serial conversion module, and the multi-function auxiliary channel parallel-to-serial conversion module, for converting the output data into differential signals for transmission. The receiving end includes: an LVDS receiver group for receiving differential signals and converting them into single-ended signals, the single-ended signals including multiple data signals, one auxiliary channel signal, and one half-rate clock signal; a serial-to-parallel conversion and synchronization control module connected to the LVDS receiver group, including: a DDR sampling unit, which uses a half-rate clock signal to sample the data signals and auxiliary channel signals respectively; for the auxiliary channel signal, the falling edge of the clock is used to sample the odd-numbered logic bits to obtain synchronization information, and the rising edge of the clock is used to sample the even-numbered logic bits to obtain auxiliary control information; a synchronization detection unit connected to the DDR sampling unit, which is used to detect the synchronization information extracted by the falling edge to obtain the capture sequence; and a digitally controlled delay unit connected to the synchronization detection unit, which is used to obtain the delay correction amount based on the capture sequence and the mapping relationship between the capture sequence and the correction signal, and apply a variable digital delay to the data signal.

[0014] Furthermore, the bit stream transmitted through the auxiliary channel has synchronization information located in the odd-numbered logical bits and auxiliary control information located in the even-numbered logical bits, employing odd-even bit interleaving encoding.

[0015] Furthermore, the synchronization information is a periodically inserted 4-bit predetermined synchronization sequence.

[0016] Furthermore, the synchronization detection unit includes a serial-to-parallel conversion register; the numerically controlled delay unit is specifically used to generate two-bit delay control signals (S1, S0) based on the shift relationship between the capture sequence (Q3, Q2, Q1, Q0) output by the serial-to-parallel conversion register and the ideal synchronization sequence, thereby dynamically selecting the delay correction amount.

[0017] Furthermore, when the transmitting end selects 0x1x1x0x as the synchronization sequence in the auxiliary control channel, the delay control signal (S1, S0) is generated through the following simplified Boolean logic: S0 = Q0 ⊙ Q1; S1 = Q0; where ⊙ represents the XOR operation.

[0018] Furthermore, the adjustment step for the delay is equal to one half-rate clock cycle.

[0019] Compared with the prior art, the embodiments of this application have the following significant advantages: 1) Synchronization reliability has been fundamentally improved: This invention independently transmits synchronization information through a dedicated out-of-band auxiliary channel at the physical layer, completely eliminating dependence on data stream content or specific encoding rules. The synchronization signal is isolated from the valid data, free from interference by its content, and there is no need to worry about the training sequence being distorted due to channel errors. Thus, it fundamentally solves the reliability bottleneck of traditional "in-band" synchronization schemes, which are prone to lock-out in high-speed, high-noise environments.

[0020] 2) Synchronization speed and determinism are significantly enhanced: Based on an independent synchronization channel, the receiver can directly and without searching calculate the phase offset (S1 S0) by detecting a predefined synchronization sequence, and complete the alignment within a few clock cycles with the help of a numerically controlled delay unit. This achieves near "synchronization upon first acquisition" or fast resynchronization, avoiding the unpredictable synchronization setup time introduced by traditional search-based state machines, and providing deterministic low-latency performance for the system.

[0021] 3) The circuit implementation is greatly simplified, and power consumption and area are optimized: The advantages of this invention are particularly prominent at the circuit level: Sampling-separation: By utilizing the rising and falling edges of the DDR clock, the synchronization and control bits are physically separated, eliminating the need for additional digital logic.

[0022] The algorithm is extremely simplified: the core logic for synchronous detection and correction generation (S0 = Q0 ⊙ Q1, S1 = Q0) requires only a minimum number of gate circuits (like an OR gate) to implement, resulting in extremely low computational latency.

[0023] Fully digital implementation: The adaptive synchronization mechanism is fully based on numerically controlled delay units and digital logic, eliminating the need for analog phase-locked loops or delay phase-locked loops. This avoids the complex design, calibration, and inherent high power consumption issues of analog circuits, making it easy to integrate and highly stable.

[0024] 4) The system architecture has a high degree of integration, resulting in rich functionality: This invention creatively integrates physical layer synchronization and lightweight logic control functions into a single, newly added physical channel through "odd-even bit interleaving" encoding. This not only solves the core bit synchronization problem but also provides additional control capabilities such as frame enable, achieving system-level optimization that "trades for the dual benefits of synchronization and control with minimal physical overhead," significantly improving the efficiency and flexibility of the overall architecture.

[0025] 5) Strong adaptability and excellent system robustness: This solution achieves continuous adaptive alignment by continuously monitoring the synchronization sequence and using digital feedforward control to dynamically compensate for transmission delay variations caused by temperature, voltage changes, or clock drift. Simultaneously, the unique "path isolation design" ensures a fixed delay for the synchronization reference path, thereby guaranteeing the absolute stability of the adaptive loop, avoiding oscillation risks, and resulting in extremely high robustness for long-term system operation.

[0026] 6) Widely applicable and possesses protocol transparency: This solution operates at the physical layer and does not rely on any higher-level communication protocols. This protocol transparency enables it to seamlessly adapt to various high-speed streaming data transmission scenarios using LVDS interfaces, such as high-speed industrial cameras, medical imaging, testing instruments, and radar data backhaul, demonstrating broad application prospects. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0028] Figure 1 This is an architecture diagram of the LVDS adaptive frame synchronization system provided in the embodiments of this application.

[0029] Figure 2 A clock phase relationship diagram is generated for the transmitting end provided in the embodiments of this application.

[0030] Figure 3 A phase relationship diagram of the single-ended signal at the receiving end provided in an embodiment of this application. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] With the widespread application of LVDS interfaces in high-speed data transmission systems and their continuously increasing speeds, the timing challenges faced by the receiving end in accurately recovering parallel data are becoming increasingly severe. Existing frame synchronization (i.e., word alignment) solutions mainly suffer from the following two limitations: (1) In-band synchronization schemes based on data content recognition (such as embedded training sequences or relying on specific coding rules): their synchronization mechanism is deeply coupled with the effective data stream. In high-speed and high-noise environments, the training sequence is easily interfered with and distorted, leading to synchronization loss; and the receiver needs to continuously search and match the code pattern, resulting in uncontrollable synchronization establishment time, complex circuit implementation, and fundamental challenges to system reliability.

[0034] (2) Protocol layer out-of-band synchronization scheme based on independent channels (such as the Flag signal defined in the IEEE 1596.3 standard): Although this scheme avoids data interference through an independent physical channel, it is essentially a packet / frame boundary signal at the protocol layer, used to identify the logical start and end of data packets. The receiving end needs to rely on a complex protocol state machine for parsing, and its design goal is to serve the upper-layer protocol encapsulation rather than the recovery of the underlying physical data. Therefore, this scheme cannot directly and efficiently solve the most fundamental physical layer core problem of bit synchronization and byte / word boundary alignment during serial-to-parallel conversion, and its application is limited in streaming data transmission scenarios that pursue extreme simplicity, low latency, and protocol transparency.

[0035] Therefore, the technical problem to be solved by this invention is to provide a frame synchronization scheme for high-speed LVDS interfaces, which can eliminate the dependence on data stream content or complex protocols, and achieve fast, reliable and circuit-simplified bit synchronization and word alignment through innovative physical layer design, thereby systematically overcoming the shortcomings of existing technologies in terms of reliability, synchronization speed and implementation complexity, and meeting the data transmission requirements of higher speed and higher reliability.

[0036] To address the aforementioned technical problems, this invention provides an LVDS adaptive data frame synchronization system based on a multi-functional out-of-band auxiliary channel and DDR sampling. The core architectural innovation of this invention lies in adding a completely independent multi-functional out-of-band auxiliary channel to the traditional multi-channel LVDS data link. This channel aims to fundamentally solve the physical layer data recovery problem; its design achieves unified synchronization and control on a single channel through deep integration of signal coding and physical sampling mechanisms.

[0037] 1. System Overall Architecture: The technical solution of the present invention is described in detail below: Data channel group: Consists of several LVDS differential pairs, used to transmit high-speed serialized payload data.

[0038] Clock channel: A pair of independent LVDS differential pairs for transmitting half-rate source synchronous clocks.

[0039] Multifunctional out-of-band auxiliary channel: A pair of independent LVDS differential pairs, which is the core of this invention. This channel transmits a composite coded signal, and synchronization and control functions are implemented on the bitstream of this channel.

[0040] 2. Transmitter encoding and signal generation: At the transmitting end, the auxiliary channel signal generation is based on a unique encoding strategy and makes full use of the system's existing clock architecture: Functional coding: The physical layer synchronization information and auxiliary control information (such as frame enable) to be transmitted are preprocessed. In a key embodiment of the invention, the synchronization information is mapped to a logically odd-numbered bit sequence, while the auxiliary control information is mapped to an even-numbered bit sequence, thereby forming interleaving at the bit level.

[0041] Signal Generation: This interleaved bitstream is generated by a dedicated parallel-to-serial converter and transmitted via an LVDS driver. The clock that generates this bitstream is sourced from the serialization clock of the data channel, ensuring timing consistency.

[0042] 3. Physical layer separation and recovery based on DDR sampling at the receiving end: The receiver design is deeply coupled with the physical characteristics of DDR sampling to achieve efficient decoupling: Clock and data recovery: The receiver uses the half-rate clock recovered from the clock channel to perform DDR sampling on the data channel and restore the serial bit stream.

[0043] Intelligent Sampling and Separation of Auxiliary Channels: For multi-functional auxiliary channels, the receiver uses the same recovered half-rate clock for DDR sampling. This is key to achieving functional separation: under the timing defined in this invention, the falling edge of the clock is used to sample the odd-numbered logic bits, directly obtaining synchronization information; the rising edge of the clock is used to sample the even-numbered logic bits, obtaining auxiliary control information. This process is directly completed by the physical characteristics of the clock edge, without the need for additional digital logic for bit separation.

[0044] Adaptive synchronization implementation: The synchronization bit stream extracted by the falling edge (e.g., consecutive bits... 01100110...) is fed into a 4-bit serial-to-parallel converter register. A synchronization detection circuit continuously monitors the register's outputs Q3Q2 Q1 Q0. At the transmitting end, a predetermined 4-bit synchronization sequence (e.g., 0110) is periodically inserted into the odd-numbered bits of the synchronization bit stream. Under ideal alignment, the receiving end register should capture the complete 0110 sequence.

[0045] However, due to initial phase uncertainty or transmission delay variations, the captured sequence may be a cyclic shift of 0110 (e.g., 1100, 1001, 0011). Each shift state uniquely corresponds to a fixed amount of data path delay error.

[0046] This invention achieves rapid adaptive correction through the following steps: Correction amount generation: Define 2-bit control signals S1 and S0 to characterize the required delay correction amount. The mapping relationship between the capture sequence and the correction signal is designed as follows:

[0047] The logic of this mapping can be simplified to an optimal implementation using Boolean algebra: S0 = Q0 ⊙ Q1 (Q0 OR Q1) S1 = Q0 (S1 is directly equal to Q0) Based on this result, the values ​​of S1 and S0 only need to be controlled by Q1 and Q0, which greatly simplifies the synchronization check circuit.

[0048] Data path delay adjustment (core innovation): The main data channels (D1_r, D0_r) are fed into a numerically controlled delay unit controlled by S1 and S0, consisting of four D flip-flops and a 4-to-1 multiplexer. This unit provides multiple fixed delay levels (e.g., 00, 01, 10, and 11 correspond to 1 to 4 unit delays respectively), where one unit delay equals one half-rate clock cycle. S1 and S0 dynamically select the delay value based on the synchronization detection result, thereby precisely adjusting the overall group delay of the data path and aligning the effective window of the data with the subsequent sampling clock.

[0049] Key Cooperative Design: The delayed serial data is directly input into a 4:1 serial-to-parallel converter module consisting of a chain of D flip-flops. This module uses eight D flip-flops, and its parallel output clock is a 4 / 4 division of a half-rate clock. This design produces a crucial synergistic effect: the digital delay adjustment performed by the numerically controlled delay unit, combined with the sampling and storage of data by the D flip-flop chain in the serial-to-parallel converter, effectively achieves the cyclic shift alignment function of the data. Specifically, adjusting the delay changes the initial phase of the data flowing into the flip-flop chain, and the flip-flop chain samples in an orderly manner under the control of the 4 / 4 clock, ultimately automatically presenting correctly aligned parallel data words at the output. This method transforms the complex dynamic data rearrangement logic into a simple implementation combining static delay control and inherent sampling timing.

[0050] Path isolation and differentiated latency design (to ensure stability and correct functionality): To avoid deadlock or oscillation in the adaptive adjustment loop, this invention implements a differentiated delay processing strategy for the two functional signals of the multi-functional out-of-band auxiliary channel: 1) Synchronization Path (Fixed Delay Reference): The synchronization information path used to generate the S1 and S0 control signals (i.e., the odd-numbered logic bits sampled by the falling edge of the clock) does not pass through the main CNC delay unit. This path uses a fixed reference delay (e.g., 1 unit delay), thus providing a stable and unchanging phase reference for the entire adaptive control loop. This is a prerequisite for the control loop to converge and not oscillate.

[0051] 2) Control Data Path (Coordinated Delay Adjustment): The control data path (i.e., the even-numbered logic bits sampled by the rising edge of the clock) used to carry auxiliary control information such as frame enable needs to undergo the exact same numerical control delay adjustment as the main data path. This is to ensure that the control information (such as the "frame valid" signal) is strictly aligned in timing with the delayed payload data. Otherwise, the control signal will point to the wrong data frame.

[0052] In summary, this invention physically adds an "out-of-band auxiliary channel," but logically and in terms of circuit processing, it is clearly separated into two paths: one is a "synchronization reference path" with a fixed delay, and the other is a "control data path" with a delay coordinated with the main data channel. The former ensures the stability of the adaptive loop, while the latter guarantees the correctness of the control function.

[0053] The transmitter 100 includes: a parallel-to-serial converter group 110, a parallel-to-serial converter 120, a clock generator 130, and an LVDS driver group 140. The parallel-to-serial converter group 110 has N identical conversion channels. Each channel first samples the 8-bit parallel input data using the CK[3] clock and 8 D flip-flops. The sampling result is selected by an 8-to-1 high-speed selector MUX (MUX1, MUX2, and MUXN). The selector selection port is connected to CK[3:1]. The output of each high-speed selector is then sampled by D flip-flops through CK[0]. Each channel realizes the conversion of 8-bit parallel input data into 1-bit high-speed serial bit stream. The parallel-to-serial converter group 110 has N channels, which can realize the conversion of 8×N parallel data into N-bit serial data. The parallel-to-serial converter 120 first samples the 4-bit control data CTL[3:0] (such as frame enable, type identifier) ​​using the CK[3] clock and four D flip-flops. The sampling output is CHC[3:0]. These are connected to the even bits of the input port of the 8-to-1 high-speed selector MUXC, and the odd bits are encoded with the synchronization code. That is, CHC[3] is connected to MUXC input port 6, CHC[2] is connected to MUXC input port 4, CHC[1] is connected to MUXC input port 2, CHC[0] is connected to MUXC input port 0, MUXC input ports 1 and 7 are directly connected to low level, and MUXC input ports 3 and 5 are directly connected to high level. That is, the odd bits are encoded with the synchronization control code 0110. The clock generator 130 inputs the reference clock CLKIN and generates four synchronization clocks CK[3:0] with different rates through the PLL. The clock frequency ratios of CK[3], CK[2], CK[1], and CK[0] are 1:2:4:8. The duty cycles of the four synchronous clocks with different rates are all around 50%. In order to ensure that all flip-flops meet the setup and hold time requirements to the greatest extent, the clock phase relationship is as follows: Figure 2 As shown. Under normal circumstances, when the PLL is locked, CLKIN and CK[3] maintain a fixed phase to meet the sampling time requirements of all input data of parallel-to-serial converter group 110 and parallel-to-serial converter 120, which depends on the phase relationship between input signals D1[7:0]~DN[7:0] / CTL[3:0] and CLKIN. CK[0] performs a stepping process on CK[1]. The first stage uses the rising edge of CK[0] to sample CK[1], and the second stage uses the inverted phase of CK[0], that is, the falling edge of CK[0] to sample the inverted phase of the output sampled by the first stage. The output ports of parallel-to-serial converter group 110, parallel-to-serial converter 120 and clock generator 130 are respectively connected to LVDS driver group 140. LVDS driver group 140 uses N+2 identical LVDS driver units to convert single-ended signals into differential signals.

[0054] The selection logic of the MUX (including MUX1 to MUXN and MUXC) is as follows: when the input selection port CK[3:1] is equal to 0, the logic value of the selector output port is equal to the logic value of the 0th path; when the input selection port CK[3:1] is equal to 1, the logic value of the selector output port is equal to the logic value of the 1st path, and so on.

[0055] The receiver 200 includes an LVDS receiver group 210, a serial-to-parallel converter group 220, and a synchronization and control unit 230. The LVDS receiver group 210 receives N+2 pairs of differential signals from the transmitter 100 and converts them into N+2 single-ended signals. The first N signals are data payload signals, the N+1th signal is an out-of-band auxiliary channel signal, and the N+2nd signal is a half-rate clock signal CLKD1. The serial-to-parallel converter group 220 consists of N identical serial-to-parallel converter circuits. Each channel first performs DDR sampling on the input single-ended signal, then samples it using the rising and falling edges of the half-rate clock signal CLKD1. The two sampled outputs are then synchronously sampled again using the falling edge of CLKD1 and output to two identical shift register groups. The shift register group consists of a numerically controlled delay unit and a serial-to-parallel converter (S2P). The S2P consists of eight D flip-flops; the first four perform serial shifting, and the last four perform parallel output. It takes one serial data input (DI) and outputs four parallel data inputs (Q0, Q1, Q2, Q3). It requires one serial shift clock (CI) and one parallel output clock (CO). The serial shift clock (CI) is connected to CLKD1, and the parallel output clock (CO) is connected to CLKD4. CLKD4 is obtained by dividing CLKD1 by four in the synchronization and control unit 230. Synchronization and control 230 uses the same DDR sampling module, numerically controlled delay unit, and serial-to-parallel converter S2P as serial-to-parallel converter group 220. The out-of-band auxiliary channel signal is divided into two paths after DDR sampling. One path outputs control data (such as frame enable, type identifier) ​​QC[3:0] through the numerically controlled delay unit and serial-to-parallel converter S2P. The other path uses 5 D flip-flops for serial-to-parallel conversion. The first three D flip-flops are used for serial shifting, and the last two D flip-flops are used for parallel output. The serial shift clock is connected to CLKD1, and the parallel output clock is connected to CLKD4. The circuit here is the result of Boolean algebra simplification of the mapping relationship between the capture sequence and the correction signal to achieve the optimal implementation. S[0] = Q0 ⊙ Q1 (Q0 OR Q1) S[1] = Q0 (S1 is directly equal to Q0) Synchronization method: via Figure 1 After the logic circuit shown is implemented, the timing waveform of its receiving end after differential-to-single-ended signal conversion is as follows: Figure 3As shown. The CLKD1 clock edge is located at the center of the single-ended signal. Parity data separation is performed through DDR sampling. In synchronization and control 230, the odd data is a cyclic sequence of ... 01100110... After serial-to-parallel conversion, the cyclic shift data (0110, 1100, 1001, 0011) of sequence 0110 can be captured. This sequence is denoted as Q3Q2Q1Q0, thus the alignment strategy can be obtained:

[0056] Boolean algebra simplification to the optimal implementation: S[0] = Q0 ⊙ Q1 (Q0 OR Q1) S[1] = Q0 (S1 is directly equal to Q0) Therefore, under this encoding, only sequence Q1Q0 needs to be captured, and Q3Q2 does not need to be considered. Therefore, the serial-to-parallel conversion only needs to convert Q1Q0. S[1:0] adjusts all CNC delay modules to achieve synchronization.

[0057] Optional variations: Those skilled in the art can make various modifications without departing from the core idea of ​​this invention. For example, the synchronization code can be other code types; the serial-to-parallel / parallel-to-serial conversion implementation can be multi-level, and the serial-to-parallel conversion bit ratio can be 16:1; the number of numerically controlled delay units can be variable, and to meet timing requirements, inverters or buffers can be inserted in the timing path to adjust the delay without changing the logic function; the clock generation can use DLL or other frequency division / multiplication methods.

[0058] In summary, this invention directly addresses the core of physical layer data recovery, aiming to solve the challenges of bit synchronization and word alignment through system-level innovation. To this end, this invention creatively introduces a dedicated out-of-band auxiliary channel for the physical layer and deeply utilizes the physical characteristics of DDR sampling to construct synchronization and control mechanisms. Specifically: at the transmitting end, the auxiliary channel signal is pre-encoded so that synchronization information and control information are located at logically even and odd bits, respectively; at the receiving end, DDR sampling is performed using a half-rate clock from the same source as the data channel, with its rising and falling edges naturally corresponding to the even and odd bits of the corresponding channel signal, respectively. In this way, the receiving circuit can achieve physical separation of synchronization bits and control bits without complex logic. According to the timing defined in this invention, bits sampled by the falling edge of the clock are directly used to generate word alignment signals, achieving continuous and adaptive bit synchronization; while bits sampled by the rising edge are parsed as auxiliary control information. By deeply integrating channel functions, encoding design, and physical sampling mechanisms, this invention simultaneously achieves highly reliable hardware-level synchronization and flexible logic control on a single physical channel, providing a highly simplified and high-performance low-level data recovery solution.

[0059] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A LVDS adaptive frame synchronization system, characterized in that, include: The sending end is used to send data; The receiving end is used to receive and recover data from the sending end; The sending end includes: The clock generation module is used to generate multiple clock signals at different rates; The data parallel-to-serial conversion module, connected to the clock generation module, includes multiple data channels and is used to convert each input multi-bit parallel data into a high-speed serial bit stream under the control of the clock signal. The multi-functional auxiliary channel parallel-to-serial conversion module is connected to the clock generation module. It includes an auxiliary channel for interleaving and encoding the input auxiliary control information and synchronization information to generate a composite bit stream. The LVDS driver group is connected to the outputs of the clock generation module, the data parallel-to-serial conversion module, and the multi-function auxiliary channel parallel-to-serial conversion module, respectively, and is used to convert the output data into differential signals for transmission; The receiving end includes: An LVDS receiver group is used to receive differential signals and convert them into single-ended signals. The single-ended signals include multiple data signals, one auxiliary channel signal, and one half-rate clock signal. The serial-to-parallel conversion and synchronization control module, connected to the LVDS receiver group, includes: The DDR sampling unit uses a half-rate clock signal to sample the data signal and the auxiliary channel signal respectively. For the auxiliary channel signal, the falling edge of the clock is used to sample the odd-numbered logic bits to obtain synchronization information, and the rising edge of the clock is used to sample the even-numbered logic bits to obtain auxiliary control information. The synchronization detection unit, connected to the DDR sampling unit, is used to detect the synchronization information extracted on the falling edge to obtain the capture sequence; The numerically controlled delay unit, connected to the synchronization detection unit, is used to obtain the delay correction amount based on the capture sequence and the mapping relationship between the capture sequence and the correction signal, and to apply a variable digital delay to the data signal.

2. The LVDS adaptive frame synchronization system of claim 1, wherein, The bit stream transmitted through the auxiliary channel has synchronization information located in the odd-numbered logical bits and auxiliary control information located in the even-numbered logical bits, employing odd-even bit interleaving encoding.

3. The LVDS adaptive frame synchronization system according to claim 2, characterized in that, The synchronization information is a pre-defined 4-bit synchronization sequence that is periodically inserted.

4. The LVDS adaptive frame synchronization system according to claim 1, characterized in that, The synchronization detection unit includes a serial-to-parallel conversion register; The numerically controlled delay unit is specifically used to generate two-bit delay control signals (S1, S0) based on the shift relationship between the capture sequence (Q3, Q2, Q1, Q0) output by the serial-to-parallel conversion register and the ideal synchronization sequence, and then dynamically select the delay correction amount.

5. The LVDS adaptive frame synchronization system according to claim 4, characterized in that, When the transmitting end selects 0x1x1x0x as the synchronization sequence in the auxiliary control channel, the delay control signal (S1, S0) is generated through the following simplified Boolean logic: S0 = Q0 ⊙ Q1; S1 = Q0; Here, ⊙ represents the XOR operation.

6. The LVDS adaptive frame synchronization system according to claim 1, characterized in that, The adjustment step for the delay is equal to one half-rate clock cycle.

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