A power design drawing automatic generation method based on a knowledge graph

Abstract

This invention discloses an automatic generation method for power design drawings based on knowledge graphs, comprising: Step 1: Constructing a power design knowledge graph; Step 2: Obtaining power design input parameters and generating drawing assembly task seeds; Step 3: Extracting conditional subgraphs and performing breadth-first traversal to generate node insertion sequences and port connection sequences, inputting an improved GraphRNN model with a port-driven mapping mechanism to generate an atomic assembly chain graph; Step 4: Constructing a drawing skeleton mesh and forming a slot mapping structure; Step 5: Constructing a slot conflict matrix and performing slot adjustment to obtain the target assembly sequence; Step 6: Generating a primitive connection script and performing primitive connection to obtain the power design drawings; Step 7: Performing verification and backtracking updates to output the final power design drawings. This invention achieves automatic generation and structural consistency optimization of power design drawings.

Description

Technical Field

[0001] This invention relates to the fields of deep learning and knowledge graph technology, and in particular to a method for automatically generating power design drawings based on knowledge graphs. Background Technology

[0002] With the continuous expansion of power system scale and the increasing complexity of distribution network structure, power design drawings play a fundamental role in engineering design, construction and operation and maintenance. For the generation of power design drawings, the existing technology mainly relies on manual drawing or auxiliary design software based on rule templates to construct drawings. However, the following problems are common in actual engineering applications.

[0003] Traditional methods for generating power design drawings rely heavily on manual experience. Designers must gradually complete the layout and connection of elements based on equipment parameters, circuit relationships, and specification requirements. This process is dependent on professional experience and inefficient, making it difficult to meet the needs of large-scale and complex power grid designs. While some automated design tools introduce rule templates or parametric configuration methods, their underlying implementation often uses fixed rule matching or simple topology splicing strategies, which are insufficient to effectively express the multi-level relationships between equipment, ports, and circuits. This results in deficiencies in the structural consistency and topological rationality of the generated results. Existing graph model-based methods mostly only model nodes or connections independently, lacking a refined description of port-level connections, and cannot guarantee the consistency between the generated graph structure and the actual electrical connection rules. Furthermore, existing technologies typically use simple grids or fixed position allocation methods during the drawing layout process, lacking a spatial mapping mechanism for power supply paths and branch relationships. This easily leads to problems such as element overlap and connection intersections, and lacks effective conflict detection and adaptive adjustment capabilities. In terms of result verification, it relies heavily on manual review or single rule verification, lacking a local backtracking and dynamic correction mechanism based on structural information, making it difficult to achieve efficient automatic generation and consistency assurance of complex power design drawings.

[0004] Therefore, how to provide a method for automatically generating power design drawings based on knowledge graphs is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] One objective of this invention is to propose an automatic generation method for power design drawings based on knowledge graphs. This invention constructs a multi-layer power design knowledge graph and introduces an improved GraphRNN model. It utilizes a port-driven structure mapping mechanism to achieve the collaborative generation of assembly atomic nodes and port connection relationships. It combines the drawing skeleton grid and slot conflict matrix to complete primitive layout and conflict adjustment, and realizes standardized drawing generation through primitive connection scripts. Furthermore, it introduces a verification and local backtracking mechanism based on standard rules to achieve automatic generation and structural consistency optimization of power design drawings.

[0006] An automatic generation method for power design drawings based on knowledge graphs according to an embodiment of the present invention includes the following steps:

[0007] Step 1: Construct a power design knowledge graph consisting of the equipment layer, port layer, loop layer, and specification layer;

[0008] Step 2: Obtain power design input parameters and generate drawing assembly task seeds in the power design knowledge graph;

[0009] Step 3: Extract the condition subgraph from the assembly task seed according to the drawing, perform breadth-first traversal according to the power supply path order, generate the node insertion sequence and port connection sequence, and input them into the improved GraphRNN model. The improved GraphRNN model introduces a port-driven knowledge graph structure mapping mechanism to generate assembly atomic nodes and port connection relationships, forming an atomic assembly chain graph.

[0010] Step 4: Construct the drawing skeleton mesh, and map the assembly atomic nodes in the atomic assembly chain diagram to the corresponding slots in the drawing skeleton mesh according to the power supply path sequence to form a slot mapping structure;

[0011] Step 5: Construct a slot conflict matrix based on the slot mapping structure, perform slot adjustment on the assembly atomic nodes with conflicts, and obtain the target assembly sequence;

[0012] Step 6: Generate a graphic element connection script based on the target assembly sequence and execute the graphic element connection to obtain the power design drawings;

[0013] Step 7: Perform verification based on the power design drawings, and re-execute steps 3 to 6 for the assembly atomic nodes according to the verification results, and output the final power design drawings.

[0014] Optionally, step one specifically includes:

[0015] Establish an equipment layer, set up power equipment nodes, transformer nodes, busbar nodes, switch equipment nodes, cable nodes, load equipment nodes and protection equipment nodes, and configure equipment number, equipment type, voltage level and rated capacity attributes for each equipment node;

[0016] Establish a port layer, set up input port nodes, output port nodes, protection port nodes and interlocking port nodes, establish a subordinate relationship between each port node and the corresponding device node, and configure port number, port category and port direction attributes;

[0017] Establish a loop layer, set up incoming loop nodes, outgoing loop nodes, tie loop nodes and protection loop nodes, and configure loop number, loop type and voltage level attributes for each loop node;

[0018] Establish a specification layer, set voltage level matching nodes, capacity matching nodes, protection coordination nodes, and element layout nodes, and configure rule number, rule category, and applicable object attribute for each specification node;

[0019] Establish subordinate edges between the device layer and the port layer, access edges between the device layer and the loop layer, connection edges between the port layer and the loop layer, and rule mapping edges between the specification layer and the device layer, port layer, and loop layer, and configure relationship type identifiers for each type of edge;

[0020] Nodes and edges are uniformly encoded. Node codes are formed by sequentially arranging node category codes and attribute field codes, with the attribute field codes arranged in the order of the fields in the node attribute set. Edge codes are formed by sequentially arranging edge category codes and relation attribute codes, with the relation attribute codes arranged in the order of the fields in the edge relation attribute set.

[0021] A knowledge graph for power design is constructed based on node encoding and edge encoding, and an index table based on node number is established.

[0022] Optionally, step two specifically involves:

[0023] Obtain power design input parameters, which include voltage level parameters, load capacity parameters, load category parameters, number of circuit parameters, and power supply mode parameters, and identify the power design input parameters by parameter number;

[0024] The power design input parameters are mapped to a set of parameter nodes, each parameter node in the set of parameter nodes corresponds to an input parameter category, and the parameter nodes are grouped according to the parameter category;

[0025] Based on the parameter node set, equipment nodes, port nodes, and loop nodes that match the parameter nodes are retrieved in the power design knowledge graph. The matching is performed by comparing node attributes item by item. The attribute comparison results are counted according to the number of matching items, and nodes with a number of matching items not less than the average value of the set of matching item numbers are selected as candidate node sets.

[0026] An initial connection set is constructed based on the access edge relationship between the device nodes and loop nodes in the candidate node set. The initial connection set consists of the device node number and the loop node number.

[0027] The device nodes in the initial connection set are sorted hierarchically according to voltage level parameters, and the device nodes of the same voltage level are sorted numerically according to load capacity parameters. The priority sequence of the device nodes is determined based on the sorting results.

[0028] Based on the priority sequence of the device nodes, a set of port nodes is obtained according to the subordinate relationship between the device nodes and the port nodes, and the port nodes are divided according to the port category to form a port group set;

[0029] Based on the set of device nodes, the set of port groups, and the set of loop nodes, a set of drawing assembly task seeds is constructed. The drawing assembly task seeds are formed by combining the device node number, the port node number, and the loop node number, and are arranged according to the priority sequence of the device nodes.

[0030] Optionally, step three specifically includes:

[0031] An improved GraphRNN model is established, which includes an assembly atom generation channel, a port connection generation channel, a structural state unit, a port state unit, and a mapping state unit. The structural state unit records the connection relationship between assembly atom nodes, the port state unit records the port occupancy status and connection order, and the mapping state unit records the correspondence between knowledge graph nodes and assembly atom nodes.

[0032] Based on the drawings, the assembly task seed extracts the conditional subgraph, and the breadth-first traversal is performed according to the power supply path order, starting from the main power node, to form the node access sequence and edge access sequence.

[0033] Construct a node insertion sequence and a port connection sequence based on the node access sequence and the edge access sequence;

[0034] A port-driven knowledge graph structure mapping mechanism is constructed. The port-driven knowledge graph structure mapping mechanism takes the port node as the starting point and expands the path along the subordinate edge between the port node and the device node, the connection edge between the port node and the loop node, and the rule mapping edge between the canonical node and the port node to form a set of mapping chains containing the port node number, device node number, loop node number and canonical node number. The set of mapping chains is written into the mapping state unit in the order of path expansion.

[0035] The node insertion sequence is input into the assembly atom generation channel. Based on the mapping chain set in the mapping state unit, the device category identifier and loop category identifier in the node insertion sequence are matched and filtered. Assembly atom nodes are generated according to the matching results. At the same time, the connection relationship of the assembly atom nodes is written into the structure state unit.

[0036] The port connection sequence is input into the port connection generation channel. Based on the connection relationship of the generated assembly atomic nodes in the structural state unit and the mapping chain set in the mapping state unit, the source port number and target port number in the port connection sequence are matched and filtered, and the port connection relationship is generated according to the matching result. At the same time, the port occupancy status and connection order are written into the port state unit.

[0037] Based on the mapping chain set in the mapping state unit, a consistency comparison is performed on the connection relationship between the assembly atomic nodes and ports, and items with inconsistent node categories, port numbers or connection directions are replaced according to the mapping chain correspondence.

[0038] Construct an atomic assembly chain graph based on the processed assembly atomic nodes and port connection relationships.

[0039] Optionally, step four specifically involves:

[0040] Construct a drawing skeleton grid, which is a two-dimensional grid structure formed by the intersection of row and column sequences. Each grid cell is defined as a slot, and each slot is configured with a slot number, row coordinate value and column coordinate value.

[0041] According to the power supply path order in the atomic assembly chain diagram, the assembly atomic nodes are sequentially sorted. The sorting starts with the assembly atomic node corresponding to the main power node and arranges the subsequent assembly atomic nodes in sequence along the power supply path.

[0042] Based on the sorted assembly atomic node sequence, the assembly atomic nodes corresponding to the main power supply path are mapped sequentially to the main row slots of the drawing skeleton grid, and column coordinate values ​​are assigned sequentially according to the node sequence position.

[0043] The assembly atomic nodes corresponding to the branch paths are mapped to the branch row slots corresponding to the main row slots according to the branch relationship in the atomic assembly chain diagram, and the corresponding column positions are determined according to the column coordinate values ​​of the connected main nodes.

[0044] For assembly atomic nodes with protection relationships, the protection node is mapped to the next row of slots in the column where the main device node is located, based on the slot position of the corresponding main device node.

[0045] During the assembly atomic node mapping process, if an assembly atomic node already exists in the target slot, the unoccupied slots in the same row are searched column by column in ascending order of column coordinates, and the current assembly atomic node is mapped to the unoccupied slot.

[0046] Record the slot number, row coordinate value, and column coordinate value corresponding to each assembly atomic node to form a slot mapping structure. The slot mapping structure consists of the correspondence between the assembly atomic node number and the slot number.

[0047] Optionally, step five specifically includes:

[0048] Based on the slot mapping structure, extract the correspondence between assembly atomic node numbers and slot numbers, and establish a mapping table between node sequences and slot coordinates;

[0049] Based on the mapping table, a slot conflict matrix is ​​constructed. The slot conflict matrix is ​​a two-dimensional matrix structure. The row index and column index correspond to the assembly atomic node number, respectively. The matrix elements represent the slot conflict relationship between corresponding node pairs. The slot conflict relationship includes slot overlap relationship, column intersection relationship and path occlusion relationship.

[0050] Conflict determination is performed on each matrix element in the slot conflict matrix. The conflict determination includes: when two assembly atomic nodes have the same slot number, it is determined to be a slot overlap conflict; when two assembly atomic nodes have the same column coordinates and have a port connection relationship and have path overlap in the same column direction, it is determined to be a column intersection conflict; when two assembly atomic nodes are on the same power supply path and the column coordinate order is inconsistent with the power supply path order, it is determined to be a path occlusion conflict.

[0051] The number of conflicts for each assembly atomic node is counted according to the slot conflict matrix, and the assembly atomic nodes are sorted from high to low according to the number of conflicts to form a conflict node sequence.

[0052] Assembly atomic nodes are selected sequentially according to the conflict node sequence. A slot adjustment operation is performed on the selected assembly atomic nodes. The slot adjustment operation includes searching for unoccupied slots column by column in ascending direction of column coordinates in the current node row and mapping the corresponding assembly atomic node to the unoccupied slot.

[0053] After each slot adjustment, update the slot mapping structure and recalculate the matrix element values ​​associated with the current assembly atomic node;

[0054] Repeat the slot adjustment and matrix update process until there are no conflict relationships in the slot conflict matrix or the number of conflicts in the slot conflict matrix no longer decreases;

[0055] Based on the adjusted slot mapping structure, the assembly atomic node numbers are read in the order of the power supply path to form the target assembly sequence.

[0056] Optionally, step six specifically includes:

[0057] Based on the target assembly sequence, read the assembly atomic node number, slot number, and port connection relationship, and establish a graphic element generation table. The graphic element generation table includes graphic element number, graphic element type identifier, slot number, port number, and connection relationship number. The graphic element number is generated corresponding to the assembly atomic node number.

[0058] Based on the primitive generation table, the primitive type identifier is mapped to the primitive symbol number according to the primitive symbol node in the knowledge graph, and the row coordinate value and column coordinate value are extracted according to the slot number to form a primitive arrangement sequence;

[0059] A graphic element connection script is generated based on the graphic element arrangement sequence. The graphic element connection script includes graphic element symbol number, insertion coordinates, port number, connection start point number, connection end point number, and connection sequence number.

[0060] Based on the insertion coordinates and element symbol numbers in the element connection script, insert the corresponding elements in the drawing coordinate system and record the correspondence between the element number and the coordinate position.

[0061] Based on the connection start point number, connection end point number, and port number in the element connection script, determine the corresponding starting port coordinates and target port coordinates;

[0062] A sequence of connecting line segments is generated based on the coordinates of the starting port and the coordinates of the target port. The sequence of connecting line segments includes horizontal line segments and vertical line segments, and an orthogonal path is constructed according to the column coordinate direction and the row coordinate direction.

[0063] Connect each graphic element port according to the connection sequence, and write the graphic element symbols and connection segment sequences into the drawing file to form the power design drawing.

[0064] Optionally, step seven specifically includes:

[0065] Based on the power design drawings, extract the set of graphic elements and the set of connection relationships, and establish a drawing verification table. The drawing verification table includes graphic element number, graphic element type identifier, port number, connection start point number, connection end point number, and connection sequence number.

[0066] Based on the drawing verification table and the specification layer rules in the knowledge graph, rule verification is performed on the primitive set and the connection relationship set. The rule verification includes voltage level consistency verification, loop connectivity verification, port connection integrity verification and protection relationship correspondence verification, and a verification identifier is generated for each verification item.

[0067] Based on the verification identifiers, the element numbers and connection relationship numbers that are abnormal are selected to form a set of abnormal items;

[0068] Based on the set of anomalies, locate the corresponding assembly atomic node number in the set of assembly atomic nodes, and extract the set of associated nodes of the assembly atomic node in the atomic assembly chain graph.

[0069] Starting from the assembly atomic node, the corresponding sub-chain structure is extracted, and a local drawing assembly task seed is constructed based on the sub-chain structure.

[0070] Input the local drawing assembly task seed into steps three to six, and perform node generation, slot mapping, conflict adjustment and element connection processing on the corresponding assembly atomic nodes and associated nodes to obtain the local update result;

[0071] Replace the corresponding elements and connection relationships in the original power design drawings with the local update results, and update the element numbers and connection sequence numbers in the drawing file;

[0072] Repeat the verification and partial update process until all verification indicators are passed or the number of abnormal items no longer decreases, then output the final power design drawings.

[0073] The beneficial effects of this invention are:

[0074] This invention constructs a multi-layered power design knowledge graph comprising device, port, loop, and specification layers. Combining an improved GraphRNN model with a port-driven knowledge graph structure mapping mechanism, it addresses the problems of insufficient structural relationship expression, difficulty in ensuring port-level connection consistency, and frequent primitive layout conflicts in existing power design drawing generation processes. It proposes a collaborative graph generation strategy based on mapping chain expansion, node sequence generation, and port connection sequence generation to achieve synchronous construction of assembly atom nodes and port connection relationships. During the graph generation stage, assembly atom generation channels and port connection generation channels are introduced. Through the joint control of structural state units, port state units, and mapping state units, the node generation process is kept consistent with the port connection process. The system effectively improves the consistency between the generated structure and electrical connection rules. During the spatial layout stage, a drawing skeleton grid and slot mapping structure are constructed, and a slot conflict matrix is ​​used to detect and dynamically adjust the positions of graphic elements. Multi-type conflict judgment and local optimization mechanisms reduce graphic element overlap and connection intersection phenomena. During the drawing generation stage, graphic element insertion and orthogonal path construction are driven by graphic element connection scripts, achieving a standardized expression of graphic element layout and connection relationships. During the result verification stage, a drawing verification mechanism based on standard layer rules is constructed, and combined with abnormal node location and sub-chain backtracking generation strategies, iterative corrections are made to the local structure to avoid computational redundancy caused by global reconstruction. Ultimately, this achieves automatic generation of power design drawings, ensures structural consistency, and enables adaptive optimization and updates. Attached Figure Description

[0075] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0076] Figure 1 This is a schematic diagram of the overall process of an automatic generation method for power design drawings based on knowledge graphs proposed in this invention.

[0077] Figure 2 This is a schematic diagram of the improved GraphRNN model structure in the automatic generation method of power design drawings based on knowledge graph proposed in this invention. Detailed Implementation

[0078] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0079] refer to Figures 1-2 A method for automatically generating power design drawings based on knowledge graphs includes the following steps:

[0080] Step 1: Construct a power design knowledge graph consisting of the equipment layer, port layer, loop layer, and specification layer;

[0081] Step 2: Obtain power design input parameters and generate drawing assembly task seeds in the power design knowledge graph;

[0082] Step 3: Extract the conditional subgraph from the assembly task seed according to the drawing, perform breadth-first traversal according to the power supply path order, generate the node insertion sequence and port connection sequence, and input them into the improved GraphRNN model. The improved GraphRNN model introduces a port-driven knowledge graph structure mapping mechanism to generate assembly atomic nodes and port connection relationships, forming an atomic assembly chain graph.

[0083] Step 4: Construct the drawing skeleton mesh, and map the assembly atomic nodes in the atomic assembly chain diagram to the corresponding slots in the drawing skeleton mesh according to the power supply path order to form a slot mapping structure;

[0084] Step 5: Construct a slot conflict matrix based on the slot mapping structure, perform slot adjustment on the assembly atomic nodes with conflicts, and obtain the target assembly sequence;

[0085] Step 6: Generate a graphic element connection script based on the target assembly sequence and execute the graphic element connection to obtain the power design drawings;

[0086] Step 7: Perform verification based on the power design drawings, and re-execute steps 3 to 6 for the assembly atomic nodes according to the verification results, and output the final power design drawings.

[0087] In this embodiment, step one specifically includes:

[0088] Establish an equipment layer, set up power equipment nodes, transformer nodes, busbar nodes, switch equipment nodes, cable nodes, load equipment nodes and protection equipment nodes, and configure equipment number, equipment type, voltage level and rated capacity attributes for each equipment node;

[0089] Establish a port layer, set up input port nodes, output port nodes, protection port nodes and interlocking port nodes, establish a subordinate relationship between each port node and the corresponding device node, and configure port number, port category and port direction attributes;

[0090] Establish a loop layer, set up incoming loop nodes, outgoing loop nodes, tie loop nodes and protection loop nodes, and configure loop number, loop type and voltage level attributes for each loop node;

[0091] Establish a specification layer, set voltage level matching nodes, capacity matching nodes, protection coordination nodes, and element layout nodes, and configure rule number, rule category, and applicable object attribute for each specification node;

[0092] Establish subordinate edges between the device layer and the port layer, access edges between the device layer and the loop layer, connection edges between the port layer and the loop layer, and rule mapping edges between the specification layer and the device layer, port layer, and loop layer, and configure relationship type identifiers for each type of edge;

[0093] Nodes and edges are uniformly coded. Node codes are formed by sequentially arranging node category codes and attribute field codes, and attribute field codes are arranged according to the field order in the node attribute set. Edge codes are formed by sequentially arranging edge category codes and relation attribute codes, and relation attribute codes are arranged according to the field order in the edge relation attribute set.

[0094] A knowledge graph for power design is constructed based on node encoding and edge encoding, and an index table based on node number is established.

[0095] In this implementation, the power design knowledge graph is organized using a multi-layered heterogeneous graph structure. Nodes of all types are identified by unique numbers and stored in node tables. Edges of all types form edge tables using starting node numbers, ending node numbers, and relationship type identifiers. Node tables and edge tables are linked through node numbers. Node attribute sets are stored as field sequences, with each field corresponding to a fixed data type and arranged in the order of the attribute set. Node codes are formed by concatenating node category identifiers with attribute field sequences, and edge codes are formed by concatenating edge category identifiers with relationship attribute field sequences. Rule mapping edges are used to record the correspondence between specification nodes and equipment nodes, port nodes, and loop nodes, and a mapping table is established using the rule number as the index key. The index table uses a key-value structure, where the key is the node number or rule number, and the value is the storage location of the node or rule in the node table. Node retrieval and relationship access are achieved through the index table.

[0096] In this embodiment, step two specifically includes:

[0097] Obtain power design input parameters, including voltage level parameters, load capacity parameters, load category parameters, circuit quantity parameters, and power supply mode parameters, and identify the power design input parameters with parameter numbers;

[0098] The power design input parameters are mapped to a set of parameter nodes. Each parameter node in the set corresponds to an input parameter category, and the parameter nodes are grouped according to the parameter category.

[0099] Based on the parameter node set, the device nodes, port nodes and loop nodes that match the parameter nodes are retrieved in the power design knowledge graph. The matching is carried out by comparing node attributes item by item. The attribute comparison results are counted according to the number of matching items, and nodes with a number of matching items not less than the average value of the set of matching item counts are selected as candidate node sets.

[0100] An initial connection set is constructed based on the access edge relationship between the device nodes and loop nodes in the candidate node set. The initial connection set consists of the device node number and the loop node number.

[0101] The device nodes in the initial connection set are sorted hierarchically according to the voltage level parameter, and the device nodes of the same voltage level are sorted numerically according to the load capacity parameter. The priority sequence of the device nodes is determined based on the sorting results.

[0102] Based on the priority sequence of device nodes, the set of port nodes is obtained according to the subordinate relationship between device nodes and port nodes, and the port nodes are divided according to port category to form a port group set;

[0103] A drawing assembly task seed set is constructed based on the device node set, port group set, and loop node set. The drawing assembly task seed is formed by combining the device node number, port node number, and loop node number, and is arranged according to the priority sequence of the device nodes.

[0104] In this implementation, the parameter node set is formed by discretizing the input parameters. Numerical parameters are divided into multiple interval numbers according to their value ranges, and categorical parameters are mapped to category numbers according to a predefined category set. Node attributes are compared item by item using a field consistency judgment method. The attribute fields of each candidate node are matched field by field with the corresponding parameter node fields, and the matched fields are accumulated to form a matching value. The average value of the set of matching items is calculated by summing the matching values ​​of all candidate nodes and dividing by the number of candidate nodes. Equipment nodes are sorted hierarchically according to voltage level from high to low, and within the same layer, they are sorted according to load capacity from large to small. The port group set is divided according to port category identifiers, and a correspondence is established between port numbers and equipment node numbers. The drawing assembly task seed set is stored using a triplet structure. Each triplet consists of an equipment node number, a port node number, and a loop node number, and is written into the sequence structure according to the priority order of the equipment nodes.

[0105] In this embodiment, step three specifically includes:

[0106] An improved GraphRNN model is established, which includes an assembly atom generation channel, a port connection generation channel, a structural state unit, a port state unit, and a mapping state unit. The structural state unit records the connection relationship between assembly atom nodes, the port state unit records the port occupancy status and connection order, and the mapping state unit records the correspondence between knowledge graph nodes and assembly atom nodes.

[0107] Based on the drawings, the assembly task seed extracts the conditional subgraph, and the breadth-first traversal is performed according to the power supply path order, starting from the main power node, to form the node access sequence and edge access sequence.

[0108] Construct a node insertion sequence and a port connection sequence based on the node access sequence and the edge access sequence;

[0109] A port-driven knowledge graph structure mapping mechanism is constructed. The port-driven knowledge graph structure mapping mechanism takes the port node as the starting point and expands the execution path along the subordinate edge between the port node and the device node, the connection edge between the port node and the loop node, and the rule mapping edge between the canonical node and the port node. This forms a set of mapping chains containing the port node number, device node number, loop node number, and canonical node number. The set of mapping chains is written into the mapping state unit in the order of path expansion.

[0110] The node insertion sequence is input into the assembly atom generation channel. Based on the mapping chain set in the mapping state unit, the device category identifier and loop category identifier in the node insertion sequence are matched and filtered. Assembly atom nodes are generated according to the matching results. At the same time, the connection relationship of the assembly atom nodes is written into the structural state unit.

[0111] Input the port connection sequence into the port connection generation channel. Based on the connection relationship of the generated assembly atomic nodes in the structural state unit and the set of mapping chains in the mapping state unit, match and filter the source port number and target port number in the port connection sequence, and generate the port connection relationship according to the matching result. At the same time, write the port occupancy status and connection order into the port state unit.

[0112] Based on the mapping chain set in the mapping state unit, a consistency comparison is performed on the connection relationship between the assembly atomic nodes and ports, and items with inconsistent node categories, port numbers or connection directions are replaced according to the mapping chain correspondence.

[0113] Construct an atomic assembly chain graph based on the processed assembly atomic nodes and port connection relationships.

[0114] In this implementation, in the port-driven knowledge graph structure mapping mechanism, the port node determines its expansion priority according to its connectivity in the conditional subgraph and the type of its associated loop, and performs layer-by-layer path expansion on the port node in priority order. During the path expansion process, dependent edges, connecting edges, and rule mapping edges are numbered and marked respectively. The mapping chain set is stored in the form of a multi-field sequence. Each mapping chain contains the port node number, associated device node number, associated loop node number, and corresponding specification node number, and is written into the mapping state unit in the order of path expansion. When the assembly atom generation channel processes the node insertion sequence, it filters the node category according to the combination relationship between the device node number and the loop node number in the mapping chain set. When the port connection generation channel processes the port connection sequence, it filters the port connection pairs according to the combination relationship between the port node number and the connecting edge number in the mapping chain set. The structure state unit and the port state unit record the connection position and port occupancy identifier in the generation process in the form of a sequence, and realize the state synchronization update through the node number and the port number.

[0115] The improved GraphRNN model adopts the serialized graph generation method of the GraphRNN model in its overall structure, representing the graph structure as a sequence of nodes and a sequence of connections. It models the node generation process and the connection generation process step by step through a recursive network. During the generation process, the node sequence is input in the order of graph traversal, and the connection sequence is gradually expanded according to the relationship between nodes. The model passes the generated structure information through hidden states, thereby realizing the continuous generation and updating of the graph structure.

[0116] In terms of basic structure, the GraphRNN model is improved by introducing a dual-channel structure of assembly atom generation channel and port connection generation channel, and setting up structural state units, port state units, and mapping state units. Among them, the mapping state unit stores the set of knowledge graph mapping chains formed by port nodes. The assembly atom generation channel filters the node categories according to the set of mapping chains, and the port connection generation channel filters the port connection pairs according to the set of mapping chains and the structural state unit, thus forming a port-driven knowledge graph structure mapping mechanism.

[0117] Through the above improvements, both the node generation process and the connection generation process are constrained by the mapping chain set. The generation result is consistent with the device relationship, port relationship and loop relationship in the knowledge graph. At the same time, the structural state unit and the port state unit record the generation process synchronously, so that the node connection relationship is consistent with the port occupancy relationship, reducing invalid connections and conflicting connections in the generation process, and improving the connectivity and consistency of the generated structure.

[0118] In this embodiment, step four specifically includes:

[0119] Construct a drawing skeleton grid, which is a two-dimensional grid structure formed by the intersection of row and column sequences. Each grid cell is defined as a slot, and each slot is assigned a slot number, row coordinate value, and column coordinate value.

[0120] According to the power supply path order in the atomic assembly chain diagram, the assembly atomic nodes are sequentially sorted. The sorting starts with the assembly atomic node corresponding to the main power supply node and arranges the subsequent assembly atomic nodes in sequence along the power supply path.

[0121] Based on the sorted assembly atomic node sequence, the assembly atomic nodes corresponding to the main power supply path are mapped sequentially to the main row slots of the drawing skeleton grid, and column coordinate values ​​are assigned sequentially according to the node sequence position.

[0122] Map the assembly atomic nodes corresponding to the branch paths to the branch row slots corresponding to the main row slots according to the branch relationship in the atomic assembly chain diagram, and determine the corresponding column positions based on the column coordinate values ​​of the connected main nodes.

[0123] For assembly atomic nodes with protection relationships, the protection node is mapped to the next row of slots in the column where the main device node is located, based on the slot position of the corresponding main device node.

[0124] During the mapping of assembly atomic nodes, if an assembly atomic node already exists in the target slot, the unoccupied slots in the same row are searched column by column in ascending order of column coordinates, and the current assembly atomic node is mapped to the unoccupied slot.

[0125] Record the slot number, row coordinates, and column coordinates corresponding to each assembly atomic node to form a slot mapping structure. The slot mapping structure consists of the correspondence between assembly atomic node numbers and slot numbers.

[0126] In this implementation, the row sequence in the drawing skeleton grid is divided into main rows, branch rows, and protection rows according to the power supply level, and the column sequence is arranged in ascending order of node number according to the power supply path sequence. The main rows correspond to the main power supply path, the branch rows are allocated row by row according to the number of branches, and the protection rows are set below the main rows or branch rows. During the mapping process, the target row coordinates of the assembly atomic nodes are determined first according to their circuit type and branch level, and then the initial column coordinates are determined according to their sequence number in the power supply path. When there are multiple branch nodes, the branch rows are allocated in sequence according to the branch sequence number, and the columns are aligned with the column coordinates of the main nodes as the reference. The slot occupancy status is marked by the slot number and updated in real time during the mapping process. The column coordinate adjustment process is limited to the same row range to keep the power supply path direction consistent. The slot mapping structure establishes a mapping table with the assembly atomic node number as the key and the slot number as the value, which is used for subsequent element connection and positioning.

[0127] In this embodiment, step five specifically includes:

[0128] Based on the slot mapping structure, extract the correspondence between the assembly atomic node number and the slot number, and establish a mapping table between the node sequence and the slot coordinates;

[0129] A slot conflict matrix is ​​constructed based on the mapping table. The slot conflict matrix is ​​a two-dimensional matrix structure. The row index and column index correspond to the assembly atomic node number, respectively. The matrix elements represent the slot conflict relationship between corresponding node pairs. The slot conflict relationship includes slot overlap relationship, column intersection relationship and path occlusion relationship.

[0130] Perform conflict determination on each matrix element in the slot conflict matrix. The conflict determination includes: when two assembly atomic nodes have the same slot number, it is determined to be a slot overlap conflict; when two assembly atomic nodes have the same column coordinates, have a port connection relationship, and have path overlap in the same column direction, it is determined to be a column intersection conflict; when two assembly atomic nodes are on the same power supply path and the column coordinate order is inconsistent with the power supply path order, it is determined to be a path occlusion conflict.

[0131] The number of conflicts for each assembly atomic node is counted based on the slot conflict matrix, and the assembly atomic nodes are sorted from high to low according to the number of conflicts to form a conflict node sequence.

[0132] The assembly atomic nodes are selected sequentially according to the conflict node sequence. The slot adjustment operation is performed on the selected assembly atomic nodes. The slot adjustment operation includes searching for unoccupied slots column by column in ascending direction in the current node row and mapping the corresponding assembly atomic nodes to the unoccupied slots.

[0133] After each slot adjustment, update the slot mapping structure and recalculate the matrix element values ​​associated with the current assembly atomic node;

[0134] Repeat the slot adjustment and matrix update process until there are no conflict relationships in the slot conflict matrix or the number of conflicts in the slot conflict matrix no longer decreases;

[0135] Based on the adjusted slot mapping structure, the assembly atomic node numbers are read in the order of the power supply path to form the target assembly sequence.

[0136] In this implementation, the matrix elements in the slot conflict matrix use multi-value encoding to represent the conflict type and conflict intensity. The conflict type corresponds to slot overlap, column intersection, and path occlusion, respectively. The conflict intensity is calculated cumulatively based on the distance difference and the number of connection relationships of the assembly atomic nodes involved in the conflict in the power supply path. The number of node conflicts is obtained by summing all non-zero elements in the corresponding matrix row. During the slot adjustment process, the assembly atomic node with the highest conflict intensity is selected first to perform position update, and candidate slots are searched column by column in ascending order of column coordinates in the same row. The conflict intensity of each candidate slot with other nodes is recalculated, and the slot with the lowest conflict intensity is selected as the target slot. After each adjustment, only the matrix row and matrix column corresponding to the affected node are locally updated to reduce redundant calculations. The target assembly sequence is generated based on the updated slot coordinates in ascending order of column coordinates while maintaining the consistent order of the power supply path.

[0137] In this embodiment, step six specifically includes:

[0138] Based on the target assembly sequence, read the assembly atomic node number, slot number, and port connection relationship, and establish an element generation table. The element generation table includes element number, element type identifier, slot number, port number, and connection relationship number. The element number is generated corresponding to the assembly atomic node number.

[0139] Based on the primitive generation table, the primitive type identifier is mapped to the primitive symbol number according to the primitive symbol node in the knowledge graph, and the row coordinate value and column coordinate value are extracted according to the slot number to form the primitive layout sequence;

[0140] Generate a graphic element connection script based on the graphic element layout sequence. The graphic element connection script includes graphic element symbol number, insertion coordinates, port number, connection start point number, connection end point number, and connection sequence number.

[0141] Based on the insertion coordinates and element symbol numbers in the element connection script, insert the corresponding elements in the drawing coordinate system and record the correspondence between the element numbers and coordinate positions;

[0142] Based on the connection start point number, connection end point number, and port number in the element connection script, determine the corresponding start port coordinates and target port coordinates;

[0143] A sequence of connecting line segments is generated based on the coordinates of the starting port and the target port. The sequence of connecting line segments includes horizontal line segments and vertical line segments, and an orthogonal path is constructed according to the column coordinate direction and the row coordinate direction.

[0144] Connect each graphic element port according to the connection sequence, and write the graphic element symbols and connection segment sequences into the drawing file to form the power design drawing.

[0145] In this implementation, the correspondence between the element type identifier and the element symbol number in the element generation table is established through a pre-established symbol mapping table, which stores the element type identifier as the key and the element symbol number as the value. The insertion coordinate is formed by directly mapping the row coordinate value and column coordinate value corresponding to the slot number to the drawing coordinate system, which uses a unified scale for coordinate conversion. The port coordinate is calculated by superimposing the predefined port relative position in the element symbol with the insertion coordinate. During the generation process, the connection segment sequence marks the direction of each segment and performs coordinate continuity verification on the connection points of adjacent segments. The element symbol and connection segment data are written to the drawing file in a hierarchical structure. The element data layer records the element number and coordinate information, and the connection data layer records the start and end coordinates of the segment and the connection sequence number. The unified management of the element and connection relationship is achieved through number association.

[0146] In this embodiment, step seven specifically includes:

[0147] Based on the set of graphic elements and the set of connection relationships extracted from the power design drawings, a drawing verification table is established. The drawing verification table includes graphic element number, graphic element type identifier, port number, connection start point number, connection end point number, and connection sequence number.

[0148] Based on the drawing verification table and the specification layer rules in the knowledge graph, rule verification is performed on the set of elements and the set of connection relationships. The rule verification includes voltage level consistency verification, loop connectivity verification, port connection integrity verification and protection relationship correspondence verification, and a verification identifier is generated for each verification item.

[0149] Based on the verification identifiers, the element numbers and connection relationship numbers that are abnormal are selected to form a set of abnormal items;

[0150] Based on the set of anomalies, locate the corresponding assembly atomic node number in the set of assembly atomic nodes, and extract the set of associated nodes of the assembly atomic node in the atomic assembly chain graph.

[0151] Starting from the assembly atomic node, extract the corresponding sub-chain structure, and construct a local drawing assembly task seed based on the sub-chain structure;

[0152] Input the local drawing assembly task seed into steps three through six, and perform node generation, slot mapping, conflict adjustment and element connection processing on the corresponding assembly atomic nodes and associated nodes to obtain the local update result.

[0153] Replace the corresponding elements and connection relationships in the original power design drawings with the results of the partial update, and update the element numbers and connection sequence numbers in the drawing file;

[0154] Repeat the verification and partial update process until all verification indicators are passed or the number of abnormal items no longer decreases, then output the final power design drawings.

[0155] In this implementation, the judgment results of each verification item in the drawing verification table are represented by multi-value identifiers, where each verification identifier corresponds to a pass or abnormal state; the abnormal item set is obtained by filtering the verification identifiers and establishing an index mapping according to the element number and the connection relationship number; during the assembly atomic node positioning process, abnormal nodes are determined by the correspondence between the element number and the assembly atomic node number, and the set of associated nodes is extracted based on the adjacency relationship in the atomic assembly chain diagram; the sub-chain structure is represented by a continuous node sequence, and the sequence range is determined by the predecessor and successor nodes of the abnormal node in the power supply path; the local drawing assembly task seed is generated by combining the node number, port number, and loop number in the sub-chain structure, while maintaining the original node order; during the local update result replacement process, only the corresponding elements and connection relationships are covered, while the rest remain unchanged, and the update positioning is completed by the element number and the connection sequence number.

[0156] Example 1: To verify the feasibility of this invention in practice, it was applied to the primary system design scenario of a 110kV substation in a certain region. This involved automated drawing generation for a power design task with multiple outgoing circuits, complex protection configurations, and diverse equipment types. This scenario involves various types of equipment, including main transformers, busbar systems, circuit breakers, disconnectors, cable lines, and relay protection devices. Traditional design methods typically rely on manual drawing of element layouts and connections in CAD software, which is not only time-consuming but also prone to errors in connection relationships, element overlap, and non-standard layouts, especially in cases of multiple circuit intersections and complex protection configurations. This makes it difficult to meet the current project requirements for design efficiency and consistency.

[0157] In this scenario, the existing design specifications and equipment library are first organized to construct a power design knowledge graph containing equipment, port, loop, and specification layers. The equipment layer describes the types and attributes of equipment such as main transformers and circuit breakers; the port layer describes the input / output and protection ports of each device; the loop layer describes the incoming, outgoing, and tie-line circuit structures; and the specification layer describes voltage level matching, protection configuration, and element layout rules. Subsequently, based on engineering input parameters, including a 110kV voltage level, a load capacity of 80MW, 6 outgoing loops, and a single busbar segmented power supply structure, these parameters are mapped to the knowledge graph to generate drawing assembly task seeds, and equipment nodes, port nodes, and loop nodes that meet the criteria are automatically selected.

[0158] In the graph generation stage, an improved GraphRNN model is used to process the conditional subgraph. Assembly atom generation channels and port connection generation channels work collaboratively, combined with a port-driven knowledge graph structure mapping mechanism. Port nodes are used as the starting point for path expansion, forming a set of mapping chains. This prioritizes device types that meet electrical connection rules during node generation and filters port pairs that conform to port connection relationships during connection generation, achieving synchronous generation of assembly atom nodes and port connection relationships. The generated atomic assembly chain graph is further input into the drawing skeleton mesh module. Through the structural division of main rows, branch rows, and protection rows, each node is mapped to its corresponding slot, forming the initial primitive layout.

[0159] To address potential overlap and connection intersection issues in graphical elements, a slot conflict matrix is ​​constructed to determine slot overlap, column intersection, and path occlusion between nodes. Nodes are then sorted according to conflict intensity, and slot positions are redistributed through a column-by-column adjustment strategy to eliminate conflicts. After layout optimization, the system automatically generates a graphical element connection script based on the target assembly sequence, inserts the elements into the drawing coordinate system, and generates orthogonal connection segments, achieving automatic drawing of complete power design drawings. Subsequently, a drawing verification mechanism based on specification layer rules is used to verify voltage level consistency, circuit connectivity, port connection integrity, and protection relationships item by item. Anomalies in local structures are re-reconstructed, regenerating only the relevant sub-chain structures to avoid global redundant calculations.

[0160] To verify the beneficial effects of the present invention, the performance of the traditional manual design method and the method of the present invention in the same design task was compared. The experimental results are shown in Table 1.

[0161] Table 1. Comparison of Automatic Generation Results of Power Design Drawings

[0162] Indicator Items Manual design method Method of the present invention Total time (minutes) to generate drawings 185 42 Compliance rate of graphic element layout specifications (%) 82.5 96.8 Number of connection errors (locations) 14 2 Number of overlapping primitives (locations) 9 1 Number of intersections (at) 11 2 First-time pass rate (%) 68.2 92.6 Number of local backtracking attempts (times) not applicable 3 Overall drawing consistency score (out of 100) 78 94

[0163] As shown in Table 1, this invention demonstrates significant advantages in several key indicators. The total time for drawing generation was reduced from 185 minutes to 42 minutes, indicating that automated generation and local backtracking mechanisms significantly improved design efficiency. The compliance rate of element layout specifications reached 96.8%, demonstrating that the layout method based on knowledge graphs and slot mapping can effectively ensure the standardization of drawings. The number of connection relationship errors, element overlaps, and connection intersections all decreased significantly, reflecting the effectiveness of the port-driven structural mapping mechanism and conflict matrix adjustment strategy in terms of structural consistency and spatial layout optimization. The first-pass pass rate was significantly improved, indicating that the generated results better meet the design rules and reduce repeated modifications. The overall consistency score increased from 78 to 94, further verifying the stability and reliability of this invention in the automatic generation of complex power design drawings.

[0164] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for automatically generating power design drawings based on knowledge graphs, characterized in that, Includes the following steps: Step 1: Construct a power design knowledge graph consisting of the equipment layer, port layer, loop layer, and specification layer; Step 2: Obtain power design input parameters and generate drawing assembly task seeds in the power design knowledge graph; Step 3: Extract the condition subgraph from the assembly task seed according to the drawing, perform breadth-first traversal according to the power supply path order, generate the node insertion sequence and port connection sequence, and input them into the improved GraphRNN model. The improved GraphRNN model introduces a port-driven knowledge graph structure mapping mechanism to generate assembly atomic nodes and port connection relationships, forming an atomic assembly chain graph. Step 4: Construct the drawing skeleton mesh, and map the assembly atomic nodes in the atomic assembly chain diagram to the corresponding slots in the drawing skeleton mesh according to the power supply path sequence to form a slot mapping structure; Step 5: Construct a slot conflict matrix based on the slot mapping structure, perform slot adjustment on the assembly atomic nodes with conflicts, and obtain the target assembly sequence; Step 6: Generate a graphic element connection script based on the target assembly sequence and execute the graphic element connection to obtain the power design drawings; Step 7: Perform verification based on the power design drawings, and re-execute steps 3 to 6 for the assembly atomic nodes according to the verification results, and output the final power design drawings.

2. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step one specifically involves: Establish an equipment layer, set up power equipment nodes, transformer nodes, busbar nodes, switch equipment nodes, cable nodes, load equipment nodes and protection equipment nodes, and configure equipment number, equipment type, voltage level and rated capacity attributes for each equipment node; Establish a port layer, set up input port nodes, output port nodes, protection port nodes and interlocking port nodes, establish a subordinate relationship between each port node and the corresponding device node, and configure port number, port category and port direction attributes; Establish a loop layer, set up incoming loop nodes, outgoing loop nodes, tie loop nodes and protection loop nodes, and configure loop number, loop type and voltage level attributes for each loop node; Establish a specification layer, set voltage level matching nodes, capacity matching nodes, protection coordination nodes, and element layout nodes, and configure rule number, rule category, and applicable object attribute for each specification node; Establish subordinate edges between the device layer and the port layer, access edges between the device layer and the loop layer, connection edges between the port layer and the loop layer, and rule mapping edges between the specification layer and the device layer, port layer, and loop layer, and configure relationship type identifiers for each type of edge; Nodes and edges are uniformly encoded. Node codes are formed by sequentially arranging node category codes and attribute field codes, with the attribute field codes arranged in the order of the fields in the node attribute set. Edge codes are formed by sequentially arranging edge category codes and relation attribute codes, with the relation attribute codes arranged in the order of the fields in the edge relation attribute set. A knowledge graph for power design is constructed based on node encoding and edge encoding, and an index table based on node number is established.

3. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step two specifically involves: Obtain power design input parameters, which include voltage level parameters, load capacity parameters, load category parameters, number of circuit parameters, and power supply mode parameters, and identify the power design input parameters by parameter number; The power design input parameters are mapped to a set of parameter nodes, each parameter node in the set of parameter nodes corresponds to an input parameter category, and the parameter nodes are grouped according to the parameter category; Based on the parameter node set, equipment nodes, port nodes, and loop nodes that match the parameter nodes are retrieved in the power design knowledge graph. The matching is performed by comparing node attributes item by item. The attribute comparison results are counted according to the number of matching items, and nodes with a number of matching items not less than the average value of the set of matching item numbers are selected as candidate node sets. An initial connection set is constructed based on the access edge relationship between the device nodes and loop nodes in the candidate node set. The initial connection set consists of the device node number and the loop node number. The device nodes in the initial connection set are sorted hierarchically according to voltage level parameters, and the device nodes of the same voltage level are sorted numerically according to load capacity parameters. The priority sequence of the device nodes is determined based on the sorting results. Based on the priority sequence of the device nodes, a set of port nodes is obtained according to the subordinate relationship between the device nodes and the port nodes, and the port nodes are divided according to the port category to form a port group set; Based on the set of device nodes, the set of port groups, and the set of loop nodes, a set of drawing assembly task seeds is constructed. The drawing assembly task seeds are formed by combining the device node number, the port node number, and the loop node number, and are arranged according to the priority sequence of the device nodes.

4. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step three specifically involves: An improved GraphRNN model is established, which includes an assembly atom generation channel, a port connection generation channel, a structural state unit, a port state unit, and a mapping state unit. The structural state unit records the connection relationship between assembly atom nodes, the port state unit records the port occupancy status and connection order, and the mapping state unit records the correspondence between knowledge graph nodes and assembly atom nodes. Based on the drawings, the assembly task seed extracts the conditional subgraph, and the breadth-first traversal is performed according to the power supply path order, starting from the main power node, to form the node access sequence and edge access sequence. Construct a node insertion sequence and a port connection sequence based on the node access sequence and the edge access sequence; A port-driven knowledge graph structure mapping mechanism is constructed. The port-driven knowledge graph structure mapping mechanism takes the port node as the starting point and expands the path along the subordinate edge between the port node and the device node, the connection edge between the port node and the loop node, and the rule mapping edge between the canonical node and the port node to form a set of mapping chains containing the port node number, device node number, loop node number and canonical node number. The set of mapping chains is written into the mapping state unit in the order of path expansion. The node insertion sequence is input into the assembly atom generation channel. Based on the mapping chain set in the mapping state unit, the device category identifier and loop category identifier in the node insertion sequence are matched and filtered. Assembly atom nodes are generated according to the matching results. At the same time, the connection relationship of the assembly atom nodes is written into the structure state unit. The port connection sequence is input into the port connection generation channel. Based on the connection relationship of the generated assembly atomic nodes in the structural state unit and the mapping chain set in the mapping state unit, the source port number and target port number in the port connection sequence are matched and filtered, and the port connection relationship is generated according to the matching result. At the same time, the port occupancy status and connection order are written into the port state unit. Based on the mapping chain set in the mapping state unit, a consistency comparison is performed on the connection relationship between the assembly atomic nodes and ports, and items with inconsistent node categories, port numbers or connection directions are replaced according to the mapping chain correspondence. Construct an atomic assembly chain graph based on the processed assembly atomic nodes and port connection relationships.

5. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step four specifically involves: Construct a drawing skeleton grid, which is a two-dimensional grid structure formed by the intersection of row and column sequences. Each grid cell is defined as a slot, and each slot is configured with a slot number, row coordinate value and column coordinate value. According to the power supply path order in the atomic assembly chain diagram, the assembly atomic nodes are sequentially sorted. The sorting starts with the assembly atomic node corresponding to the main power node and arranges the subsequent assembly atomic nodes in sequence along the power supply path. Based on the sorted assembly atomic node sequence, the assembly atomic nodes corresponding to the main power supply path are mapped sequentially to the main row slots of the drawing skeleton grid, and column coordinate values ​​are assigned sequentially according to the node sequence position. The assembly atomic nodes corresponding to the branch paths are mapped to the branch row slots corresponding to the main row slots according to the branch relationship in the atomic assembly chain diagram, and the corresponding column positions are determined according to the column coordinate values ​​of the connected main nodes. For assembly atomic nodes with protection relationships, the protection node is mapped to the next row of slots in the column where the main device node is located, based on the slot position of the corresponding main device node. During the assembly atomic node mapping process, if an assembly atomic node already exists in the target slot, then the unoccupied slots in the same row are searched column by column in ascending order of column coordinates, and the current assembly atomic node is mapped to the unoccupied slot. Record the slot number, row coordinate value, and column coordinate value corresponding to each assembly atomic node to form a slot mapping structure. The slot mapping structure consists of the correspondence between the assembly atomic node number and the slot number.

6. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step five specifically involves: Based on the slot mapping structure, extract the correspondence between assembly atomic node numbers and slot numbers, and establish a mapping table between node sequences and slot coordinates; Based on the mapping table, a slot conflict matrix is ​​constructed. The slot conflict matrix is ​​a two-dimensional matrix structure. The row index and column index correspond to the assembly atomic node number, respectively. The matrix elements represent the slot conflict relationship between corresponding node pairs. The slot conflict relationship includes slot overlap relationship, column intersection relationship and path occlusion relationship. Conflict determination is performed on each matrix element in the slot conflict matrix. The conflict determination includes: when two assembly atomic nodes have the same slot number, it is determined to be a slot overlap conflict; when two assembly atomic nodes have the same column coordinates and have a port connection relationship and have path overlap in the same column direction, it is determined to be a column intersection conflict; when two assembly atomic nodes are on the same power supply path and the column coordinate order is inconsistent with the power supply path order, it is determined to be a path occlusion conflict. The number of conflicts for each assembly atomic node is counted according to the slot conflict matrix, and the assembly atomic nodes are sorted from high to low according to the number of conflicts to form a conflict node sequence. Assembly atomic nodes are selected sequentially according to the conflict node sequence. A slot adjustment operation is performed on the selected assembly atomic nodes. The slot adjustment operation includes searching for unoccupied slots column by column in ascending direction of column coordinates in the current node row and mapping the corresponding assembly atomic node to the unoccupied slot. After each slot adjustment, update the slot mapping structure and recalculate the matrix element values ​​associated with the current assembly atomic node; Repeat the slot adjustment and matrix update process until there are no conflict relationships in the slot conflict matrix or the number of conflicts in the slot conflict matrix no longer decreases; Based on the adjusted slot mapping structure, the assembly atomic node numbers are read in the order of the power supply path to form the target assembly sequence.

7. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step six specifically involves: Based on the target assembly sequence, read the assembly atomic node number, slot number, and port connection relationship, and establish a graphic element generation table. The graphic element generation table includes graphic element number, graphic element type identifier, slot number, port number, and connection relationship number. The graphic element number is generated corresponding to the assembly atomic node number. Based on the primitive generation table, the primitive type identifier is mapped to the primitive symbol number according to the primitive symbol node in the knowledge graph, and the row coordinate value and column coordinate value are extracted according to the slot number to form a primitive arrangement sequence; A graphic element connection script is generated based on the graphic element arrangement sequence. The graphic element connection script includes graphic element symbol number, insertion coordinates, port number, connection start point number, connection end point number, and connection sequence number. Based on the insertion coordinates and element symbol numbers in the element connection script, insert the corresponding elements in the drawing coordinate system and record the correspondence between the element number and the coordinate position. Based on the connection start point number, connection end point number, and port number in the element connection script, determine the corresponding starting port coordinates and target port coordinates; A sequence of connecting line segments is generated based on the coordinates of the starting port and the coordinates of the target port. The sequence of connecting line segments includes horizontal line segments and vertical line segments, and an orthogonal path is constructed according to the column coordinate direction and the row coordinate direction. Connect each graphic element port according to the connection sequence, and write the graphic element symbols and connection segment sequences into the drawing file to form the power design drawing.

8. The method for automatically generating power design drawings based on knowledge graphs according to claim 1, characterized in that, Step seven specifically involves: Based on the power design drawings, extract the set of graphic elements and the set of connection relationships, and establish a drawing verification table. The drawing verification table includes graphic element number, graphic element type identifier, port number, connection start point number, connection end point number, and connection sequence number. Based on the drawing verification table and the specification layer rules in the knowledge graph, rule verification is performed on the primitive set and the connection relationship set. The rule verification includes voltage level consistency verification, loop connectivity verification, port connection integrity verification and protection relationship correspondence verification, and a verification identifier is generated for each verification item. Based on the verification identifiers, the element numbers and connection relationship numbers that are abnormal are filtered to form a set of abnormal items; Based on the set of anomalies, locate the corresponding assembly atomic node number in the set of assembly atomic nodes, and extract the set of associated nodes of the assembly atomic node in the atomic assembly chain graph. Starting from the assembly atomic node, the corresponding sub-chain structure is extracted, and a local drawing assembly task seed is constructed based on the sub-chain structure. Input the local drawing assembly task seed into steps three to six, and perform node generation, slot mapping, conflict adjustment and element connection processing on the corresponding assembly atomic nodes and associated nodes to obtain the local update result; Replace the corresponding elements and connection relationships in the original power design drawings with the local update results, and update the element numbers and connection sequence numbers in the drawing file; Repeat the verification and partial update process until all verification indicators are passed or the number of abnormal items no longer decreases, then output the final power design drawings.

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