An ultra-wideband doherty power amplifier system and control method

Abstract

This invention provides an ultra-wideband Doherty power amplifier system and control method, comprising a control layer, a physical layer, and an optimization layer. The physical layer employs three parallel gallium nitride high electron mobility transistors, combined with a broadband collaborative synthesis network of a multilayer PCB planar transformer synthesizer with a leakage inductance resonant parasitic absorption mechanism, to achieve bandwidth expansion. The optimization layer introduces an improved MOEA / D algorithm with group delay flatness constraints. The control layer uses an FPGA-embedded model to assist in iterative learning and control of the ILC unit. This invention effectively solves the nonlinear divergence problem caused by strong physical-control coupling in a three-channel amplifier module architecture within the ultra-wideband range, simultaneously achieving high back-off efficiency and fast, stable convergence of the digital predistortion algorithm in the 0.6–4.9 GHz frequency band.

Description

Technical Field

[0001] This invention belongs to the interdisciplinary field of radio frequency microwave engineering, wireless communication transmitter technology and digital signal processing control, and specifically relates to an ultra-wideband Doherty power amplifier system and control method. Background Technology

[0002] In existing mobile communication technologies, the 5G NR (New Radio) standard introduces a large number of new Sub-6GHz frequency bands while needing to be compatible with traditional low-frequency bands (600MHz-2.7GHz). Traditional base station architectures typically use independent power amplifiers (PAs) for each frequency band, resulting in extremely bulky rooftop systems and high maintenance costs. To ensure signal integrity, the power amplifiers must operate under significant power back-off (OBO). Traditional Class A / B amplifiers have extremely low efficiency in the back-off region (typically <20%), leading to significant energy waste and heat dissipation pressure. Traditional Doherty power amplifiers face two core challenges: first, bandwidth limitation: traditional DPAs rely on quarter-wavelength transmission lines for impedance inversion, resulting in a relative bandwidth typically limited to 10%~20%; second, insufficient back-off depth: dual-path DPAs typically only provide a high-efficiency back-off range of 6dB, which is insufficient to handle the PAPR of 5G signals exceeding 10dB.

[0003] To extend the backoff range, a three-way Doherty architecture power amplifier emerged. However, implementing a digital three-way Doherty amplifier in the ultra-wideband range of 0.6~4.9GHz faces a severe "physical-control" coupling problem. Existing technologies lack a system solution that can be designed from the physical layer (circuit parameters) to the logic layer (control algorithm), making it difficult to achieve high efficiency, high linearity, and fast and stable control convergence in the ultra-wideband range. The specific technical defects are as follows: (1) Traditional combining network design is difficult to maintain an ideal load modulation trajectory in the entire frequency band, resulting in poles and zeros drifting with frequency; efficiency is reduced, and a strong memory effect is generated, making the nonlinear behavior of the PA extremely complex; (2) The contradiction between high efficiency and controllability: Traditional hardware design methods often unilaterally pursue the maximization of static efficiency. This single-objective optimization can easily lead to the circuit exhibiting extremely high Q values ​​at certain frequency points (especially the band edge), with extremely steep phase response, i.e., huge group delay fluctuations; for digital predistortion (DPD) or iterative learning control (ILC) algorithms, even small errors will be amplified, making it difficult for the algorithm to lock in, or even causing oscillations; (3) Existing industrial processes are usually fragmented: "hardware first, software later". Since the control algorithm has no knowledge of the physical characteristics and sensitivity distribution of the hardware, it uses a "trial and error" method to scan the entire frequency band, resulting in extremely long calibration convergence time, which is easy to get trapped in local minima and cannot meet the requirements of rapid startup and real-time self-healing of 5G base stations. Summary of the Invention

[0004] To address the current technical challenges in the industry, such as limited bandwidth, insufficient back-off depth, and the severe "physical-control" coupling between ultra-wideband hardware and digital control algorithms leading to easy divergence, this invention develops an ultra-wideband Doherty power amplifier system and control method. The system comprises a control layer, a physical layer, and an optimization layer. The physical layer employs three parallel gallium nitride high electron mobility transistors, combined with a multilayer PCB planar transformer synthesizer with a leakage inductance resonant parasitic absorption mechanism to construct a synthesis network, achieving bandwidth expansion. The optimization layer introduces an improved MOEA / D algorithm with constraints on group delay flatness to generate a hardware feature fingerprint library offline that balances high efficiency and digital controllability. The control layer uses an assisted iterative learning control (ILC) unit with an FPGA built-in model to call hardware features for collaborative initialization in real time and implements frequency-selective variable step-size iteration and piecewise linearization strategies. This invention effectively solves the nonlinear divergence problem caused by the strong "physical-control" coupling of the three-way Doherty architecture in the ultra-wideband range, simultaneously achieving high back-off efficiency and fast, stable convergence of the digital predistortion algorithm within the 0.6–4.9 GHz frequency band.

[0005] On one hand, the present invention provides an ultra-wideband Doherty power amplifier system, which includes: a physical layer, an optimization layer and a control layer, wherein the control layer includes: a digital co-controller FPGA, an RF transmit channel group, a power amplification module and a broadband co-synthesis network; The digital co-controller FPGA is a digital predistortion (DPD) closed-loop system including non-volatile memory, error calculation eK unit, model-aided iterative learning control (ILC) unit, signal decomposition module, and feedback channel ADC; the signal decomposition module receives the update coefficients from the model-aided iterative learning control (ILC) unit, performs predistortion processing on the baseband input signal, and generates three independent digital baseband pilot signals. The radio frequency transmission channel group includes: three parallel signal conversion modules that convert the digital baseband pilot signal into radio frequency analog pilot signal. Each signal conversion module consists of a wideband digital-to-analog converter (DAC) and a radio frequency upconverter. Each signal conversion module is coupled to the output terminal of the digital co-controller FPGA. The power amplification module includes three amplification modules: a carrier amplifier Main PA, a first peak amplifier Peak1 PA, and a second peak amplifier Peak2 PA; the drain output of the three amplification modules is connected to the input of the broadband collaborative synthesis network, the output of the broadband collaborative synthesis network is connected to a 50Ω load and a feedback channel ADC, and the output of the feedback channel ADC is connected to an error calculation eK unit. The physical layer includes: a three-way amplification architecture constructed from three parallel gallium nitride high electron mobility transistors as the core amplification device, and a multi-layer PCB planar spiral transformer synthesizer with a leakage inductance resonant parasitic absorption mechanism; each gallium nitride high electron mobility transistor carries one amplification module, and the multi-layer PCB planar spiral transformer synthesizer constitutes a broadband collaborative synthesis network. The optimization layer includes: an offline-running improved MOEA / D algorithm; the improved MOEA / D algorithm determines the hardware circuit element parameters of the physical layer through a physical perception-based multi-objective evolutionary algorithm, generates optimized hardware circuit element parameters, and forms a hardware feature fingerprint database. The digital collaborative controller FPGA stores and calls the hardware feature fingerprint library in real time, and dynamically adjusts the control strategy according to the hardware feature fingerprint library.

[0006] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, the improved MOEA / D algorithm includes: Population size for initialization N 100 initial solutions are generated uniformly, each initial solution being a vector of hardware circuit component parameters; combined with the Chebyshev decomposition method, the multi-objective problem is decomposed into 100 scalar optimization subproblems; saturation efficiency η sat and rollback efficiency η 6dB The first and second optimization objectives are set as the first and second optimization objectives, respectively. A constraint term for the group delay flatness of the entire frequency band from 0.6 to 4.9 GHz is introduced as a third constraint objective to ensure digital controllability. The first, second, and third optimization objectives are evaluated simultaneously, and they constitute the optimization objective vector. F(x), A "system controllability" constraint is formed, and a controllability screening mechanism is adopted to finally form a Pareto optimal solution set; each optimal solution in the Pareto optimal solution set corresponds to a set of hardware circuit element parameters that take into account efficiency, flat group delay, and digital controllability. The Pareto optimal solution set includes the Pareto optimal matching hardware circuit element parameters and initial phase offset for each frequency point within the 0.6~4.9GHz full frequency band. θ init Amplitude ratio A init and hardware sensitivity threshold S sense (f) The Pareto optimal solution set forms the hardware feature fingerprint database.

[0007] In this invention, the hardware circuit element parameters are decision variables of the improved MOEA / D algorithm, and there are generally 15 hardware circuit element parameters: transformer line w Coil spacing s Primary turns n _pri Secondary turns n _sec Interlayer coupling distance d _couple Coupling coefficient k Carrier input matching capacitor Cm _main peak1 input matching capacitor Cm _peak1 peak2 input matching capacitor Cm _peak2 Main output parasitic compensation capacitor Cds _comp1 peak1 output parasitic compensation capacitor Cds _comp2 Resonant auxiliary inductor L _resonant Length of main grid offset line L bias_gate_main Peak grid offset line length L bias_gate_peak Drain bias line length L bias_drain Among them, the planar spiral transformer synthesizer (broadband collaborative synthesis network) includes 6 hardware circuit element parameters, the three-channel PA input matching network includes 3 hardware circuit element parameters, the output parasitic absorption / leakage inductance resonant network includes 3 hardware circuit element parameters, and the gate & drain bias network includes 3 hardware circuit element parameters.

[0008] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, the improved MOEA / D algorithm includes a group delay flatness constraint term that is a group delay ripple. Group delay fluctuation This represents the phase sensitivity of the impedance's imaginary part as a function of frequency gradient.

[0009] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, in the improved MOEA / D algorithm, the first optimization objective, the second optimization objective, and the third constrained objective constitute an optimization objective vector. F(x) ; The first optimization objective is to maximize the average saturation efficiency across the entire frequency band. : (1), The second optimization objective is to maximize the 6dB backoff efficiency. : (2), In equations (1) and (2), For sampling frequency points, Number of frequency points; The third constraint objective is to minimize the maximum group delay fluctuation. : (3), in, f This refers to all sampling frequency points within the range of 0.6 to 4.9 GHz. This refers to the transmission phase of the signal at that frequency point; The controllability screening mechanism is as follows: if the parameters of a certain hardware circuit element are as shown in equation (3) Minimize GD ripple Exceeding the preset threshold 2ns This indicates that the circuit has a drastic phase jump at the corresponding frequency point, which is a high-Q resonant point. The algorithm will directly eliminate such hardware circuit element parameters and impose a large penalty value on such hardware circuit element parameters, eliminating them in the population iteration. Only when they fall within the stable convergence region of the ILC algorithm are the corresponding hardware circuit element parameters retained in the Pareto optimal solution set. Where Q is the quality factor of the broadband collaborative synthesis network.

[0010] In this invention, each solution in the final Pareto optimal solution set represents a physical circuit design that achieves an optimal balance between "efficiency" and "digital controllability". In this invention, "efficiency" refers to both saturation efficiency and backoff efficiency.

[0011] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, the hardware circuit element parameters of the physical layer include: the peripheral matching circuit element parameters of the multilayer PCB planar spiral transformer.

[0012] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, the model-assisted iterative learning control ILC unit performs real-time phase and amplitude calibration through the ILC algorithm, which is a hybrid iterative strategy based on design priors; The ILC algorithm includes: Initial Iteration Input u 0 (n) The mapping is derived from the inverse model parameters in the Pareto optimal solution set output by the improved MOEA / D algorithm, when the system is configured to operate at a frequency f k At that time, the controller looks up the frequency in a table.f k Optimal initial phase offset θ init and amplitude ratio A init The and Directly used as the input for the 0th iteration of the ILC algorithm u 0 (n) : (4), The ILC algorithm iteratively corrects the input signal using the update law formula (6). u k (n) To minimize error Output, Satisfying formula (5): (5), In formula (5), This represents the ideal target baseband signal sequence. This represents the actual output signal sequence after being acquired and down-converted by the ADC in the feedback channel; This represents the system's target linear gain constant, used to normalize the output signal to the same order of magnitude as the input signal; Update law formula (6): u k+1 (n)=u k (n)+L(f)·e k (n) (6), in, u k (n) For the first k The input driving signal for the next iteration L(f) The gain matrix is ​​the frequency-selective learning law; L(f) The weight distribution is negatively correlated with the "high Q resonant point" identified during the MOEA / D optimization process, which suppresses iterative divergence at a specific frequency.

[0013] Furthermore, in the ultra-wideband Doherty power amplifier system described in this invention, the ILC algorithm adaptively adjusts based on frequency domain sensitivity. L(f) ; The The structure is as follows: The improved MOEA / D algorithm calculates the frequency domain sensitivity of the entire frequency band in the offline stage. This forms a high-sensitivity frequency band spectrum and constructs... L(f), L(f) according to Ssense (f) Adaptive adjustment; the adaptive adjustment strategy is as follows: at the flat frequency point, set To achieve rapid convergence; at sensitive frequency points, set .

[0014] In this invention, the flat frequency point is: within the 0.6–4.9 GHz operating frequency band, the frequency point with small group delay fluctuations, gentle phase changes, and low impedance sensitivity; that is to say... GD ripple The smaller the value, the smoother the phase change with frequency; this frequency point is called the flat frequency point. Flat frequency point = GD ripple Very small, phase ∂∠S 21 / ∂f is a frequency point with a gradual change. Sensitive frequencies are: high-Q resonant frequencies in the range of 0.6–4.9 GHz, characterized by large group delay fluctuations, drastic phase jumps, steep impedance changes with frequency, and a tendency to cause control algorithm divergence.

[0015] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, the ILC algorithm automatically executes a piecewise linearization strategy based on the real-time output power of the power amplifier module. The piecewise linearization strategy includes: Phase 1: Low Power Phase P out <P sat <-12dB, only the carrier amplifier Main PA works, only the predistortion coefficient of the carrier amplifier Main PA is updated, and nonlinear compensation is performed using a low-order memory polynomial MP; Phase 2: Medium Power Phase -12dB < P out <P sat <6dB corresponds to the 12dB to 6dB power back-off region. The carrier amplifier Main PA remains operational, the first peak amplifier Peak1 PA is on, and the second peak amplifier Peak2 PA is off, at which point the initial Doherty load modulation effect begins to appear. The phase and amplitude coefficients of the carrier amplifier Peak1 PA and the first peak amplifier Peak2 PA are updated synchronously to enhance the nonlinear compensation. Phase 3: High-Power Phase P out ≥P sat -6dB, corresponding Back to the saturation region, the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA are all turned on. At the same time, the phase and amplitude coefficients of the three amplification modules are updated, and the cross term order compensation of the generalized memory polynomial GMP is added to compensate for the strong Doherty load modulation nonlinearity. Among them, Pout P represents the actual output power of the power amplifier module. sat This represents the saturated output power of the power amplifier module.

[0016] Furthermore, in the ultra-wideband Doherty power amplifier system of the present invention, the primary coil leakage inductance of the multilayer PCB planar spiral transformer synthesizer is configured to resonate in series with the parasitic output capacitance Cds of the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA at the center frequency, thereby canceling the parasitic reactance. The multilayer PCB planar spiral transformer synthesizer adopts a multilayer edge-coupled structure on a high-frequency board, with a coupling coefficient k of 0.7~0.8. The secondary coil inductance value Ls of the multilayer PCB planar spiral transformer synthesizer is a hardware circuit element parameter decision variable of the improved MOEA / D algorithm, and Ls balances the saturation efficiency η at the 4.9GHz frequency point. sat rollback efficiency η 6dB Group delay fluctuations.

[0017] On the other hand, the present invention provides a control method for an ultra-wideband Doherty power amplifier system, wherein the ultra-wideband Doherty power amplifier system is any of the ultra-wideband Doherty power amplifier systems described above; comprising the following steps: Step S1: Cooperative Initialization After the system is powered on, it loads the hardware feature fingerprint library to complete parameter parsing and cache initialization.

[0018] Step S2: Wideband Pilot Scan Multiple sets of orthogonal broadband pilot signals covering the entire frequency band from 0.6 to 4.9 GHz are generated to quickly detect the current channel state information and the transient nonlinear characteristics of the power amplifier.

[0019] Step S3: Error Acquisition and Weighting The system collects feedback signals, calculates the error vector, and dynamically adjusts the error weights by calling the hardware sensitivity threshold.

[0020] Step S4: Variable Step Size ILC Iteration The driving signal and predistortion coefficients are updated by using weighted error and frequency-selective learning law, and the high-sensitivity frequency points are automatically switched to conservative step size mode to prevent divergence.

[0021] Step S5: State Locking and Maintenance After the error converges, the calibration parameters are locked and the system enters the working mode. During communication idle time slots, low-frequency background fine-tuning is performed to correct hardware drift errors.

[0022] Furthermore, in the control method of an ultra-wideband Doherty power amplifier system provided by the present invention, the ultra-wideband Doherty power amplifier system is any of the ultra-wideband Doherty power amplifier systems described above. Includes the following steps: Step S1: Cooperative Initialization After the system is powered on, the model-assisted iterative learning control ILC unit of the digital co-controller FPGA actively loads the hardware feature fingerprint library from the non-volatile memory to complete parameter parsing and cache initialization. Step S2: Wideband Pilot Scan Under the instruction of the model-assisted iterative learning control ILC unit, the signal decomposition module generates multiple sets of orthogonal broadband pilot signals covering the entire frequency band from 0.6 to 4.9 GHz. The broadband pilot signals are converted into radio frequency analog pilot signals by three parallel broadband digital-to-analog converters (DACs) and radio frequency upconverters in the radio frequency transmission channel group. The three digital baseband pilot signals are then coupled to the power amplifier module to quickly detect the current channel state information (CSI) and the transient nonlinear characteristics of the three amplifier modules. Step S3: Error Acquisition and Weighting After the power amplifier module amplifies the RF pilot signal, it is combined by a broadband collaborative synthesis network to output a feedback RF signal. The feedback channel ADC acquires the feedback RF signal and converts it into a feedback digital signal. The error vector ek unit acquires the feedback signal at the output of the power amplifier module and calculates the error vector ek between the feedback signal and the ideal signal. k Simultaneously, the model-assisted iterative learning control ILC unit calls the hardware sensitivity threshold loaded in step S1 to dynamically adjust the error weights of the current operating frequency point and generate a weighted error vector. Step S4: Variable Step Size ILC Iteration The model-assisted iterative learning control ILC unit uses weighted error and frequency-selective learning law to calculate the correction amount and update the complex gain coefficients and predistortion polynomial coefficients of the three baseband signals; for high-sensitivity frequency points marked in the hardware feature fingerprint database, the algorithm automatically switches to conservative step size mode to prevent iterative divergence. The model-assisted iterative learning control ILC unit executes steps S2 to S4 sequentially at preset sampling frequencies within the range of 0.6 to 4.9 GHz. After completing the iterative convergence of a single frequency point, it automatically switches to the next frequency point until all frequency points across the entire frequency band are calibrated, and then uniformly enters the working mode of step S5. Step S5: State Locking and Maintenance The model-assisted iterative learning control ILC unit detects the magnitude of the error vector NMSE after iteration in real time. When the magnitude of the error vector NMSE is less than the preset threshold, it is determined that the system has reached the convergence state. The calibration parameters of the current frequency point are immediately stored in the operating coefficient library of the digital co-controller FPGA. At the same time, instructions are sent to the power amplifier module and the broadband co-synthesis network, and the system officially enters the communication signal amplification and transmission working mode. During the communication process, the model-assisted iterative learning control ILC unit utilizes the communication idle time slots to perform low-frequency background fine-tuning of the working status of the power amplifier module and the broadband collaborative synthesis network, correcting errors caused by hardware drift in real time.

[0023] The beneficial effects of this invention are: (1) By overcoming the bandwidth limitation, the planar transformer with parasitic parameter absorption topology and specific coupling coefficient is used to overcome the bandwidth limitation of traditional quarter-wavelength lines and achieve ultra-wideband coverage of 0.6~4.9GHz.

[0024] (2) Breaking the bottleneck of control algorithm divergence: For the first time, the group delay flatness (controllability) of the digital domain is used as the core constraint of physical hardware design. The high Q resonance point is eliminated by the improved MOEA / D algorithm, which fundamentally eliminates the hardware hidden danger of the ILC / DPD algorithm diverging in the band.

[0025] (3) Extremely fast digital convergence performance: A cross-layer collaborative control strategy of "hardware feature fingerprint library + ILC" is proposed. The system does not need to "blindly try and fail" and the initial state is in the quasi-ideal point, which improves the convergence speed of the control algorithm by an order of magnitude. Only 3 to 5 iterations are needed to meet the 3GPP transmission index. Attached Figure Description

[0026] Figure 1 This is a diagram showing the overall hardware architecture of the ultra-wideband Doherty power amplifier system according to Embodiment 1 of the present invention. Figure 2 This is a flowchart of the improved MOEA / D algorithm optimization in Embodiment 1 of the present invention; Figure 3 This is a flowchart of the adaptive calibration process of the ILC algorithm in Embodiment 1 of the present invention; Figure 4 The simulated test curves of saturation efficiency and back-off efficiency in the 0.6~4.9GHz frequency band of Embodiment 1 of the present invention are shown. Detailed Implementation

[0027] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments are now described in detail with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the detailed embodiments, conventional conditions or conditions provided by the manufacturer shall apply.

[0028] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. Specific Implementation Method 1

[0029] The present invention provides an ultrawideband Doherty power amplifier system, comprising: a physical layer, an optimization layer, and a control layer, wherein the control layer comprises: a digital co-controller FPGA, an RF transmit channel group, a power amplification module, and a broadband co-synthesis network; The aforementioned digital co-controller FPGA is a digital predistortion (DPD) closed-loop system comprising a non-volatile memory, an error calculation eK unit, a model-aided iterative learning control (ILC) unit, a signal decomposition module, and a feedback channel ADC. The signal decomposition module receives the update coefficients from the model-aided iterative learning control (ILC) unit, performs predistortion processing on the baseband input signal, and generates three independent digital baseband pilot signals. The aforementioned radio frequency transmission channel group includes: three parallel signal conversion modules that convert the aforementioned digital baseband pilot signals into radio frequency analog pilot signals. Each signal conversion module consists of a wideband digital-to-analog converter (DAC) and a radio frequency upconverter. Each signal conversion module is coupled to the output terminal of the aforementioned digital co-controller FPGA. The aforementioned power amplification module includes three amplification modules: a carrier amplifier Main PA, a first peak amplifier Peak1 PA, and a second peak amplifier Peak2 PA; the drain output terminals of the aforementioned three amplification modules are connected to the input terminals of the aforementioned broadband collaborative synthesis network, the output terminals of the aforementioned broadband collaborative synthesis network are connected to a 50Ω load and a feedback channel ADC, and the output terminals of the feedback channel ADC are connected to an error calculation ek unit; The aforementioned physical layer includes: a three-way amplification architecture constructed from three parallel gallium nitride high electron mobility transistors as the core amplification device, and a multilayer PCB planar spiral transformer synthesizer with a leakage inductance resonant parasitic absorption mechanism; each gallium nitride high electron mobility transistor carries one amplification module, and the multilayer PCB planar spiral transformer synthesizer constitutes a broadband collaborative synthesis network. The aforementioned optimization layer includes: an offline-running improved MOEA / D algorithm; the improved MOEA / D algorithm uses a physical perception-based multi-objective evolutionary algorithm to determine the hardware circuit element parameters of the aforementioned physical layer, generate optimized hardware circuit element parameters, and form a hardware feature fingerprint database. The aforementioned digital co-controller FPGA stores and calls up the hardware feature fingerprint library in real time, and dynamically adjusts the control strategy based on the hardware feature fingerprint library.

[0030] In some embodiments, the gallium nitride high electron mobility transistor described above is a Wolfspeed CGH40010F type gallium nitride high electron mobility transistor.

[0031] In some implementations, the improved MOEA / D algorithm described above includes: Population size for initialization N 100 initial solutions are generated uniformly, each initial solution being a vector of hardware circuit component parameters; combined with the Chebyshev decomposition method, the multi-objective problem is decomposed into 100 scalar optimization subproblems; saturation efficiency η sat and backoff efficiency η 6dB The first and second optimization objectives are set as the first and second optimization objectives, respectively. A constraint term for the group delay flatness of the entire frequency band from 0.6 to 4.9 GHz is introduced as a third constraint objective to ensure digital controllability. The first, second, and third optimization objectives are evaluated simultaneously, and they constitute the optimization objective vector. F(x), The "system controllability" constraint is formed, and the controllability screening mechanism is adopted to finally form the Pareto optimal solution set; each optimal solution in the Pareto optimal solution set corresponds to a set of hardware circuit element parameters that take into account efficiency, flat group delay, and digital controllability. The Pareto optimal solution set mentioned above includes the Pareto optimal matching hardware circuit element parameters and initial phase offset for each frequency point within the entire frequency band from 0.6 to 4.9 GHz. θ init Amplitude ratio A init and hardware sensitivity threshold S sense (f) The above Pareto optimal solution set forms the above hardware feature fingerprint database.

[0032] In some implementations, in the improved MOEA / D algorithm described above, the group delay flatness constraint term is the group delay ripple. GD ripple Group delay fluctuation GDripple This represents the phase sensitivity of the impedance's imaginary part as a function of frequency gradient.

[0033] In some implementations, in the improved MOEA / D algorithm described above, the first optimization objective, the second optimization objective, and the third constrained objective constitute an optimization objective vector. F(x) ; The first optimization objective mentioned above is to maximize the average saturation efficiency across the entire frequency band. : (1), The second optimization objective mentioned above is to maximize the 6dB backoff efficiency. : (2), In equations (1) and (2), For sampling frequency points, Number of frequency points; The third constraint objective mentioned above is to minimize the maximum group delay variability. GD ripple : (3), in, f This refers to all sampling frequency points within the range of 0.6 to 4.9 GHz. This refers to the transmission phase of the signal at that frequency point; The above controllability screening mechanism is as follows: if the parameters of a certain hardware circuit element are as shown in equation (3) Minimize GD ripple Exceeding the preset threshold 2ns This indicates that the circuit has a drastic phase jump at the corresponding frequency point, which is a high-Q resonant point. The algorithm will directly eliminate such hardware circuit element parameters and impose a large penalty value on such hardware circuit element parameters, eliminating them in the population iteration. Only when they fall within the stable convergence region of the ILC algorithm are the corresponding hardware circuit element parameters retained in the Pareto optimal solution set. Where Q is the quality factor of the aforementioned broadband collaborative synthesis network.

[0034] In some implementations, each solution in the final Pareto optimal solution set represents a physical circuit design that achieves an optimal balance between "efficiency" and "digital controllability".

[0035] In some implementations, at the 4.9 GHz frequency, MOEA / D automatically selects a solution with a secondary coil inductance of Ls≈1.55nH (instead of the theoretically highest efficiency of 1.45nH). Although this sacrifices 0.5% efficiency, it reduces the group delay ripple at this frequency by 40%, ensuring the stability of subsequent control.

[0036] In some implementations, the hardware circuit element parameters of the physical layer include: peripheral matching circuit element parameters of the multilayer PCB planar spiral transformer synthesizer.

[0037] In some implementations, the broadband cooperative synthesis network is a parasitic parameter absorption topology, which is based on the parasitic absorption mechanism of leakage inductance resonance.

[0038] In some implementations, the parasitic absorption mechanism based on leakage inductance resonance is as follows: utilizing the leakage inductance of the primary coil of a multilayer PCB planar spiral transformer synthesizer. With parasitic output capacitance Construct a series resonant circuit with a low Q value; set the resonant frequency. Located in the center of the operating frequency band, precisely controlling the spacing gap and line width of the PCB coils reduces leakage inductance. L leak Adjust to the target value; achieve this through formula (7). C ds The load impedance seen by gallium nitride high electron mobility transistors is mainly real when absorbed into the matching network, thus extending the bandwidth. (7), in, ω 0 =2πf 0 , ω 0 ω is the angular frequency.

[0039] In some implementations, the resonant frequency f 0 It is 2.8GHz.

[0040] In some implementations, the primary coil leakage inductance of the multilayer PCB planar spiral transformer synthesizer is configured to resonate in series with the parasitic output capacitance Cds of the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA at the center frequency, thereby canceling the parasitic reactance.

[0041] In some implementations, the model-assisted iterative learning control ILC unit described above performs real-time phase and amplitude calibration through the ILC algorithm, which is a hybrid iterative strategy based on design priors. The above ILC algorithm includes: Initial Iteration Input u 0 (n) The mapping is derived from the inverse model parameters in the Pareto optimal solution set output by the improved MOEA / D algorithm, when the system is configured to operate at a frequency f k At that time, the controller looks up the frequency in a table. f k Optimal initial phase offset θ init and amplitude ratio A init The above and Directly used as the input for the 0th iteration of the ILC algorithm u 0 (n) : (4), The ILC algorithm iteratively corrects the input signal using the update law formula (6). u k (n) To minimize error Output, Satisfying formula (5): (5), In formula (5), This represents the ideal target baseband signal sequence. This represents the actual output signal sequence after being acquired and down-converted by the ADC in the feedback channel; This represents the system's target linear gain constant, used to normalize the output signal to the same order of magnitude as the input signal; Update law formula (6): u k+1 (n)=u k (n)+L(f)·e k (n) (6), in, u k (n) For the first k The input driving signal for the next iteration L(f) The gain matrix is ​​the frequency-selective learning law; the above L(f) The weight distribution is negatively correlated with the "high-Q resonant point" identified during the MOEA / D optimization process, which suppresses iterative divergence at a specific frequency; In some implementations, the above-described ILC algorithm adaptively adjusts based on frequency domain sensitivity. L(f) ; The above The structure is as follows: The improved MOEA / D algorithm calculates the frequency domain sensitivity of the entire frequency band in the offline stage. This forms a high-sensitivity frequency band spectrum, and Construct L(f), L(f) according to S sense (f) Adaptive adjustment; the above adaptive adjustment strategy is: at flat frequency points, set To achieve rapid convergence; at sensitive frequency points, set .

[0042] In some implementations, the above-mentioned ILC algorithm automatically executes a piecewise linearization strategy based on the real-time output power of the power amplifier module; The above piecewise linearization strategies include: Phase 1: Low Power Phase P out <P sat <-12dB, only the carrier amplifier Main PA works, only the predistortion coefficient of the carrier amplifier Main PA is updated, and nonlinear compensation is performed using a low-order memory polynomial MP; Phase 2: Medium Power Phase -12dB < P out <P sat <6dB corresponds to the 12dB to 6dB power back-off region. The carrier amplifier Main PA remains operational, the first peak amplifier Peak1 PA is on, and the second peak amplifier Peak2 PA is off, at which point the initial Doherty load modulation effect begins to appear. The phase and amplitude coefficients of the carrier amplifier Peak1 PA and the first peak amplifier Peak2 PA are updated synchronously to enhance the nonlinear compensation. Phase 3: High-Power Phase P out ≥P sat -6dB, corresponding Back to the saturation region, the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA are all turned on. At the same time, the phase and amplitude coefficients of the three amplification modules are updated, and the cross term order compensation of the generalized memory polynomial GMP is added to compensate for the strong Doherty load modulation nonlinearity. Among them, P out P represents the actual output power of the power amplifier module. sat This represents the saturated output power of the power amplifier module.

[0043] In some embodiments, the primary coil leakage inductance of the multilayer PCB planar spiral transformer synthesizer is configured to resonate in series with the parasitic output capacitance Cds of the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA at the center frequency, thereby canceling the parasitic reactance. The aforementioned multilayer PCB planar spiral transformer synthesizer employs a multilayer edge-coupled structure on a high-frequency board, with a coupling coefficient k of 0.7~0.8. The secondary coil inductance value Ls of the multilayer PCB planar spiral transformer synthesizer is a hardware circuit element parameter decision variable for the improved MOEA / D algorithm, and Ls balances the saturation efficiency η at the 4.9GHz frequency point. sat rollback efficiency η 6dB Group delay fluctuations.

[0044] In some implementations, the turns ratio and coupling coefficient of the transformer in a multilayer PCB planar spiral transformer synthesizer This determines the load trajectories of the Main PA, Peak1 PA, and Peak2 PA. During the low-power phase, only the Main PA operates. The transformer secondary presents high impedance, which is reflected in the primary... The first stage provides high load impedance for the Main PA, improving low-power efficiency. During the medium-power stage, the Main PA and Peak1 PA operate, injecting current through the transformer's magnetic coupling to modulate the decrease in the Main PA's load impedance. During the high-power stage, the Main PA, Peak1 PA, and Peak2 PA operate, all three supplying power to the load, minimizing the Main PA's load impedance. , output maximum power.

[0045] In some implementations, the coupling coefficient The value is set to 0.7~0.8. By utilizing the phase shift effect caused by leakage inductance, the phase alignment of the three signals at the junction point is optimized, and reactive power loss is reduced.

[0046] In some embodiments, the aforementioned multilayer PCB planar spiral transformer synthesizer employs a multilayer edge-coupled structure on a Rogers RO4350B high-frequency board. Specific Implementation Method Two: The present invention discloses a control method for an ultra-wideband Doherty power amplifier system, wherein the ultra-wideband Doherty power amplifier system is the ultra-wideband Doherty power amplifier system in Specific Embodiment 1; the method includes the following steps: Step S1: Cooperative Initialization After the system is powered on, it loads the hardware feature fingerprint library to complete parameter parsing and cache initialization.

[0048] Step S2: Wideband Pilot Scan Multiple sets of orthogonal broadband pilot signals covering the entire frequency band from 0.6 to 4.9 GHz are generated to quickly detect the current channel state information and the transient nonlinear characteristics of the power amplifier.

[0049] Step S3: Error Acquisition and Weighting The system collects feedback signals, calculates the error vector, and dynamically adjusts the error weights by calling the hardware sensitivity threshold.

[0050] Step S4: Variable Step Size ILC Iteration The driving signal and predistortion coefficients are updated by using weighted error and frequency-selective learning law, and the high-sensitivity frequency points are automatically switched to conservative step size mode to prevent divergence.

[0051] Step S5: State Locking and Maintenance After the error converges, the calibration parameters are locked and the system enters the working mode. During communication idle time slots, low-frequency background fine-tuning is performed to correct hardware drift errors.

[0052] In other embodiments, the present invention provides a control method for an ultra-wideband Doherty power amplifier system, wherein the ultra-wideband Doherty power amplifier system is the ultra-wideband Doherty power amplifier system in specific embodiment one. Includes the following steps: Step S1: Cooperative Initialization After the system is powered on, the model-assisted iterative learning control ILC unit of the digital co-controller FPGA actively loads the hardware feature fingerprint library from the non-volatile memory to complete parameter parsing and cache initialization. Step S2: Wideband Pilot Scan Under the instruction of the model-assisted iterative learning control ILC unit, the signal decomposition module generates multiple sets of orthogonal broadband pilot signals covering the entire frequency band from 0.6 to 4.9 GHz. The broadband pilot signals are converted into radio frequency analog pilot signals by three parallel broadband digital-to-analog converters (DACs) and radio frequency upconverters in the radio frequency transmission channel group. These signals are then coupled to the power amplifier module to quickly detect the current channel state information (CSI) and the transient nonlinear characteristics of the three amplifier modules. Step S3: Error Acquisition and Weighting After the power amplifier module amplifies the RF pilot signal, it is combined by a broadband collaborative synthesis network to output a feedback RF signal. The feedback channel ADC acquires the feedback RF signal and converts it into a feedback digital signal. The error vector ek unit acquires the feedback signal at the output of the power amplifier module and calculates the error vector ek between the feedback signal and the ideal signal. kSimultaneously, the model-assisted iterative learning control ILC unit calls the hardware sensitivity threshold loaded in step S1 to dynamically adjust the error weights of the current operating frequency point and generate a weighted error vector. Step S4: Variable Step Size ILC Iteration The model-assisted iterative learning control ILC unit uses weighted error and frequency-selective learning law to calculate the correction amount and update the complex gain coefficients and predistortion polynomial coefficients of the three baseband signals; for high-sensitivity frequency points marked in the hardware feature fingerprint database, the algorithm automatically switches to conservative step size mode to prevent iterative divergence. The model-assisted iterative learning control ILC unit executes steps S2 to S4 sequentially at preset sampling frequencies within the range of 0.6 to 4.9 GHz. After completing the iterative convergence of a single frequency point, it automatically switches to the next frequency point until all frequency points across the entire frequency band are calibrated, and then uniformly enters the working mode of step S5. Step S5: State Locking and Maintenance The model-assisted iterative learning control ILC unit detects the magnitude of the error vector NMSE after iteration in real time. When the magnitude of the error vector NMSE is less than the preset threshold, it is determined that the system has reached the convergence state. The calibration parameters of the current frequency point are immediately stored in the operating coefficient library of the digital co-controller FPGA. At the same time, instructions are sent to the power amplifier module and the broadband co-synthesis network, and the system officially enters the communication signal amplification and transmission working mode. During the communication process, the model-assisted iterative learning control ILC unit utilizes the communication idle time slots to perform low-frequency background fine-tuning of the working status of the power amplifier module and the broadband collaborative synthesis network, correcting errors caused by hardware drift in real time.

[0053] The present invention will be further described in detail below with reference to specific embodiments.

[0054] Example 1: This invention provides an ultra-wideband Doherty power amplifier system, comprising: a physical layer, an optimization layer, and a control layer. The control layer includes: a digital co-controller FPGA, an RF transmit channel group, a power amplification module, and a broadband co-synthesis network, such as... Figure 1 As shown.

[0055] The digital co-controller FPGA is a digital predistortion (DPD) closed-loop system that includes non-volatile memory, error calculation eK unit, model-aided iterative learning control (ILC) unit, signal decomposition module, and feedback channel ADC. The signal decomposition module receives the update coefficients from the model-aided iterative learning control (ILC) unit, performs predistortion processing on the baseband input signal, and generates three independent digital baseband pilot signals.

[0056] The radio frequency transmission channel group includes three parallel signal conversion modules that convert digital baseband pilot signals into radio frequency analog pilot signals. Each signal conversion module consists of a wideband digital-to-analog converter (DAC) and a radio frequency upconverter. Each signal conversion module is coupled to the output of the digital co-controller FPGA.

[0057] The power amplifier module includes three amplifier modules: a carrier amplifier Main PA, a first peak amplifier Peak1 PA, and a second peak amplifier Peak2 PA. The drain output of the three amplifier modules is connected to the input of the broadband collaborative synthesis network. The output of the broadband collaborative synthesis network is connected to a 50Ω load and a feedback channel ADC. The output of the feedback channel ADC is connected to the error calculation eK unit.

[0058] The physical layer includes: a three-way amplification architecture constructed from three parallel gallium nitride high electron mobility transistors as the core amplification device, and a multi-layer PCB planar spiral transformer synthesizer with a leakage inductance resonant parasitic absorption mechanism; each gallium nitride high electron mobility transistor carries one amplification module, and the multi-layer PCB planar spiral transformer synthesizer constitutes a broadband collaborative synthesis network.

[0059] The optimization layer includes: an offline-running improved MOEA / D algorithm; the improved MOEA / D algorithm determines the hardware circuit element parameters of the physical layer through a physical perception-based multi-objective evolutionary algorithm, generates optimized hardware circuit element parameters, and forms a hardware feature fingerprint database.

[0060] The digital collaborative controller FPGA stores and calls the hardware feature fingerprint library in real time, and dynamically adjusts the control strategy according to the hardware feature fingerprint library.

[0061] The device selection and characteristics of the ultrawideband Doherty power amplifier system in this embodiment 1 are as follows: The three gallium nitride high electron mobility transistors selected Wolfspeed's CGH40010F gallium nitride (GaN) HEMT high electron mobility transistors are used as the core amplification devices; this device is an unmatched transistor, which provides great freedom in broadband matching design.

[0062] The key parameters of the CGH40010F gallium nitride (GaN) HEMT high electron mobility transistor are: drain supply voltage ( ): 28V, providing high voltage swing; saturated output power ( Typical power: 13W (approximately 41dBm); The theoretical maximum power of the three-channel amplifier module (Main PA + Peak1 PA + Peak2 PA) can reach 13×3≈39W (approximately 46dBm), meeting the coverage requirements of micro base stations; Frequency range: DC-6GHz, fully covering the 0.6~4.9GHz target frequency band required by this invention; Efficiency: Typical efficiency at saturation point is 65%, laying the foundation for high-efficiency design; Package: 440166 flange package, with low thermal resistance. R θJC = 8.0 ℃ / W This is beneficial for heat dissipation under high power density.

[0063] In this embodiment 1, by introducing non-uniformly distributed harmonic controlled lines into the output matching network, dynamic notch filtering is applied to the second and third harmonic impedances of the CGH40010F gallium nitride (GaN) HEMT high electron mobility transistor, thereby increasing the peak output capability of the single transistor by 0.5 dB to 0.8 dB beyond the theoretical typical value. Simultaneously, utilizing the 0.1-degree-level phase alignment accuracy in the digital domain, the vector synthesis efficiency of the broadband cooperative synthesis network is increased to over 92%, thus compensating for the insertion loss of the ultra-wideband circuit and ensuring full-band output power. .

[0064] This embodiment 1 presents a planar transformer synthesizer based on parasitic parameter absorption carrying a broadband collaborative synthesis network, breaking through the traditional... Line bandwidth limitations.

[0065] Topology: The broadband cooperative synthesis network is built on Rogers RO4350B high-frequency board (20mil thick, dielectric constant 3.66, loss tangent 0.0037) and adopts an edge-coupled planar spiral transformer structure. The input (primary side) is divided into three paths, which are connected to the drains of Main PA, Peak1 PA and Peak2 PA respectively. The output (secondary side) is connected to a 50-ohm load.

[0066] The parasitic absorption mechanism based on leakage inductance resonance is as follows: utilizing the leakage inductance of the primary coil of the multilayer PCB planar spiral transformer synthesizer. With parasitic output capacitance Construct a series resonant circuit with a low Q value; set the resonant frequency. Located in the center of the operating frequency band, precisely controlling the spacing gap and line width of the PCB coils reduces leakage inductance. L leak Adjust to the target value; achieve this through formula (7). C dsThe load impedance seen by gallium nitride high electron mobility transistors is mainly real when absorbed into the matching network, thus extending the bandwidth. (7), in, ω 0 =2πf 0 , ω 0 ω is the angular frequency.

[0067] resonant frequency f 0 It is 2.8GHz.

[0068] The primary coil leakage inductance of the multilayer PCB planar spiral transformer synthesizer is set to resonate in series with the parasitic output capacitance Cds of the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA at the center frequency, thus canceling the parasitic reactance.

[0069] The turns ratio and coupling coefficient of the transformer in a multilayer PCB planar spiral transformer synthesizer This determines the load trajectories of MainPA, Peak1PA, and Peak2PA. During the low-power phase, only MainPA operates. The transformer secondary presents high impedance, which is reflected in the primary... The first stage provides high load impedance for the Main PA, improving low-power efficiency. During the medium-power stage, the Main PA and Peak1 PA operate, injecting current through the transformer's magnetic coupling to modulate the decrease in the Main PA's load impedance. During the high-power stage, the Main PA, Peak1 PA, and Peak2 PA operate, all three supplying power to the load, minimizing the Main PA's load impedance. , output maximum power.

[0070] Coupling coefficient The value is set to 0.7~0.8. By utilizing the phase shift effect caused by leakage inductance, the phase alignment of the three signals at the junction point is optimized, and reactive power loss is reduced.

[0071] The improved MOEA / D algorithm's process of synthesizing and optimizing hardware circuit component parameters, such as... Figure 2 As shown. After determining the circuit topology, determining the specific component parameters (such as transformer size and matching capacitor value) is a high-dimensional multi-objective optimization problem. This embodiment 1 uses an improved MOEA / D algorithm for offline design. The improved MOEA / D algorithm includes: initializing the population size. N100 initial solutions are generated uniformly, each initial solution being a vector of hardware circuit component parameters; combined with the Chebyshev decomposition method, the multi-objective problem is decomposed into 100 scalar optimization subproblems; the saturation efficiency η is... sat and backoff efficiency η 6dB The first and second optimization objectives are set as objectives, respectively. A third constraint, the group delay flatness across the entire 0.6–4.9 GHz frequency band, is introduced as a constraint to ensure digital controllability. The first, second, and third optimization objectives are evaluated simultaneously, and a controllability screening mechanism is used to ultimately form the Pareto optimal solution set. Each optimal solution in the Pareto optimal solution set corresponds to a set of hardware circuit component parameters that balance efficiency, group delay flatness, and digital controllability. The Pareto optimal solution set includes the Pareto optimal matching hardware circuit component parameters and the initial phase offset for each frequency point within the 0.6–4.9 GHz frequency band. θ init Amplitude ratio A init and hardware sensitivity threshold S sense (f) The Pareto optimal solution set forms a hardware feature fingerprint database. In the improved MOEA / D algorithm, the group delay flatness constraint term is the group delay ripple. GD ripple Group delay fluctuation GD ripple This represents the phase sensitivity of the impedance's imaginary part as a function of frequency gradient.

[0072] The optimization process of the improved MOEA / D algorithm is as follows: (1) Start design → Start the entire optimization process: Initialize the population & decompose subproblems: Initialize the population size N 100 initial solutions are generated uniformly, each initial solution being a vector of hardware circuit component parameters; using the Chebyshev decomposition method, the multi-objective problem is decomposed into 100 scalar optimization subproblems; decision variables include transformer linewidth. Coil spacing Number of turns Matching capacitors for each circuit Offset line length There are a total of 15 variables.

[0073] (2) Evolutionary Iteration Loop - Generation k, this is the core optimization loop, which will be executed repeatedly until the termination condition is met: Genetic operations: crossover and mutation, the core operations of evolutionary algorithms, are performed on the current population to generate new candidate solutions and maintain population diversity; ADS / Matlab co-simulation: Input the new candidate solution into ADS (RF / microwave circuit simulation) and Matlab (algorithm / control simulation) for co-simulation to obtain performance indicators; Controllability check: Check if the group delay is less than the set threshold, and verify the controllability of the system; Yes: The solution satisfies the constraints, and the neighborhood solutions and EP population are updated; No: Discard the solution, or reduce its fitness through the penalty function to avoid it being selected in subsequent iterations; Termination judgment: Check if the maximum number of iterations has been reached; No: Return to "genetic operation" and start the next round of evolution; Yes: Exit the loop, enter the result extraction stage, and classify it as the Pareto optimal solution.

[0074] Constructing an optimization objective vector using the objective function and the third constraint objective This creates a constraint on "system controllability"; The primary optimization objective is to maximize the average saturation efficiency across the entire frequency band. : (1), The second optimization objective is to maximize the 6dB backoff efficiency: (2), In equations (1) and (2), For sampling frequency points, Number of frequency points; The third constraint objective is to minimize the maximum group delay fluctuation. GD ripple : (3), in, f This refers to all sampling frequency points within the range of 0.6 to 4.9 GHz. This refers to the transmission phase of the signal at that frequency point; The controllability screening mechanism is as follows: if the parameters of a certain hardware circuit element are as shown in equation (3) Minimize GD ripple Exceeded the preset threshold 2 ns This indicates that the circuit has a drastic phase jump at the corresponding frequency point, which is a high-Q resonant point. The algorithm will directly eliminate such hardware circuit element parameters and impose a large penalty value on such hardware circuit element parameters, eliminating them in the population iteration. Only when they fall within the stable convergence region of the ILC algorithm are the corresponding hardware circuit element parameters retained in the Pareto optimal solution set. Where Q is the quality factor of the broadband collaborative synthesis network.

[0075] In the optimization process and controllability screening, the algorithm not only evaluates efficiency, but also calculates the S-parameter phase response of each individual.

[0076] While such circuits with high Q resonant points may be extremely efficient at a certain point, they are very unfriendly to the digital DPD algorithm and are prone to divergence. The algorithm directly eliminates such solutions and imposes a large penalty value on them, causing them to be eliminated in the population iteration. Each solution in the final Pareto optimal solution set represents a physical circuit design that achieves the best balance between "efficiency" and "digital controllability".

[0077] (3) Result output stage: Extract Pareto optimal solution: Select non-dominated solutions (Pareto front) under multiple objectives from the final population. These solutions achieve the best trade-off between various optimization objectives (such as performance, power consumption, and latency). Generate hardware fingerprint library: Organize the Pareto optimal solution set into hardware fingerprint library for subsequent ILC (iterative learning control) initialization. End, complete the entire design process.

[0078] like Figure 3 As shown, the adaptive calibration process of the ILC algorithm is as follows: When the ultra-wideband Doherty power amplifier system is running, the I / Q signals first pass through the signal decomposition module. Based on the turn-on threshold of the three amplification modules (determined by the hardware design), the signal amplitude is reduced. Mapped to three-way drive signal x main 、x peak1 、x peak2 The digital co-controller FPGA executes the following closed-loop control process: (1) Cooperative initialization Start calibration → Initiate calibration process.

[0079] Initialization parameters: Set the initial iteration drive signal u 0 and iterative learning law L(f) This prepares for subsequent iterations; initial iteration input u 0 (n) The mapping is derived from the inverse model parameters in the Pareto optimal solution set output by the improved MOEA / D algorithm, when the system is configured to operate at a frequency f k At that time, the controller looks up the frequency in a table. f k Optimal initial phase offset θ init and amplitude ratio A init The and Directly used as the input for the 0th iteration of the ILC algorithm u 0 (n) : (4), Frequency-level calibration cycle for each frequency point f k Real-time iteration of the ILC algorithm: setting the current frequency point f k Specify the target frequency point to be calibrated; the FPGA sends the drive signal. u k The FPGA sends the current iteration's drive control signal to the hardware system; the ILC algorithm iteratively corrects the input signal using the update law formula (6). u k (n) To minimize error Output, Satisfying formula (5): (5), In formula (5), y ideal (n) This represents the ideal target baseband signal sequence. y maezn (n) This represents the actual output signal sequence after being acquired and down-converted by the ADC in the feedback channel; This represents the system's target linear gain constant, used to normalize the output signal to the same order of magnitude as the input signal; in this embodiment 1... y maezn (n) It can also be used y k express 。

[0080] Error judgment: Yes (Error < threshold): The current frequency point has been calibrated to the required standard. Save the calibration coefficient for this frequency point.

[0081] No (Error ≥ Threshold): Return to the "FPGA Send Drive Signal" step and update the drive signal. u k+1 Apply the update law formula (6) to continue iterative optimization; u k+1 (n)=u k (n)+L(f)·e k (n) (6), in, u k (n) For the first k The input driving signal for the next iteration L(f) This is the gain matrix for the frequency-selective learning law; L(f) Construction: The improved MOEA / D algorithm calculates the frequency domain sensitivity of the entire frequency band in the offline stage, forms a high-sensitivity frequency band spectrum, and constructs... L(f), L(f) according to S sense (f) Adaptive adjustment; the adaptive adjustment strategy is as follows: at the flat frequency point (low sensitivity), set... L(f)≈ A step size of 0.8 is used to achieve fast convergence; at sensitive frequencies (high sensitivity, such as band edges), a specific step size is set. This is equivalent to walking carefully along the edge of a cliff to prevent the system state from jumping out of the stability region due to excessive step size. This strategy effectively suppresses iterative divergence at high Q-value frequencies, ensuring robustness across the entire frequency band.

[0082] The ILC algorithm automatically executes a piecewise linearization strategy based on the real-time output power of the power amplifier module. Piecewise linearization strategies include: Phase 1: Low Power Phase P out <P sat <-12dB, only the carrier amplifier Main PA works, only the predistortion coefficient of the carrier amplifier Main PA is updated, and nonlinear compensation is performed using a low-order memory polynomial MP; Phase 2: Medium Power Phase -12dB < P out <P sat <6dB corresponds to the 12dB to 6dB power back-off region. The carrier amplifier Main PA remains operational, the first peak amplifier Peak1 PA is on, and the second peak amplifier Peak2 PA is off, at which point the initial Doherty load modulation effect begins to appear. The phase and amplitude coefficients of the carrier amplifier Peak1 PA and the first peak amplifier Peak2 PA are updated synchronously to enhance the nonlinear compensation. Phase 3: High-Power Phase P out ≥P sat -6dB, corresponding Back to the saturation region, the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA are all turned on. At the same time, the phase and amplitude coefficients of the three amplification modules are updated, and the cross term order compensation of the generalized memory polynomial GMP is added to compensate for the strong Doherty load modulation nonlinearity. Where Pout is the actual output power of the power amplifier module, and Psat is the saturated output power of the power amplifier module. Experimental verification and performance data. Full-band traversal and completion, check if all frequency points in the full-band have been calibrated; No: switch to the next frequency point and repeat the above frequency point-level calibration cycle; Yes: all frequency points are calibrated, end the calibration process, and the system enters normal working mode.

[0083] This embodiment 1 uses Rogers RO4350B board material and Wolfspeed CGH40010F device for simulation testing, and performs detailed static performance and dynamic signal tests. The results are shown in Table 1 and... Figure 4 As shown. (1) Static performance test bandwidth: return loss in the range of 0.6GHz to 4.9GHz. All values ​​are better than -10dB, verifying the broadband matching capability of the parasitic absorption network; Power and efficiency: At the 2.6GHz frequency point, the saturated output power reaches 46.8dBm and the saturation efficiency is 68%; At the 6dB backoff point, the efficiency is maintained at around 52%, which is significantly better than the traditional Class B amplifier (about 25%) and dual-channel DPA (about 40%); In the entire frequency band (0.6~4.9GHz), the 6dB backoff efficiency remains above 45%. (2) Dynamic signal testing was conducted using 5G NR FR1 test signal (100MHz bandwidth, PAPR=8.5dB, 256-QAM): Linearity: When DPD was not enabled, ACLR was approximately -28dBc; after enabling coordinated ILC control, ACLR rapidly improved to -52dBc, meeting the 3GPP base station transmission index requirements; Convergence speed: Compared to the traditional full-band scanning ILC algorithm which requires approximately 30 to 50 iterations to lock, the method in this embodiment 1 can usually converge NMSE (normalized mean square error) to below -40dB within 3 to 5 iterations, improving the convergence speed by an order of magnitude.

[0084] Table 1 Performance indicators of the ultrawideband Doherty power amplifier system in Example 1

[0085] This invention has been described through the specific embodiments described above. Those skilled in the art should understand that various modifications and equivalent substitutions can be made to this invention without departing from its scope. Parts not described in detail in this specification are well-known to those skilled in the art. Furthermore, various modifications can be made to this invention for specific situations or circumstances without departing from the scope of this application. Therefore, this invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims of this invention.

Claims

1. An ultrawideband Doherty power amplifier system, characterized in that, include: The system comprises a physical layer, an optimization layer, and a control layer, wherein the control layer includes: a digital co-controller FPGA, an RF transmit channel group, a power amplifier module, and a broadband co-synthesis network; The digital co-controller FPGA is a digital predistortion (DPD) closed-loop system including non-volatile memory, error calculation eK unit, model-aided iterative learning control (ILC) unit, signal decomposition module, and feedback channel ADC; the signal decomposition module receives the update coefficients from the model-aided iterative learning control (ILC) unit, performs predistortion processing on the baseband input signal, and generates three independent digital baseband pilot signals. The radio frequency transmission channel group includes: three parallel signal conversion modules that convert the digital baseband pilot signal into radio frequency analog pilot signal. Each signal conversion module consists of a wideband digital-to-analog converter (DAC) and a radio frequency upconverter. Each signal conversion module is coupled to the output terminal of the digital co-controller FPGA. The power amplification module includes three amplification modules: a carrier amplifier Main PA, a first peak amplifier Peak1 PA, and a second peak amplifier Peak2 PA; the drain output of the three amplification modules is connected to the input of the broadband collaborative synthesis network, the output of the broadband collaborative synthesis network is connected to a 50Ω load and a feedback channel ADC, and the output of the feedback channel ADC is connected to an error calculation eK unit. The physical layer includes: a three-way amplification architecture constructed from three parallel gallium nitride high electron mobility transistors as the core amplification device, and a multi-layer PCB planar spiral transformer synthesizer with a leakage inductance resonant parasitic absorption mechanism; each gallium nitride high electron mobility transistor carries one amplification module, and the multi-layer PCB planar spiral transformer synthesizer constitutes a broadband collaborative synthesis network. The optimization layer includes: an offline-running improved MOEA / D algorithm; the improved MOEA / D algorithm determines the hardware circuit element parameters of the physical layer through a physical perception-based multi-objective evolutionary algorithm, generates optimized hardware circuit element parameters, and forms a hardware feature fingerprint database. The digital collaborative controller FPGA stores and calls the hardware feature fingerprint library in real time, and dynamically adjusts the control strategy according to the hardware feature fingerprint library.

2. The ultra-wideband Doherty power amplifier system according to claim 1, characterized in that, The improved MOEA / D algorithm includes: Population size for initialization N 100 initial solutions are generated uniformly, each initial solution being a vector of hardware circuit component parameters; combined with the Chebyshev decomposition method, the multi-objective problem is decomposed into 100 scalar optimization subproblems; saturation efficiency η sat and rollback efficiency η 6dB The first and second optimization objectives are set as the first and second optimization objectives, respectively. A constraint term for the group delay flatness of the entire frequency band from 0.6 to 4.9 GHz is introduced as a third constraint objective to ensure digital controllability. The first, second, and third optimization objectives are evaluated simultaneously, and they constitute the optimization objective vector. F(x), A "system controllability" constraint is formed, and a controllability screening mechanism is adopted to finally form a Pareto optimal solution set; each optimal solution in the Pareto optimal solution set corresponds to a set of hardware circuit element parameters that take into account efficiency, flat group delay, and digital controllability. The Pareto optimal solution set includes the Pareto optimal matching hardware circuit element parameters and initial phase offset for each frequency point within the 0.6~4.9GHz full frequency band. θ init Amplitude ratio A init and hardware sensitivity threshold S sense (f) The Pareto optimal solution set forms the hardware feature fingerprint database.

3. The ultra-wideband Doherty power amplifier system according to claim 2, characterized in that, In the improved MOEA / D algorithm, the group delay flatness constraint term is the group delay ripple. GD ripple Group delay fluctuation GD ripple This represents the phase sensitivity of the impedance's imaginary part as a function of frequency gradient.

4. The ultra-wideband Doherty power amplifier system according to claim 3, characterized in that, In the improved MOEA / D algorithm; The first optimization objective is to maximize the average saturation efficiency across the entire frequency band. : （1）， The second optimization objective is to maximize the 6dB backoff efficiency. : （2）， In equations (1) and (2), represents the sampling frequency. Number of frequency points; The third constraint objective is to minimize the maximum group delay fluctuation. GD ripple : （3）， in, f This refers to all sampling frequency points within the range of 0.6 to 4.9 GHz. This refers to the transmission phase of the signal at that frequency point; The controllability screening mechanism is as follows: if the parameters of a certain hardware circuit element are as shown in equation (3) Minimize GD ripple Exceeding the preset threshold 2ns This indicates that the circuit has a drastic phase jump at the corresponding frequency point, which is a high-Q resonant point. The algorithm will directly eliminate such hardware circuit element parameters and impose a large penalty value on such hardware circuit element parameters, eliminating them in the population iteration. Only when they fall within the stable convergence region of the ILC algorithm are the corresponding hardware circuit element parameters retained in the Pareto optimal solution set. Where Q is the quality factor of the broadband collaborative synthesis network.

5. The ultra-wideband Doherty power amplifier system according to claim 4, characterized in that, The hardware circuit component parameters of the physical layer include: the peripheral matching circuit component parameters of the multilayer PCB planar spiral transformer synthesizer.

6. The ultra-wideband Doherty power amplifier system according to claim 5, characterized in that, The model-assisted iterative learning control ILC unit performs real-time phase and amplitude calibration through the ILC algorithm, which is a hybrid iterative strategy based on design priors. The ILC algorithm includes: Initial Iteration Input u 0 (n) The mapping is derived from the inverse model parameters in the Pareto optimal solution set output by the improved MOEA / D algorithm, when the system is configured to operate at a frequency f k At that time, the controller looks up the frequency in a table. f k Optimal initial phase offset θ init and amplitude ratio A init The and Directly used as the input for the 0th iteration of the ILC algorithm u 0 (n) : （4）， The ILC algorithm iteratively corrects the input signal using the update law formula (6). u k (n) To minimize error Output, Satisfying formula (5): （5）， In formula (5), y ideal (n) This represents the ideal target baseband signal sequence. y maezn (n) This represents the actual output signal sequence after being acquired and down-converted by the ADC in the feedback channel; This represents the system's target linear gain constant, used to normalize the output signal to the same order of magnitude as the input signal; Update law formula (6): u k+1 (n)=u k (n)+L(f)·e k (n) （6）， in, u k (n) For the first k The input driving signal for the next iteration L(f) The gain matrix is ​​the frequency-selective learning law; L (f) The weight distribution is negatively correlated with the "high-Q resonant point" identified during the MOEA / D optimization process, which suppresses iterative divergence at a specific frequency.

7. The ultra-wideband Doherty power amplifier system according to claim 6, characterized in that, The ILC algorithm adaptively adjusts based on frequency domain sensitivity. L(f) ; The L(f) The structure is as follows: The improved MOEA / D algorithm calculates the frequency domain sensitivity of the entire frequency band in the offline stage. This forms a high-sensitivity frequency band spectrum and constructs... L(f), L(f) according to S sense (f) Adaptive adjustment; The adaptive adjustment strategy is as follows: at the flat frequency point, set... L(f)≈ 0.8, to achieve fast convergence; at sensitive frequency points, set .

8. The ultra-wideband Doherty power amplifier system according to claim 7, characterized in that, The ILC algorithm automatically executes a piecewise linearization strategy based on the real-time output power of the power amplifier module. The piecewise linearization strategy includes: Phase 1 : Low power phase P out < P sat < -12 dB, only carrier amplifier Main PA is working, only updating pre-distortion coefficients of carrier amplifier Main PA, using low order memory polynomial MP for non-linear compensation; Phase 2: Medium Power Phase -12dB < P out <P sat <6dB corresponds to the 12dB to 6dB power back-off region. The carrier amplifier Main PA remains operational, the first peak amplifier Peak1 PA is on, and the second peak amplifier Peak2 PA is off, at which point the initial Doherty load modulation effect begins to appear. The phase and amplitude coefficients of the carrier amplifier Peak1 PA and the first peak amplifier Peak2 PA are updated synchronously to enhance the nonlinearity compensation. Phase 3: High-Power Phase P out ≥P sat -6dB, corresponding Back to the saturation region, the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA are all turned on. At the same time, the phase and amplitude coefficients of the three amplification modules are updated, and the cross term order compensation of the generalized memory polynomial GMP is added to compensate for the strong Doherty load modulation nonlinearity. Among them, P out P represents the actual output power of the power amplifier module. sat This represents the saturated output power of the power amplifier module.

9. The ultra-wideband Doherty power amplifier system according to claim 1, characterized in that, The primary coil leakage inductance of the multilayer PCB planar spiral transformer synthesizer is configured to resonate in series with the parasitic output capacitance Cds of the carrier amplifier Main PA, the first peak amplifier Peak1 PA, and the second peak amplifier Peak2 PA at the center frequency, thereby canceling the parasitic reactance. The multilayer PCB planar spiral transformer synthesizer adopts a multilayer edge-coupled structure on a high-frequency board, with a coupling coefficient k of 0.7~0.

8. The secondary coil inductance value Ls of the multilayer PCB planar spiral transformer synthesizer is a hardware circuit element parameter decision variable of the improved MOEA / D algorithm, and Ls balances the saturation efficiency η at the 4.9GHz frequency point. sat rollback efficiency η 6dB Group delay fluctuations.

10. A control method for an ultra-wideband Doherty power amplifier system, characterized in that, The ultra-wideband Doherty power amplifier system is the ultra-wideband Doherty power amplifier system according to any one of claims 1 to 9; Includes the following steps: Step S1: Cooperative Initialization After the system is powered on, the model-assisted iterative learning control ILC unit of the digital co-controller FPGA actively loads the hardware feature fingerprint library from the non-volatile memory to complete parameter parsing and cache initialization. Step S2: Wideband Pilot Scan Under the instruction of the model-assisted iterative learning control ILC unit, the signal decomposition module generates multiple sets of orthogonal broadband pilot signals covering the entire frequency band from 0.6 to 4.9 GHz. The broadband pilot signals are converted into radio frequency analog pilot signals by three parallel broadband digital-to-analog converters (DACs) and radio frequency upconverters in the radio frequency transmission channel group. The three digital baseband pilot signals are then coupled to the power amplifier module to quickly detect the current channel state information (CSI) and the transient nonlinear characteristics of the three amplifier modules. Step S3: Error Acquisition and Weighting After the power amplifier module amplifies the RF pilot signal, it is combined by a broadband collaborative synthesis network to output a feedback RF signal. The feedback channel ADC acquires the feedback RF signal and converts it into a feedback digital signal. The error vector ek unit acquires the feedback signal at the output of the power amplifier module and calculates the error vector ek between the feedback signal and the ideal signal. k Simultaneously, the model-assisted iterative learning control ILC unit calls the hardware sensitivity threshold loaded in step S1 to dynamically adjust the error weights of the current operating frequency point and generate a weighted error vector. Step S4: Variable Step Size ILC Iteration The model-assisted iterative learning control ILC unit uses weighted error and frequency-selective learning law to calculate the correction amount and update the complex gain coefficients and predistortion polynomial coefficients of the three baseband signals; for high-sensitivity frequency points marked in the hardware feature fingerprint database, the algorithm automatically switches to conservative step size mode to prevent iterative divergence. The model-assisted iterative learning control ILC unit executes steps S2 to S4 sequentially at preset sampling frequencies within the range of 0.6 to 4.9 GHz. After completing the iterative convergence of a single frequency point, it automatically switches to the next frequency point until all frequency points across the entire frequency band are calibrated, and then uniformly enters the working mode of step S5. Step S5: State Locking and Maintenance The model-assisted iterative learning control ILC unit detects the magnitude of the error vector NMSE after iteration in real time. When the magnitude of the error vector NMSE is less than the preset threshold, it is determined that the system has reached the convergence state. The calibration parameters of the current frequency point are immediately stored in the operating coefficient library of the digital co-controller FPGA. At the same time, instructions are sent to the power amplifier module and the broadband co-synthesis network, and the system officially enters the communication signal amplification and transmission working mode. During the communication process, the model-assisted iterative learning control ILC unit utilizes the communication idle time slots to perform low-frequency background fine-tuning of the working status of the power amplifier module and the broadband collaborative synthesis network, correcting errors caused by hardware drift in real time.

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