Power bypass analysis method for ML-DSA digital signatures, electronic devices, media

Abstract

This invention discloses a power consumption bypass analysis method, electronic device, and medium for ML-DSA digital signatures, comprising: for bypass leakage due to repeated private key calls, constructing a first Hamming weight template using a first power consumption trajectory and matching it with a second power consumption trajectory to obtain a first candidate set; for leakage of the output variable of the dot product, constructing a second Hamming weight template and matching it to obtain a second candidate set; for the challenge polynomial in the NTT operation, combining a neural network trained by the first Hamming weight trajectory with a third Hamming weight template to analyze the second trajectory to recover the polynomial coefficients; and combining the first and second candidate Hamming weight sets with the challenge polynomial coefficients, using a majority voting mechanism to enumerate the key and recover the ML-DSA private key.

Description

Technical Field

[0001] This invention relates to the field of information security technology, and in particular to a power consumption bypass analysis method, electronic device, and medium for ML-DSA digital signatures. Background Technology

[0002] In this era of rapid information technology development, the importance of information security is self-evident. Digital signature algorithms, as a crucial tool for ensuring information security, have always been a hot topic in cryptographic research. In recent years, with the increasing threat of quantum computing, quantum-resistant cryptography technologies have developed rapidly, among which the ML-DSA algorithm, as a standard algorithm for quantum-resistant digital signatures, has been widely used.

[0003] However, when cryptographic algorithms are implemented on physical devices such as chips, the physical characteristics of the hardware inevitably lead to the leakage of side-channel signals such as power consumption and electromagnetic radiation. Side-channel analysis, since its inception, has proven to be a highly threatening passive attack analysis method against cryptographic chips. By collecting these side-channel traces during chip operation and analyzing the correlation between these traces and key sensitive variables, attackers can recover core secrets in digital signature algorithms (such as the algorithm's private key), resulting in serious information leakage. Among the current mainstream side-channel analysis methods, power consumption side-channel analysis is one of the most widely used and effective techniques.

[0004] The ML-DSA digital signature algorithm employs a Fiat-Shamir paradigm with aborts in its signing process. This unique construction means that each signing operation often requires multiple rounds of iterative computation using the same private key, continuing until the generated signature meets specific security conditions before being output. This multi-round iteration characteristic leads to the algorithm's private key being repeatedly used during a single signing process, resulting in multiple instances of side-channel information leakage.

[0005] In the field of security assessment before chips leave the factory, it is essential to comprehensively consider and prevent various potential attack methods to ensure the security of chips in actual deployment.

[0006] However, the field of chip implementation security analysis currently lacks an efficient side-channel analysis method that can comprehensively utilize the information leaked during multiple iterations of the ML-DSA signature process. Due to the lack of evaluation and verification of such a systematic method, existing chip implementations are highly susceptible to hidden and exploitable side-channel attack vulnerabilities, posing a significant threat to information security. Summary of the Invention

[0007] In view of this, embodiments of the present invention provide a power consumption bypass analysis method, an electronic device, and a medium for ML-DSA digital signatures.

[0008] In a first aspect, embodiments of the present invention provide a power consumption bypass analysis method for ML-DSA digital signatures, the method comprising:

[0009] Obtain the first power consumption trajectory and the second power consumption trajectory generated by the first chip and the second chip during the ML-DSA digital signature process;

[0010] To address the issue of multiple bypass leaks caused by repeated private key calls during ML-DSA digital signatures, a first Hamming weight template is constructed using a first power consumption trajectory; template matching is then performed based on a second power consumption trajectory using the first Hamming weight template to obtain a first candidate Hamming weight set.

[0011] For the output variable of the private key in the ML-DSA digital signature process, a second Hamming weight template is constructed using the first power consumption trajectory; based on the second power consumption trajectory, template matching is performed using the second Hamming weight template to obtain a second set of candidate Hamming weights.

[0012] For the challenge polynomial involved in the dot product operation during the ML-DSA digital signature process, a bypass leakage caused by the NTT operation based on the challenge polynomial is addressed. A third Hamming weight template is constructed using the first power consumption trajectory, and a neural network is trained. The trained neural network is then used to analyze the second power consumption trajectory, and template matching is performed based on the second power consumption trajectory using the third Hamming weight template to obtain the coefficient values ​​of the challenge polynomial.

[0013] The private key for the ML-DSA digital signature is obtained by enumerating the key based on majority voting, using the first candidate Hamming weight set, the second candidate Hamming weight set, and the challenge polynomial coefficient values.

[0014] In a second aspect, embodiments of the present invention provide an electronic device, comprising:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores one or more computer programs that can be executed by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the power bypass analysis method for ML-DSA digital signatures described above.

[0018] Thirdly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described power consumption bypass analysis method for ML-DSA digital signatures.

[0019] Fourthly, embodiments of the present invention provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the aforementioned power bypass analysis method for ML-DSA digital signatures.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0021] This invention provides a power consumption bypass analysis method for ML-DSA digital signatures. It addresses multiple bypass leaks caused by repeated private key calls during the ML-DSA digital signature process, analyzes the output variables of dot product operations on the private key during ML-DSA digital signatures, and analyzes challenge polynomials. By integrating the above bypass information, it achieves efficient key enumeration under low computational cost and low trace length conditions. This invention not only significantly reduces data acquisition costs and computational overhead but also greatly improves the success rate of key recovery and its engineering practicality, providing a powerful evaluation tool for further ensuring the security of cryptographic chips. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart of a power consumption bypass analysis method for ML-DSA digital signatures provided in an embodiment of the present invention;

[0024] Figure 2 A bypass leakage diagram of the private key coefficient s[0] and the dot product result x[0] provided in the embodiments of the present invention;

[0025] Figure 3 Bypass leakage diagram of the first three rounds of NTT operation for the challenge polynomial provided in this embodiment of the invention;

[0026] Figure 4 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that, unless otherwise specified, the features in the following embodiments and implementation methods can be combined with each other.

[0029] like Figure 1 and Figure 2 As shown, this embodiment of the invention provides a power consumption bypass analysis method for ML-DSA digital signatures, the method comprising:

[0030] Step S1: Obtain the first power consumption trajectory and the second power consumption trajectory generated by the first chip and the second chip performing the ML-DSA digital signature process.

[0031] Specifically, the first hardware device (i.e., the modeling device) is coupled to an oscilloscope, and a random message is input to cause the first chip deployed on the first hardware device (i.e., the modeling device) to perform ML-DSA digital signature. The first power consumption trajectory generated during the ML-DSA digital signature process is collected by the oscilloscope.

[0032] The second hardware device (i.e., the target device) is coupled to an oscilloscope, and a random message is input to cause the second chip deployed on the second hardware device (i.e., the target device) to perform ML-DSA digital signature. The second power consumption trajectory generated during the ML-DSA digital signature process is collected by the oscilloscope.

[0033] Furthermore, the first chip and the second chip are of the same model; for example, in this instance, the first chip and the second chip are STM32F415 microcontrollers; the ML-DSA digital signature algorithm is programmed onto the first chip deployed on the first hardware device and the second chip deployed on the second hardware device (i.e., the target device), and the ML-DSA digital signature algorithm key generation and ML-DSA digital signature process are controlled and executed through the ChipWhisperer power bypass acquisition platform.

[0034] Furthermore, in this example, the oscilloscope's sampling frequency is set to be greater than or equal to 100 MS / s.

[0035] Step S2: To address the multiple bypass leaks caused by repeated private key calls during the ML-DSA digital signature process, a first Hamming weight template is constructed using the first power consumption trajectory; template matching is performed based on the second power consumption trajectory and the first Hamming weight template to obtain a first candidate Hamming weight set.

[0036] Specifically, based on the first power consumption trajectory, and addressing the multiple bypass leaks caused by repeated private key calls during the ML-DSA digital signature process, the modeling interest points are determined through the correlation coefficient curve of the first power consumption trajectory to construct the corresponding first Hamming weight template; such as Figure 2 As shown, Figure 2 The bypass leakage diagram of the private key coefficient s[0] and the dot product result x[0] is shown. Figure 2 The horizontal axis represents the curve sampling point, the gray curve represents the collected power consumption curve, and the data corresponds to the power consumption on the left vertical axis; the blue and red curves are the correlation coefficient curves of the power consumption curves of the private key s[0] and the dot product result x[0] (correlation coefficient between power consumption and Hamming weight), and the data corresponds to the correlation coefficient on the right vertical axis.

[0037] Based on the second power consumption trajectory, template matching is performed using the constructed first Hamming weight template. The top-K Hamming weights with the highest matching probability in the template matching results are saved as the first candidate Hamming weight set corresponding to the private key coefficients. (In this example, top-K=5).

[0038] Furthermore, in this example, the first Hamming weight template constructed to address multiple bypass leaks caused by repeated private key calls during the ML-DSA digital signature process is used to calculate the actual Hamming weight of the private key coefficients within the first candidate Hamming weight set. The accuracy rate is 95.10% when using only one private key bypass leak and 99.40% when using six private key bypass leaks.

[0039] It should be noted that this example utilizes the multiple bypass leaks caused by repeated private key calls during the ML-DSA digital signature process. This effectively reduces the number of power consumption curves required for successful analysis. Furthermore, by employing methods such as averaging, it effectively suppresses measurement noise introduced by the environment and equipment, thereby significantly optimizing the template matching process. Compared to traditional template matching that relies solely on single-iteration leaks, this invention significantly improves the accuracy of template matching and enhances the reliability of private key analysis.

[0040] Step S3: For the output variable of the private key in the ML-DSA digital signature process, construct a second Hamming weight template using the first power consumption trajectory; perform template matching based on the second power consumption trajectory and the second Hamming weight template to obtain a second candidate Hamming weight set.

[0041] It should be noted that, according to the polynomial dot product operator, the relationship between the private key coefficients of the i-th algorithm, the dot product result, and the coefficients of the challenge polynomial can be expressed as a constraint equation:

[0042]

[0043] In the formula, These represent the dot product result, challenge polynomial coefficients, and private key coefficients over the NTT field, respectively. This represents the Montgomery Reduce in the ML-DSA algorithm.

[0044] Specifically, based on the first power consumption trajectory, the output variables of the dot product operation of the private key in the ML-DSA digital signature process are used to determine the modeling interest points through the correlation coefficient curve of the first power consumption trajectory, thereby constructing the corresponding second Hamming weight template.

[0045] Based on the second power consumption trajectory, template matching is performed using the constructed second Hamming weight template. The top-K Hamming weights with the highest matching probability in the template matching results are saved as the set of second candidate Hamming weights corresponding to the private key coefficients. (In this example, top-K=5).

[0046] Furthermore, in this example, the second Hamming weight template is constructed based on the output variables of the dot product operation on the private key during the ML-DSA digital signature process. The actual Hamming weight of the statistical dot product output coefficients is located in the second candidate Hamming weight set. The accuracy rate was 96.35%.

[0047] It should be noted that in this example, template matching is performed on the output variable of the dot product operation of the private key during the ML-DSA digital signature process, thus providing crucial additional side-channel information for private key analysis. Furthermore, combined with the subsequent key enumeration method, this example constructs multi-dimensional mathematical constraints, further compressing the candidate key space for the private key, greatly reducing the algorithmic complexity of exhaustive search, and thus significantly improving the efficiency of the final key recovery.

[0048] Step S4: For the challenge polynomial involved in the dot product operation during the ML-DSA digital signature process, based on the bypass leakage generated by the NTT operation of the challenge polynomial, a third Hamming weight template is constructed using the first power consumption trajectory, and a neural network is trained; the second power consumption trajectory is analyzed through the trained neural network, and template matching is performed based on the second power consumption trajectory using the third Hamming weight template to obtain the coefficient value of the challenge polynomial.

[0049] Furthermore, the input and output of the NTT (Number Theoretic Transform) operation can be represented as:

[0050]

[0051] In the formula, Let them represent polynomials over the NTT field and polynomials over the integer field, respectively.

[0052] Specifically, step S4 includes the following sub-steps:

[0053] Step S401: For the first three rounds of butterfly operations in NTT, a neural network is trained with the modeling interest points on the first power consumption trajectory as input and the number of values ​​of the challenge polynomial as the output label.

[0054] Specifically, for the first round of butterfly operations in NTT, the first neural network is trained using the modeled points of interest (POIs) on the first power consumption trajectory as input and the number of possible values ​​of the challenge polynomial as output labels. This includes: collecting 3000 randomly generated challenge polynomials from the first round of NTT operations; dividing the first power consumption trajectories into training and validation sets in a 7.5:2.5 ratio; the first neural network inputs x modeled points of interest (POIs) selected on the first power consumption trajectory, and outputs y labels (y=2 or 3 in this example), each label corresponding to one of the y possible values ​​of the challenge polynomial (y=2 corresponds to {0, 1}, y=3 corresponds to {-1, 0, 1}). The cross-entropy function is used as the loss function, the learning rate is set to 0.0001, the training rounds are 300, and the batch size is 32.

[0055] For the second round of butterfly operation in NTT, the modeling interest points on the first power consumption trajectory are used as input, and the number of values ​​of the challenge polynomial is used as the output label to train the second neural network.

[0056] For the third round of butterfly operation in NTT, the modeling interest points on the first power consumption trajectory are used as input, and the number of values ​​of the challenge polynomial is used as the output label to train the third neural network.

[0057] The training process for the second and third neural networks is the same as that for the first neural network.

[0058] In this example, the first, second, and third neural networks use a multilayer perceptron (MLP), and their parameter settings are shown in Table 1 below.

[0059] Table 1: Neural Network Parameter Table

[0060]

[0061] Figure 3 The bypass leakage diagram for the first three rounds of the challenge polynomial in the NTT operation provided for this example. Figure 3 In (a) of the diagram, the orange curve represents the coefficient. Correlation coefficient curve of bypass curve in NTT's first-level butterfly operation (correlation coefficient between power consumption and coefficient value {0,1}); the blue curve represents the coefficient. The correlation coefficient curve of the bypass curve in NTT's first-level butterfly operation (correlation coefficient between power consumption and coefficient values ​​{-1,0,1}). Figure 3 In (b) of the diagram, all curves are coefficients. The correlation coefficient curve of the bypass curve in NTT's second-layer butterfly operation (correlation coefficient between power consumption and coefficient values ​​{0,1}), where the green, orange, and blue curves represent the correlation coefficients of power consumption and coefficient values ​​{0,1}, respectively. The correlation coefficient at that time. Figure 3 In (c) of the diagram, the blue curve represents the current... hour, The correlation coefficient curve of power consumption curve in NTT's third-layer butterfly operation (correlation coefficient between power consumption and coefficient values ​​{0,1}).

[0062] Step S402: For the butterfly operation in the last round of NTT, the bypass leakage generated by the NTT operation is performed according to the challenge polynomial. Based on the first power consumption trajectory, the modeling interest point is determined through the correlation coefficient curve of the first power consumption trajectory, thereby constructing the corresponding third Hamming weight template.

[0063] Step S403: Based on the second power consumption trajectory, perform template matching using the constructed third Hamming weight template, and save the top-K Hamming weights with the highest matching probability in the template matching results as the third candidate Hamming weight set corresponding to the private key coefficients. (In this example, top-K=5); the second power consumption trajectory is analyzed using the trained first, second, and third neural networks, and combined with the third candidate Hamming weight set. We obtain the coefficient values ​​of the challenge polynomial.

[0064] The first neural network is used to recover the coefficients of the challenge polynomial from the 128th to the 255th, the second neural network is used to recover the coefficients of the challenge polynomial from the 64th to the 127th, the third neural network is used to recover the coefficients of the challenge polynomial from the 32nd to the 64th, and the third candidate Hamming weight set is used. The coefficients used to challenge polynomial residues.

[0065] Furthermore, in the embodiment, the accuracies of the first, second, and third neural networks trained for the first three rounds of butterfly operation bypass leakage are 99.99%, 99.86%, and 100%, respectively; for the third Hamming weight template constructed using the challenge polynomial NTT domain coefficients, its actual Hamming weight is statistically analyzed to be located in the third candidate Hamming weight set. The accuracy rate was 91.92%; the accuracy rate for successfully recovering the challenging polynomial in this example was 97.90%.

[0066] It should be noted that this example addresses the challenge polynomial involved in dot product operations during the ML-DSA digital signature process. By utilizing the bypass leakage generated by NTT operations on the challenge polynomial and combining the sparsity characteristics of the challenge polynomial with deep learning, the coefficients of the challenge polynomial can be successfully recovered using only the bypass leakage from the four-round number theory transformation (NTT) process. Compared to existing recovery methods, this invention significantly reduces the number of required bypass leakage traces, effectively lowering the cost of power consumption data acquisition and the difficulty of actual analysis.

[0067] Step S5, based on the first candidate Hamming weight set Second candidate Hamming weight set And challenging polynomial coefficients Perform key enumeration based on majority voting to obtain the private key for the ML-DSA digital signature.

[0068] Specifically, let For the modulus of ML-DSA digital signatures, enumerate The Hamming weight values ​​within the range are located in the first candidate Hamming weight set. The candidate private key coefficients are calculated, and their coefficients are compared with those of each challenge polynomial. The dot product results are calculated, and the Hamming weight of each dot product result is located in the second candidate Hamming weight set. The private key coefficient with the highest frequency in the sequence is output as the private key coefficient of the recovered ML-DSA digital signature. This key enumeration process is repeated until all private key coefficients have been recovered.

[0069] Furthermore, step S5 can also be ported to GPU execution to achieve parallelization and accelerate iteration. Specifically, by allocating a thread block to handle key enumeration for each private key coefficient, 256 threads are allocated within each thread block, and each thread processes a non-overlapping subset of the candidate private key coefficient set. For each candidate value assigned to a thread, the thread executes a preset... Perform the second dot product operation and count the Hamming weights of the dot product results to be located in the second candidate Hamming weight set. The frequency of each value is determined. After all threads within a block complete their local computation, some results are stored in shared memory and reduced within the block. Then, a block-level reduction operation is performed to select the candidate value with the highest frequency. Finally, the selected candidate value is written to global memory as the recovered coefficient. For a total of 1024 private key coefficients, the above key enumeration is implemented on the GPU to improve the efficiency of the algorithm. In this embodiment, step S5 requires an average number of constraint equations to recover a total of 1024 algorithm private keys. The value is 24, requiring 6 bypass power traces to fully recover the algorithm's private key. This key enumeration process takes approximately 3 seconds.

[0070] It should be noted that this example employs a majority voting-based key enumeration mechanism in the key deduction stage. Compared to traditional exhaustive verification methods, this mechanism not only effectively reduces unnecessary redundant computations but also possesses stronger fault tolerance, enabling stable recovery of the algorithm's private key under more stringent (less power consumption trace) conditions. This further enhances the practical application value and data utilization efficiency of this bypass analysis method. Simultaneously, this example leverages the parallel computing capabilities of GPUs, performing deep parallelization and acceleration optimization on the computationally intensive parts of the key enumeration process. Compared to key enumeration analysis methods relying on traditional CPU serial computation, this invention significantly shortens program execution time, overcomes hardware computing power bottlenecks, and significantly improves processing efficiency when facing large-scale key space searches.

[0071] In summary, this invention provides a power consumption bypass analysis method for ML-DSA digital signatures. It addresses multiple bypass leaks caused by repeated private key calls during ML-DSA digital signature processing, analyzes the output variables of dot product operations on the private key during ML-DSA digital signature processing, and analyzes challenge polynomials. By integrating the above bypass information, it achieves efficient key enumeration under low computational load and low trace length conditions, effectively filling the gap in chip security analysis in this field. This invention not only significantly reduces data acquisition costs and computational overhead but also greatly improves the success rate of key recovery and engineering practicality, providing a powerful evaluation tool for further ensuring the security of cryptographic chips.

[0072] like Figure 4 As shown, this application provides an electronic device including a memory 101 for storing one or more programs and a processor 102. When the one or more programs are executed by the processor 102, they implement the method as described in any of the first aspects above.

[0073] The system also includes a communication interface 103. The memory 101, processor 102, and communication interface 103 are electrically connected directly or indirectly to each other to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The memory 101 can be used to store software programs and modules, and the processor 102 executes various functional applications and data processing by executing the software programs and modules stored in the memory 101. The communication interface 103 can be used for signaling or data communication with other node devices.

[0074] The memory 101 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0075] The processor 102 can be an integrated circuit chip with signal processing capabilities. The processor 102 can be a general-purpose processor 102, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0076] In the embodiments provided in this application, it should be understood that the disclosed methods and systems can also be implemented in other ways. The method and system embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0077] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0078] On the other hand, embodiments of this application provide a computer-readable storage medium storing a computer program thereon. When executed by processor 102, the computer program implements the methods described in any of the first aspects above. If the functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0079] The above embodiments are only used to illustrate the design concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes or modifications made based on the principles and design ideas disclosed in the present invention are within the protection scope of the present invention.

Claims

1. A method for power side-channel analysis against ML-DSA digital signatures, characterized in that, The method includes: Obtain the first power consumption trajectory and the second power consumption trajectory generated by the first chip and the second chip during the ML-DSA digital signature process; To address the issue of multiple bypass leaks caused by repeated private key calls during ML-DSA digital signatures, a first Hamming weight template is constructed using a first power consumption trajectory; template matching is then performed based on a second power consumption trajectory using the first Hamming weight template to obtain a first candidate Hamming weight set. For the output variable of the private key in the ML-DSA digital signature process, a second Hamming weight template is constructed using the first power consumption trajectory; based on the second power consumption trajectory, template matching is performed using the second Hamming weight template to obtain a second set of candidate Hamming weights. For the challenge polynomial involved in the dot product operation during the ML-DSA digital signature process, a bypass leakage caused by the NTT operation based on the challenge polynomial is addressed. A third Hamming weight template is constructed using the first power consumption trajectory, and a neural network is trained. The trained neural network is then used to analyze the second power consumption trajectory, and template matching is performed based on the second power consumption trajectory using the third Hamming weight template to obtain the coefficient values ​​of the challenge polynomial. The private key for the ML-DSA digital signature is obtained by enumerating the key based on majority voting, using the first candidate Hamming weight set, the second candidate Hamming weight set, and the challenge polynomial coefficient values.

2. The power side-channel analysis method against ML-DSA digital signatures according to claim 1, characterized in that, The first chip and the second chip are of the same model.

3. The power consumption bypass analysis method for ML-DSA digital signatures according to claim 1, characterized in that, The process of obtaining the coefficient values ​​of the challenge polynomial includes: For the first, second, and third rounds of butterfly operations in NTT, the modeling interest points on the first power consumption trajectory are used as inputs, and the number of values ​​of the challenge polynomial is used as the output label to train the first neural network, the second neural network, and the third neural network respectively. For the butterfly operation in the last round of NTT, the bypass leakage generated by the NTT operation is performed according to the challenge polynomial, and the third Hamming weight template is constructed based on the first power consumption trajectory; Based on the second power consumption trajectory, template matching is performed using the constructed third Hamming weight template to obtain the third candidate Hamming weight set; The second power consumption trajectory is analyzed by training the first, second, and third neural networks, and combined with the third candidate Hamming weight set to obtain the challenge polynomial coefficient values.

4. The power consumption bypass analysis method for ML-DSA digital signatures according to claim 1 or 3, characterized in that, Construct a Hamming weight template using the first power consumption trajectory; The process of obtaining the candidate Hamming weight set by template matching based on the second power consumption trajectory using the Hamming weight template includes: Based on the first power consumption trajectory, the modeling interest points are determined through the correlation coefficient curve of the first power consumption trajectory, thereby constructing the corresponding Hamming weight template. Based on the second power consumption trajectory, template matching is performed using the constructed Hamming weight template. The top K Hamming weights with the highest matching probability in the template matching results are saved as the candidate Hamming weight set corresponding to the private key coefficient.

5. The power consumption bypass analysis method for ML-DSA digital signatures according to claim 3, characterized in that, The number of possible values ​​for the challenge polynomial is 2 or 3; when the number of possible values ​​for the challenge polynomial is 2, the value of the challenge polynomial is 0 and 1; when the number of possible values ​​for the challenge polynomial is 3, the value of the challenge polynomial is -1, 0 and 1.

6. The power consumption bypass analysis method for ML-DSA digital signatures according to claim 1, characterized in that, The process of obtaining the private key for the ML-DSA digital signature by performing key enumeration based on majority voting using the first candidate Hamming weight set, the second candidate Hamming weight set, and the challenge polynomial coefficient values ​​includes: Let q be the modulus of the ML-DSA digital signature, and enumerate the candidate private key coefficients whose Hamming weight values ​​are located in the first candidate Hamming weight set within the range of [-2-4×q, 2+4×q]. Calculate the dot product of the candidate private key coefficients with the coefficients of each challenge polynomial, and count the frequency of the Hamming weight of each dot product in the set of the second candidate Hamming weights. The most frequent candidate private key coefficient is used as the private key coefficient for the recovered ML-DSA digital signature.

7. The power consumption bypass analysis method for ML-DSA digital signatures according to claim 1 or 6, characterized in that, The process of obtaining the private key for the ML-DSA digital signature by performing key enumeration based on majority voting using the first candidate Hamming weight set, the second candidate Hamming weight set, and the challenge polynomial coefficient values ​​is deployed on a GPU.

8. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more of the computer programs being executed by the at least one processor to enable the at least one processor to perform the power bypass analysis method for ML-DSA digital signatures as claimed in any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the power consumption bypass analysis method for ML-DSA digital signatures as described in any one of claims 1-7.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the power consumption bypass analysis method for ML-DSA digital signatures as described in any one of claims 1-7.

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