Packet processing method and device based on FPGA and intelligent network card

Abstract

This application discloses a packet processing method, apparatus, and smart network interface card (NIC) based on FPGA, applied in the field of communication technology. By configuring different first and second rule templates in a first dual-port RAM (different dual-port RAMs can be configured with different rule templates), the method simultaneously performs rule matching on the packets to be processed through the first and second ports of the first dual-port RAM to obtain the first and second matching results corresponding to each first dual-port RAM, thereby determining the forwarding strategy for the packets to be processed. This application can provide multiple types of matching rules based on the limited system resources of FPGA and can improve packet matching efficiency.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a message processing method and apparatus and a smart network interface card based on FPGA implementation. Background Technology

[0002] Network devices typically extract the five-tuple information from network packets and perform rule matching on the network packets according to fixed five-tuple matching rules to obtain the processing strategy for the network packets. In the above scheme, the rule template for tuple matching rules is fixed and the five-tuple information for matching rules is limited, resulting in inflexible rule matching. As the number of packets that network devices need to process is increasing, this scheme requires the system to configure a large number of matching rules, thus consuming system resources and reducing matching efficiency during packet rule matching. Summary of the Invention

[0003] The purpose of this application is to provide a message processing method based on FPGA, which can provide multiple matching rule templates based on the limited system resources of FPGA and improve message matching efficiency.

[0004] In a first aspect, this application provides a message processing method based on an FPGA, wherein the FPGA includes multiple first dual-port RAMs, each having a first port and a second port, and different first dual-port RAMs are configured with different rule templates. The method includes: For any first dual-port RAM, The pre-configured first rule template and second rule template are written from the first port / second port into the first dual-port RAM. The first rule template is different from the second rule template. Obtain message feature information of the message to be processed, extract the message feature information using the first rule template to obtain the first matching information, and extract the message feature information using the second rule template to obtain the second matching information; The first information to be matched is matched with the first rule template through the first port, and the second information to be matched is matched with the second rule template through the second port, so as to obtain the first matching result corresponding to the first rule template and the second matching result corresponding to the second rule template. Based on the first and second matching results corresponding to each first dual-port RAM, the forwarding strategy for the packets to be processed is determined.

[0005] In one possible implementation, writing a pre-configured first rule template and a second rule template from the first port / second port into the first dual-port RAM includes: The mapping relationship between the port number of the first port of the first dual-port RAM and the template number of the first rule template, and the mapping relationship between the port number of the second port of the first dual-port RAM and the template number of the second rule template; For any first rule configuration information in the first rule template, the first rule configuration information includes the first configuration keyword, rule number, priority and forwarding action. The first configuration keyword is at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. For any storage address of the first dual-port RAM, write the first rule configuration information from the first port / second port to that storage address; And / or, For any second rule configuration information in the second rule template, the second rule configuration information includes the second configuration keyword, rule number, priority and forwarding action. The second configuration keyword is at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. The first configuration keyword is different from the second configuration keyword. For any storage address of the first dual-port RAM, write the second rule configuration information from the first port / second port to that storage address.

[0006] In one possible implementation, the FPGA further includes multiple second dual-port RAMs, each corresponding one-to-one with the multiple first dual-port RAMs. The dual-port RAMs have third and fourth ports. The method further includes: For any second dual-port RAM, set a cascading indicator for the third / fourth port of the second dual-port RAM. The cascading indicator is used to indicate whether the first rule template corresponding to the first port of the corresponding first dual-port RAM supports cascading rules, and whether the second rule template corresponding to the second port supports cascading rules. When the cascading indicators for the third and fourth ports of each of the second dual-port RAMs are not enabled, among which, For any second dual-port RAM, based on the first rule template and the second rule template configured in the first dual-port RAM corresponding to the second dual-port RAM, a hash collision table corresponding to the first rule template and a hash collision table corresponding to the second rule template are configured in the second dual-port RAM through the third port / fourth port. Each hash collision entry in the hash collision table includes multiple hash collision sub-entries. Each hash collision sub-entry includes a valid bit, a port number, and a matching address. The valid bit indicates whether the hash collision sub-entry is idle or occupied. The port number is used to indicate the port number of the third port or the port number of the fourth port. The matching address is the storage address of the first dual-port RAM.

[0007] In one possible implementation, the hash collision table corresponding to the first rule template and the hash collision table corresponding to the second rule template are configured in the second dual-port RAM via the third port / fourth port, including: For any first configuration keyword in the first rule template, the first hash algorithm and the second hash algorithm are used to calculate the first configuration keyword to obtain the first hash value and the second hash value. The first hash value is used as the storage address of the second dual-port RAM. The valid bits in each hash collision sub-item in the hash collision item corresponding to the storage address are read. If there is a hash collision sub-item with a free valid bit, the valid bits are filled with the occupancy, the second hash value, the port number of the third port, and the first storage address of the configured first dual-port RAM and written to the hash collision sub-item. If there is no hash collision sub-item with a free valid bit, overflow processing is performed. For any second configuration keyword in the second rule template, the first hash algorithm and the second hash algorithm are used to calculate the third hash value and the fourth hash value respectively. The third hash value is used as the storage address of the second dual-port RAM. The valid bits in each hash collision sub-item in the hash collision item corresponding to the storage address are read. If there is a hash collision sub-item with a free valid bit, the valid bit is set to occupied, the fourth hash value, the port number of the fourth port, and the second storage address of the configured first dual-port RAM and written to the hash collision sub-item. If there is no hash collision sub-item with a free valid bit, overflow processing is performed.

[0008] In one possible implementation, first matching information is obtained by extracting message feature information using a first rule template, and second matching information is obtained by extracting the message feature information using a second rule template, including: Obtain the message characteristic information of the message to be processed. The message characteristic information includes at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. Based on the mapping relationship between the port number of the first port of the first dual-port RAM and the template number of the first rule template, the first configuration keyword corresponding to the first port of the first dual-port RAM is determined, and the message feature information is filtered by the first configuration keyword to obtain the first matching information corresponding to the first configuration keyword. Based on the mapping relationship between the port number of the second port of the first dual-port RAM and the template number of the second rule template, the second configuration keyword corresponding to the second port of the first dual-port RAM is determined. The message feature information is filtered by the second configuration keyword to obtain the second matching information corresponding to the second configuration keyword.

[0009] In one possible implementation, the first information to be matched is matched against the first rule template through a first port, and simultaneously the second information to be matched is matched against the second rule template through a second port, to obtain a first matching result corresponding to the first rule template and a second matching result corresponding to the second rule template, including: The first hash algorithm is used to perform a hash operation on the first information to be matched to obtain the first target hash value. The first target hash value is used as the storage address of the second dual-port RAM. The first storage address of the corresponding first dual-port RAM is read from the storage address. The first information to be matched is matched with the first configuration keyword corresponding to the first storage address. The first matching result is output. The first matching result carries whether it hits, rule number, priority and forwarding action. The first hash algorithm is used to perform a hash operation on the second information to be matched to obtain the second target hash value. The second target hash value is used as the storage address of the second dual-port RAM. The corresponding second storage address of the first dual-port RAM is read from the storage address. The second information to be matched is matched with the second configuration keyword corresponding to the second storage address. The second matching result is output. The second matching result carries whether it hits, rule number, priority and forwarding action. Based on the first and second matching results corresponding to each first dual-port RAM, the forwarding strategy for the packets to be processed is determined, including: Among the first matching results and the second matching results that have been matched, the forwarding action corresponding to the rule number with the highest priority is selected as the forwarding strategy for the message to be processed.

[0010] In one possible implementation, the FPGA further includes multiple second dual-port RAMs, each corresponding one-to-one with a multiple first dual-port RAMs. The dual-port RAMs have third and fourth ports. The method also includes: For any second dual-port RAM, set a cascading indicator for the third / fourth port of the second dual-port RAM. The cascading indicator is used to indicate whether the first rule template corresponding to the first port of the corresponding first dual-port RAM supports cascading rules, and whether the second rule template corresponding to the second port supports cascading rules. When the cascading indication of the third / fourth port of each of the second dual-port RAMs is enabled, the first configuration keywords corresponding to each first port are concatenated into a cascading rule keyword, and the first configuration keywords corresponding to each second port are concatenated into a cascading rule keyword, wherein... For any second dual-port RAM, the first hash algorithm and the second hash algorithm are used to calculate the concatenation rule key to obtain the fifth hash value and the sixth hash value. The fifth hash value is used as the storage address of the second dual-port RAM. The corresponding hash collision sub-item is configured at the storage address. The hash collision sub-item includes the valid bit, the sixth hash value, the port number of the third port / fourth port, and the third storage address of the configured first dual-port RAM.

[0011] In one possible implementation, the method further includes: The message feature information is filtered using cascading rule keywords to obtain the third matching information corresponding to the cascading rule keywords; The third target hash value is obtained by performing a hash operation on the third information to be matched using the first hash algorithm. In each second dual-port RAM, the third target hash value is used as the storage address of the second dual-port RAM. The storage address is used to read the third storage address of the corresponding first dual-port RAM, thereby obtaining the third storage address of each first dual-port RAM. Read the corresponding first configuration keywords from the third storage address of each first dual-port RAM; The third information to be matched is matched against each of the first configuration keywords. If each of the first configuration keywords is matched, the message to be processed is determined to have matched the cascading rule keywords.

[0012] Secondly, this application provides a message processing device based on an FPGA, wherein the FPGA includes multiple first dual-port RAMs, each having a first port and a second port, and different first dual-port RAMs are configured with different rule templates. The device includes: The configuration module is used to write a pre-configured first rule template and a second rule template from the first port / second port into the first dual-port RAM for any one of the first dual-port RAMs. The first rule template is different from the second rule template. The message processing module is used to obtain message feature information of the message to be processed, extract the message feature information using a first rule template to obtain first matching information, and extract the message feature information using a second rule template to obtain second matching information. The rule matching module is used to match the first information to be matched with the first rule template through the first port, and at the same time match the second information to be matched with the second rule template through the second port, so as to obtain the first matching result corresponding to the first rule template and the second matching result corresponding to the second rule template. The strategy template is used to determine the forwarding strategy for the packets to be processed based on the first matching result and the second matching result corresponding to each first dual-port RAM.

[0013] Thirdly, this application provides a smart network interface card (NIC) that includes the FPGA-based message processing device described above.

[0014] This application configures a first rule template and a second rule template in a first dual-port RAM. Different dual-port RAMs can be configured with different rule templates. Each rule template can support multiple matching keywords, including inner and outer information of the message. The configuration rules in the first and second rule templates share a storage resource, enabling the configuration of a large number of matching rules based on the limited system resources of the FPGA. Each rule template can support flexible configuration of multiple message feature information. When performing rule matching on messages, the simultaneous reading feature of the two ports of the dual-port RAM can be used to achieve the function of matching multiple rule templates at the same time, which can improve the efficiency of message query. Attached Figure Description

[0015] Figure 1 A first flowchart of a message processing method based on FPGA provided in an embodiment of this application; Figure 2 A second flowchart of a message processing method based on FPGA provided in an embodiment of this application; Figure 3 A third flowchart illustrating the message processing method based on FPGA implementation provided in this application embodiment; Figure 4 The fourth flowchart of the message processing method based on FPGA provided in the embodiments of this application; Figure 5 The fifth flowchart of the message processing method based on FPGA provided in the embodiments of this application; Figure 6 The sixth flowchart of the message processing method based on FPGA provided in the embodiments of this application; Figure 7This is a system block diagram of a message processing device based on FPGA provided in an embodiment of this application. Detailed Implementation

[0016] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0017] Please refer to Figure 1 This application provides a message processing method based on FPGA. The FPGA includes multiple first dual-port RAMs. Each first dual-port RAM has a first port and a second port. Different first dual-port RAMs are configured with different rule templates. The method includes steps S101-S105.

[0018] S101, for any one of the first dual-port RAMs, write the pre-configured first rule template and second rule template from the first port / second port into the first dual-port RAM, wherein the first rule template and the second rule template are different; S102, obtain message feature information of the message to be processed, extract the message feature information using the first rule template to obtain the first matching information, and extract the message feature information using the second rule template to obtain the second matching information; S103, the first information to be matched is matched with the first rule template through the first port, and the second information to be matched is matched with the second rule template through the second port, so as to obtain the first matching result corresponding to the first rule template and the second matching result corresponding to the second rule template; S104, based on the first matching result and the second matching result corresponding to each first dual-port RAM, determine the forwarding strategy for the message to be processed.

[0019] In this embodiment, an on-chip RAM is used to implement the first dual-port RAM. The first dual-port RAM has two ports, namely the first port and the second port. Each port includes a data line, an address line, a read enable control line, and a write enable control line.

[0020] In this embodiment, when configuring the matching rules in the first dual-port RAM, address and data writing operations are performed through the first port / second port of the first dual-port RAM to configure the first rule template and the second rule template. The first rule template / second rule template is used to match message rules. Therefore, each dual-port RAM can be configured with two different rule templates, and different first dual-port RAMs can be configured with different rule templates, enabling the configuration of a large number of matching rules.

[0021] For example, the message characteristic information of the message to be processed is obtained. The received message to be processed is parsed to obtain the message characteristic information. The message characteristic information includes, but is not limited to, source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, Ethernet type, service type, and interface index. For example, the message characteristic information can be the inner layer information (service layer) and / or outer layer information (tunnel layer) of the message. Different message types require different message characteristic information.

[0022] Based on the matching keywords in the first rule template, the packet feature information is extracted to obtain the first information to be matched. Based on the matching keywords in the second rule template, the packet feature information is extracted to obtain the second information to be matched. For example, if the matching keywords in the first rule template are the source IP address and the destination IP address, the source IP address and the destination IP address are extracted from the packet feature information to serve as the first information to be matched.

[0023] The first and second matching information are input into the first dual-port RAM. The first matching information is matched against the first rule template through the first port, and simultaneously the second matching information is matched against the second rule template through the second port, resulting in a first matching result corresponding to the first rule template and a second matching result corresponding to the second rule template. The first matching result carries whether there is a hit, the rule number, the priority, and the forwarding action, while the second matching result carries the same information.

[0024] Each dual-port RAM is configured with a different rule template. Therefore, based on the rule templates configured for each dual-port RAM, information is extracted from the packets to be processed to obtain the matching information corresponding to each dual-port RAM. The matching information is then matched with its rule template to obtain the corresponding matching results. Therefore, based on the first and second matching results corresponding to each first dual-port RAM, the forwarding strategy of the packets to be processed is determined, that is, the forwarding action of the packets to be processed is determined.

[0025] In this embodiment, by configuring a first rule template and a second rule template in the first dual-port RAM, different rule templates can be configured in different dual-port RAMs. Each rule template can support multiple matching keywords, including inner and outer information of the message. The configuration rules in the first and second rule templates share a storage resource, enabling the configuration of a large number of matching rules based on the limited system resources of the FPGA. Each rule template can support flexible configuration of multiple message feature information, realizing the function of simultaneous rule matching of inner and outer information of the message. When performing rule matching on the message, the simultaneous reading characteristic of the two ports of the dual-port RAM can be used to realize the function of matching multiple rule templates at the same time, which can improve the efficiency of message query.

[0026] In one embodiment, such as Figure 2 As shown, writing the pre-configured first rule template and second rule template from the first port / second port into the first dual-port RAM includes: S201, Construct the mapping relationship between the port number of the first port of the first dual-port RAM and the template number of the first rule template, and construct the mapping relationship between the port number of the second port of the first dual-port RAM and the template number of the second rule template; S202, for any first rule configuration information in the first rule template, the first rule configuration information includes the first configuration keyword, rule number, priority, and forwarding action; S203, for any storage address of the first dual-port RAM, write the first rule configuration information from the first port / second port to that storage address; S204, for any second rule configuration information in the second rule template, the second rule configuration information includes the second configuration keyword, rule number, priority and forwarding action, and the first configuration keyword is different from the second configuration keyword; S205, for any storage address of the first dual-port RAM, write the second rule configuration information from the first port / second port to that storage address.

[0027] For example, a first rule template can be configured with multiple first rule configuration information, and a second rule template can be configured with multiple second rule configuration information. The first configuration keywords are at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. The second configuration keywords are at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. Priority can be understood as the rule's priority. Forwarding actions include dropping, forwarding, and modifying. For example, the first configuration keywords are source IP address and destination IP address, and the second configuration keywords are source port and destination port.

[0028] For example, the first configuration keyword includes a 48-bit first configuration field, a 48-bit second configuration field, and a 12-bit third configuration field, wherein the first configuration field is different from the second configuration field. Set the first field number corresponding to the first configuration field, and set the second field number corresponding to the second configuration field. If the first field number / second field number is 0, the corresponding first configuration field / second configuration field is the source port SP[15:0] + the source IP address SIP[31:0] of IPv4 / the source IP address SIP[31:0] of IPv6. If the received packet is an IPv4 packet, the first configuration field / second configuration field is the source port SP[15:0] + the source IP address SIP[31:0] of IPv4. If the received packet is an IPv6 packet, the first configuration field / second configuration field is the source port SP[15:0] + the source IP address SIP[31:0] of IPv6. If the first field number / second field number is 1, the corresponding first configuration field / second configuration field is the destination port DP[15:0] + the destination IP address DIP[31:0] of IPv4 / For IPv6, the destination IP address is DIP[31:0]. If the received packet is an IPv4 packet, the first configuration field / second configuration field is the destination port DP[15:0] + the destination IP address is DIP[31:0]. For IPv4, the destination IP address is DIP[31:0]. If the received packet is an IPv6 packet, the first configuration field / second configuration field is the destination port DP[15:0] + IPv6 destination IP address DIP[31:0]; If the first field number / second field number is 2, the corresponding first configuration field / second configuration field is the IPv6 source IP address SIP[79:32]; If the first field number / second field number is 3, the corresponding first configuration field / second configuration field is the IPv6 source IP address SIP[127:80]; If the first field number / second field number is 4, the corresponding first configuration field / second configuration field is the IPv6 destination IP address DIP[79:32]; If the first field number / second field number is 5, the corresponding first configuration field / second configuration field is the IPv6 destination IP address DIP[127:80]; If the first field number / second field number is 6, the corresponding first configuration field / second configuration field is the source MAC address SMAC[47:0]; If the first field number / second field number is 7, the corresponding first configuration field / second configuration field is the destination MAC address DMAC[47:0] 0]; If the first field number / second field number is 8, the corresponding first configuration field / second configuration field is the VLAN field {VLAN4[11:0],VLAN3[11:0],VLAN2[11:0],VLAN1[11:0]}, where VLAN1 is the outermost layer;If the first field number / second field number is 9, the corresponding first configuration field / second configuration field is the MPLS field {MPLS2[15:0],MPLS1[31:0]}; if the first field number / second field number is 10, the corresponding first configuration field / second configuration field is the Ethernet type ETHERTYPE[15:0]+MPLS4[31:0]; if the first field number / second field number is 11, the corresponding first configuration field / second configuration field is the MPLS field {MPLS3[31:0],MPLS2[31:16]}. The 12-bit third configuration field includes the protocol number, PV4 / IPV6 packet identifier, and reserved bits. The configured configuration fields may differ for different types of packets.

[0029] When configuring rules for the first dual-port RAM, data can be written through either the first or second port of the dual-port RAM to write configuration keywords in the first and second rule templates.

[0030] In one embodiment, such as Figure 3 As shown, the FPGA also includes multiple second dual-port RAMs, each corresponding one-to-one with a multiple first dual-port RAMs. Each dual-port RAM has a third port and a fourth port. The method further includes: S301, for any second dual-port RAM, set the cascading indication of the third port / fourth port of the second dual-port RAM; S302, when the cascading indications of the third and fourth ports of each second dual-port RAM are not enabled, wherein, for any second dual-port RAM, based on the first rule template and the second rule template configured in the first dual-port RAM corresponding to the second dual-port RAM, the hash collision table corresponding to the first rule template and the hash collision table corresponding to the second rule template are configured in the second dual-port RAM through the third port / fourth port.

[0031] For any second dual-port RAM, a cascading indicator is set for the third / fourth port of the second dual-port RAM. The cascading indicator is used to indicate whether the first rule template corresponding to the first port of the corresponding first dual-port RAM of the second dual-port RAM supports cascading rules, and whether the second rule template corresponding to the second port of the corresponding first dual-port RAM of the second dual-port RAM supports cascading rules. For example, a cascading indicator of 1 indicates that cascading rules are supported, and a cascading indicator of 0 indicates that cascading rules are not supported.

[0032] For example, suppose the FPGA includes two first dual-port RAMs and two second dual-port RAMs, denoted as first dual-port RAM1, first dual-port RAM2, second dual-port RAM1, and second dual-port RAM2, respectively. The third and fourth ports of each of the second dual-port RAM1 and the second dual-port RAM2 do not support cascading rules. That is, the first matching keyword KeyA1 in the first rule template of the first dual-port RAM1 and the first matching keyword keyA2 in the first rule template of the first dual-port RAM2 do not support cascading rules, and the second matching keyword KeyB1 in the second rule template of the first dual-port RAM1 and the second matching keyword keyB2 in the second rule template of the second dual-port RAM2 do not support cascading rules. When performing rule matching on the message, KeyA1, keyA2, KeyB1, and KeyB2 are used for rule matching, respectively.

[0033] For example, each hash collision entry in the hash collision table includes multiple hash collision sub-entries. Each hash collision sub-entry includes a valid bit, a port number, and a matching address. The valid bit indicates whether the hash collision sub-entry is free or occupied. The port number is used to indicate the port number of the third port or the port number of the fourth port. The matching address is the storage address of the first dual-port RAM.

[0034] In this embodiment, a first rule template and a second rule template are configured in the first dual-port RAM, and a hash collision table is configured in the second dual-port RAM (i.e., the hash collision table corresponding to the first rule template and the hash collision table corresponding to the second rule template). The combination of the first and second dual-port RAMs enables the rule matching function for packets. By setting a cascading indicator on the port of the second dual-port RAM, the cascading and non-cascading functions of the rule templates in the various first dual-port RAMs can be realized. When the port does not support cascading, two different rule templates can be configured in a single first dual-port RAM, and different rule templates can be configured in different first dual-port RAMs. This allows for the configuration of a large number of matching rules in the on-chip dual-port RAM of the FPGA, enabling rule matching for various types of packets.

[0035] In one embodiment, configuring the hash collision table corresponding to the first rule template and the hash collision table corresponding to the second rule template in the second dual-port RAM via the third port / fourth port includes: For any first configuration keyword in the first rule template, the first hash algorithm and the second hash algorithm are used to calculate the first configuration keyword to obtain the first hash value and the second hash value. The first hash value is used as the storage address of the second dual-port RAM. The valid bits in each hash collision sub-item in the hash collision item corresponding to the storage address are read. If there is a hash collision sub-item with a free valid bit, the valid bits are filled with the occupancy, the second hash value, the port number of the third port, and the first storage address of the configured first dual-port RAM and written to the hash collision sub-item. If there is no hash collision sub-item with a free valid bit, overflow processing is performed. For any second configuration keyword in the second rule template, the first hash algorithm and the second hash algorithm are used to calculate the third hash value and the fourth hash value respectively. The third hash value is used as the storage address of the second dual-port RAM. The valid bits in each hash collision sub-item in the hash collision item corresponding to the storage address are read. If there is a hash collision sub-item with a free valid bit, the valid bit is set to occupied, the fourth hash value, the port number of the fourth port, and the second storage address of the configured first dual-port RAM and written to the hash collision sub-item. If there is no hash collision sub-item with a free valid bit, overflow processing is performed.

[0036] For example, it supports four levels of hash collision prevention, meaning the storage space corresponding to the storage address of the second dual-port RAM can store four hash collision sub-items. Taking the first rule template as an example: Iterate through each first configuration keyword in the first rule template. Calculate the first first configuration keyword using the first hash algorithm and the second hash algorithm respectively to obtain the first first hash value and the first second hash value. Use the first first hash value as the first storage address of the second dual-port RAM. Use the valid identifier 1, the first second hash value, the port number of the third port, and the configured storage address of the first dual-port RAM as the configured first hash collision sub-item, and write it to the storage space corresponding to that first storage address. The second first configuration key is processed using the first hash algorithm and the second hash algorithm respectively to obtain the second first hash value and the second second hash value. If the second first hash value is inconsistent with the first first hash value, the second first hash value is used as the second storage address of the second dual-port RAM. The first second hash collision sub-item is written to the storage space corresponding to the second storage address, with the valid identifier 1, the second second hash value, the port number of the third port, and the configured storage address of the first dual-port RAM. If the second first hash value is consistent with the first first hash value, the second first hash collision sub-item is written to the storage space corresponding to the first storage address, with the valid identifier 1, the second second hash value, the port number of the third port, and the configured storage address of the first dual-port RAM. This process continues until all four hash collision sub-items corresponding to the first storage address are occupied, in which case overflow processing is performed. This completes the configuration of the hash collision table corresponding to the first rule template.

[0037] In this embodiment, by designing a multi-level anti-hash collision system, the matching address in the hash collision sub-item is mapped to the address of the first dual-port RAM, which can expand the entries of the hash collision table, thereby effectively improving the hash collision rate and the utilization rate of the rule template. For example, based on this embodiment, the collision rate is increased from 20% to 4%.

[0038] In one embodiment, such as Figure 3 As shown, the first matching information is obtained by extracting message feature information using a first rule template, and the second matching information is obtained by extracting the message feature information using a second rule template, including: S301, Obtain the message characteristic information of the message to be processed. The message characteristic information is at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. S302, based on the mapping relationship between the port number of the first port of the first dual-port RAM and the template number of the first rule template, determine the first configuration keyword corresponding to the first port of the first dual-port RAM, filter the message feature information with the first configuration keyword, and obtain the first matching information corresponding to the first configuration keyword; S303, based on the mapping relationship between the port number of the second port of the first dual-port RAM and the template number of the second rule template, determine the second configuration keyword corresponding to the second port of the first dual-port RAM, filter the message feature information with the second configuration keyword, and obtain the second matching information corresponding to the second configuration keyword.

[0039] For example, the first configuration keywords are the source IP address and the destination IP address, and the second configuration keywords are the source port and the destination port. Filtering the packet feature information yields the source IP address and the destination IP address, which are the first matching information, and the source port and the destination port, which are the second matching information.

[0040] Since each rule template has a different configuration keyword, it is necessary to process the message feature information so that the matching information corresponding to the configuration keyword can be obtained when matching rules.

[0041] In one embodiment, such as Figure 4 As shown, the first information to be matched is matched with the first rule template through the first port, and the second information to be matched is matched with the second rule template through the second port, to obtain the first matching result corresponding to the first rule template and the second matching result corresponding to the second rule template, including: S401, the first hash algorithm is used to perform a hash operation on the first information to be matched to obtain the first target hash value. The first target hash value is used as the storage address of the second dual-port RAM. The first storage address of the corresponding first dual-port RAM is read from the storage address. The first information to be matched is matched with the first configuration keyword corresponding to the first storage address according to the rule, and the first matching result is output. S402, the second target hash value is obtained by performing a hash operation on the second information to be matched using the first hash algorithm. The second target hash value is used as the storage address of the second dual-port RAM. The second storage address of the corresponding first dual-port RAM is read from the storage address. The second information to be matched is matched with the second configuration keyword corresponding to the second storage address according to the rule, and the second matching result is output. S403: Among the first matching results and the second matching results that have been matched, select the forwarding action corresponding to the rule number with the highest priority as the forwarding strategy for the message to be processed.

[0042] For example, the following explanation uses support for four levels of hash collision prevention. The first information to be matched is hashed using a first hash algorithm and a second hash algorithm to obtain a first target hash value and a fourth target hash value. The first target hash value is used as the storage address of the second dual-port RAM. The four hash collision sub-items corresponding to this storage address are read. The valid bits and second hash values ​​of each of the four hash collision sub-items are read. The fourth target hash value is compared with the four second hash values. If they match, the first storage address of the first dual-port RAM in the corresponding hash collision sub-item is read. If they do not match, no matching process is performed. In the first dual-port RAM, the first information to be matched is matched against the first configuration keyword corresponding to the first storage address through the first port, and a first matching result is output. The first matching result carries whether a match was achieved, the rule number, the priority, and the forwarding action.

[0043] For example, the following explanation uses support for four levels of hash collision prevention. The second information to be matched is hashed using a first hash algorithm and a second hash algorithm to obtain a second target hash value and a fifth target hash value. The second target hash value is used as the storage address of the second dual-port RAM. The four hash collision sub-items corresponding to this storage address are read. The valid bits and fourth hash values ​​of each of the four hash collision sub-items are read. The fifth target hash value is compared with the four fourth hash values. If they match, the second storage address of the corresponding hash collision sub-item in the first dual-port RAM is read. If they do not match, no matching process is performed. In the first dual-port RAM, the second information to be matched is matched against the second configuration keyword corresponding to the second storage address through the second port, and a first matching result is output. The first matching result carries whether a match was achieved, the rule number, the priority, and the forwarding action.

[0044] Similarly, each second dual-port RAM and each first dual-port RAM performs rule matching on the packets to be processed, obtaining each first matching result and each second matching result. Among the first matching results and second matching results that have been matched, the forwarding action corresponding to the rule number with the highest priority is selected as the forwarding strategy for the packets to be processed, thereby realizing the rule matching processing of the packets.

[0045] In one embodiment, such as Figure 5 As shown, the method also includes: S501, for any second dual-port RAM, set the cascading indication of the third port / fourth port of the second dual-port RAM; S502, when the cascading indication of the third port / fourth port of each second dual-port RAM is enabled, the first configuration keywords corresponding to each first port are concatenated into a cascading rule keyword / the first configuration keywords corresponding to each second port are concatenated into a cascading rule keyword; S503: For any second dual-port RAM, the first hash algorithm and the second hash algorithm are used to calculate the concatenation rule key to obtain the fifth hash value and the sixth hash value. The fifth hash value is used as the storage address of the second dual-port RAM. The corresponding hash collision sub-item is configured at the storage address. The hash collision sub-item includes the valid bit, the sixth hash value, the port number of the third port / fourth port, and the third storage address of the configured first dual-port RAM.

[0046] For any second dual-port RAM, a cascading indicator is set for the third / fourth port of the second dual-port RAM. The cascading indicator is used to indicate whether the first rule template corresponding to the first port of the corresponding first dual-port RAM of the second dual-port RAM supports cascading rules, and whether the second rule template corresponding to the second port of the corresponding first dual-port RAM of the second dual-port RAM supports cascading rules. For example, a cascading indicator of 1 indicates that cascading rules are supported, and a cascading indicator of 0 indicates that cascading rules are not supported.

[0047] For example, assume the FPGA includes two first dual-port RAMs and two second dual-port RAMs, denoted as First Dual-Port RAM1, First Dual-Port RAM2, Second Dual-Port RAM1, and Second Dual-Port RAM2, respectively. The concatenation indication of the third port in each of the second dual-port RAMs is 1, and the concatenation indication of the fourth port in each of the second dual-port RAMs is 0. The first matching keyword in the first rule template of the first dual-port RAM1 is the source IP address and the destination IP address; the second matching keyword in the second rule template of the first dual-port RAM1 is the source MAC address and the destination MAC address; the first matching keyword in the first rule template of the first dual-port RAM2 is the source port and the destination port; and the second matching keyword in the second rule template of the first dual-port RAM2 is VLAN. Concatenating the source IP address and the destination IP address, and the source port and the destination port, yields the concatenation rule keyword: source IP address + destination IP address + source port + destination port. When performing rule matching on packets, the matching rules include source IP address + destination IP address + source port + destination port, source MAC address and destination MAC address, and VLAN.

[0048] When setting cascading instructions, the settings can be configured according to the actual application scenario. In the above embodiment, the third ports of each of the second dual-port RAM1 and the second dual-port RAM2 support cascading, while the fourth ports of each of the second dual-port RAM1 and the second dual-port RAM2 do not support cascading. Alternatively, both the third and fourth ports of each of the second dual-port RAM1 and the second dual-port RAM2 can be configured to support cascading. Different cascading combinations of rule templates can be set according to actual needs, and no restrictions are imposed here.

[0049] For example, taking the above embodiment as an example, when configuring the hash collision table, the first hash algorithm and the second hash algorithm are used to calculate the cascading rule key (source IP address + destination IP address + source port + destination port) to obtain the fifth hash value and the sixth hash value. The fifth hash value is used as the storage address of the second dual-port RAM1 and the second dual-port RAM2. The corresponding hash collision sub-entry is configured at this storage address. The hash collision sub-entry includes the valid bit, the sixth hash value, the port number of the third port / fourth port, and the configured third storage address of the first dual-port RAM1. The hash collision sub-entries stored at this storage address of the second dual-port RAM1 and the second dual-port RAM2 are consistent. For the second matching key in the second rule template being the source MAC address and the destination MAC address, and the second matching key in the second rule template of the first dual-port RAM2 being VLAN, the configuration of the corresponding hash collision table can be referred to the above. Figure 3 The embodiments shown will not be described in detail here.

[0050] In this embodiment, the configuration of cascading rule keywords also supports multi-level anti-hash collision. For specific implementation details, please refer to the above embodiments, which will not be repeated here.

[0051] In this embodiment, by setting the cascading method of rule templates, it is possible to support the cascading of multiple rule templates. For example, if the bit width of the dual-port RAM is insufficient to support the combination of multiple types of matching keywords, by setting the cascading method between each dual-port RAM, longer byte rule templates can be implemented, thereby expanding the rule templates.

[0052] In one embodiment, such as Figure 6 As shown, the method also includes: S601, filter the message feature information using the cascading rule keyword to obtain the third matching information corresponding to the cascading rule keyword; S602, the first hash algorithm is used to perform a hash operation on the third information to be matched to obtain the third target hash value; S603, in each second dual-port RAM, the third target hash value is used as the storage address of the second dual-port RAM. The storage address is read to the third storage address of the corresponding first dual-port RAM, thereby obtaining the third storage address of each first dual-port RAM. S604 reads the corresponding first configuration keywords from the third storage address of each first dual-port RAM; S605, the third information to be matched is matched with each of the first configuration keywords according to the rules. If each of the first configuration keywords is matched at the same time, it is determined that the message to be processed has matched the cascading rule keyword.

[0053] For example, the above embodiment will be used as an example for explanation. The cascading rule keywords are source IP address + destination IP address + source port + destination port. The packet feature information is filtered to obtain the source IP address, destination IP address, source port, and destination port from the packet feature information. This information is used as the third matching information. The third matching information is hashed using the first hash algorithm and the second hash algorithm respectively to obtain the third target hash value and the sixth target hash value. In the second dual-port RAM1 and the second dual-port RAM2, the third target hash value is used as the storage address. The corresponding hash collision sub-item is read from this storage address. The valid bits and the sixth hash value in the four hash collision sub-items are read respectively. The sixth target hash value is compared with the four sixth hash values. If they match, the third storage address of the first dual-port RAM1 and the first dual-port RAM2 in the corresponding hash collision sub-item is read. The configuration keyword "source IP address + destination IP address" is read from the third storage address of the first dual-port RAM1, and the configuration keyword "source port + destination port" is read from the third storage address of the first dual-port RAM2. The source IP address + destination IP address in the third match information is matched with the keyword "source IP address + destination IP address", and the source port + destination port in the third match information is matched with the keyword "source port + destination port". If both match, the packet to be processed is determined to have matched the cascading rule keyword "source IP address + destination IP address + source port + destination port".

[0054] In this embodiment, when determining the forwarding strategy for a packet to be processed, it is necessary not only to determine whether the packet matches the concatenation rule keyword, but also to process the rule matching of the packet according to the concatenation indications of other ports in the second dual-port RAM. For example, the fourth port in the second dual-port RAM supports non-concatenation mode. By matching the packet to be processed with the second rule template corresponding to the fourth port, and based on the matching results of the rule templates of each dual-port RAM and the matching results of the concatenation rule keyword, the forwarding strategy for the packet to be processed is determined. Specific implementation methods can be referred to the above. Figure 4 The implementation method will not be described in detail here. Taking the above embodiment as an example, the packet to be processed is matched with the second configuration keyword "source MAC address and destination MAC address" of the first dual-port RAM1 to determine the corresponding matching result 1. At the same time, the packet to be processed is matched with the second configuration keyword "VALN" of the first dual-port RAM2 to determine the corresponding matching result 2. Based on the matching result of the cascading rule keyword, matching result 1 and matching result 2, the final forwarding strategy of the packet to be processed is determined according to the priority of the rule.

[0055] Based on the same inventive concept, this application also provides a message processing device based on FPGA. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the message processing device based on FPGA provided below can be found in the limitations of the message processing method based on FPGA above, and will not be repeated here.

[0056] Please refer to Figure 7 This application provides a message processing device based on an FPGA. The FPGA includes multiple first dual-port RAMs, each having a first port and a second port. Different first dual-port RAMs are configured with different rule templates. The device includes: Configuration module 701 is used to write a pre-configured first rule template and a second rule template from the first port / second port into the first dual-port RAM for any one of the first dual-port RAMs, wherein the first rule template and the second rule template are different. The message processing module 702 is used to obtain message feature information of the message to be processed, extract the message feature information using a first rule template to obtain first matching information, and extract the message feature information using a second rule template to obtain second matching information. The rule matching module 703 is used to match the first information to be matched with the first rule template through the first port, and at the same time match the second information to be matched with the second rule template through the second port, so as to obtain the first matching result corresponding to the first rule template and the second matching result corresponding to the second rule template. The strategy module 704 is used to determine the forwarding strategy of the packet to be processed based on the first matching result and the second matching result corresponding to each first dual-port RAM.

[0057] This application provides a smart network interface card (NIC) including the FPGA-based message processing device described above. The smart NIC includes the FPGA-based message processing device, a communication interface, a processor, a memory, and a bus. The processor, memory, communication interface, and FPGA-based message processing device are communicatively connected to each other via the bus. The memory can be used to store computer programs, which may include instructions and data. In embodiments of this application, the memory can be various types of storage media, such as random access memory, static random access memory, non-volatile RAM, DDR, etc. The memory may include a hard disk and / or RAM. The processor can be a general-purpose processor, which is a processor that performs specific steps and / or operations by reading and executing computer programs stored in memory (e.g., RAM), and is used to process data output by the FPGA-based message processing device. The general-purpose processor can be, for example, but not limited to, a central processing unit (CPU). Furthermore, the processor can also be a dedicated processor, which is a processor specifically designed to perform specific steps and / or operations. Dedicated processors can be, for example, but not limited to, ASICs and FPGAs. Additionally, the processor can be a combination of multiple processors, such as a multi-core processor. Communication interfaces can include input / output interfaces, physical interfaces, and logical interfaces used for interconnecting devices within a network device, as well as interfaces used for interconnecting network devices with other devices (e.g., network devices). Physical interfaces can be gigabit Ethernet interfaces, used for interconnecting network devices with other devices. Logical interfaces are internal interfaces of the network device, used for interconnecting devices within the network device. Buses can be of any type, used for interconnecting processors, memory, communication interfaces, and FPGA-based message processing devices. Specifically, interconnection between any device among the processor, memory, and communication interfaces and the FPGA-based message processing device can refer to the interconnection between that device and other devices within the FPGA-based message processing device.

[0058] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0059] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0061] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0062] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A message processing method based on FPGA implementation, characterized in that, The FPGA includes multiple first dual-port RAMs, each having a first port and a second port. Different first dual-port RAMs are configured with different rule templates. The method includes: For any first dual-port RAM, The pre-configured first rule template and second rule template are written from the first port / second port into the first dual-port RAM, wherein the first rule template is different from the second rule template. Obtain message feature information of the message to be processed, extract the message feature information using the first rule template to obtain first matching information, and extract the message feature information using the second rule template to obtain second matching information; The first information to be matched is matched with the first rule template through the first port, and the second information to be matched is matched with the second rule template through the second port at the same time, so as to obtain the first matching result corresponding to the first rule template and the second matching result corresponding to the second rule template. Based on the first matching result and the second matching result corresponding to each first dual-port RAM, the forwarding strategy of the message to be processed is determined.

2. The message processing method based on FPGA implementation according to claim 1, characterized in that, Writing to the first dual-port RAM from the first port / second port according to a pre-configured first rule template and second rule template includes: Construct a mapping relationship between the port number of the first port of the first dual-port RAM and the template number of the first rule template, and construct a mapping relationship between the port number of the second port of the first dual-port RAM and the template number of the second rule template; For any first rule configuration information in the first rule template, the first rule configuration information includes a first configuration keyword, rule number, priority and forwarding action. The first configuration keyword is at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. For any storage address of the first dual-port RAM, the first rule configuration information is written from the first port / second port to that storage address; And / or, For any second rule configuration information in the second rule template, the second rule configuration information includes a second configuration keyword, rule number, priority and forwarding action. The second configuration keyword is at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type. The first configuration keyword is different from the second configuration keyword. For any storage address of the first dual-port RAM, the second rule configuration information is written from the first port / second port to that storage address.

3. The message processing method based on FPGA implementation according to claim 2, characterized in that, The FPGA further includes multiple second dual-port RAMs, each of which corresponds one-to-one with the multiple first dual-port RAMs. Each dual-port RAM has a third port and a fourth port. The method further includes: For any second dual-port RAM, a cascading indication is set for the third port / fourth port of the second dual-port RAM. The cascading indication is used to indicate whether the first rule template corresponding to the first port of the corresponding first dual-port RAM supports cascading rules, and whether the second rule template corresponding to the second port supports cascading rules. When the cascading indicators for the third and fourth ports of each of the second dual-port RAMs are not enabled, among which, For any second dual-port RAM, based on the first rule template and the second rule template configured in the first dual-port RAM corresponding to the second dual-port RAM, a hash collision table corresponding to the first rule template and a hash collision table corresponding to the second rule template are configured in the second dual-port RAM through the third port / fourth port. Each hash collision entry in the hash collision table includes multiple hash collision sub-entries. Each hash collision sub-entry includes a valid bit, a port number, and a matching address. The valid bit indicates whether the hash collision sub-entry is idle or occupied. The port number is used to indicate the port number of the third port or the port number of the fourth port. The matching address is the storage address of the first dual-port RAM.

4. The message processing method based on FPGA implementation according to claim 3, characterized in that, Configure the hash collision table corresponding to the first rule template and the hash collision table corresponding to the second rule template in the second dual-port RAM through the third port / fourth port, including: For any first configuration keyword in the first rule template, the first hash algorithm and the second hash algorithm are used to calculate the first configuration keyword to obtain the first hash value and the second hash value. The first hash value is used as the storage address of the second dual-port RAM. The valid bits in each hash collision sub-item in the hash collision item corresponding to the storage address are read. If there is a hash collision sub-item with a free valid bit, the valid bit is filled with the occupancy, the second hash value, the port number of the third port, and the first storage address of the configured first dual-port RAM and written to the hash collision sub-item. If there is no hash collision sub-item with a free valid bit, overflow processing is performed. For any second configuration keyword in the second rule template, the first hash algorithm and the second hash algorithm are used to calculate the third hash value and the fourth hash value. The third hash value is used as the storage address of the second dual-port RAM. The valid bits in each hash collision sub-item in the hash collision item corresponding to the storage address are read. If there is a hash collision sub-item with a free valid bit, the valid bit is set to occupied, the fourth hash value, the port number of the fourth port, and the second storage address of the configured first dual-port RAM and written to the hash collision sub-item. If there is no hash collision sub-item with a free valid bit, overflow processing is performed.

5. The message processing method based on FPGA implementation according to claim 3, characterized in that, Extracting first matching information from the message feature information using the first rule template, and extracting second matching information from the message feature information using the second rule template, includes: Obtain message characteristic information of the message to be processed, wherein the message characteristic information is at least one of the following: source IP address, destination IP address, source port, destination port, IP protocol number, source MAC address, destination MAC address, VLAN, MPLS, and Ethernet type; Based on the mapping relationship between the port number of the first port of the first dual-port RAM and the template number of the first rule template, the first configuration keyword corresponding to the first port of the first dual-port RAM is determined, and the message feature information is filtered by the first configuration keyword to obtain the first matching information corresponding to the first configuration keyword. Based on the mapping relationship between the port number of the second port of the first dual-port RAM and the template number of the second rule template, the second configuration keyword corresponding to the second port of the first dual-port RAM is determined, and the message feature information is filtered by the second configuration keyword to obtain the second matching information corresponding to the second configuration keyword.

6. The message processing method based on FPGA implementation according to claim 5, characterized in that, The first information to be matched is matched with the first rule template through the first port, and the second information to be matched is matched with the second rule template through the second port, to obtain a first matching result corresponding to the first rule template and a second matching result corresponding to the second rule template, including: The first target hash value is obtained by performing a hash operation on the first information to be matched using a first hash algorithm. The first target hash value is used as the storage address of the second dual-port RAM. The first storage address of the corresponding first dual-port RAM is read from the storage address. The first information to be matched is matched with the first configuration keyword corresponding to the first storage address. The first matching result is output. The first matching result carries whether it hits, rule number, priority and forwarding action. The second target hash value is obtained by performing a hash operation on the second information to be matched using the first hash algorithm. The second target hash value is used as the storage address of the second dual-port RAM. The second storage address of the corresponding first dual-port RAM is read from the storage address. The second information to be matched is matched with the second configuration keyword corresponding to the second storage address. The second matching result is output. The second matching result carries whether it hits, rule number, priority and forwarding action. Based on the first matching result and the second matching result corresponding to each first dual-port RAM, the forwarding strategy for the packet to be processed is determined, including: Among the first matching results and the second matching results that have been matched, the forwarding action corresponding to the rule number with the highest priority is selected as the forwarding strategy for the message to be processed.

7. The message processing method based on FPGA implementation according to claim 2, characterized in that, The FPGA further includes multiple second dual-port RAMs, each of which corresponds one-to-one with the multiple first dual-port RAMs. Each dual-port RAM has a third port and a fourth port. The method further includes: For any second dual-port RAM, a cascading indication is set for the third port / fourth port of the second dual-port RAM. The cascading indication is used to indicate whether the first rule template corresponding to the first port of the corresponding first dual-port RAM supports cascading rules, and whether the second rule template corresponding to the second port supports cascading rules. When the cascading indication of the third / fourth port of each of the second dual-port RAMs is enabled, the first configuration keywords corresponding to each first port are concatenated into a cascading rule keyword, and the first configuration keywords corresponding to each second port are concatenated into a cascading rule keyword, wherein... For any one of the second dual-port RAMs, the first hash algorithm and the second hash algorithm are used to calculate the concatenation rule key to obtain the fifth hash value and the sixth hash value. The fifth hash value is used as the storage address of the second dual-port RAM. A corresponding hash collision sub-item is configured at the storage address. The hash collision sub-item includes the valid bit, the sixth hash value, the port number of the third port / fourth port, and the third storage address of the configured first dual-port RAM.

8. The message processing method based on FPGA implementation according to claim 7, characterized in that, The method further includes: The message feature information is filtered using the cascading rule keywords to obtain third matching information corresponding to the cascading rule keywords; The third target hash value is obtained by performing a hash operation on the third information to be matched using the first hash algorithm. In each second dual-port RAM, the third target hash value is used as the storage address of the second dual-port RAM. The storage address is used to read the third storage address of the corresponding first dual-port RAM, thereby obtaining the third storage address of each first dual-port RAM. Read the corresponding first configuration keywords from the third storage address of each first dual-port RAM; The third information to be matched is matched with each of the first configuration keywords according to the rules. If each of the first configuration keywords is matched at the same time, it is determined that the message to be processed matches the cascading rule keywords.

9. A message processing device based on FPGA, characterized in that, The FPGA includes multiple first dual-port RAMs, each having a first port and a second port. Different first dual-port RAMs are configured with different rule templates. The device includes: The configuration module is used to write a pre-configured first rule template and a second rule template from the first port / second port into the first dual-port RAM for any one of the first dual-port RAMs, wherein the first rule template and the second rule template are different; The message processing module is used to obtain message feature information of the message to be processed, extract the message feature information using the first rule template to obtain first matching information, and extract the message feature information using the second rule template to obtain second matching information. The rule matching module is used to match the first information to be matched with the first rule template through the first port, and at the same time match the second information to be matched with the second rule template through the second port, so as to obtain a first matching result corresponding to the first rule template and a second matching result corresponding to the second rule template. A strategy template is used to determine the forwarding strategy of the packet to be processed based on the first matching result and the second matching result corresponding to each first dual-port RAM.

10. A smart network interface card (NIC), characterized in that, The smart network interface card includes the packet processing device based on FPGA as described in claim 9.

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