Method and system for converting gigabit ethernet and PCIe protocols based on FPGA

Abstract

This invention discloses a method and system for 10 Gigabit Ethernet to PCIe protocol conversion based on FPGA. The method is implemented using FPGA and includes: optimizing the TCP receiving module in the network protocol stack; converting PCIe data to 10 Gigabit Ethernet UDP / TCP data; and converting the UDP / TCP data received from 10 Gigabit Ethernet back to PCIe data. This invention utilizes the parallel processing capabilities of FPGA to implement the conversion between 10 Gigabit Ethernet and PCIe interface protocols in hardware, eliminating the need for CPU intervention and external DDR memory, thus reducing system overhead and improving system performance.

Description

Technical Field

[0001] This invention relates to the field of communication link conversion technology, and more specifically, to a method and system for converting 10 Gigabit Ethernet and PCIe protocols based on FPGA. Background Technology

[0002] With the rapid development of embedded technology, Field-Programmable Gate Arrays (FPGAs) are increasingly widely used in electronic systems due to their low latency, strong parallel processing capabilities, and high flexibility. In the field of high-speed data communication, both 10 Gigabit Ethernet (10 Gigabit Ethernet) and PCIe interfaces are common high-speed data transmission interfaces. 10 Gigabit Ethernet is mainly used for long-distance communication between devices, while PCIe is mainly used for high-speed peripheral connections within the host computer. In practical applications, it is often necessary to achieve data interoperability between 10 Gigabit Ethernet and PCIe. For example, in scenarios such as high-speed data acquisition, network accelerator cards, and industrial control, it is necessary to convert network data to PCIe for host processing, or to send host data to the network via 10 Gigabit Ethernet.

[0003] In existing technologies, data interaction between 10 Gigabit Ethernet and PCIe typically relies on the central processing unit (CPU) to process protocols via software. Specifically, when data is transmitted from 10 Gigabit Ethernet to a PCIe device, the CPU needs to participate in the parsing of Transmission Control Protocol (TCP) or User Datagram Protocol (UDP) and Internet Protocol (IP), and then send the parsed data through the PCIe interface; conversely, when data is transmitted from a PCIe device to 10 Gigabit Ethernet, the CPU also needs to encapsulate it using TCP or UDP protocols and IP protocols. This CPU-dependent protocol processing approach has the following technical drawbacks: 1) CPU participation in the parsing and encapsulation of the network protocol stack consumes a large amount of processor resources, increasing system overhead; 2) Software processing is limited by the CPU's clock speed and the operating system's scheduling mechanism, making it difficult to achieve nanosecond-level low-latency transmission; 3) Traditional solutions typically require external DDR memory for data caching to match the speed differences between different interfaces, increasing the complexity of system design, hardware costs, and PCB area; 4) In some existing hardware implementations, the TCP protocol processing module typically requires a large amount of Block Random Access Memory (BRAM) resources for data caching and reassembly, causing resource shortages within the FPGA and limiting the implementation of other functional modules.

[0004] Therefore, how to achieve efficient protocol conversion between 10 Gigabit Ethernet and PCIe, reduce CPU overhead, reduce hardware resource consumption, and improve transmission efficiency has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This invention provides a method and system for converting 10 Gigabit Ethernet and PCIe protocols based on FPGA. By utilizing the parallel processing characteristics of FPGA, the conversion between 10 Gigabit Ethernet and PCIe interface protocols is implemented in hardware, without the need for CPU intervention and external DDR memory, thereby reducing system overhead and improving system performance.

[0006] The technical solution adopted in this invention is: A method for converting between 10 Gigabit Ethernet and PCIe protocols based on FPGA, the method being implemented using FPGA; the method includes: Optimize the TCP receive module in the network protocol stack; PCIe data to 10 Gigabit Ethernet UDP / TCP data conversion: The XDMA IP core receives PCIe data sent by the host and writes it into the first BRAM. When the amount of data in the first BRAM reaches a first preset threshold, the protocol conversion module starts reading the first BRAM, reads data of a preset length and writes it into the FIFO buffer for buffering, and converts the data into an AXI4-Stream format signal for output. The 10 Gigabit Ethernet transmitting module encapsulates the AXI4-Stream format signal with UDP / TCP, IP, and MAC protocols, and then sends it to external network devices through the 10G Ethernent Subsystem IP core. UDP / TCP data received via 10 Gigabit Ethernet is converted into PCIe data: Ethernet data sent by external network devices is received through the 10 Gigabit Ethernet receiving module. After sequential parsing of MAC protocol, IP protocol, and UDP / TCP protocol, the payload data is extracted. The protocol conversion module writes the payload data into a FIFO buffer for buffering. When the amount of data in the FIFO buffer reaches a second preset threshold, a write operation to the second BRAM is initiated to write the data into the second BRAM. When the amount of data in the second BRAM reaches a third preset threshold, the protocol conversion module sends an interrupt signal to the host to notify the host to read the data in the second BRAM.

[0007] Furthermore, the TCP receiving module optimization step, which does not require the use of BRAM resources for data caching, specifically includes: During TCP packet reception, the first data packet and the data validity signal are acquired; the data validity signal is used to indicate the number of valid bytes in the current data packet. Based on the data validity signal, determine whether the first data packet is pre-aligned by a preset byte: if it is pre-aligned by a preset byte, output the data directly; if it is not pre-aligned by a preset byte, use the data validity signal as the shift signal for the next data packet, and concatenate the tail of the first data packet with the head of the shifted next data packet to form a new byte-aligned data frame. Subsequent data packets will repeat the same operation until all data packets are converted into data frames aligned to the preset bytes and then output.

[0008] Furthermore, the PCIe data to 10 Gigabit Ethernet UDP / TCP data conversion step also includes a timeout processing step: when the amount of data in the first BRAM does not reach the first preset threshold, and the amount of remaining data in the FIFO buffer is less than the preset length, and the waiting time exceeds the preset timeout duration, all remaining data in the FIFO buffer is read at once.

[0009] Furthermore, the conversion of UDP / TCP data received via 10 Gigabit Ethernet into PCIe data also includes timeout processing: when the amount of data in the second BRAM has not reached the third preset threshold and the waiting time exceeds the preset timeout duration, the protocol conversion module sends an interrupt signal to the host, notifying the host to read all remaining data in the second BRAM.

[0010] Furthermore, the network protocol stack supports UDP and TCP protocol transmission functions, and supports ARP request and response, broadcast addressing, and PING request and response functions; the network protocol stack can be configured as a client mode or a server mode according to application requirements.

[0011] Furthermore, the XDMA IP core is configured to perform PCIe data transmission and reception operations using the first BRAM and the second BRAM without requiring an external DDR memory.

[0012] Another technical solution adopted by the present invention is: A 10 Gigabit Ethernet to PCIe protocol conversion system based on FPGA, wherein the system is deployed on an FPGA and the FPGA integrates: The PCIe transceiver module includes an XDMA IP core, a first BRAM, and a second BRAM. It interacts with the host via the XDMA IP core. The XDMA IP core is connected to the first BRAM and the second BRAM via an AIX interface. It is used to write PCIe data sent by the host into the first BRAM and to read data from the second BRAM and send it to the host in response to the host's interrupt signal. The protocol conversion module is connected to the first BRAM, the second BRAM and the 10 Gigabit Ethernet transceiver module respectively. It includes a FIFO buffer and programmable logic resources, and is used to implement the format conversion and buffer control between PCIe data and 10 Gigabit Ethernet data. The 10 Gigabit Ethernet transceiver module includes a 10G Ethernent Subsystem IP core, a MAC protocol processing unit, an IP protocol processing unit, and a network protocol stack processing unit. The 10G Ethernent Subsystem IP core enables UDP / TCP data transmission and reception with external network devices. The MAC protocol processing unit, IP protocol processing unit, and network protocol stack processing unit are used to encapsulate or parse the 10 Gigabit Ethernet physical layer protocol, MAC layer protocol, IP protocol, and UDP / TCP protocol.

[0013] Furthermore, the network protocol stack processing unit includes a TCP receiving module, which includes: The data buffer unit, connected to the MAC protocol processing unit, is used to receive and temporarily store TCP data frames transmitted by the MAC layer. The protocol parsing unit, connected to the data buffer unit, is used to parse the header information of TCP data frames and verify the integrity of the data frames. The timeout processing unit is connected to the protocol parsing unit and the data buffer unit respectively, and is used to trigger a retransmission request or error handling mechanism when a data reception timeout or abnormality is detected. The data forwarding unit, connected to the protocol parsing unit and the protocol conversion module, is used to transmit the parsed valid TCP data to the protocol conversion module.

[0014] Furthermore, the protocol conversion module also includes a timeout processing unit, which is used to trigger the transmission or interruption request of the remaining data when the waiting time exceeds the preset timeout duration and the data volume does not reach the preset threshold.

[0015] Compared with the prior art, the present invention has the following advantages: 1) This invention uses FPGA hardware to implement the conversion between 10 Gigabit Ethernet protocol and PCIe protocol, eliminating the need for CPU to participate in network protocol stack processing, greatly reducing system overhead, and achieving high bandwidth and low latency data transmission, which can meet the needs of latency-sensitive application scenarios such as high-frequency trading and real-time control; 2) This invention optimizes the TCP receiving module in the 10 Gigabit Ethernet protocol stack. It achieves 8-byte alignment by data splicing, eliminating the need for BRAM resources for caching, reducing the network protocol stack's occupation of BRAM resources, reducing the consumption of internal FPGA resources, and freeing up storage resources on the FPGA for other functional modules. 3) This invention can complete PCIe data transmission and reception operations using only the on-chip BRAM resources of the FPGA, without the need for external DDR memory, which simplifies the system hardware design, reduces system cost and complexity, and reduces PCB area and system power consumption. 4) This invention incorporates a timeout handling mechanism during the protocol conversion process. When the amount of data does not reach the preset threshold and the waiting time exceeds the preset timeout duration, it actively triggers the sending or interruption request of the remaining data to ensure the integrity of data transmission and avoid transmission failure caused by data retention. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a block diagram of a 10 Gigabit Ethernet to PCIe protocol conversion system based on FPGA according to the present invention; Figure 2 This is a schematic diagram of the principle structure of the network client protocol stack in this invention; Figure 3 This is a schematic diagram of the principle structure of the network server-side protocol stack in this invention; Figure 4 This is a schematic diagram of the data frame format received by the TCP receiving module in this invention; Figure 5 This is a flowchart illustrating the optimized processing of the TCP receiving module in this invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0018] like Figure 1 As shown in the figure, this embodiment provides an FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion system. The system is deployed on an FPGA, which integrates a PCIe transceiver module, a protocol conversion module, and a 10 Gigabit Ethernet transceiver module.

[0019] The PCIe transceiver module is mainly implemented using the XDMA IP core and BRAM resources. The XDMA IP core is an IP core provided by a certain company for implementing PCIe and Direct Memory Access (DMA) functions. It can be configured in endpoint mode and supports high-speed data exchange with the host.

[0020] In this embodiment, the PCIe transceiver module includes an XDMA IP core, a first BRAM, and a second BRAM. The first BRAM is used to cache PCIe data sent by the host, and the second BRAM is used to cache UDP / TCP data to be uploaded to the host. The XDMA IP core is responsible for processing PCIe data, converting the host's memory write request into a write operation to the first BRAM, and simultaneously responding to the host's memory read request by reading data from the second BRAM and returning it to the host.

[0021] The 10 Gigabit Ethernet transceiver module is mainly implemented through a 10G Ethernet Subsystem IP core. This IP core is provided by a certain company to implement 10 Gigabit Ethernet functionality, integrating the MAC layer and physical layer protocol processing functions of 10 Gigabit Ethernet.

[0022] In this embodiment, a network protocol stack is further constructed on this basis, including Address Resolution Protocol (ARP) request and response, broadcast addressing, Internet Control Message Protocol (ICMP) PING request and response, UDP sending and receiving, TCP sending and receiving, and other functions. Figure 2 and Figure 3 As shown, the network protocol stack can be configured in client or server mode, allowing users to choose the appropriate mode based on their application needs. The network protocol stack is implemented using a hardware description language and is entirely completed within the programmable logic resources of the FPGA, requiring no CPU intervention.

[0023] The protocol conversion module connects the PCIe transceiver module and the 10 Gigabit Ethernet transceiver module. It mainly includes a first-in-first-out (FIFO) buffer and programmable logic resources, responsible for data format conversion and buffer control. The protocol conversion module adapts the AXI4-Stream format signals to the BRAM read / write interface, and manages the data length.

[0024] In actual operation, the system described in this invention utilizes a PCIe transceiver module, a protocol conversion module, and a 10 Gigabit Ethernet transceiver module working in parallel to achieve full-duplex bidirectional data transmission. Specifically, when the host needs to send data, the data stream passes through the PCIe transceiver module, enters the protocol conversion module, and is then sent out via the 10 Gigabit Ethernet transceiver module. When data arrives on the network, the data stream passes through the 10 Gigabit Ethernet transceiver module, enters the protocol conversion module, and is then uploaded to the host via the PCIe transceiver module. The data streams in both directions are independent of each other, isolated and rate-matched through a FIFO buffer within the protocol conversion module, enabling simultaneous, bidirectional data transmission and fully leveraging the high-speed performance of 10 Gigabit Ethernet and PCIe.

[0025] This implementation provides a method for converting between 10 Gigabit Ethernet and PCIe protocols based on FPGA, including the following steps: Step 1: Optimize the TCP receive module in the network protocol stack. like Figure 5 As shown, the optimized processing flow is as follows: During TCP packet reception, the first data packet and the data validity signal are acquired; the data validity signal is used to indicate the number of valid bytes in the current data packet. Based on the data validity signal, determine whether the first data packet is pre-aligned by a preset byte: if it is pre-aligned by a preset byte, output the data directly; if it is not pre-aligned by a preset byte, use the data validity signal as the shift signal for the next data packet, and concatenate the tail of the first data packet with the head of the shifted next data packet to form a new byte-aligned data frame. Subsequent data packets will repeat the same operation until all data packets are converted into data frames aligned to the preset bytes and then output.

[0026] In this embodiment, the preset byte size is 8 bytes. The current data packet and data validity signal are acquired. The data validity signal is used to determine whether the data packet tail is 8-byte aligned, i.e., whether the value of the data validity signal is a multiple of 8. If the current data packet tail is 8-byte aligned, the data is output directly; if the current data packet tail is not 8-byte aligned, ... Figure 4 As shown, if the current data packet only has 4 bytes of data at the end, the next data packet will shift its entire data 4 bytes to the right and concatenate the current data packet's data with the next data packet's data at the beginning to form a new 8-byte aligned data frame. Subsequent data packets will perform the same operation in sequence, dynamically adjusting the continuous data stream to an 8-byte aligned output through shifting and concatenation.

[0027] Note: In traditional TCP receive module designs, due to the variable length of TCP packets and the possibility that packet tails may not align to byte boundaries for subsequent processing, BRAM buffering is typically required for temporary data storage and reassembly. This approach consumes valuable BRAM resources, increasing FPGA resource consumption, especially in high-throughput scenarios like 10 Gigabit Ethernet, where BRAM resource consumption is even more significant. To address these issues, the TCP receive module in the network protocol stack is optimized by shifting and concatenating data to achieve byte alignment. The entire alignment process does not require BRAM buffering; it can be completed using only shift registers and combinational logic. The shift registers are implemented using FPGA flip-flops and lookup tables, without consuming BRAM resources. Compared to traditional solutions that require BRAM buffering of the entire data packet before reassembly, this invention significantly reduces the network protocol stack's BRAM resource consumption, freeing up FPGA storage resources for other functional modules.

[0028] Step 2: The PCIe data received by the XDMA IP core is converted into 10 Gigabit Ethernet UDP / TCP data; the specific process is as follows: 1) The PCIe data sent by the host is written into the first BRAM through the XDMA IP core; the XDMA IP core is responsible for processing the PCIe transaction layer protocol and converting the memory write request initiated by the host into a write operation to the first BRAM; the first BRAM adopts a dual-port RAM design, with one end connected to the XDMA IP core for writing and the other end connected to the protocol conversion module for reading. 2) The protocol conversion module monitors the amount of data in the first BRAM in real time. When the amount of data written to the first BRAM reaches the first preset threshold N, the protocol conversion module starts reading the first BRAM. The length of the data read is the maximum transmission unit (MTU) of 10 Gigabit Ethernet. This length can be adjusted according to the actual network configuration, usually 1518 bytes or 9000 bytes. The read data is first written to the FIFO buffer for buffering, and then converted into an AXI4-Stream format signal for output to the 10 Gigabit Ethernet transmitting module. The AXI4-Stream format is a standard interface defined by a certain company for high-speed data stream transmission, which includes data signals, valid signals, ready signals, and last signals. 3) After receiving the AXI4-Stream format signal, the 10 Gigabit Ethernet transmitting module encapsulates it sequentially via UDP / TCP, IP, and MAC protocols according to the configured transmission protocol type. The UDP encapsulation adds a UDP header, including source port, destination port, length, and checksum fields. The TCP encapsulation adds a TCP header, including source port, destination port, sequence number, acknowledgment number, and flags. The IP encapsulation adds an IP header, including source IP address, destination IP address, and protocol type fields. The MAC encapsulation adds an Ethernet header, including source MAC address, destination MAC address, and type fields. Finally, the 10G Ethernet Subsystem IP core converts the encapsulated data frame into serial data and sends it to the external network device via the physical layer.

[0029] As a further step in this embodiment, to ensure the integrity of data transmission, a timeout handling mechanism is added during the protocol conversion process. Specifically, when the amount of data in the first BRAM has not reached the first preset threshold N, but the amount of remaining data in the FIFO buffer is less than the preset length M, and the waiting time exceeds the preset timeout duration of 1 millisecond, the protocol conversion module will read all the remaining data in the FIFO buffer at once and send it out through the 10 Gigabit Ethernet transmission module. This mechanism avoids the problem of data being stuck for a long time due to insufficient data volume, ensuring the timeliness and integrity of data transmission.

[0030] Note: This step enables data transmission from the host PCIe interface to the 10 Gigabit Ethernet interface. PCIe reception processing can be completed using only the on-chip BRAM resources of the FPGA, eliminating the need for external DDR memory and simplifying hardware design. At the same time, the timeout handling mechanism ensures the integrity of 10 Gigabit Ethernet data transmission and avoids data loss.

[0031] Step 3: Convert the UDP / TCP data received via 10 Gigabit Ethernet into PCIe data; the specific process is as follows: 1) The 10G Ethernet Subsystem IP core receives data sent by external network devices, processes it through the physical layer and MAC layer, and extracts the Ethernet frame; then, the network protocol stack performs the following steps in sequence: MAC protocol parsing to extract IP packets; IP protocol parsing, determining the upper-layer protocol type based on the protocol field in the IP header, and extracting UDP / TCP packets; UDP / TCP protocol parsing, extracting the payload data. 2) The protocol conversion module writes the extracted payload data into a FIFO buffer for caching. When the amount of data cached in the FIFO buffer reaches the second preset threshold N, the protocol conversion module initiates a write operation to the second BRAM, writing the data in the FIFO into the second BRAM. The second BRAM also adopts a dual-port RAM design, with one end connected to the protocol conversion module for writing and the other end connected to the XDMA IP core for reading. The second preset threshold is equal to the first preset threshold. 3) When the amount of data written to the second BRAM reaches the third preset threshold M, the protocol conversion module sends an XDMA interrupt request to the host; the XDMA IP core supports the interrupt mechanism and can send a message signal to the host to interrupt MSI or MSI-X; after the host detects the interrupt signal, it starts the XDMA read operation of the second BRAM and uploads the data to the host through the PCIe bus; wherein, the third preset threshold is equal to the preset length; As a further step in this embodiment, similar to the sending direction, a timeout handling mechanism is also added to the receiving direction. Specifically, when the amount of data written in the second BRAM has not reached the third preset threshold M, and the waiting time exceeds the preset timeout duration of 1 millisecond, the protocol conversion module directly sends an interrupt signal to the host, notifying the host to read all remaining data in the second BRAM. This mechanism ensures the timeliness and integrity of data upload.

[0032] Note: This step enables data transmission from the 10 Gigabit Ethernet interface to the host PCIe interface. PCIe transmission processing can be completed using only the BRAM resources on the FPGA, without the need for external DDR memory. At the same time, the timeout handling mechanism ensures the integrity of PCIe data upload.

[0033] This invention uses FPGA hardware to implement protocol conversion, eliminating the need for CPU participation in network protocol stack processing. Data transmission and reception can be completed using only the BRAM resources on the FPGA, and a timeout handling mechanism is added to ensure data integrity. It features low latency, high bandwidth, and low resource consumption.

[0034] It should be noted that the technical solution of this invention is not only applicable to 10 Gigabit Ethernet, but can also be extended to other Ethernet interfaces of different speeds, such as Gigabit Ethernet, 40 Gigabit Ethernet, and 100 Gigabit Ethernet, depending on actual needs. This can be achieved simply by replacing the corresponding Ethernet IP core and adjusting the data path width. Furthermore, the 8-byte alignment optimization method of the TCP receive module can also be adjusted to other alignment granularities, such as 16-byte alignment, 32-byte alignment, and 64-byte alignment, to meet the needs of different application scenarios.

[0035] Furthermore, the protocol conversion method of the present invention is not only applicable to the conversion between 10 Gigabit Ethernet and PCIe, but can also be extended to the protocol conversion between other high-speed interfaces, such as USB and PCIe, SATA and PCIe, etc., simply by replacing the corresponding interface IP core and maintaining the general design of the protocol conversion module.

[0036] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the principles and essence of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for converting between 10 Gigabit Ethernet and PCIe protocols based on FPGA, characterized in that, The method is implemented based on FPGA; the method includes: Optimize the TCP receive module in the network protocol stack; PCIe data to 10 Gigabit Ethernet UDP / TCP data conversion: The XDMA IP core receives PCIe data sent by the host and writes it into the first BRAM. When the amount of data in the first BRAM reaches a first preset threshold, the protocol conversion module starts reading the first BRAM, reads data of a preset length and writes it into the FIFO buffer for buffering, and converts the data into an AXI4-Stream format signal for output. The 10 Gigabit Ethernet transmitting module encapsulates the AXI4-Stream format signal with UDP / TCP, IP, and MAC protocols, and then sends it to external network devices through the 10G Ethernent Subsystem IP core. UDP / TCP data received via 10 Gigabit Ethernet is converted into PCIe data: Ethernet data sent by external network devices is received through the 10 Gigabit Ethernet receiving module. After sequential parsing of MAC protocol, IP protocol, and UDP / TCP protocol, the payload data is extracted. The protocol conversion module writes the payload data into a FIFO buffer for buffering. When the amount of data in the FIFO buffer reaches a second preset threshold, a write operation to the second BRAM is initiated to write the data into the second BRAM. When the amount of data in the second BRAM reaches a third preset threshold, the protocol conversion module sends an interrupt signal to the host to notify the host to read the data in the second BRAM.

2. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion method according to claim 1, characterized in that, The TCP receive module optimization steps, which do not require the use of BRAM resources for data caching, specifically include: During TCP packet reception, the first data packet and the data validity signal are acquired; the data validity signal is used to indicate the number of valid bytes in the current data packet. Based on the data validity signal, determine whether the first data packet is pre-aligned by a preset byte: if it is pre-aligned by a preset byte, output the data directly; if it is not pre-aligned by a preset byte, use the data validity signal as the shift signal for the next data packet, and concatenate the tail of the first data packet with the head of the shifted next data packet to form a new byte-aligned data frame. Subsequent data packets will undergo the same operation repeatedly until all data packets are converted into data frames aligned to the preset bytes and then output.

3. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion method according to claim 1, characterized in that, The process of converting PCIe data to 10 Gigabit Ethernet UDP / TCP data also includes a timeout handling step: when the amount of data in the first BRAM does not reach the first preset threshold, the amount of remaining data in the FIFO buffer is less than the preset length, and the waiting time exceeds the preset timeout duration, all remaining data in the FIFO buffer is read at once.

4. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion method according to claim 1, characterized in that, The conversion of UDP / TCP data received via 10 Gigabit Ethernet into PCIe data also includes timeout handling: when the amount of data in the second BRAM has not reached the third preset threshold and the waiting time exceeds the preset timeout duration, the protocol conversion module sends an interrupt signal to the host, notifying the host to read all remaining data in the second BRAM.

5. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion method according to claim 1, characterized in that, The network protocol stack supports UDP and TCP protocol transmission functions, and supports ARP request and response, broadcast addressing, and PING request and response functions; the network protocol stack can be configured as client mode or server mode according to application requirements.

6. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion method according to claim 1, characterized in that, The XDMA IP core is configured to perform PCIe data transmission and reception operations using the first BRAM and the second BRAM without requiring an external DDR memory.

7. An FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion system, characterized in that, The system is deployed based on an FPGA, which integrates: The PCIe transceiver module includes an XDMA IP core, a first BRAM, and a second BRAM. It interacts with the host via the XDMA IP core. The XDMA IP core is connected to the first BRAM and the second BRAM via an AIX interface. It is used to write PCIe data sent by the host into the first BRAM and to read data from the second BRAM and send it to the host in response to the host's interrupt signal. The protocol conversion module is connected to the first BRAM, the second BRAM and the 10 Gigabit Ethernet transceiver module respectively. It includes a FIFO buffer and programmable logic resources, and is used to implement the format conversion and buffer control between PCIe data and 10 Gigabit Ethernet data. The 10 Gigabit Ethernet transceiver module includes a 10G Ethernent Subsystem IP core, a MAC protocol processing unit, an IP protocol processing unit, and a network protocol stack processing unit. The 10G Ethernent Subsystem IP core enables UDP / TCP data transmission and reception with external network devices. The MAC protocol processing unit, IP protocol processing unit, and network protocol stack processing unit are used to encapsulate or parse the 10 Gigabit Ethernet physical layer protocol, MAC layer protocol, IP protocol, and UDP / TCP protocol.

8. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion system according to claim 7, characterized in that, The network protocol stack processing unit includes a TCP receiving module, which includes: The data buffer unit, connected to the MAC protocol processing unit, is used to receive and temporarily store TCP data frames transmitted by the MAC layer. The protocol parsing unit, connected to the data buffer unit, is used to parse the header information of TCP data frames and verify the integrity of the data frames. The timeout processing unit is connected to the protocol parsing unit and the data buffer unit respectively, and is used to trigger a retransmission request or error handling mechanism when a data reception timeout or abnormality is detected. The data forwarding unit, connected to the protocol parsing unit and the protocol conversion module, is used to transmit the parsed valid TCP data to the protocol conversion module.

9. The FPGA-based 10 Gigabit Ethernet to PCIe protocol conversion system according to claim 7, characterized in that, The protocol conversion module also includes a timeout processing unit, which is used to trigger the transmission or interruption request of the remaining data when the waiting time exceeds the preset timeout duration and the data volume does not reach the preset threshold.

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