A data alignment circuit based on a time-interleaved ADC topology

Abstract

The application discloses a data alignment circuit based on a time-interleaved ADC topology and relates to the technical field of analog-to-digital converters, and aims to solve the problem of inaccurate timing correspondence in the data conversion process of a traditional data alignment circuit. The data alignment circuit comprises a first-stage flip-flop circuit, a second-stage flip-flop circuit and a third-stage flip-flop circuit; the clock input ends of the flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC; the output end of the third-stage flip-flop circuit is connected to the input end of a serializer-deserializer; the first-stage flip-flop circuit comprises a plurality of first flip-flop sub-circuits; the data input ends of the first flip-flop sub-circuits are connected to the sub-ADCs in different rows of the time-interleaved ADC, respectively. The data alignment circuit based on the time-interleaved ADC topology can be used to keep accurate timing correspondence in the process of massive data conversion and transmission between the time-interleaved ADC and the serializer-deserializer.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more particularly to a data alignment circuit based on a time-interleaved ADC topology. Background Technology

[0002] Analog-to-digital converters (ADCs), as the core bridge connecting the physical analog world and digital processing systems, directly determine the capability boundaries of the entire electronic system. With the rapid development of wireless communication, radar detection, high-speed oscilloscopes, and other fields, the requirements for signal bandwidth, dynamic range, sampling rate, and resolution in electronic systems are increasing rapidly. Time-interleaved (TI) ADCs use a set of sampling clocks with precise phase differences to control sub-channel ADCs to alternately sample and quantize the same analog signal. This ingeniously combines multiple sub-channel ADCs in parallel in the time domain, breaking through the technological limitations of single-channel ADC sampling rates and multiplying the ADC sampling rate, thus becoming the mainstream architecture for ultra-high-speed ADCs.

[0003] As sampling rates advance towards the GSps level, time-interleaved ADCs are widely used. ADCs generate raw data streams of up to tens of Gbps per second, exceeding the transmission limits of traditional parallel buses. At this point, serializer-deserializers (SERDES) become the inevitable choice for high-speed data transmission. SERDES acts like a data highway, converting wide-band parallel data streams into high-speed serial streams, achieving ultra-high data throughput with only a few differential pairs. However, the output of a time-interleaved ADC is multi-channel parallel timing data, while the input of a SERDES is serialized timing data; the two have inherent differences in data bit width, transmission timing, and synchronization.

[0004] Therefore, how to provide a data alignment circuit based on time-interleaved ADC topology to ensure accurate timing correspondence during the conversion and transmission of massive amounts of data between time-interleaved ADC and SERDES inputs has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a data alignment circuit based on a time-interleaved ADC topology, which maintains accurate timing correspondence during massive data conversion and transmission between a time-interleaved ADC and a serializer-decoder.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A data alignment circuit based on time-interleaved ADC topology includes a first-stage flip-flop circuit, a second-stage flip-flop circuit, and a third-stage flip-flop circuit. The output of the first-stage flip-flop circuit is connected to the data input of the second-stage flip-flop circuit, and the output of the second-stage flip-flop circuit is connected to the data input of the third-stage flip-flop circuit; the clock inputs of the first-stage flip-flop circuit, the second-stage flip-flop circuit, and the third-stage flip-flop circuit are connected to the sampling clock of the sub-ADC of the time-interleaved ADC; the output of the third-stage flip-flop circuit is connected to the input of the serializer-deserializer. The first-stage trigger circuit includes multiple first trigger sub-circuits; the data input terminal of each first trigger sub-circuit is respectively connected to a sub-ADC in a different row of the time-interleaved ADC.

[0007] Optionally, the sub-ADCs of the time-interleaved ADC are arranged in an array of M rows × N columns, where M and N are both positive integers. The number of the first flip-flop sub-circuits in the first-stage flip-flop circuit is 1 / n times M, where n is a positive integer greater than or equal to 1. Each first flip-flop sub-circuit includes n × N D flip-flops, and the clock inputs of all the D flip-flops in the first flip-flop sub-circuit are connected. The second-stage flip-flop circuit includes a single-stage flip-flop circuit or multiple cascaded flip-flop circuits, and the number of stages in the second-stage flip-flop circuit is... .

[0008] Optionally, any row of sub-ADCs in the time-interleaved ADC includes a first sub-ADC and a second sub-ADC; the first flip-flop sub-circuit includes a first D flip-flop and a second D flip-flop, the data input terminal of the first D flip-flop is connected to the output terminal of the first sub-ADC, and the data input terminal of the second D flip-flop is connected to the output terminal of the second sub-ADC; the clock input terminals of the first D flip-flop and the second D flip-flop are connected to a first target sampling clock; the first target sampling clock is a sub-ADC sampling clock whose sampling time is located within the overlapping period of the sampling clocks of the first sub-ADC and the second sub-ADC.

[0009] Optionally, when the second-stage flip-flop circuit includes a first-stage flip-flop circuit, the second-stage flip-flop circuit includes M / 2 second flip-flop sub-circuits; the clock inputs of all D flip-flops in the second flip-flop sub-circuits are connected; the second flip-flop sub-circuits are connected to the outputs of the two first flip-flop sub-circuits with the shortest latching time interval.

[0010] Optionally, the clock input of the second flip-flop sub-circuit is connected to a second target sampling clock; the second target sampling clock is a sub-ADC sampling clock whose sampling time is within the overlapping period of the first sampling clock and the second sampling clock; the first sampling clock and the second sampling clock are sub-ADC sampling clocks corresponding to the latching times of the two first flip-flop sub-circuits connected to the second flip-flop sub-circuit.

[0011] Optionally, the clock input terminals of all D flip-flops in the third-stage flip-flop circuit are connected; the D flip-flops in the third-stage flip-flop circuit are connected one-to-one with the D flip-flops in the second-stage flip-flop circuit.

[0012] Optionally, the clock input of the third-stage flip-flop circuit is connected to a third target sampling clock; the third target sampling clock is a sub-ADC sampling clock whose sampling time is located within the overlapping clock of the third sampling clock and the fourth sampling clock; the third sampling clock and the fourth sampling clock are sub-ADC sampling clocks corresponding to the latching time of the second flip-flop sub-circuit.

[0013] Optionally, the number of D flip-flops in the first-stage flip-flop circuit, the second-stage flip-flop circuit, and the third-stage flip-flop circuit is the same as the number of sub-ADCs in the time-interleaved ADC.

[0014] Optionally, the first trigger sub-circuit is connected to the sub-ADCs in adjacent n rows of the time-interleaved ADC.

[0015] Optionally, if there are multiple sub-ADC sampling clocks whose sampling time falls within the overlapping period of the sampling clocks of the first sub-ADC and the second sub-ADC, then the sub-ADC sampling clock with the shortest interval between its sampling time and the midpoint of the target overlapping period is determined as the first target sampling clock, and the target overlapping period is the overlapping period of the sampling clocks of the first sub-ADC and the second sub-ADC.

[0016] Compared with existing technologies, this invention provides a data alignment circuit based on a time-interleaved ADC topology, comprising a first-stage flip-flop circuit, a second-stage flip-flop circuit, and a third-stage flip-flop circuit. The output of the first-stage flip-flop circuit is connected to the data input of the second-stage flip-flop circuit, and the output of the second-stage flip-flop circuit is connected to the data input of the third-stage flip-flop circuit. The clock inputs of the first-stage, second-stage, and third-stage flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC. The output of the third-stage flip-flop circuit is connected to the input of the serializer-deserializer. The first-stage flip-flop circuit includes multiple first-stage flip-flop sub-circuits. This data alignment circuit utilizes the D flip-flops in the first-stage, second-stage, and third-stage flip-flop circuits to buffer the output results of the ADC, thereby aligning the sub-ADC output data of all channels to a low-speed clock edge before transmitting it to SERDES. The data alignment circuit, based on the layout of the time-interleaved sub-ADCs, connects the data input terminals of each first flip-flop sub-circuit to corresponding sub-ADCs in different rows of the time-interleaved ADC. This fully considers the setup and hold times of digital signals, reducing the risk of metastability and timing violations. It ensures accurate timing correspondence between the time-interleaved ADC and the serializer-decoder during massive data conversion and transmission, improving circuit reliability. Furthermore, this invention utilizes the sub-ADCs of the time-interleaved ADC as the trigger clock for the flip-flops, eliminating the need for additional circuitry to generate a low-frequency clock. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 The present invention provides a time-interleaved ADC and SERDES system framework; Figure 2 A schematic diagram of a data alignment circuit based on a time-interleaved ADC topology is provided for this invention. Figure 3 This is a schematic diagram showing the connection relationship between the first trigger sub-circuit and the sub-ADC provided by the present invention; Figure 4 This invention provides a layout diagram of a 2×4 array time-interleaved ADC. Figure 5 The timing diagram of the 8-channel time-interleaved ADC provided by this invention; Figure 6 The data alignment circuit diagram based on an 8-channel time-interleaved ADC provided by this invention; Figure 7This is a time-series diagram illustrating the data alignment provided by the present invention.

[0018] Figure label: 1-First stage flip-flop circuit, 11-First flip-flop sub-circuit, 111-First D flip-flop, 112-Second D flip-flop, 2-Second stage flip-flop circuit, 21-Second flip-flop sub-circuit, 3-Third stage flip-flop circuit, 4-Time-interleaved ADC, 41-First sub-ADC, 42-Second sub-ADC, 5-Time-interleaved ADC sampling clock generation circuit, 51-First target sampling clock, 6-Serializer-decoder. Detailed Implementation

[0019] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0022] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0024] See Figure 1 A 16-channel time-interleaved ADC with a resolution of 6 bits and a sampling rate of 10 GSps samples the input signal at a rate of 10 GHz and outputs the quantization result of the ADC at a rate of 10 GHz, which is a 6-bit digital signal. The data alignment circuit buffers the ADC output and aligns it to a low-speed clock, that is, outputs 96 bits of data at a rate of 156.25 MHz. Finally, the data and this aligned clock are sent to the input of the SERDES. Currently, traditional data alignment circuits use multi-phase clocks to sample the input signal in parallel. By detecting the sampling timing deviation between channels, digital delay, phase interpolation, or calibration compensation is used to align the data of each channel on the time axis before merging and outputting. However, this cannot ensure that the massive amount of data between the time-interleaved ADC and SERDES maintains a precise timing relationship during conversion and transmission.

[0025] To address the aforementioned issues, this invention provides a data alignment circuit based on a time-interleaved ADC topology. By using the sampling clock of the sub-ADCs and employing triggers to buffer the ADC output results, the buffering and pacing scheme aligns the sub-ADC output data of all channels to a single low-speed clock edge before transmitting it to the SERDES, based on the specific time-interleaved ADC layout. A detailed description follows.

[0026] Please see Figure 2 The present invention provides a data alignment circuit based on time-interleaved ADC topology, comprising: a first-stage flip-flop circuit 1, a second-stage flip-flop circuit 2, and a third-stage flip-flop circuit 3.

[0027] The output of the first-stage flip-flop circuit 1 is connected to the data input of the second-stage flip-flop circuit 2, and the output of the second-stage flip-flop circuit 2 is connected to the data input of the third-stage flip-flop circuit 3. The data input of the first-stage flip-flop circuit 1 is connected to the output of the time-interleaved ADC 4. The clock inputs of the first-stage flip-flop circuit 1, the second-stage flip-flop circuit 2, and the third-stage flip-flop circuit 3 are connected to the sampling clock of the sub-ADC of the time-interleaved ADC, that is, connected to the sampling clock generation circuit 5 of the time-interleaved ADC. The output of the third-stage flip-flop circuit 3 is connected to the input of the serializer-deserializer 6.

[0028] The first-stage flip-flop circuit 1 includes multiple first-stage flip-flop sub-circuits 11; the data input terminals of each first-stage flip-flop sub-circuit 11 are respectively connected to the corresponding sub-ADCs in different rows of the time-interleaved ADC4. The first-stage flip-flop circuit 1, the second-stage flip-flop circuit 2, and the third-stage flip-flop circuit 3 are all circuits composed of D flip-flops, and the number of D flip-flops in the first-stage flip-flop circuit 1, the second-stage flip-flop circuit 2, and the third-stage flip-flop circuit 3 is the same as the number of sub-ADCs in the time-interleaved ADC4. It should be noted that the flip-flops with connection relationships in each stage of the flip-flop circuit are connected in a one-to-one correspondence.

[0029] Specifically, the sub-ADCs of the time-interleaved ADC4 are arranged in an array of M rows × N columns, where M and N are both positive integers. The number of first flip-flop sub-circuits 11 in the first-stage flip-flop circuit 1 is 1 / n times M, and each first flip-flop sub-circuit 11 includes n × N D flip-flops. Each first flip-flop sub-circuit 11 is connected to the sub-ADCs in adjacent n rows of the time-interleaved ADC4, and different first flip-flop sub-circuits 11 are connected to sub-ADCs in different rows. Preferably, n=1. When the number of rows of sub-ADCs in the time-interleaved ADC is particularly large, n=2 or n=3, etc., can also be used. For example, when n=1, each first flip-flop sub-circuit 11 is connected one-to-one with a row of sub-ADCs in the time-interleaved ADC4, such as... Figure 2 As shown, the first row of sub-ADC arrays, the second row of sub-ADC arrays...the Mth row of sub-ADC arrays in the time-interleaved ADC4 each consists of only one row of sub-ADC arrays; when n=2, each first flip-flop sub-circuit 11 is connected to two adjacent rows of ADCs in the time-interleaved ADC4, as shown below. Figure 2 As shown, the first row of sub-ADC arrays, the second row of sub-ADC arrays...the Mth row of sub-ADC arrays in the time-interleaved ADC4 each includes two adjacent rows of sub-ADC arrays. The clock inputs of all D flip-flops in the first flip-flop sub-circuit 11 are connected; the second-stage flip-flop circuit 2 includes a single-stage flip-flop circuit or multiple cascaded flip-flop circuits. Cascading means that the data input of the subsequent flip-flop circuit is connected to the output of the preceding flip-flop circuit. The number of stages in the second-stage flip-flop circuit 2 is... For example, when M=8 and n=2, the second-stage flip-flop circuit 2 includes a single-stage flip-flop circuit; when M=8 and n=1, the second-stage flip-flop circuit 2 includes two-stage flip-flop circuits.

[0030] As an optional approach, see Figure 3 The time-interleaved ADC includes a first sub-ADC 41 and a second sub-ADC 42 in any row. The first flip-flop sub-circuit 11 includes a first D flip-flop 111 and a second D flip-flop 112. The data input of the first D flip-flop 111 is connected to the output of the first sub-ADC 41, and the data input of the second D flip-flop 112 is connected to the output of the second sub-ADC 42. The clock inputs of the first D flip-flop 111 and the second D flip-flop 112 are connected and connected to a first target sampling clock 51. The first target sampling clock 51 is the sub-ADC sampling clock whose sampling time falls within the overlap period of the sampling clocks of the first sub-ADC 41 and the second sub-ADC 42. The target overlap period is the overlap period of the sampling clocks of the first sub-ADC 41 and the second sub-ADC 42. It should be noted that both the first sub-ADC 41 and the second sub-ADC 42 can include one or more sub-ADCs. If there are multiple sub-ADCs, one sub-ADC is connected to one D flip-flop. The sub-ADC sampling clock is the sampling clock corresponding to the sub-ADC of the time-interleaved ADC.

[0031] As an alternative approach, if there are multiple sub-ADC sampling clocks whose sampling time falls within the overlapping period of the sampling clocks of the first sub-ADC41 and the second sub-ADC42, the sub-ADC sampling clock with the shortest interval between its sampling time and the midpoint of the target overlapping period can be determined as the first target sampling clock. Alternatively, the sub-ADC sampling clock with the longest interval between its sampling time and the end of the target overlapping period can be determined as the first target sampling clock. Or, any sub-ADC sampling clock can be used as the first target sampling clock, provided that the time interval between its sampling time and the end of the overlapping period is sufficient for the trigger's operating time.

[0032] As an optional approach, when the second-stage flip-flop circuit includes a first-stage flip-flop circuit, the second-stage flip-flop circuit 2 includes M / 2 second flip-flop sub-circuits 21; the second flip-flop sub-circuits 21 are connected to the outputs of the two first flip-flop sub-circuits with the shortest latching interval. The clock inputs of all D flip-flops in the second flip-flop sub-circuit 21 are connected; the clock inputs of the second flip-flop sub-circuit 21 are connected to a second target sampling clock; the second target sampling clock is a sub-ADC sampling clock whose sampling time falls within the overlapping period of the first sampling clock and the second sampling clock; the first sampling clock and the second sampling clock are the sub-ADC sampling clocks corresponding to the latching times of the two first flip-flop sub-circuits connected to the second flip-flop sub-circuit.

[0033] As an alternative approach, if there are multiple sub-ADC sampling clocks whose sampling time falls within the overlapping period of the first and second sampling clocks, the sub-ADC sampling clock with the shortest interval to the midpoint of the overlapping period can be determined as the second target sampling clock. Alternatively, the sub-ADC sampling clock with the longest time interval between its latching time and the end of the overlapping period can be determined as the second target sampling clock. Or, any sub-ADC sampling clock whose sampling time is sufficiently long to allow for sufficient trigger operating time can also be used as the second target sampling clock.

[0034] When the second-stage flip-flop circuit includes multiple flip-flop circuits, the data input terminal of the subsequent flip-flop circuit is connected to the output terminals of the two preceding flip-flop circuits. The connection principle of the remaining circuits is the same as the connection principle between the second-stage flip-flop circuit and the first-stage flip-flop circuit, and will not be repeated here.

[0035] As an optional approach, the clock inputs of all D flip-flops in the third-stage flip-flop circuit 3 are connected, and the clock input of the third-stage flip-flop circuit 3 is connected one-to-one with the D flip-flops in the second-stage flip-flop circuit 2. The clock input of the third-stage flip-flop circuit 3 is connected to the third target sampling clock; the third target sampling clock is the sub-ADC sampling clock whose sampling time falls within the overlapping period of the third and fourth sampling clocks; the third and fourth sampling clocks are the sub-ADC sampling clocks corresponding to the latching time of the second flip-flop sub-circuit connected to the third-stage flip-flop circuit 3. It should be noted that the second-stage flip-flop circuit connected to the third-stage flip-flop circuit, i.e., the last stage flip-flop circuit in the second-stage flip-flop circuit, only includes two second flip-flop sub-circuits.

[0036] As an alternative, if the sampling time of a sub-ADC sampling clock falls within the overlapping period of the third and fourth sampling clocks, the sub-ADC sampling clock with the shortest interval between its sampling time and the midpoint of that overlapping period is determined as the third target sampling clock. Alternatively, the sub-ADC sampling clock with the longest time interval between its sampling time and the end of the overlapping period is determined as the third target sampling clock. Or, any sub-ADC sampling clock whose sampling time is sufficiently long to reach the end of the overlapping period can also be used as the third target sampling clock.

[0037] See Figures 4-7 The above-mentioned data alignment circuit based on the time-interleaved ADC topology will be explained using an 8-channel time-interleaved ADC as an example.

[0038] like Figure 4 As shown, the sub-ADCs of the time-interleaved ADC are arranged in a 2-row × 4-column array. Figure 4 The numbers in the table represent the sub-ADC indices; the sub-ADC with index i is denoted as subADC. The sampling clocks of the numbered sub-ADCs of the time-interleaved ADC are as follows: Figure 5 As shown. CK_ADC represents the sampling clock of the TI-ADC, with a frequency of f and a period of T, CK_subADC The sampling clock of the sub-ADC with index i is denoted as subADC. The output data is DADT_subADC .

[0039] like Figure 6 As shown, based on Figure 4 The data alignment circuit of the 8-channel time-interleaved ADC includes a first-stage flip-flop circuit 1, a second-stage flip-flop circuit 2, and a third-stage flip-flop circuit 3, wherein the second-stage flip-flop circuit includes a first-stage flip-flop circuit. The first-stage flip-flop circuit includes four first-stage flip-flop sub-circuits 11, each of which includes two D flip-flops: a first D flip-flop 111 and a second D flip-flop 112. The data input terminals of the first-stage flip-flop sub-circuits in the first row from top to bottom are connected to the output terminals of sub-ADCs numbered 0 and 2. The data input terminals of the first-stage flip-flop sub-circuits in the second row are connected to the output terminals of sub-ADCs numbered 3 and 1. The data input terminals of the first-stage flip-flop sub-circuits in the third row are connected to the output terminals of sub-ADCs numbered 6 and 4. The data input terminals of the first-stage flip-flop sub-circuits in the fourth row are connected to the output terminals of sub-ADCs numbered 7 and 5.

[0040] See Figure 7 Assuming the sub-ADC outputs the quantization result on the rising edge of the clock, the sub-ADC sampling clocks whose sampling times fall within the overlapping period of the sampling clocks of sub-ADCs numbered 2 and 0 include CK_subADC. <3> CK_subADC <4> CK_subADC <5> CK_subADC <6> CK_subADC <7> , among which, CK_subADC <5> The interval between the sampling time and the midpoint of the overlapping period is the shortest; therefore, CK_subADC <5> This serves as the first target sampling clock for the first flip-flop sub-circuit in the first row. The principle for determining the first target sampling clock for the first flip-flop sub-circuit in the remaining rows is the same and will not be repeated. The alignment principle for the first-stage flip-flop circuit is based on CK_subADC. <5> As the trigger clock for the D flip-flop, for the subADC <2> and subADC <0> Output signal DATA_subADC <2> and DATA_subADC <0> Latch the data and record the output as DATA2. Use CK_subADC. <1> As the trigger clock for the D latch, for the subADC <4> and subADC <6> Output signal DATA_subADC <4> and DATA_subADC <6> Latch the data and record the output as DATA1. Use CK_subADC. <6> As the trigger clock for the D latch, for the subADC <1> and subADC <3> Output signal DATA_subADC <1> and DATA_subADC <3> Latch the data and record the output as DATA3; use CK_subADC <2> As the trigger clock for the D latch, for the subADC <5> and subADC <7> Output signal DATA_subADC <5> and DATA_subADC <7> Latch the data and output it as DATA4.

[0041] The second-stage flip-flop circuit includes two second flip-flop sub-circuits 21, since the latching time of DATA1 corresponds to the sampling clock CK_subADC. <1> The latching time of DATA2 corresponds to the sampling clock CK_subADC <5> The latch time of DATA3 corresponds to the sampling clock CK_subADC <6> The latch time of DATA4 corresponds to the sampling clock CK_subADC <2> The latching intervals for DATA2 and DATA3 are the shortest, as are those for DATA1 and DATA4. Therefore, the data input of one second flip-flop sub-circuit is connected to the output of the first flip-flop sub-circuit corresponding to DATA2 and DATA3. The data input of the other second flip-flop sub-circuit is connected to the output of the first flip-flop sub-circuit corresponding to DATA1 and DATA4. The sampling time is located at CK_subADC. <5> and CK_subADC <6> The sampling clock within the overlapping period includes CK_subADC <0> CK_subADC <1> CK_subADC <2> CK_subADC <3> CK_subADC <4> , among which, CK_subADC <0> The interval between the sampling time and the end time of the overlapping period is the longest, so CK_subADC can be used. <0> This is determined to be the second target sampling clock. Similarly, CK_subADC is... <4> The second target sampling clock is determined as another second flip-flop sub-circuit. The alignment principle between the second-stage and third-stage flip-flop circuits is based on CK_subADC. <4> As the trigger clock for the D latch, DATA1 and DATA4 are latched, and the output is denoted as DATA5; similarly, CK_subADC is used. <0> As the trigger clock for the D latch, DATA2 and DATA3 are latched, and the output is denoted as DATA6. Finally, CK_subADC is used. <6> The D flip-flop, used as the trigger clock in the third-stage flip-flop circuit, latches DATA5 and DATA6, and its output is denoted as OUT. The frequency of OUT is related to CK_subADC. <6> The frequency is consistent with f / 8, which realizes the ADC data output speed reduction.

[0042] like Figure 7 As shown, under the orange shade, the 8 sub-ADCs output the quantization results once in sequence, which is called the first cycle. Under the blue shade, the second cycle is marked. The figure marks the ideal position of the D flip-flop output when the ADC output data of the first cycle is processed by the data alignment circuit. It can be seen that the data generated in the first cycle is aligned and output before the end of the second cycle.

[0043] Figure 2 The aforementioned data alignment circuit based on a time-interleaved ADC topology utilizes D flip-flops in the first, second, and third stage flip-flops to buffer the ADC output, aligning the sub-ADC output data of all channels to a single low-speed clock edge before transmitting it to the SERDES. Specifically, the data alignment circuit, based on the layout of the time-interleaved sub-ADCs, connects the data input terminals of each first flip-flop sub-circuit to corresponding sub-ADCs in different rows of the time-interleaved ADC. This fully considers the setup and hold times of digital signals, reducing the risk of metastability and timing violations. It ensures accurate timing correspondence during massive data conversion and transmission between the time-interleaved ADC and the serializer-decoder, improving circuit reliability. Furthermore, this invention uses the sub-ADCs of the time-interleaved ADC as the trigger clock for the flip-flops, eliminating the need for additional circuitry to generate a low-frequency clock.

[0044] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0045] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A data alignment circuit based on a time-interleaved ADC topology, characterized in that, This includes a first-stage flip-flop circuit, a second-stage flip-flop circuit, and a third-stage flip-flop circuit; The output of the first-stage flip-flop circuit is connected to the data input of the second-stage flip-flop circuit, and the output of the second-stage flip-flop circuit is connected to the data input of the third-stage flip-flop circuit; the clock inputs of the first-stage flip-flop circuit, the second-stage flip-flop circuit, and the third-stage flip-flop circuit are connected to the sampling clock of the sub-ADC of the time-interleaved ADC. The output of the third-stage flip-flop circuit is connected to the input of the serializer-deserializer. The first-stage trigger circuit includes multiple first trigger sub-circuits; the data input terminal of each first trigger sub-circuit is respectively connected to a sub-ADC in a different row of the time-interleaved ADC.

2. The data alignment circuit based on time-interleaved ADC topology according to claim 1, characterized in that, The sub-ADCs of the time-interleaved ADC are arranged in an M x N array, where M and N are both positive integers. The number of first flip-flop sub-circuits in the first-stage flip-flop circuit is 1 / n times M, where n is a positive integer greater than or equal to 1. Each first flip-flop sub-circuit includes n x N D flip-flops, and the clock inputs of all the D flip-flops in the first flip-flop sub-circuit are connected. The second-stage flip-flop circuit includes a single-stage flip-flop circuit or multiple cascaded flip-flop circuits, and the number of stages in the second-stage flip-flop circuit is... .

3. The data alignment circuit based on time-interleaved ADC topology according to claim 2, characterized in that, Any row of sub-ADCs in the time-interleaved ADC includes a first sub-ADC and a second sub-ADC; the first flip-flop sub-circuit includes a first D flip-flop and a second D flip-flop, the data input terminal of the first D flip-flop is connected to the output terminal of the first sub-ADC, and the data input terminal of the second D flip-flop is connected to the output terminal of the second sub-ADC; the clock input terminals of the first D flip-flop and the second D flip-flop are connected to a first target sampling clock; the first target sampling clock is the sub-ADC sampling clock whose sampling time is located within the overlapping period of the sampling clocks of the first sub-ADC and the second sub-ADC.

4. The data alignment circuit based on time-interleaved ADC topology according to claim 3, characterized in that, When the second-stage flip-flop circuit includes a first-stage flip-flop circuit, the second-stage flip-flop circuit includes M / 2 second flip-flop sub-circuits; the clock inputs of all D flip-flops in the second flip-flop sub-circuits are connected; the second flip-flop sub-circuits are connected to the outputs of the two first flip-flop sub-circuits with the shortest latching time interval.

5. The data alignment circuit based on time-interleaved ADC topology according to claim 4, characterized in that, The clock input terminal of the second flip-flop sub-circuit is connected to the second target sampling clock; the second target sampling clock is the sub-ADC sampling clock whose sampling time is within the overlapping period of the first sampling clock and the second sampling clock; the first sampling clock and the second sampling clock are the sub-ADC sampling clocks corresponding to the latching times of the two first flip-flop sub-circuits connected to the second flip-flop sub-circuit.

6. The data alignment circuit based on time-interleaved ADC topology according to claim 3, characterized in that, The clock input terminals of all D flip-flops in the third-stage flip-flop circuit are connected; the D flip-flops in the third-stage flip-flop circuit are connected one-to-one with the D flip-flops in the second-stage flip-flop circuit.

7. The data alignment circuit based on time-interleaved ADC topology according to claim 6, characterized in that, The clock input terminal of the third-stage flip-flop circuit is connected to the third target sampling clock; the third target sampling clock is a sub-ADC sampling clock whose sampling time is located within the overlapping period of the third sampling clock and the fourth sampling clock; the third sampling clock and the fourth sampling clock are sub-ADC sampling clocks corresponding to the latching time of the second flip-flop sub-circuit.

8. The data alignment circuit based on time-interleaved ADC topology according to claim 1, characterized in that, The number of D flip-flops in the first-stage flip-flop circuit, the second-stage flip-flop circuit, and the third-stage flip-flop circuit is the same as the number of sub-ADCs in the time-interleaved ADC.

9. The data alignment circuit based on time-interleaved ADC topology according to claim 2, characterized in that, The first trigger sub-circuit is connected to the sub-ADC of adjacent n rows in the time-interleaved ADC.

10. The data alignment circuit based on time-interleaved ADC topology according to claim 3, characterized in that, If there are multiple sub-ADC sampling clocks whose sampling time falls within the overlapping period of the sampling clocks of the first sub-ADC and the second sub-ADC, then the sub-ADC sampling clock with the shortest interval between its sampling time and the midpoint of the target overlapping period is determined as the first target sampling clock, and the target overlapping period is the overlapping period of the sampling clocks of the first sub-ADC and the second sub-ADC.

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