Photodetector and method of manufacturing the same

Abstract

A photodetector and its fabrication method are disclosed. The photodetector includes: an SOI substrate comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially; a deep trench isolation structure penetrating the top silicon layer and connected to the buried oxide layer; a well region located within the top silicon layer, surrounded by the deep trench isolation structure and the buried oxide layer; a gate structure located on the surface of the well region; lightly doped regions with the opposite conductivity type to the well region, located within the well regions on both sides of the gate structure, the lightly doped regions including a first lightly doped region, a second lightly doped region located on both sides of the gate structure, and a photosensitive lightly doped region spaced apart from the second lightly doped region, the photosensitive lightly doped region and the gate structure being located on both sides of the second lightly doped region; a drain region located within the first lightly doped region; a source region located within the second lightly doped region; and a photosensitive heavily doped region located within the photosensitive lightly doped region. This invention can improve responsivity and reduce noise interference.

Description

Technical Field

[0001] This invention relates to the field of photodetectors, and more particularly to a photodetector and its fabrication method. Background Technology

[0002] Photodetectors, as a core optoelectronic conversion device, play a crucial role in image sensing, environmental monitoring, optical communication, and medical imaging. With the rapid development of the Internet of Things (IoT) and 5G technologies, the demand for high-sensitivity, low-power, and integrated photodetectors is becoming increasingly urgent, especially in applications requiring high dynamic range (>80dB) and fast response (<50μs) under low-light conditions.

[0003] Traditional methods typically use p-type silicon, n-type silicon, or germanium wafers (with a layer thickness of 200μm-500μm) as bulk substrates, or employ epitaxial wafers to optimize doping uniformity. Isolation relies on deep well implantation and high-temperature annealing to activate doping, forming isolation wells (3μm-10μm deep).

[0004] However, on the one hand, photogenerated holes generated by the photoreceiving unit are prone to lateral and longitudinal diffusion in the bulk substrate (diffusion length is 10-50 micrometers). Therefore, most holes (60%-80%) cannot reach the back channel of the MOSFET, but instead recombine and disappear from the bulk substrate boundary, isolation well edge, or surface. As a result, charge diffusion loss is severe (charge collection efficiency is only 40%-60%), leading to low responsivity (responsivity remains at 0.1 A / W-0.5 A / W), which cannot meet the high sensitivity requirements (such as ≥1 A / W for low-light imaging). Simulations show that at 1 mW / cm 2 Under incident light, the output current is only 1 / 3 of the traditional peak value, which seriously affects the dynamic range and the detection accuracy of weak signals.

[0005] On the other hand, although deep-well ion implantation can form a potential barrier, the uneven doping gradient leads to tiny leakage paths in the isolation wall, allowing holes to easily escape across the well, thus resulting in incomplete isolation. Simultaneously, high-temperature annealing induces lattice defects and interface traps, causing bulk substrate potential fluctuations (±0.2V) and threshold voltage drift (10%-20%), introducing noise and drift. As a result, the signal-to-noise ratio (SNR) decreases by 30%-50%, and the device exhibits poor stability during long-term operation (drift rate >1% / h). Especially under high-temperature (>100°C) or high-humidity environments, the noise current can increase to the nA level, amplifying measurement errors.

[0006] Therefore, the device suffers from insufficient responsiveness and severe noise interference, which makes it unable to meet the requirements of emerging applications such as smartphone night photography or autonomous driving vision systems. Summary of the Invention

[0007] The technical problem solved by this invention is to provide a photodetector and its fabrication method to improve responsivity and reduce noise interference.

[0008] To solve the above-mentioned technical problems, the present invention provides a photodetector, characterized in that it comprises: an SOI substrate, including a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially; a deep trench isolation structure penetrating the top silicon layer and connected to the buried oxide layer; a well region located within the top silicon layer, wherein the deep trench isolation structure and the buried oxide layer together surround the well region; a gate structure located on the surface of the well region; a lightly doped region with a conductivity type opposite to that of the well region, wherein the lightly doped region is located within the well regions on both sides of the gate structure, the lightly doped region including a first lightly doped region, a second lightly doped region located on both sides of the gate structure, and a photosensitive lightly doped region spaced apart from the second lightly doped region, wherein the photosensitive lightly doped region and the gate structure are respectively located on both sides of the second lightly doped region; a drain region located within the first lightly doped region; a source region located within the second lightly doped region; and a photosensitive heavily doped region located within the photosensitive lightly doped region.

[0009] Accordingly, the present invention also provides a method for fabricating a photodetector, comprising: providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially, the top silicon layer comprising a device region; forming a deep trench isolation structure surrounding the device region within the top silicon layer, the deep trench isolation structure penetrating the top silicon layer, the deep trench isolation structure and the buried oxide layer together surrounding the device region; after forming the deep trench isolation structure, performing ion implantation on the device region to form a well region within the top silicon layer, the deep trench isolation structure and the buried oxide layer together surrounding the device region; and after forming the deep trench isolation structure, performing ion implantation on the device region to form a well region within the top silicon layer, the deep trench isolation structure and the buried oxide layer together surrounding the device region. The layers together surround the well region; a gate structure is formed on the surface of the well region; lightly doped regions with the opposite conductivity type to the well region are formed in the well regions on both sides of the gate structure, the lightly doped regions include a first lightly doped region, a second lightly doped region, and a photosensitive lightly doped region spaced apart from the second lightly doped region, the photosensitive lightly doped region and the gate structure are respectively located on both sides of the second lightly doped region; a drain region is formed in the first lightly doped region and a source region is formed in the second lightly doped region; a photosensitive heavily doped region is formed in the photosensitive lightly doped region.

[0010] Optionally, the process for forming the lightly doped region includes a first ion implantation process, the parameters of which include: the implanted ions are arsenic ions, the implantation energy is below 15 keV, and the implantation dose is 1 × 10⁻⁶.12 cm -2 The injection angle is 7°.

[0011] Optionally, the process for forming the drain region and the source region includes a second ion implantation process, the parameters of which include: the implanted ions are arsenic ions, the implantation energy is below 40 keV, and the implantation dose is 2 × 10⁻⁶. 15 cm -2 The following describes the process for forming the photosensitive heavily doped region, which includes a third ion implantation process. The parameters of this third ion implantation process include: the implanted ions are phosphorus ions, the implantation energy is below 35 keV, and the implantation dose is 1 × 10⁻⁶. 13 cm -2 the following.

[0012] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the photodetector and its fabrication method provided by the technical solution of the present invention, the well region is located in the top silicon layer, the gate structure is located on the surface of the well region, and the lightly doped region is located in the well region with the opposite conductivity type to the well region. The lightly doped region includes a first lightly doped region, a second lightly doped region, and a photosensitive lightly doped region separated from the second lightly doped region, which are located on both sides of the gate structure. The photosensitive lightly doped region and the gate structure are located on both sides of the second lightly doped region. The drain region is located in the first lightly doped region, the source region is located in the second lightly doped region, and the photosensitive heavily doped region is located in the photosensitive lightly doped region. Therefore, the source region, drain region, gate structure, and well region can constitute a MOSFET structure, and the photosensitive lightly doped region, photosensitive heavily doped region, and well region can constitute a photosensitive part. The well region serves as the well of the MOSFET structure and the base region of the photosensitive part. Building upon this, because the deep trench isolation structure penetrates the top silicon layer and connects to the buried oxide layer, it forms a fully enclosed structure that together surrounds the well region. Therefore, the MOSFET structure and the photosensitive element are completely isolated as independent islands. This achieves not only complete and reliable isolation, eliminating any diffusion paths for charges, but also eliminates the need for high-temperature annealing, thereby reducing or even preventing charge diffusion, limiting hole diffusion length, and avoiding the risks of high-temperature-induced lattice defects and interface traps. This improves responsivity and reduces noise interference. Attached Figure Description

[0013] Figures 1 to 13 This is a cross-sectional structural diagram of each step in the fabrication method of the photodetector according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures: 100, SOI substrate; 101, Device region; 110, Bottom silicon layer; 120, Buried oxide layer; 130, Top silicon layer; 131, Deep trench isolation opening; 132, Deep trench isolation material layer; 133, Deep trench isolation structure; 210. First mask layer; 211. First buffer layer; 220. Second buffer layer; 300, Tunnel Area; 400. Gate structure; 410. Gate sidewall; 500, Lightly doped region; 510, First lightly doped region; 520, Second lightly doped region; 530, Photosensitive lightly doped region; 610, Source region; 620, Drain region; 630, Photosensitive heavily doped region 700. Interlayer dielectric layer; 710. Metal plug structure; 800. Another interlayer dielectric layer; 810. First conductive interconnect layer; 820. First conductive plug; 830. Second conductive interconnect layer; 900, passivation layer. Detailed Implementation

[0015] As described in the background section, traditional photodetectors suffer from severe charge diffusion losses (charge collection efficiency of only 40%-60%) and incomplete isolation, resulting in low responsivity (responsivity remains at 0.1 A / W-0.5 A / W). Furthermore, high-temperature annealing induces lattice defects and interface traps, introducing noise and drift, leading to significant noise interference.

[0016] To address the aforementioned technical problems, the present invention provides a photodetector and its fabrication method. The photodetector includes: an SOI substrate comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially; a deep trench isolation structure penetrating the top silicon layer and connected to the buried oxide layer; a well region located within the top silicon layer, surrounded by the deep trench isolation structure and the buried oxide layer; a gate structure located on the surface of the well region; lightly doped regions with the opposite conductivity type to the well region, located within the well regions on both sides of the gate structure, including a first lightly doped region, a second lightly doped region located on both sides of the gate structure, and a photosensitive lightly doped region spaced apart from the second lightly doped region, with the photosensitive lightly doped region and the gate structure located on opposite sides of the second lightly doped region; a drain region located within the first lightly doped region; a source region located within the second lightly doped region; and a photosensitive heavily doped region located within the photosensitive lightly doped region. This improves responsivity and reduces noise interference.

[0017] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0019] Figures 1 to 13 This is a cross-sectional structural diagram of each step in the fabrication method of the photodetector according to an embodiment of the present invention.

[0020] Please refer to Figure 1 Provides SOI substrate 100.

[0021] The SOI substrate 100 may include a bottom silicon layer 110, a buried oxide layer 120 and a top silicon layer 130 stacked sequentially.

[0022] In this embodiment, the SOI substrate 100 is a P-type substrate.

[0023] The top silicon layer 130 may include a device region 101, which corresponds to the location of the subsequently formed well region 300.

[0024] Furthermore, the thickness of the top silicon 130 layer is less than 200nm.

[0025] Furthermore, the thickness of the buried oxygen layer 120 is less than 1 micrometer.

[0026] In this embodiment, the SOI substrate 100 is subjected to RCA standard cleaning before subsequent steps. Then, the natural oxidant on the surface of the SOI substrate 100 is removed by diluted HF etching to ensure that the surface of the top silicon 130 of the provided SOI substrate 100 is atomically smooth.

[0027] RCA standard cleaning can include: SC-1 cleaning to remove organic matter and SC-2 cleaning to remove metal ions.

[0028] Preferably, the ratio of HF to H2O in the diluted HF is 1:100.

[0029] Next, a deep trench isolation structure 133 is formed within the top silicon layer 130, surrounding the device region 101. For specific steps on forming the deep trench isolation structure 133, please refer to [link to documentation]. Figures 2 to 5 .

[0030] Please refer to Figure 2 A patterned first mask layer 210 is formed on the SOI substrate 100.

[0031] Specifically, the method for forming the first mask layer 210 may include: spin-coating photoresist on the surface of the SOI substrate 100; exposing the photoresist to define the active region 610 pattern; and then performing soft baking and development to form the first mask layer 210.

[0032] Furthermore, the material of the first mask layer 210 may include positive photoresist.

[0033] Preferably, the thickness of the spin-coated photoresist can be 1 μm.

[0034] Preferably, in the spin coating process, the rotation speed is 4000 rpm.

[0035] Furthermore, a 248nm KrF lithography machine can be used to expose the photoresist to define the active region 610 pattern.

[0036] Preferably, the resolution of the pattern of the first mask layer 210 is 0.15 μm.

[0037] Preferably, the process parameters for the soft baking process to form the first mask layer 210 include: a temperature of 90°C and a duration of 1 minute.

[0038] In this embodiment, before forming the first mask layer 210, a first buffer layer 211 is grown on the surface of the top silicon layer 130 to serve as an etching buffer film when etching the deep trench isolation opening 131 later.

[0039] Furthermore, the material of the first buffer layer 211 is silicon dioxide.

[0040] Preferably, the thickness of the first buffer layer 211 can be 110 angstroms.

[0041] Preferably, the first buffer layer 211 can be formed by a thermal oxidation process, wherein the process parameters of the thermal oxidation process include a dry oxygen environment at 850°C.

[0042] Please refer to Figure 3 Using the first mask layer 210 as a mask, the top silicon layer 130 is etched until the surface of the buried oxide layer 120 is exposed, and a deep trench isolation opening 131 is formed in the top silicon layer 130.

[0043] The deep trench isolation opening 131 is used to provide space for the deep trench isolation structure 133.

[0044] In this embodiment, the deep trench isolation opening 131 surrounds the device region 101.

[0045] Specifically, the depth of the deep trench isolation opening 131 is less than 1.5 micrometers.

[0046] Furthermore, a dry etching process can be used to form deep trench isolation openings 131.

[0047] Please refer to Figure 4 A deep trench isolation material layer 132 is deposited inside the deep trench isolation opening 131 and on the surface of the first mask layer 210, and the deep trench isolation material layer 132 fills the deep trench isolation opening 131.

[0048] Furthermore, a high-density plasma chemical vapor deposition (HDP-CVD) process can be used to deposit a deep trench isolation material layer 132 to better avoid voids in the deep trench isolation material layer 132 filling the deep trench isolation opening 131, thus ensuring the isolation effect of the deep trench isolation structure 133 constructed in this way.

[0049] Please refer to Figure 5 Remove the first mask layer 210, the first buffer layer 211 and the deep trench isolation material layer 132 on the top silicon 130, and form a deep trench isolation structure 133 in the top silicon 130.

[0050] In this embodiment, the deep trench isolation structure 133 penetrates the top silicon layer 130. The deep trench isolation structure 133 and the buried oxide layer 120 together surround the device region 101 to form a fully enclosed structure of a pair of device regions 101 except for the top surface of the device region 101.

[0051] Furthermore, the material of the deep trench isolation structure 133 can be silicon dioxide.

[0052] Furthermore, the width of the deep trench isolation structure 133 along the surface of the SOI substrate 100 is less than 0.2 μm, and the height of the deep trench isolation structure 133 is less than 1.5 μm.

[0053] Specifically, the method for removing the deep trench isolation material layer 132 on the first mask layer 210, the first buffer layer 211 and the top silicon 130 may include: using a chemical mechanical polishing (CMP) process to polish the deep trench isolation material layer 132 on the first mask layer 210, the first buffer layer 211 and the top silicon 130 until the surface of the top silicon 130 is exposed.

[0054] Of course, the first mask layer 210 can be removed first by means of ashing process, and then the first buffer layer 211 and the deep trench isolation material layer 132 on the top silicon 130 can be etched back, or the first buffer layer 211 and the deep trench isolation material layer 132 on the top silicon 130 can be polished by chemical mechanical polishing process until the surface of the top silicon 130 is exposed.

[0055] Next, please refer to Figure 6 Ion implantation is performed on device region 101 to form well region 300 in top silicon 130.

[0056] The well region 300 serves as the well for the subsequently formed MOSFET and the base region for the photoelectric sensing unit.

[0057] Since the deep trench isolation structure 133 and the buried oxide layer 120 together surround the device region 101, the deep trench isolation structure 133 and the buried oxide layer 120 together also surround the well region 300.

[0058] Furthermore, well region 300 can be a P-well.

[0059] Specifically, the dopant ions in well region 300 can be boron ions.

[0060] Furthermore, the ion doping concentration of well region 300 is 1×10⁻⁶. 12 cm -2 Up to 1×10 13 cm -2 .

[0061] In this embodiment, the method of ion implantation of device region 101 to form well region 300 includes: forming a second mask layer (not shown) on the surface of top silicon 130 to expose device region 101; and performing ion implantation on device region 101 using the second mask layer as a mask.

[0062] Furthermore, the pattern resolution of the patterned second mask layer is below 0.15 micrometers.

[0063] Furthermore, the process parameters for ion implantation in device region 101 may include: the implanted ions are boron ions; the implantation energy is below 30 keV; and the implantation dose is 3 × 10⁻⁶. 12 cm -2 the following.

[0064] In this embodiment, a second buffer layer 220 is formed on the surface of the top silicon 130 of at least the device region 101 before the second mask layer is formed. Accordingly, the second mask layer is located on the surface of the second buffer layer 220.

[0065] The second buffer layer 220 can serve as an ion implantation buffer layer during ion implantation of the device region 101 to protect the MOSFET and prevent damage to the MOSFET channel.

[0066] Furthermore, the material of the second buffer layer 220 can be silicon oxide.

[0067] Preferably, the thickness of the second buffer layer 220 is less than 10 nanometers.

[0068] Preferably, the second buffer layer 220 can be formed by a low-temperature dry oxidation process at 750°C.

[0069] In this embodiment, the second mask layer and the second buffer layer 220 are removed after the well region 300 is formed.

[0070] Please refer to Figure 7 A gate structure 400 is formed on the surface of the well region 300.

[0071] Specifically, the gate structure 400 includes a gate oxide layer (not shown) located on the surface of the well region 300, and a gate (not shown) located on the surface of the gate oxide layer.

[0072] Furthermore, the method for forming the gate structure 400 may include: forming a gate oxide material layer (not shown) on the surface of the well region 300 using a dry oxidation growth process; depositing an amorphous silicon layer (not shown) on the surface of the gate oxide material layer using a low-pressure chemical vapor deposition (LPCVD) process; then, converting the amorphous silicon layer into a polycrystalline silicon layer (not shown) through in-situ doping and annealing; etching the polycrystalline silicon layer until the surface of the top silicon 130 of the device region 101 is exposed to complete the patterning of the polycrystalline silicon layer and form the gate structure 400, wherein the gate oxide material layer under the polycrystalline silicon layer is the gate oxide layer.

[0073] Preferably, the dry oxidation growth process for forming the gate oxide material layer is carried out at a temperature of 900°C.

[0074] The gate oxide layer has a thickness of 3 to 4 nanometers. This ensures that the gate leakage current is less than 0.1 pA / μm when the bias voltage is 5V.

[0075] Preferably, the thickness of the amorphous silicon layer is less than 150 nanometers.

[0076] Preferably, the process parameters for the low-pressure chemical vapor deposition process for depositing the amorphous silicon layer include: a temperature of 580°C; and a reaction gas including SiH4. The in-situ doping of the amorphous silicon layer into a polycrystalline silicon layer is in-situ phosphorus doping, with a doping dose below 5 × 10¹⁵ cm⁻³. Therefore, it is compatible with monolayer polycrystalline silicon (1 Poly, 1 P) processes.

[0077] The gate length of the gate is less than 150 nanometers.

[0078] Furthermore, the polysilicon layer can be etched using reactive ion etching (RIE etching), where the reactive gas can include chlorine or HBr gas.

[0079] Please refer to Figure 8 Lightly doped regions 500 are formed in the well regions 300 on both sides of the gate structure 400.

[0080] In this embodiment, the lightly doped region 500 has the opposite conductivity type to the well region 300.

[0081] Specifically, the lightly doped region 500 is an N-type doped region.

[0082] Furthermore, the ion doping concentration of the lightly doped region 500 is 1×10⁻⁶. 15 cm -2 Up to 3×10 15 cm -2 .

[0083] Furthermore, the dopant ions in the lightly doped region 500 may include arsenic.

[0084] By first forming the gate structure 400 and then forming the lightly doped region 500, the self-aligned formation of the lightly doped region 500 is achieved.

[0085] In this embodiment, the lightly doped region 500 may include: a first lightly doped region 510, a second lightly doped region 520, and a photosensitive lightly doped region 530.

[0086] The first lightly doped region 510 and the second lightly doped region 520 are located on opposite sides of the gate structure 400. The photosensitive lightly doped region 530 and the second lightly doped region 520 are spaced apart from each other and are located on the same side of the gate structure 400, wherein the photosensitive lightly doped region 530 and the gate structure 400 are located on opposite sides of the second lightly doped region 520.

[0087] Furthermore, the process for forming the lightly doped region 500 may include a first ion implantation process.

[0088] In this embodiment, the parameters of the first ion implantation process may include: the implanted ions are arsenic ions, the implantation energy is below 15 keV, and the implantation dose is 1×10⁻⁶. 12 cm -2 The injection angle is 7°.

[0089] Please refer to Figure 9 In this embodiment, after the lightly doped region 500 is formed and before the source region 610 and drain region 620 are subsequently formed, a gate sidewall 410 is formed on the sidewall of the gate structure 400.

[0090] This isolates the doping of the subsequently formed source region 610, drain region 620, and photosensitive heavily doped region 630, thus protecting the parasitic channel of the MOSFET.

[0091] Preferably, the thickness of the gate sidewall 410 is less than 60 nanometers in the direction perpendicular to the sidewall of the gate structure 400.

[0092] Specifically, the method for forming the gate sidewall 410 may include: forming a gate sidewall 410 material film (not shown) on the surface of the top silicon 130 and the surface of the gate structure 400; and etching and removing the gate sidewall 410 material film on the surface of the top silicon 130 and the top surface of the gate structure 400 by an anisotropic etching process.

[0093] Furthermore, low-stress Si3N4 can be deposited by PECVD as the material for the gate sidewall 410, and the anisotropic etching process can be RIE anisotropic etching.

[0094] Next, please refer to Figure 10 A drain region 620 is formed in the first lightly doped region 510, and a source region 610 is formed in the second lightly doped region 520.

[0095] Specifically, both the drain region 620 and the source region 610 are N-type doped regions.

[0096] Furthermore, the dopants in the drain region 620 and the source region 610 may include arsenic.

[0097] Specifically, the method for forming the source region 610 and the drain region 620 may include: forming a patterned third mask layer (not shown) on the surface of the top silicon 130 by photolithography, the third mask layer exposing the lightly doped region 500 surface at the corresponding positions of the source region 610 and the drain region 620; and performing ion implantation using the third mask layer as a mask.

[0098] Furthermore, the process for forming the drain region 620 and the source region 610 may include a second ion implantation process.

[0099] In this embodiment, the parameters of the second ion implantation process may include: the implanted ions are arsenic ions, the implantation energy is below 40 keV, and the implantation dose is 2 × 10⁻⁶. 15 cm -2 the following.

[0100] In this embodiment, after the source region 610 and the drain region 620 are formed, the third mask layer is removed.

[0101] Please continue to refer to this. Figure 10 Within the lightly doped photosensitive region 530, there is a heavily doped photosensitive region 630.

[0102] Specifically, the photosensitive heavily doped region 630 is an N-type doped region.

[0103] The PN junction formed between the photosensitive heavily doped region 630 and the well region 300 has a junction depth of less than 0.3 micrometers, and the distance between the photosensitive heavily doped region 630 and the source region 610 is less than 0.15 micrometers.

[0104] Specifically, the method for forming the photosensitive heavily doped region 630 includes: forming a patterned fourth mask layer (not shown) on the surface of the top silicon 130 by photolithography, the fourth mask layer exposing the surface of the lightly doped region 500 at the corresponding position of the photosensitive heavily doped region 630; and performing ion implantation using the fourth mask layer as a mask.

[0105] Furthermore, the process for forming the photosensitive heavily doped region 630 may include a third ion implantation process.

[0106] In this embodiment, the parameters of the third ion implantation process may include: the implanted ion is a phosphorus ion, the implantation energy is below 35 keV, and the implantation dose is 1×10⁻⁶. 13 cm -2 the following.

[0107] In this embodiment, after forming the photosensitive heavily doped region 630, the fourth mask layer is removed.

[0108] Please continue to refer to this. Figure 10 After forming the source region 610, the drain region 620, and the photosensitive heavily doped region 630, annealing activation is performed.

[0109] Specifically, the annealing activation method may include: performing a first RTA annealing to activate the lightly doped region 500; and after the first RTA annealing, performing a second RTA annealing to activate the source region 610, the drain region 620, and the photosensitive heavily doped region 630.

[0110] This annealing activation not only activates the lightly doped region 500, source region 610, drain region 620, and photosensitive heavily doped region 630, but also repairs doping damage and ensures doping uniformity greater than 96%.

[0111] Preferably, the annealing temperature of the first RTA annealing is 750°C and the duration is 15 seconds.

[0112] Preferably, the annealing temperature of the second RTA annealing is 900°C and the duration is 5 seconds.

[0113] Thus, the source region 610, the drain region 620, and the gate structure 400 are used to form a MOSFET structure, and the well region 300 serves as the well of the MOSFET structure. Meanwhile, the lightly doped photosensitive region 530 and the heavily doped photosensitive region 630 are used to form a photosensitive part, and the well region 300 serves as the base region of the photosensitive part.

[0114] Next, please refer to Figure 11 An interlayer dielectric layer 700 is deposited on the surface of the deep trench isolation structure 133, the metal silicide layer and the gate structure 400.

[0115] Preferably, the thickness of the interlayer dielectric layer 700 is less than 400 nanometers.

[0116] Furthermore, the material of the interlayer dielectric layer 700 can be silicon dioxide.

[0117] Furthermore, the HDP-CVD process can be used to deposit an interlayer dielectric layer of 700.

[0118] Please continue to refer to this. Figure 11 Next, a metal silicide layer (not shown) and several metal plug structures 710 are formed.

[0119] A metal silicide layer is located on the surface of the drain region 620, the source region 610, the photosensitive heavily doped region 630, and the gate in the gate structure 400. A metal plug structure 710 penetrates the interlayer dielectric layer 700 and contacts the surface of the metal silicide layer, so as to lead out the gate structure 400, the source region 610, the drain region 620, and the photosensitive heavily doped region 630 through a number of metal plug structures 710.

[0120] Specifically, the material for the metal silicide layer can be CoSi2.

[0121] Specifically, the method for forming the metal silicide layer and the metal plug structure 710 may include: etching the interlayer dielectric layer 700 until a portion of the surface of the source region 610, the drain region 620, the photosensitive heavily doped region 630, and the gate is exposed, forming a plurality of conductive openings (not shown) within the interlayer dielectric layer 700; forming a metal silicide layer on a portion of the surface of the source region 610, the drain region 620, the photosensitive heavily doped region 630, and the gate exposed at the bottom of the conductive openings; and then filling the conductive openings to form the metal plug structure 710 on the surface of the metal silicide layer.

[0122] Preferably, the diameter of the conductive opening is less than 0.15 μm.

[0123] Preferably, the contact resistance between the metal silicide layer and the metal plug structure 710 is less than 0.3Ω.

[0124] Please refer to Figure 12 After forming the metal plug structure 710, a patterned first conductive interconnect layer 810 is formed on a local surface of the interlayer dielectric layer 700 and the surface of the metal plug structure 710. Then, another interlayer dielectric layer 800 is formed on the surface of the first conductive interconnect layer 810 and the surface of the interlayer dielectric layer 700. Next, a first conductive plug 820 is formed penetrating the other interlayer dielectric layer 800, with the bottom of the first conductive plug 820 contacting the first conductive interconnect layer 810. Finally, a patterned second conductive interconnect layer 830 is formed on the surface of the other interlayer dielectric layer 800, contacting the top surface of the first conductive plug 820.

[0125] Preferably, the material of the first conductive interconnect layer 810 may include aluminum, and the thickness of the first conductive interconnect layer 810 is less than 500 nanometers.

[0126] Preferably, the thickness of the other interlayer dielectric layer 800 is less than 300 nanometers.

[0127] Furthermore, the material of the first conductive plug 820 may include tungsten.

[0128] Preferably, the material of the second conductive interconnect layer 830 may include aluminum, and the thickness of the second conductive interconnect layer 830 is less than 700 nanometers.

[0129] Please refer to Figure 13 A passivation layer 900 is formed on the surface of another interlayer dielectric layer 800 and the surface of the second conductive interconnect layer 830. Then, a photosensitive window (not shown) is formed in the passivation layer 900 to expose the photosensitive heavily doped region 630.

[0130] Preferably, the area of ​​the photosensitive window is 10 μm2 or more.

[0131] Preferably, the passivation layer 900 has a thickness of 300 nanometers or more.

[0132] Furthermore, the material of the passivation layer 900 may include Si3N4.

[0133] In this embodiment, after the passivation layer 900 is formed, DC / AC electrical tests are performed, which may specifically include: testing the IV characteristics under a bias voltage of 5V and verifying the photoresponse.

[0134] Accordingly, this invention also provides a photodetector; please refer to further details. Figure 13The photodetector may include: an SOI substrate 100, a deep trench isolation structure 133, a well region 300, a gate structure 400, a lightly doped region 500, a drain region 620, a source region 610, and a photosensitive heavily doped region 630.

[0135] The SOI substrate 100 includes a bottom silicon layer 110, a buried oxide layer 120, and a top silicon layer 130 stacked sequentially.

[0136] In this embodiment, the SOI substrate 100 is a P-type substrate.

[0137] Furthermore, the thickness of the top silicon 130 layer is less than 200nm.

[0138] Furthermore, the thickness of the buried oxygen layer 120 is less than 1 micrometer.

[0139] In this embodiment, the well region 300 is located within the top silicon layer 130.

[0140] Furthermore, well region 300 is a P-well.

[0141] Specifically, the dopant ions in well region 300 can be boron ions.

[0142] Furthermore, the ion doping concentration of well region 300 can be 1×10⁻⁶. 12 cm -2 Up to 1×10 13 cm -2 To modulate the back channel.

[0143] In this embodiment, the deep trench isolation structure 133 penetrates the top silicon layer 130 and is connected to the buried oxide layer 120. The deep trench isolation structure 133 and the buried oxide layer 120 together surround the well region 300. The deep trench isolation structure 133 and the buried oxide layer 120 constitute a fully enclosed structure of the well region 300 (except for its top surface).

[0144] Furthermore, the material of the deep trench isolation structure 133 can be silicon dioxide.

[0145] Furthermore, the width of the deep trench isolation structure 133 along the surface of the SOI substrate 100 is less than 0.2 μm, and the height of the deep trench isolation structure is less than 1.5 μm.

[0146] Preferably, the resolution of the pattern of the deep trench isolation structure 133 is 0.15 μm.

[0147] In this embodiment, the gate structure 400 is located on the surface of the well region 300.

[0148] Specifically, the gate structure 400 includes a gate oxide layer (not shown) located on the surface of the well region 300, and a gate (not shown) located on the surface of the gate oxide layer.

[0149] The gate oxide layer has a thickness of 3 to 4 nanometers. This ensures that the gate leakage current is less than 0.1 pA / μm when the bias voltage is 5V.

[0150] The gate can be an amorphous silicon layer.

[0151] Preferably, the thickness of the amorphous silicon layer is less than 150 nanometers.

[0152] Preferably, the gate length is less than 150 nanometers.

[0153] In this embodiment, the lightly doped region 500 has the opposite conductivity type to the well region 300.

[0154] Specifically, the lightly doped region 500 is an N-type doped region.

[0155] Furthermore, the ion doping concentration of the lightly doped region 500 is 1×10⁻⁶. 15 cm -2 Up to 3×10 15 cm -2 .

[0156] Furthermore, the dopant ions in the lightly doped region 500 include arsenic.

[0157] In this embodiment, the lightly doped region 500 is located within the well region 300 on both sides of the gate structure 400.

[0158] The first lightly doped region 510 and the second lightly doped region 520 are located on opposite sides of the gate structure 400. The photosensitive lightly doped region 530 and the second lightly doped region 520 are spaced apart from each other and are located on the same side of the gate structure 400, wherein the photosensitive lightly doped region 530 and the gate structure 400 are located on opposite sides of the second lightly doped region 520.

[0159] In this embodiment, the drain region 620 is located within the first lightly doped region 510.

[0160] In this embodiment, the source region 610 is located within the second lightly doped region 520.

[0161] Since the drain region 620 is located within the first lightly doped region 510 and the source region 610 is located within the second lightly doped region 520, there are lightly doped regions 500 with lower doping concentration at the edges of the drain region 620 and the source region 610, thereby optimizing the hot carrier tolerance of the parasitic MOSFET.

[0162] Specifically, both the drain region 620 and the source region 610 are N-type doped regions.

[0163] Furthermore, the dopants in the drain region 620 and the source region 610 may include arsenic.

[0164] Preferably, the doping ion concentration in the source region 610 is 2 × 10⁻⁶. 15 cm -2 The following further strengthens the hole capture threshold.

[0165] In this embodiment, the photosensitive heavily doped region 630 is located in the photosensitive lightly doped region 530.

[0166] Specifically, the photosensitive heavily doped region 630 is an N-type doped region.

[0167] The junction depth of the PN junction formed between the photosensitive heavily doped region 630 and the well region 300 is less than 0.3 μm, and the spacing between the photosensitive heavily doped region 630 and the source region 610 is less than 0.15 μm. Therefore, ensuring 100% hole flow to the source region 610 results in an increase in the potential of the SOI substrate 100 (ΔV_sub>0.5V) and a decrease in the threshold voltage (ΔVth≈-0.2V). Compared to conventional techniques, charge transport loss is reduced to <5%, the dynamic range is extended to >80 dB, and the response time is shortened to <50 μs (conventional >100 μs).

[0168] In the photodetector of this embodiment, the well region 300 is located within the top silicon layer 130, the gate structure 400 is located on the surface of the well region 300, and the lightly doped region 500 is located within the well region 300, having the opposite conductivity type to the well region 300. The lightly doped region 500 includes a first lightly doped region 510, a second lightly doped region 520 located on both sides of the gate structure 400, and a photosensitive lightly doped region 530 spaced apart from the second lightly doped region 520. The photosensitive lightly doped region 530 and the gate structure 400 are respectively located on the second lightly doped region 510. On both sides of the doped region 520, the drain region 620 is located within the first lightly doped region 510, the source region 610 is located within the second lightly doped region 520, and the photosensitive heavily doped region 630 is located within the photosensitive lightly doped region 530. Therefore, the source region 610, the drain region 620, the gate structure 400, and the well region 300 can constitute a MOSFET structure, and the photosensitive lightly doped region 530, the photosensitive heavily doped region 630, and the well region 300 can constitute a photosensitive part. Among them, the well region 300 serves as the well of the MOSFET structure and the base region of the photosensitive part.

[0169] On this basis, since the deep trench isolation structure 133 penetrates through the top silicon 130 and is connected to the buried oxide layer 120, the deep trench isolation structure 133 and the buried oxide layer 120 form a fully enclosed structure to jointly enclose the well region 300. Therefore, the MOSFET structure and the photoinductive part are completely isolated into independent islands. Thus, not only complete and reliable isolation is achieved, making the charge have no diffusion path, but the realization of this isolation does not rely on the preparation process of high-temperature annealing. Furthermore, the diffusion of charge is reduced or even avoided, the hole diffusion length is limited, and the risk of high-temperature-induced lattice defects and interface traps is avoided. Thereby, the responsivity is improved and the noise interference is reduced.

[0170] In particular, compared with the solution of the traditional technology, the photo-generated hole collection efficiency of the photodetector in the embodiment of the present invention is increased to more than 95% (only 40%-60% in the solution of the traditional technology), and the responsivity jumps to ≥1.2 A / W (only 0.1 A / W - 0.5 A / W in the solution of the traditional technology). Under the incident light of 1 mW / cm 2 the output current I_ds > 1 mA, achieving a gain of 2-3 times. Moreover, by completely blocking the lateral and longitudinal charge diffusion, the signal-to-noise ratio is increased by 50%, significantly reducing the noise interference (<nA level), which is particularly suitable for low-light imaging such as night vision sensors.

[0171] In addition, through the synergistic effect of the buried oxide layer and the barrier of the deep trench isolation structure, the hole diffusion length can be limited to <1 μm, supporting multi-channel parasitic detection, increasing the comprehensive sensitivity index by more than 3 times, reducing the power consumption to <0.5 mW (under pure 5V), and reducing the volume by 50% (<0.5 mm 2 )

[0172] In addition, the complete isolation protects the complete parasitic structure. Therefore, there is no independent threshold injection, and the back channel can be modulated by controlling the ion doping concentration of the well region 300.

[0173] In addition, compared with the solution of the traditional technology, the photosensitive lightly doped region 530 and the photosensitive heavily doped region 630 are not blocked by the MOSFET structure, maximizing the light incidence. Moreover, the layout of the MOSFET structure and the photoinductive part optimizes the hot carrier tolerance (lifetime > 10 7 h), enhancing the stability (drift < 0.5% / h), which is particularly suitable for portable devices such as smartphone image modules under pure 5V BCD operation.

[0174] In this embodiment, the sidewall of the gate structure 400 further has a gate sidewall 410. Thus, the doping of the source region 610, the drain region 620, and the photosensitive heavily doped region 630 can be isolated, protecting the parasitic channel of the MOSFET.

[0175] Preferably, the thickness of the gate sidewall 410 is less than 60 nanometers in the direction perpendicular to the sidewall of the gate structure 400.

[0176] Preferably, low-stress Si3N4 can be used as the material for the grid sidewall 410.

[0177] In this embodiment, the photodetector may further include an interlayer dielectric layer 700.

[0178] In this embodiment, the interlayer dielectric layer 700 is located on the surface of the deep trench isolation structure 133 and the gate structure 400.

[0179] Preferably, the thickness of the interlayer dielectric layer 700 is less than 400 nanometers.

[0180] Furthermore, the material of the interlayer dielectric layer 700 can be silicon dioxide.

[0181] In this embodiment, the photodetector may further include a metal silicide layer.

[0182] Specifically, the material for the metal silicide layer can be CoSi2.

[0183] The metal silicide layer is located on the surface of the drain region 620, the source region 610, the photosensitive heavily doped region 630, and the gate.

[0184] In this embodiment, the photodetector may further include: a plurality of metal plug structures 710.

[0185] In this embodiment, the metal plug structure 710 penetrates the interlayer dielectric layer 700 and contacts the surface of the metal silicide layer, so as to lead out the gate structure 400, the source region 610, the drain region 620 and the photosensitive heavily doped region 630 through a plurality of metal plug structures 710.

[0186] Preferably, the contact resistance between the metal silicide layer and the metal plug structure 710 is less than 0.3Ω.

[0187] In this embodiment, the photodetector may further include a first conductive interconnect layer 810.

[0188] The first conductive interconnect layer 810 is located on a local surface of the interlayer dielectric layer 700 and the surface of the metal plug structure 710.

[0189] Preferably, the material of the first conductive interconnect layer 810 may include aluminum, and the thickness of the first conductive interconnect layer 810 is less than 500 nanometers.

[0190] In this embodiment, the photodetector may further include another interlayer dielectric layer 800.

[0191] Specifically, another interlayer dielectric layer 800 is located on the surface of the first conductive interconnect layer 810 and the surface of the interlayer dielectric layer 700.

[0192] Preferably, the thickness of the other interlayer dielectric layer 800 is less than 300 nanometers.

[0193] In this embodiment, the photodetector may further include a first conductive plug 820.

[0194] The first conductive plug 820 penetrates the first conductive plug 820 of the other interlayer dielectric layer 800, and the bottom of the first conductive plug 820 contacts the first conductive interconnect layer 810.

[0195] Furthermore, the material of the first conductive plug 820 may include tungsten.

[0196] In this embodiment, the photodetector may further include a second conductive interconnect layer 830.

[0197] The second conductive interconnect layer 830 is located on the surface of the other interlayer dielectric layer 800 and is in contact with the top surface of the first conductive plug 820.

[0198] Preferably, the material of the second conductive interconnect layer 830 may include aluminum, and the thickness of the second conductive interconnect layer 830 is less than 700 nanometers.

[0199] In this embodiment, the photodetector may further include a passivation layer 900.

[0200] The passivation layer 900 is located on the surface of another interlayer dielectric layer 800 and the surface of the second conductive interconnect layer 830. The passivation layer 900 has a photosensitive window (not shown) that exposes the photosensitive heavily doped region 630.

[0201] Preferably, the area of ​​the photosensitive window is 10 μm2 or more.

[0202] Preferably, the passivation layer 900 has a thickness of 300 nanometers or more.

[0203] Furthermore, the material of the passivation layer 900 may include Si3N4.

[0204] The materials, forming process, working principle, specific implementation method and beneficial effects of the photodetector involved in the embodiments of the present invention can be found in the preparation method of the photodetector in the embodiments of the present invention, and will not be repeated here.

[0205] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A photodetector, characterized in that, include: SOI substrate, comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially; A deep trench isolation structure penetrates the top silicon layer and is connected to the buried oxide layer; The well region is located within the top silicon layer, and the deep trench isolation structure and the buried oxide layer together surround the well region. A gate structure is located on the surface of the well region; A lightly doped region with the opposite conductivity type to the well region is located in the well regions on both sides of the gate structure. The lightly doped region includes a first lightly doped region, a second lightly doped region, and a photosensitive lightly doped region separated from the second lightly doped region, which are located on both sides of the gate structure. The photosensitive lightly doped region and the gate structure are located on both sides of the second lightly doped region. The drain region located within the first lightly doped region; The source region is located within the second lightly doped region; The photosensitive heavily doped region is located within the lightly doped photosensitive region.

2. The photodetector as described in claim 1, characterized in that, The trap region is a P trap, the lightly doped region, the drain region, the source region and the photosensitive heavily doped region are all N type doped regions, the ion doping concentration of the trap region is 1x10 12 cm -2 to 1x10 13 cm -2 , the ion doping concentration of the lightly doped region is 1x10 15 cm -2 to 3x10 15 cm -2 .

3. The photodetector as described in claim 2, characterized in that, The dopant ions in the lightly doped region, the drain region, and the source region include arsenic, and the dopant ions in the photosensitive heavily doped region include phosphorus.

4. The photodetector as described in claim 1, characterized in that, The width of the deep trench isolation structure along the surface of the SOI substrate is less than 0.2 micrometers, and the height of the deep trench isolation structure is less than 1.5 micrometers.

5. The photodetector as described in claim 1, characterized in that, The junction depth of the PN junction formed between the photosensitive heavily doped region and the well region is less than 0.3 micrometers, and the distance between the photosensitive heavily doped region and the source region is less than 0.15 micrometers.

6. The photodetector as described in claim 1, characterized in that, The gate structure includes a gate oxide layer located on the surface of the well region and a gate located on the surface of the gate oxide layer.

7. The photodetector as described in claim 1, characterized in that, Also includes: An interlayer dielectric layer is located on the surfaces of the deep trench isolation structure and the gate structure; A metal silicide layer is located on the surface of the drain region, the source region, the photosensitive heavily doped region, and the gate structure; A plurality of metal plug structures are provided, the metal plug structures penetrating the interlayer dielectric layer and contacting the surface of the metal silicide layer, so as to bring out the gate structure, the source region, the drain region and the photosensitive heavily doped region through the plurality of metal plug structures.

8. A method for fabricating a photodetector, characterized in that, include: An SOI substrate is provided, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked sequentially, the top silicon layer comprising a device region; A deep trench isolation structure is formed within the top silicon layer, surrounding the device region. The deep trench isolation structure penetrates the top silicon layer, and together with the buried oxide layer, the deep trench isolation structure surrounds the device region. After forming the deep trench isolation structure, ion implantation is performed on the device region to form a well region in the top silicon layer. The deep trench isolation structure and the buried oxide layer together surround the well region. A gate structure is formed on the surface of the well region; Lightly doped regions with the opposite conductivity type to the well regions are formed in the well regions on both sides of the gate structure. The lightly doped regions include a first lightly doped region, a second lightly doped region, and a photosensitive lightly doped region spaced apart from the second lightly doped region, respectively located on both sides of the gate structure. The photosensitive lightly doped region and the gate structure are respectively located on both sides of the second lightly doped region. A drain region is formed in the first lightly doped region, and a source region is formed in the second lightly doped region; A photosensitive heavily doped region is formed within the lightly doped photosensitive region.

9. The method for fabricating a photodetector as described in claim 8, characterized in that, The process of forming the lightly doped region includes a first ion implantation process, parameters of the first ion implantation process include: the implanted ions are arsenic ions, the implantation energy is below 15 keV, the implantation dose is 1x1013cm 12 cm -2 Hereinafter, the implantation angle is 7°.

10. The method for fabricating a photodetector as described in claim 8, characterized in that, The process of forming the drain region and the source region comprises a second ion implantation process, parameters of the second ion implantation process comprising: the implanted ions are arsenic ions, the implantation energy is below 40 keV, the implantation dose is 2×10 15 cm -2 below; The process for forming the photosensitive heavily doped region includes a third ion implantation process. The parameters of this third ion implantation process include: the implanted ions are phosphorus ions, the implantation energy is below 35 keV, and the implantation dose is 1 × 10⁻⁶. 13 cm -2 the following.

Images