Method for manufacturing solar cell and solar cell

Abstract

This application relates to the field of solar cell technology, and particularly to a method for fabricating a solar cell and a solar cell, comprising: providing a substrate having opposing first and second surfaces; forming a PN junction and a first passivation layer on the first surface, the first passivation layer being located on the PN junction; forming multiple spaced first grid electrodes on the surface of the first passivation layer using a sintering process, and forming multiple spaced second grid electrodes on the second surface; performing a laser process on the first grid electrodes and their adjacent regions; and applying a reverse voltage between the first and second grid electrodes, wherein the adjacent region is defined as the region within a predetermined distance from the edge of the first grid electrode, the predetermined distance being no greater than 1.5 cm. This application embodiment is beneficial for improving the photoelectric conversion performance of the fabricated solar cell.

Description

Cross-references to related applications

[0001] This application is a divisional application of Chinese invention patent application filed on November 24, 2022, with application number 202211485637.5 and invention title "Method for preparing solar cells and solar cells". Technical Field

[0002] This application relates to the field of solar cells, and particularly to a method for preparing a solar cell and a solar cell. Background Technology

[0003] Solar cells have good photoelectric conversion capabilities. In solar cells, a metallization process is required on the silicon wafer surface to form multiple fine grids and a main grid, thereby collecting the current generated by the silicon wafer. Typically, the metallization process includes a sintering step to sinter the metal paste printed on the silicon wafer surface, allowing the metal paste to penetrate the passivation layer and make electrical contact with the doped conductive layer or the emitter, for collecting charge carriers in the doped conductive layer.

[0004] However, the photoelectric conversion performance of the solar cells obtained after fabricating the grid lines using the current grid line fabrication process is not good. Summary of the Invention

[0005] This application provides a method for preparing a solar cell and a solar cell, which at least helps to improve the photoelectric conversion performance of the solar cell.

[0006] This application provides a method for fabricating a solar cell, comprising: providing a substrate having a first surface and a second surface opposite to each other; forming a PN junction and a first passivation layer on the first surface, the first passivation layer being located on the PN junction; forming a plurality of spaced first grid electrodes on the surface of the first passivation layer and a plurality of spaced second grid electrodes on the second surface using a sintering process; performing a laser process on the first grid electrodes and the adjacent region of the first grid electrodes; and applying a reverse voltage between the first grid electrodes and the second grid electrodes, wherein the adjacent region is defined as the region within a preset distance from the edge of the first grid electrode, the preset distance being no greater than 1.5 cm.

[0007] In addition, the laser power of the laser process is 1W to 60W, and / or the scanning speed is 2000mm / s to 50000mm / s.

[0008] In addition, the method for performing laser processing on the first gate electrode and the adjacent area of ​​the first gate electrode includes: continuously scanning the first gate electrode and the adjacent area of ​​the first gate electrode with a laser to form a laser processing area in the first gate electrode and the adjacent area, wherein the projection of the laser processing area on the surface of the first passivation layer covers the first gate electrode and the adjacent area.

[0009] In addition, the method for performing laser processing on the first gate electrode and the adjacent area of ​​the first gate electrode includes: using a laser to intermittently scan the first gate electrode and the adjacent area of ​​the first gate electrode to form a plurality of laser processing areas in the first gate electrode and the adjacent area, wherein the plurality of laser processing areas are arranged at intervals.

[0010] In addition, the laser is a nanosecond-level green laser, with a pulse width of 1ns to 200ns, and / or a laser power of 1W to 30W, and / or a scanning speed of 2000mm / s to 50000mm / s.

[0011] In addition, the magnitude of the current generated by the reverse voltage is 1A to 40A.

[0012] In addition, the steps of performing the laser process and the reverse voltage also include: forming metal micelles.

[0013] In addition, the metal micelles form conductive contact sites in the first passivation layer.

[0014] Additionally, the method of passing a reverse current between the first gate electrode and the second gate electrode includes: providing a power supply, the negative terminal of which is electrically connected to one of the first gate electrode or the second gate electrode, and the positive terminal of which is electrically connected to the other of the first gate electrode or the second gate electrode, to apply a reverse bias voltage between the first gate electrode and the second gate electrode.

[0015] In addition, the power supply further includes a clamp, through which the first gate electrode is electrically connected to the negative terminal of the power supply, wherein the clamp is electrically connected to the negative terminal of the power supply, and the clamp is also in electrical contact with at least one end of the first gate electrode.

[0016] In addition, the laser process further includes controlling the temperature of the plurality of first gate electrodes and the adjacent regions of the first gate electrodes so that the temperature of the first gate electrodes and the adjacent regions of the first gate electrodes is less than or equal to 50°C.

[0017] In addition, a method for controlling the temperature of the first gate electrode and the adjacent region of the first gate electrode includes: providing a temperature control station having a temperature control surface, and placing the second gate electrode on the temperature control surface.

[0018] In addition, a doped layer is formed before the first passivation layer is formed. The PN junction is formed between the doped layer and the substrate. The method of forming the first gate electrode on the surface of the first passivation layer by sintering includes: printing metal paste on the top surface of the first passivation layer in the area where the gate electrode is to be formed; and performing under-sintering treatment on the metal paste so that the metal paste penetrates the first passivation layer and makes electrical contact with the doped layer.

[0019] In addition, the peak temperature for under-sintering treatment is 200℃~750℃.

[0020] In addition, a doped layer is formed before the first passivation layer is formed. The PN junction is formed between the doped layer and the substrate. The material of the doped layer is the same as the material of the substrate. The first gate electrode is electrically connected to the doped layer.

[0021] In addition, a doped layer is formed before the first passivation layer is formed. The PN junction is formed between the doped layer and the substrate. The doped layer includes a first tunneling layer and a first doped conductive layer stacked sequentially in a direction away from the substrate. The doping element type of the first doped conductive layer is different from the doping element type of the substrate. The first gate electrode is electrically connected to the first doped conductive layer.

[0022] In addition, this application embodiment also provides a solar cell, which is prepared by the solar cell preparation method described in any of the above claims, comprising: a substrate having a first surface and a second surface opposite to each other; a PN junction and a first passivation layer located on the first surface, the first passivation layer being located on the PN junction; a plurality of spaced-apart first grid line electrodes located on the surface of the first passivation layer; and a plurality of spaced-apart second grid line electrodes located on the second surface.

[0023] The technical solution provided in this application has at least the following advantages: In the technical solution of the solar cell fabrication method provided in this application embodiment, an emitter is formed on the first surface of the substrate, and the doped layer and the substrate form a PN junction for separating photogenerated carriers. In the same process step, the first grid electrode and the adjacent area of ​​the first grid electrode on the first surface are laser-treated, and a reverse current is passed between the first grid electrode and the second grid electrode to reverse bias the PN junction. Under laser irradiation, a large number of carriers are generated in the first grid electrode and the adjacent area of ​​the first grid electrode. At the same time, due to the reverse bias of the PN junction, electrons in the carriers can be trapped on the surface of the doped layer and the first grid electrode, and then react with the first grid electrode, causing metal ions in the first grid electrode to precipitate and form metal micelles. The metal micelles form conductive contact sites in the doped layer and the first passivation layer, which can reduce contact impedance, thereby improving the fill factor of the solar cell and improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0025] Figure 1 This is a cross-sectional structural diagram corresponding to the step of providing a substrate in a method for fabricating a solar cell according to an embodiment of this application; Figure 2 This is a schematic cross-sectional view of the step of forming a doped layer in a method for fabricating a solar cell according to an embodiment of this application. Figure 3 This is a schematic cross-sectional view of the step of forming a doped layer in another method for fabricating a solar cell according to an embodiment of this application. Figure 4 This is a schematic cross-sectional view of the step of forming the first passivation layer in a method for fabricating a solar cell according to an embodiment of this application. Figure 5 This is a schematic cross-sectional view of the step of forming the second passivation layer in another method for fabricating a solar cell according to an embodiment of this application. Figure 6 This is a top view structural diagram corresponding to the step of forming an antireflection layer in a method for fabricating a solar cell according to an embodiment of this application; Figure 7 A top view of the structure corresponding to the step of forming the first grid electrode and the second grid electrode in another method for fabricating a solar cell according to an embodiment of this application; Figure 8This is a top view of the structure corresponding to the step of forming the first grid electrode in a method for fabricating a solar cell according to an embodiment of this application. Figure 9 This is a top view of the structure corresponding to the laser process step in a method for fabricating a solar cell according to an embodiment of this application. Figure 10 This is a side view of the structure corresponding to the laser process step in a method for fabricating a solar cell according to an embodiment of this application. Figure 11 This is a three-dimensional structural diagram corresponding to the laser process step in a method for fabricating a solar cell according to an embodiment of this application. Detailed Implementation

[0026] As is known from the background technology, the photoelectric conversion performance of solar cells obtained after fabricating grid lines using the current grid line fabrication process is poor.

[0027] This application provides a method for fabricating a solar cell. The method involves laser processing of a first grid electrode and its adjacent region on a first surface. Simultaneously, a reverse current is passed between the first and second grid electrodes to reverse-bias the PN junction. Under laser irradiation, a large number of charge carriers are generated in the first grid electrode and its adjacent region. Due to the reverse bias of the PN junction, electrons from these charge carriers are trapped on the doped layer and the surface of the first grid electrode, reacting with the first grid electrode to precipitate metal ions and form metal micelles. These metal micelles form conductive contact sites in the doped layer and the first passivation layer, reducing contact impedance and thus improving the fill factor and photoelectric conversion efficiency of the solar cell.

[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application.

[0030] refer to Figure 1 A substrate 100 is provided, the substrate 100 having opposing first surfaces and second surfaces.

[0031] The substrate 100 is used to receive incident light and generate photogenerated carriers. In some embodiments, the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The substrate 100 is an N-type semiconductor substrate, meaning that the substrate 100 is doped with N-type dopant ions, which may be any one of phosphorus ions, arsenic ions, or antimony ions. In some embodiments, the substrate 100 may also be a P-type semiconductor substrate, where the substrate 100 is doped with P-type dopant ions, which may be any one of boron ions, gallium ions, or indium ions.

[0032] Both the first and second surfaces of the substrate 100 can be used to receive incident or reflected light. In some embodiments, the first surface can be the back surface of the substrate 100, and the second surface can be the front surface of the substrate 100. In some embodiments, the first surface can also be the front surface of the substrate 100, in which case the second surface is the back surface of the substrate 100.

[0033] In some embodiments, a texturing process can be performed on the first and second surfaces of the substrate 100 to form a pyramidal textured surface on the first and second surfaces of the substrate 100. This can enhance the absorption and utilization efficiency of the first and second surfaces of the substrate 100 for incident light. In some embodiments, one of the first or second surfaces of the substrate 100 is a pyramidal textured surface, while the other of the first or second surface can be a non-pyramidal textured surface, such as a layered step morphology. This allows the film layer formed on the layered step morphology to have higher density and uniformity, thereby improving the quality of the formed film layer.

[0034] In some embodiments, the solar cell is a TOPCON (Tunnel Oxide Passivated Contact) cell. In some embodiments, the solar cell may also be a PERC (Passivated Emitter and Rear Cell) cell or an HJT (Heterojunction technology solar cell) cell.

[0035] refer to Figures 2 to 4 A doped layer 110 and a first passivation layer 120 are formed on the first surface in a direction opposite to the substrate 100. The doped layer 110 and the substrate 100 form a PN junction. The PN junction can receive incident light irradiating the first surface of the substrate 100 and generate electron-hole pairs. When the substrate 100 is an N-type substrate, the separated electrons move into the substrate 100, and the separated holes move into the doped layer 110.

[0036] In some embodiments, the material of the doped layer is the same as that of the substrate 100, and the doped layer 110 is used as the emitter of the solar cell. The doped layer 110 is a single-layer structure, and the doping element type of the doped layer 110 is different from that of the substrate 100, and it is used to form a PN junction with the substrate 100.

[0037] In some embodiments, when the doped layer 110 serves as an emitter, the method of formation may include: refer to Figure 2 An initial substrate is provided, and a diffusion process is performed on one surface of the initial substrate to diffuse a dopant element into a portion of the initial substrate, forming a doped layer 110. The portion of the initial substrate other than the doped layer 110 forms a substrate 100. In some embodiments, when the substrate 100 is an N-type substrate, a boron diffusion process can be performed on the surface of the initial substrate, and when the substrate 100 is a P-type substrate, a phosphorus diffusion process can be performed on the surface of the initial substrate.

[0038] refer to Figure 3 In some embodiments, the doped layer 110 includes a first tunneling layer 111 and a first doped conductive layer 112 sequentially stacked along a direction away from the substrate 100. The doping element type of the first doped conductive layer 112 is different from that of the substrate 100. The first tunneling layer 111 and the first doped conductive layer 112 are used to form a passivation contact structure. In some embodiments, when the doped layer 110 is a passivation contact structure, and the first doped conductive layer 112 in the passivation contact structure forms a PN junction with the substrate 100, the first surface can be the back surface of the substrate 100, used to form a back junction. A back junction refers to a PN junction formed on the back surface of the substrate 100.

[0039] The first doped conductive layer 112 is used to form a field passivation layer. The field passivation effect is as follows: an electrostatic field pointing towards the interior of the substrate 100 is formed at the interface of the substrate 100, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and resulting in a lower recombination rate of carriers at the interface of the substrate 100. This leads to a larger open-circuit voltage, short-circuit current, and fill factor of the solar cell, thus improving the photoelectric conversion performance of the solar cell. In some embodiments, the material of the first doped conductive layer 112 can be at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0040] The first tunneling layer 111 is in direct contact with the first surface of the substrate 100, serving to achieve interface passivation of the first surface of the substrate 100, thereby achieving a chemical passivation effect, promoting the recombination of photogenerated carriers, and improving the fill factor and conversion efficiency of the solar cell. In some embodiments, the material of the first tunneling layer 111 can be a dielectric material, such as at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0041] In some embodiments, the method of forming the first tunneling layer 111 and the first doped conductive layer 112 may include: refer to Figure 3 A first tunneling layer 111 is formed on the first surface of the substrate 100 using a deposition process, such as chemical vapor deposition. In some embodiments, when the material of the first tunneling layer 111 is silicon oxide, the first tunneling layer 111 can also be formed using an in-situ generation process, such as thermal oxidation or nitric acid passivation.

[0042] After the first tunneling layer 111 is formed, an amorphous silicon layer is formed on the surface of the first tunneling layer 111 away from the substrate 100 using a deposition process. Then, a crystallization process is performed on the amorphous silicon layer to convert it into a polycrystalline silicon layer. After the polycrystalline silicon layer is formed, a doping process can be performed on the polycrystalline silicon layer to form a first doped conductive layer 112. Specifically, conductive ions can be doped into the polycrystalline silicon layer by ion implantation or source diffusion, such as phosphorus ions or boron ions.

[0043] The first passivation layer 120 can effectively passivate the first surface of the substrate 100. For example, it can effectively chemically passivate the dangling bonds on the first surface of the substrate 100, reduce the defect state density on the first surface of the substrate 100, and effectively suppress carrier recombination on the first surface of the substrate 100. In some embodiments, the first passivation layer 120 can be a single-layer structure; in other embodiments, the first passivation layer 120 can be a multilayer structure. In some embodiments, the material of the first passivation layer 120 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0044] refer to Figure 4 In some embodiments, the method of forming the first passivation layer 120 may include forming the first passivation layer 120 on the surface of the doped layer 110 away from the substrate 100 using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0045] refer to Figure 5 A second passivation layer 130 is formed on the second surface.

[0046] In some embodiments, the second passivation layer 130 includes at least a second tunneling layer 131 and a second doped conductive layer 132 sequentially stacked along a direction away from the substrate 100, wherein the doping element type of the second doped conductive layer 132 is the same as the doping element type of the substrate 100. That is, the second passivation layer 130 is used to form a passivation contact structure.

[0047] In some embodiments, when the doped layer 110 serves as the emitter and the second passivation layer 130 forms a passivation contact structure, the resulting solar cell is a TOPCON cell.

[0048] In some embodiments, if the second passivation layer 130 includes a second tunneling layer 131 and a second doped conductive layer 132, the method for forming the second tunneling layer 131 and the second doped conductive layer 132 can be similar to the method for forming the first tunneling layer 111 and the first doped conductive layer 112 described above, and will not be repeated hereafter.

[0049] In some embodiments, the material of the second tunneling layer 131 can be a dielectric material, such as at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon, and the material of the second doped conductive layer 132 can be at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0050] It is understandable that since the doped layer 110 located on the first surface forms a PN junction with the substrate 100, the doping element type of the second doped conductive layer 132 is the same as that of the substrate 100, so that the second doped conductive layer 132 and the substrate 100 form a high-low junction, which can create a potential barrier effect for the charge carriers and increase the rate at which the charge carriers in the substrate 100 are transported to the second doped conductive layer 132.

[0051] refer to Figure 6 In some embodiments, when the second passivation layer 130 includes a second tunneling layer 131 and a second doped conductive layer 132, it further includes forming an antireflection layer 140 on the surface of the second passivation layer 130. The antireflection layer 140 is used to reduce the reflection of incident light by the second surface of the substrate 100, thereby increasing the absorption and utilization rate of incident light by the substrate 100. In some embodiments, the antireflection layer 140 may be a single-layer or multi-layer structure, and the material of the antireflection layer 140 may be at least one of alumina, silicon oxide, silicon nitride, or silicon oxynitride.

[0052] In some embodiments, the antireflection layer 140 may be formed using a PECVD process.

[0053] In some embodiments, the material of the second passivation layer may also be at least one of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride, that is, the second passivation layer 130 serves as passivation and anti-reflection. In some embodiments, if the doped layer 110 is used to form an emitter, the material of the second passivation layer 130 may also be at least one of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride, and the formed solar cell may be a PERC cell.

[0054] refer to Figure 7 as well as Figure 8 , Figure 7 for Figure 8 A cross-sectional structural diagram along the aa' direction shows that multiple spaced first gate electrodes 150 are formed on the surface of the first passivation layer 120 using a sintering process.

[0055] In some embodiments, when the doped layer 110 serves as the emitter, the first gate electrode 150 is electrically connected to the emitter and is used to collect charge carriers in the emitter. In some embodiments, when the doped layer 110 is a passivated contact structure, the first gate electrode 150 is electrically connected to the first doped conductive layer 112 and is used to collect charge carriers in the first doped conductive layer 112.

[0056] In some embodiments, a method for forming the first gate electrode 150 on the surface of the first passivation layer 120 using a sintering process includes: A metal paste is printed on the top surface of the first passivation layer 120 in the region where the gate electrode is to be formed. In some embodiments, the metal paste contains highly corrosive components such as glass powder, so that during sintering, the corrosive components will corrode the passivation layer and part of the doped layer 110, thereby allowing the metal paste to penetrate into the passivation layer and part of the doped layer 110. In some embodiments, a screen printing process can be used to print the metal paste on the top surface of the passivation layer. In some embodiments, the material of the metal paste may include silver.

[0057] The metal paste is subjected to under-sintering treatment to allow it to penetrate the first passivation layer 120 and make electrical contact with the doped layer 110. Under-sintering treatment refers to heat-treating the metal paste at a lower temperature than sintering treatment, so that the metal paste can penetrate into the doped layer 110.

[0058] In some embodiments, the peak temperature for under-sintering is 200°C to 750°C. For example, it can be 200°C to 250°C, 250°C to 300°C, 300°C to 350°C, 350°C to 390°C, 390°C to 440°C, 440°C to 490°C, 490°C to 530°C, 530°C to 580°C, 580°C to 640°C, 640°C to 660°C, 660°C to 700°C, or 700°C to 750°C. Within this temperature range, the heat treatment temperature is relatively low, preventing damage to the first passivation layer 120 and the doped layer 110 caused by the sintering process. Furthermore, due to the lower sintering temperature, the sintering depth of the metal paste in the doped layer 110 is smaller, thereby reducing the contact area between the formed first gate electrode 150 and the doped layer 110, thus enabling the solar cell to obtain a higher open-circuit voltage.

[0059] It is understandable that a smaller sintering depth, resulting in a smaller contact area between the first gate electrode 150 and the doped layer 110, may affect the fill factor of the solar cell, leading to a lower fill factor. However, in this embodiment, after the sintering process, an additional laser processing step and a step of reverse biasing the PN junction are added to form contact sites in the doped layer 110 and the first passivation layer 120, reducing contact impedance and thus improving the fill factor of the solar cell. Therefore, by combining under-sintering treatment, laser processing, and the step of introducing reverse current to reverse bias the PN junction, both the open-circuit voltage and the fill factor can be improved simultaneously, thereby enhancing the photoelectric conversion efficiency of the solar cell.

[0060] In addition, within the temperature range of 200℃ to 750℃, the heat treatment temperature is not too low, so that the metal slurry can be burned through to the preset depth at this heat treatment temperature.

[0061] refer to Figure 7 Multiple second gate line electrodes 160 are formed on the surface of the second passivation layer 130 at intervals.

[0062] In some embodiments, when the second passivation layer 130 includes at least a second tunneling layer 131 and a second doped conductive layer 132 stacked sequentially in a direction away from the substrate 100, the second gate electrode 160 is electrically connected to the second doped conductive layer 132.

[0063] It is worth noting that the method for forming the second gate electrode 160 can be the same as the method for forming the first gate electrode 150, that is, metal paste can be printed on the surface of the second passivation layer 130, and then the metal paste can be sintered to form the second gate electrode 160. For details, please refer to the description of forming the first gate electrode 150.

[0064] refer to Figure 8 In the same process step, laser processing is performed on the first gate electrode 150 and the adjacent area of ​​the first gate electrode 150, and a reverse current is passed between the first gate electrode 150 and the second gate electrode 160 to reverse bias the PN junction. The adjacent area is defined as the area within a preset distance d from the edge of the first gate electrode 150.

[0065] Laser treatment is performed on the first gate electrode 150 and its adjacent area on the first surface. Simultaneously, a reverse current is passed between the first gate electrode 150 and the second gate electrode 160 to reverse bias the PN junction. Under laser irradiation, a large number of charge carriers are generated in the first gate electrode 150 and its adjacent area. Furthermore, due to the reverse bias of the PN junction, electrons from these charge carriers are trapped on the surface of the doped layer 110 and the first gate electrode 150. These electrons react with the first gate electrode 150, causing metal ions to precipitate and form metal micelles. These metal micelles form conductive contact sites in the doped layer 110 and the first passivation layer 120, reducing contact impedance and thus improving the fill factor and photoelectric conversion efficiency of the solar cell.

[0066] In some embodiments, the metal paste includes silver, which has good electrical conductivity. Silver ions are deposited in the first gate electrode 150 to form silver micelles. The silver micelles form conductive contact sites on the doped layer 110, the first passivation layer 120, and the first surface, reducing contact impedance. This not only increases the fill factor but also improves the efficiency of carrier transport to the first gate electrode 150, thereby improving the carrier collection capability of the first gate electrode 150.

[0067] Since the charge carriers generated by the laser process react with the first gate electrode 150, laser irradiation is performed on the first gate electrode 150 and its adjacent area. This generates a large number of charge carriers in the adjacent area of ​​the first gate electrode 150, thereby reducing the distance the charge carriers travel to the first gate electrode 150, reducing transmission loss, and ensuring that most of the charge carriers generated by the laser process can react with the first gate electrode 150, thus improving reaction efficiency.

[0068] Furthermore, since the laser process is performed only on the first grid line electrode 150 and the area adjacent to the first grid line electrode 150, the area of ​​the solar cell processed by the laser process is smaller, the laser process time is shortened, and thus the processing efficiency can be improved.

[0069] Understandably, the laser in the laser process can irradiate the doped layer 110 or the substrate 100 to generate more charge carriers in the doped layer 110 or the substrate 100.

[0070] In some embodiments, the preset distance d is no greater than 1.5 cm. In some embodiments, the preset distance d can be equal to 1.5 cm; in some embodiments, the preset distance d can also be less than 1.5 cm, for example, it can be 0.005 cm, 0.01 cm, 0.015 cm, 0.02 cm, 0.05 cm, 0.1 cm, 0.2 cm, 0.4 cm, 0.5 cm, 0.6 cm, 0.8 cm, 1 cm, 1.2 cm, 1.3 cm, or 1.5 cm. Setting the preset distance d within this range allows for a larger width of the adjacent area, enabling the laser process to process a larger area, thereby generating more charge carriers. These charge carriers can then react with the first gate electrode 150 to precipitate metal ions, forming more contact sites and improving the fill factor. Furthermore, within this range, the preset distance d is not too large, thus improving the efficiency of the laser process.

[0071] In some embodiments, the preset distance d can also be greater than 1.5 cm. For example, all areas of the first surface except the first gate electrode 150 can be irradiated with laser, thereby generating a larger number of charge carriers, so that more electrons react with the first gate electrode 150, causing metal ions in the first gate electrode 150 to be deposited and forming more contact sites.

[0072] In some embodiments, the laser power of the laser process is 1W to 60W, for example, it can be 1W to 5W, 5W to 10W, 10W to 15W, 15W to 20W, 20W to 25W, 25W to 30W, 30W to 35W, 35W to 40W, 45W to 50W, 50W to 55W, or 55W to 60W; the scanning speed is 2000mm / s to 50000mm / s, for example, it can be 2000mm / s to 5000mm / s, 5000mm / s to 8000mm / s, or 8000mm / s. The speed ranges from 10000 mm / s to 12000 mm / s, 12000 mm / s to 16000 mm / s, 16000 mm / s to 19000 mm / s, 19000 mm / s to 25000 mm / s, 25000 mm / s to 30000 mm / s, 30000 mm / s to 35000 mm / s, 35000 mm / s to 40000 mm / s, 40000 mm / s to 45000 mm / s, or 45000 mm / s to 50000 mm / s. Within this range, the laser energy generated by the laser process can reach the doped layer 110 or the substrate 100, thereby generating charge carriers in the emitter and the substrate 100. Furthermore, within this range, a larger number of charge carriers are generated, allowing more charge carriers to react with the first gate electrode 150. In addition, within this range, the laser energy of the laser process is not too high, preventing the laser energy from causing thermal damage to the substrate 100 and the first gate electrode 150.

[0073] In some embodiments, the laser used in the laser process can be any one of infrared laser, green laser, ultraviolet laser, or ultraviolet-green-infrared laser, and the laser used in the laser processing can be any one of CO2 laser, excimer laser, Ti:sapphire laser, semiconductor laser, or high-power short-pulse (fs-ns) laser.

[0074] For different lasers, different laser power, different pulse width, or different scanning speed can be set to generate a larger number of charge carriers.

[0075] For example, in some embodiments, the laser can be a nanosecond-level green laser with a pulse width of 1ns to 200ns, such as 1ns to 10ns, 10ns to 20ns, 20ns to 35ns, 35ns to 40ns, 40ns to 60ns, 60ns to 80ns, 80ns to 110ns, 110ns to 150ns, 150ns to 180ns, or 180ns to 200ns; the laser power is 1W to 30W, such as 1W to 30W, 1W to 5W, 5W to 8W, 8W to 12W, 12W to 16W, 16W to 19W, 19W to 22W, 22W to 26W, 26W to 28W, or 28W to 30W; the scanning speed is 2 000mm / s~50000mm / s, for example, it can be 2000mm / s~5000mm / s, 5000mm / s~8000mm / s, 8000mm / s~10000mm / s, 10000mm / s~12000mm / s, 12000mm / s~16000mm / s, 16000mm / s~19000mm / s, 19000mm / s~25000mm / s, 25000mm / s~30000mm / s, 30000mm / s~35000mm / s, 35000mm / s~40000mm / s, 40000mm / s~45000mm / s or 45000mm / s~50000mm / s.

[0076] In some embodiments, a method for performing laser processing on the first gate electrode 150 and its adjacent region includes: continuously scanning the first gate electrode 150 and its adjacent region using a laser to form a laser-processed region on the first gate electrode 150 and its adjacent region. The projection of the laser-processed region onto the surface of the first passivation layer 120 covers the first gate electrode 150 and its adjacent region. That is, the entire area of ​​the first gate electrode 150 and its adjacent region is considered as the region to be laser-processed. The laser process performs laser processing on each location of the first gate electrode 150 and its adjacent region, so that the first gate electrode 150 and its adjacent region are all transformed into laser-processed regions. This results in a larger area of ​​the laser-processed region, thereby generating more charge carriers. These charge carriers then react with the first gate electrode 150, resulting in more deposited metal ions, thus creating more contact sites on the doped layer 110, the first gate electrode 150, and the first surface.

[0077] refer to Figure 9In some embodiments, the method of performing laser processing on the first gate electrode 150 and its adjacent region includes: using a laser to intermittently scan the first gate electrode 150 and its adjacent region to form multiple laser processing regions 170 in the first gate electrode 150 and its adjacent region, with the multiple laser processing regions 170 arranged at intervals. That is, the laser process performs a patterned scan of the first gate electrode 150 and its adjacent region, so that a portion of the first gate electrode 150 and its adjacent region are processed by the laser process to form laser processing regions 170, while the remaining portion of the first gate electrode 150 and its adjacent region are not processed by the laser process, resulting in a smaller area of ​​the formed laser processing regions 170. Thus, the area of ​​the laser processing regions 170 can be controlled by the scanning method of the laser process, thereby controlling the number of generated charge carriers to ensure that the number of charge carriers meets the requirements.

[0078] Since the first gate electrode 150 is electrically in contact with the doped layer 110, and the doped layer 110 forms a PN junction with the substrate 100, when the PN junction is reverse biased, it can trap electrons in the charge carriers. The trapped electrons react with the first gate electrode 150. Therefore, in some embodiments, the first gate electrode 150 and its adjacent area are laser-processed so that the generated charge carriers are closer to the first gate electrode 150. This allows the charge carriers generated in the area adjacent to the first gate electrode 150 to react quickly with the first gate electrode after the PN junction is reverse biased, thereby increasing the number of contact bit lines generated.

[0079] In some embodiments, a laser process can be configured to simultaneously laser process the first gate electrode 150, the adjacent region of the first gate electrode 150, the second gate electrode 160, and the adjacent region of the second gate electrode 160.

[0080] refer to Figure 10 In some embodiments, the laser 10 used in the laser process can be a mobile laser 10, located at the first gate electrode 150 (reference). Figure 9 Above, when the laser 10 emits a laser, by moving the laser 10, laser scanning can be performed on the first gate electrode 150 and the adjacent area of ​​the first gate electrode 150.

[0081] Reverse current refers to the current flowing between the first gate electrode 150 and the second gate electrode 160, causing the current flowing through the PN junction from the N-region to the P-region, thereby reversing the PN junction. This means the built-in electric field in the PN junction is in the same direction as the applied electric field, and the PN junction is not conductive. This confines electrons in the charge carriers within the doped layer 110. In some embodiments, the magnitude of the reverse current is 1A to 40A, for example, 1A to 5A, 5A to 10A, 10A to 15A, 15A to 20A, 20A to 25A, 25A to 30A, 30A to 35A, or 35A to 40A. Within this range, the PN junction is reverse-biased, and a larger number of charge carriers are confined to the doped layer 110 and the surface of the first gate electrode 150, causing electrons in the charge carriers to react with the first gate electrode 150, promoting the deposition of metal ions in the first gate electrode 150.

[0082] In some embodiments, the method of passing a reverse current between the first gate electrode 150 and the second gate electrode 160 includes: providing a power supply, the negative terminal of which is electrically connected to one of the first gate electrode 150 or the second gate electrode 160, and the positive terminal of which is electrically connected to the other of the first gate electrode 150 or the second gate electrode 160, to apply a reverse bias voltage between the first gate electrode 150 and the second gate electrode 160. Since the first gate electrode 150 and the second gate electrode 160 are located on opposite surfaces of the substrate 100, a circuit can be formed between the substrate 100 and the doped layer 110 when a reverse bias voltage is applied between the first gate electrode 150 and the second gate electrode 160. The first gate electrode 150 or the second gate electrode 160, which is electrically connected to the negative terminal of the power supply, is electrically connected to the P region of the PN junction, and the first gate electrode 150 or the second gate electrode 160, which is electrically connected to the positive terminal of the power supply, is electrically connected to the N region of the PN junction, so that the voltage of the N region in the PN junction is higher than the voltage of the P region, and the current flows from the N region to the P region, so that the PN junction is not conducting.

[0083] In some embodiments, the dopant element in the doped layer 110 is P-type, and the dopant element in the substrate 100 is N-type. That is, the substrate 100 forms the N-region of the PN junction, and the doped layer 110 forms the P-region of the PN junction. Based on this, in some embodiments, the method of passing a reverse current between the first gate electrode 150 and the second gate electrode 160 includes: electrically connecting the negative terminal of a power supply to the first gate electrode 150 and electrically connecting the positive terminal of the power supply to the second gate electrode 160. That is, the negative terminal of the power supply is electrically connected to the P-region, and the positive terminal of the power supply is electrically connected to the N-region, such that the voltage in the N-region is higher than the voltage in the P-region, forming a reverse bias between the PN junctions.

[0084] In some embodiments, if the doping element type in the doped layer 110 is N-type and the doping element type in the substrate 100 is P-type, then the negative terminal of the power supply is electrically connected to the second gate electrode 160, and the positive terminal of the power supply is electrically connected to the first gate electrode 150, so that the N-region is connected to the positive terminal of the power supply and the P-region is connected to the negative terminal of the power supply.

[0085] refer to Figure 7 , Figure 10 as well as Figure 11 In some embodiments, if the doped element type in the doped layer 110 is P-type and the doped element type in the substrate 100 is N-type, the system further includes: a clamp 20, through which the first gate electrode 150 is electrically connected to the negative terminal of the power supply. The clamp 20 is electrically connected to the negative terminal of the power supply and also makes electrical contact with at least one end of the first gate electrode 150. The clamp 20 is electrically connected to the negative terminal of the power supply to lead out the electrical signal from the negative terminal. In some embodiments, the clamp 20 and the negative terminal of the power supply can be electrically connected via a wire. The clamp 20 is electrically connected to at least one end of the first gate electrode 150. On the one hand, it is used to transmit the signal of the negative power supply to the first gate electrode 150 so that the first gate electrode 150 is connected to the negative voltage. On the other hand, since the clamp 20 is only electrically connected to the end of the first gate electrode 150, it can avoid excessive shading of the surface of the first gate electrode 150, so that during laser processing, the laser irradiates the first gate electrode 150 and the adjacent area of ​​the first gate electrode 150.

[0086] In some embodiments, the clamp 20 may make electrical contact with only one end of the first gate electrode 150; in some embodiments, in order to improve the reliability of the electrical contact between the clamp 20 and the first gate electrode 150, the clamp 20 is configured to make contact with both ends of the first gate electrode 150, thereby enhancing the transmission rate of the negative power supply signal to the first gate electrode 150.

[0087] Understandably, during the laser processing step, the laser can generate a thermal effect on the first gate electrode 150 and its adjacent area, potentially leading to excessively high temperatures in the first gate electrode 150 or its adjacent area. This can adversely affect the film layer of the first gate electrode 150 and its adjacent area. For example, it can impact the performance of the first passivation layer 120, the doped layer 110, or the substrate 100 near the first gate electrode 150, thereby damaging the photoelectric conversion performance of the solar cell.

[0088] Based on the above considerations, in some embodiments, the laser processing step further includes controlling the temperature of the multiple first gate electrodes 150 and their adjacent regions to ensure that the temperature of the first gate electrodes 150 and their adjacent regions is less than or equal to 50°C. This prevents overheating of the first gate electrodes 150 and their adjacent regions during the laser processing.

[0089] In some embodiments, a method for controlling the temperature of the first gate electrode 150 and its adjacent region includes: refer to Figure 7 , Figure 10 as well as Figure 11 A temperature control console 30 is provided, which has a temperature control surface whose temperature can be adjusted. In some embodiments, a cooling system may be provided in the temperature control console 30 for adjusting the temperature of the temperature control surface. In some embodiments, the cooling system may be a water cooling system.

[0090] The solar cell is placed on the temperature control surface of the temperature control station 30. Since the first grid electrode 150 and its adjacent area need to be laser-processed, the side with the second grid electrode 160 is placed on the temperature control surface to perform laser processing on the first grid electrode 150 and its adjacent area.

[0091] In some embodiments, the temperature of the temperature control surface can be controlled to be lower, so that the surface temperature of the second gate electrode 160 and the second passivation layer 130 is lower. This causes the higher-temperature first gate electrode 150 and its adjacent region, such as the first passivation layer 120, to exchange heat with the lower-temperature second gate electrode 160 and the second passivation layer 130, thereby cooling the first gate electrode 150 and its adjacent region.

[0092] It is easy to see that the second grid electrode 160 and the second passivation layer 130 are located on the temperature control surface, which allows the temperature control surface to regulate the temperature of the entire second passivation layer 130. This enables heat exchange between the entire first passivation layer 120 and the first grid electrode 150 and the second passivation layer 130 and the second grid electrode 160, which helps to maintain a relatively balanced overall temperature of the solar cell.

[0093] In the solar cell fabrication method provided in the above embodiments, the first grid electrode 150 and its adjacent area on the first surface are laser-treated. Simultaneously, a reverse current is passed between the first grid electrode 150 and the second grid electrode 160 to reverse-bias the PN junction. Under laser irradiation, a large number of charge carriers are generated in the first grid electrode 150 and its adjacent area. Furthermore, due to the reverse bias of the PN junction, electrons in the charge carriers are trapped on the surface of the doped layer 110 and the first grid electrode 150, reacting with the first grid electrode 150 and causing metal ions to precipitate and form metal micelles. These metal micelles form conductive contact sites in the doped layer 110 and the first passivation layer 120, reducing contact impedance and thus improving the fill factor and photoelectric conversion efficiency of the solar cell.

[0094] In addition, this application also provides a solar cell, which is prepared using the solar cell preparation method provided in the above embodiments, with reference to... Figure 7 The system includes: a substrate 100 having a first surface and a second surface opposite to each other; a doped layer 110 and a first passivation layer 120 stacked on the first surface in a direction away from the substrate 100, the doped layer 110 and the substrate 100 forming a PN junction; a second passivation layer 130 on the second surface; a plurality of spaced first gate electrodes 150 on the surface of the first passivation layer 120; and a plurality of spaced second gate electrodes 160 on the surface of the second passivation layer 130.

[0095] After forming the first gate electrode 150 and the second gate electrode 160, laser processing is performed on the first surface of the first gate electrode 150 and its adjacent area. Simultaneously, a reverse current is passed between the first gate electrode 150 and the second gate electrode 160 to reverse bias the PN junction. This results in a large number of electrons from charge carriers in the first gate electrode 150 and its adjacent area being trapped by the PN junction on the surface of the doped layer 110 and the first gate electrode 150. These electrons then react with the first gate electrode 150, causing metal ions to precipitate and form metal micelles. These metal micelles form conductive contact sites in the doped layer 110 and the first passivation layer 120, reducing contact impedance and thus improving the fill factor and photoelectric conversion efficiency of the solar cell.

[0096] In some embodiments, the material of the doped layer 110 is the same as that of the substrate 100, and the doped layer 110 is used as the emitter of the solar cell. The doped layer 110 is a single-layer structure, and the type of doping element in the doped layer 110 is different from that in the substrate 100, and it is used to form a PN junction with the substrate 100. The first gate electrode 150 is electrically connected to the doped layer 110.

[0097] In some embodiments, the doped layer 110 may also include: a first tunneling layer 111 sequentially stacked along a direction away from the substrate 100 (see reference). Figure 3 ) and the first doped conductive layer 112 (reference) Figure 3 The doping element type of the first doped conductive layer 112 is different from that of the substrate 100. The first tunneling layer 111 and the first doped conductive layer 112 are used to form a passivation contact structure. The first gate electrode 150 is electrically connected to the first doped conductive layer 112.

[0098] The first passivation layer 120 can provide a good passivation effect on the first surface of the substrate 100. In some embodiments, the first passivation layer 120 can be a single-layer structure, and in other embodiments, the first passivation layer 120 can be a multi-layer structure. In some embodiments, the material of the first passivation layer 120 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The first gate electrode 150 penetrates the first passivation layer 120 and is electrically connected to the doped layer 110.

[0099] In some embodiments, the second passivation layer 130 includes at least a second tunneling layer 131 and a second doped conductive layer 132 sequentially stacked along a direction away from the substrate 100, wherein the doping element type of the second doped conductive layer 132 is the same as that of the substrate 100. That is, the second passivation layer 130 is used to form a passivation contact structure. The second gate electrode 160 is electrically connected to the second doped conductive layer 132.

[0100] In some embodiments, when the second passivation layer 130 includes a second tunneling layer 131 and a second doped conductive layer 132, it further includes forming an antireflection layer 140 on the surface of the second passivation layer 130. The antireflection layer 140 is used to reduce the reflection of incident light by the second surface of the substrate 100, thereby increasing the absorption and utilization rate of incident light by the substrate 100. In some embodiments, the antireflection layer 140 may be a single-layer or multi-layer structure, and the material of the antireflection layer 140 may be at least one of alumina, silicon oxide, silicon nitride, or silicon oxynitride.

[0101] In some embodiments, the material of the second passivation layer 130 may also be at least one of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride. That is, the second passivation layer 130 may not serve as a passivation contact structure, but may instead provide passivation and anti-reflection effects.

[0102] Although this application discloses preferred embodiments as described above, it is not intended to limit the claims. Any person skilled in the art can make several possible changes and modifications without departing from the concept of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

[0103] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for preparing a solar cell, characterized in that, include: A substrate is provided, the substrate having opposing first and second surfaces; A PN junction and a first passivation layer are formed on a first surface, wherein the first passivation layer is located on the PN junction; A sintering process is used to form multiple spaced first gate electrodes on the surface of the first passivation layer and multiple spaced second gate electrodes on the second surface. Laser processing is performed on the first gate electrode and its adjacent region, and a reverse voltage is applied between the first gate electrode and the second gate electrode. The adjacent region is defined as the region within a preset distance from the edge of the first gate electrode, and the preset distance is no greater than 1.5 cm.

2. The method for preparing a solar cell according to claim 1, characterized in that, The laser power of the laser process is 1W to 60W, and / or the scanning speed is 2000mm / s to 50000mm / s.

3. The method for preparing a solar cell according to claim 2, characterized in that, The method for performing laser processing on the first gate electrode and its adjacent area includes: continuously scanning the first gate electrode and its adjacent area using a laser to form a laser processing area in the first gate electrode and its adjacent area, wherein the projection of the laser processing area onto the surface of the first passivation layer covers the first gate electrode and its adjacent area.

4. The method for preparing a solar cell according to claim 2, characterized in that, The method for performing laser processing on the first gate electrode and its adjacent area includes: using a laser to intermittently scan the first gate electrode and its adjacent area to form a plurality of laser processing areas in the first gate electrode and its adjacent area, wherein the plurality of laser processing areas are arranged at intervals.

5. The method for preparing a solar cell according to claim 3 or 4, characterized in that, The laser is a nanosecond-level green laser, with a pulse width of 1ns to 200ns, and / or a laser power of 1W to 30W, and / or a scanning speed of 2000mm / s to 50000mm / s.

6. The method for preparing a solar cell according to claim 1, characterized in that, The magnitude of the current generated by the reverse voltage is 1A~40A.

7. The method for preparing a solar cell according to claim 1, characterized in that, The steps of performing the laser process and the reverse voltage further include: Metal micelles are formed.

8. The method for preparing a solar cell according to claim 7, characterized in that, The metal micelles form conductive contact sites in the first passivation layer.

9. The method for preparing a solar cell according to claim 1, characterized in that, The method of passing a reverse current between the first gate electrode and the second gate electrode includes: providing a power supply, the negative terminal of which is electrically connected to one of the first gate electrode or the second gate electrode, and the positive terminal of which is electrically connected to the other of the first gate electrode or the second gate electrode, to apply a reverse bias voltage between the first gate electrode and the second gate electrode.

10. The method for preparing a solar cell according to claim 9, characterized in that, The power supply further includes a clamp, through which the first gate electrode is electrically connected to the negative terminal of the power supply, wherein the clamp is electrically connected to the negative terminal of the power supply, and the clamp is also in electrical contact with at least one end of the first gate electrode.

11. The method for preparing a solar cell according to claim 1, characterized in that, The laser process further includes controlling the temperature of the plurality of first gate electrodes and the adjacent regions of the first gate electrodes to make the temperature of the first gate electrodes and the adjacent regions of the first gate electrodes less than or equal to 50°C.

12. The method for preparing a solar cell according to claim 11, characterized in that, A method for controlling the temperature of the first gate electrode and its adjacent region includes: A temperature control station is provided, the temperature control station having a temperature control surface, and the second grid line electrode is placed on the temperature control surface.

13. The method for preparing a solar cell according to claim 1, characterized in that, Before forming the first passivation layer, a doped layer is also formed, and the PN junction is formed between the doped layer and the substrate. The method for forming the first gate electrode on the surface of the first passivation layer by sintering includes: Metal paste is printed on the top surface of the first passivation layer in the region where the gate electrode is to be formed; The metal paste is subjected to under-sintering treatment to allow the metal paste to penetrate the first passivation layer and make electrical contact with the doped layer.

14. The method for preparing a solar cell according to claim 13, characterized in that, The peak temperature of the undersintering treatment is 200℃~750℃.

15. The method for preparing a solar cell according to claim 1, characterized in that, Before forming the first passivation layer, a doped layer is also formed. The PN junction is formed between the doped layer and the substrate. The material of the doped layer is the same as the material of the substrate. The first gate electrode is electrically connected to the doped layer.

16. The method for preparing a solar cell according to claim 1, characterized in that, Before forming the first passivation layer, a doped layer is also formed. The PN junction is formed between the doped layer and the substrate. The doped layer includes a first tunneling layer and a first doped conductive layer stacked sequentially in a direction away from the substrate. The doping element type of the first doped conductive layer is different from that of the substrate. The first gate electrode is electrically connected to the first doped conductive layer.

17. A solar cell, prepared by the method for preparing a solar cell according to any one of claims 1 to 16, characterized in that, include: A substrate having opposing first and second surfaces; A PN junction and a first passivation layer are located on the first surface, wherein the first passivation layer is located on the PN junction; Multiple spaced-apart first gate line electrodes are located on the surface of the first passivation layer; Multiple spaced-apart second gate line electrodes are located on the second surface.

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