Ethernet multi-link fault diagnosis and recovery method and system based on FPGA

Abstract

The application provides a FPGA-based Ethernet multi-link fault diagnosis and recovery method and system. The method comprises the following steps: a CPU loads a FPGA bit stream file, and starts a FPGA internal function module and a periodic sending of a probe packet; the FPGA internal function module performs self-checking during operation, and when an error is detected, the corresponding internal function module and its previous stage module are reset; the probe packet is looped back through a FPGA internal virtual network port loopback channel for loopback detection, and when no loopback probe packet is received within a continuous preset probe period, the FPGA records a link timeout state; the CPU determines a fault link according to the link timeout state; the CPU controls the FPGA to reset the fault link; and when the link is reset and the fault link timeout is detected again within a continuous preset probe period, the CPU reloads the FPGA bit stream file. The application realizes active monitoring, accurate positioning and hierarchical recovery of multi-link faults, and significantly improves the reliability and real-time performance of industrial Ethernet communication.

Description

Technical Field

[0001] This invention relates to the field of industrial control network communication technology, and more specifically, to an FPGA-based Ethernet multi-link fault diagnosis and recovery method and system. Background Technology

[0002] With the continuous improvement of industrial automation, Distributed Control Systems (DCS) are widely used in power, chemical, nuclear industries, and large-scale manufacturing. DCS systems typically rely on Industrial Ethernet to achieve data exchange between controllers, field devices, and monitoring systems. Compared to traditional fieldbus technology, Industrial Ethernet offers advantages such as high transmission speed, flexible network topology, and ease of expansion, meeting the real-time and reliability requirements of modern industrial control systems. Therefore, Ethernet communication has gradually become the core data transmission method in DCS systems.

[0003] In practical engineering applications, to ensure communication reliability and continuous system operation, industrial control systems typically employ redundant link designs, such as dual-link or multi-link backup structures, to maintain system communication functionality even when some links fail. In existing technologies, a common implementation involves the CPU directly connecting to the Ethernet physical layer chip (PHY) for communication control. This approach has a relatively simple hardware structure, but it is limited by the number of Ethernet interfaces provided by the CPU itself, making it difficult to support multi-link redundancy structures or multi-port expansion. Therefore, its applicability is limited in industrial scenarios requiring high communication reliability.

[0004] Another approach involves introducing a Field-Programmable Gate Array (FPGA) between the CPU and the PHY. The FPGA enables Ethernet interface expansion and related data processing functions, thus constructing a multi-link communication structure. This solution offers advantages such as flexible interface expansion and strong customizability, making it widely used in industrial control systems. However, in complex industrial environments, such as those with strong ionizing radiation or strong electromagnetic interference, single-event upsets or other anomalies may occur in the FPGA's internal memory cells, leading to changes in internal logic states and consequently causing Ethernet link transmission failures. In existing technologies, FPGAs typically only provide a certain degree of self-testing or partial recovery capabilities for internal functional modules. When link-level faults or configuration anomalies occur, the CPU usually performs a complete FPGA reset or reloads the bitstream file to restore communication functionality. This often makes it difficult to pinpoint the specific faulty link in a timely manner and lacks effective recovery mechanisms for different fault types.

[0005] Furthermore, in multi-link communication systems, if an anomaly occurs in one link and the source of the fault cannot be quickly identified and appropriate recovery measures taken, it can easily lead to communication interruption or even a complete system shutdown, thereby affecting the stable operation of the industrial control system. Therefore, in industrial Ethernet communication systems, how to effectively monitor the status of multi-link communication and promptly locate and recover from faults when anomalies occur remains a problem that requires further improvement in existing technologies. Summary of the Invention

[0006] This invention aims to address the insufficient fault recovery capability in existing CPU+FPGA Ethernet solutions by providing a hierarchical recovery and precise diagnosis method and system for Ethernet multi-link fault diagnosis based on FPGA. Through virtual network port loopback self-test and three-layer reset mechanism, it achieves intelligent hierarchical recovery from the module level, link level to the chip level, greatly improving the self-healing capability and reliability of industrial Ethernet communication links in harsh environments.

[0007] This invention achieves hierarchical processing at different levels by constructing a three-tiered fault recovery mechanism at the module, link, and chip levels: the internal functional modules of the FPGA can perform self-tests and module-level resets autonomously during operation; when a link malfunctions but the module self-test does not find a problem, the CPU can perform a link-level reset on the faulty link; if the link-level reset still cannot restore communication, the CPU further reloads the FPGA bitstream file to achieve chip-level recovery, thereby avoiding the blind overall reload of link malfunctions in traditional solutions.

[0008] Meanwhile, this invention introduces periodic probe messages and a virtual loopback detection mechanism. The FPGA actively generates and sends probe messages with specific identifiers according to a preset period, and performs loopback detection at the detection points of the sending and receiving links through the internal virtual network port loopback module, thereby realizing real-time and proactive monitoring of the link status.

[0009] Furthermore, this invention can accurately distinguish between the fault types of the transmitting and receiving links and perform targeted link reset operations based on the fault type, thereby avoiding unnecessary reloading of the FPGA bit stream and improving the reliability and recovery efficiency of multi-link communication systems. In industrial Ethernet multi-link communication systems, this method can quickly diagnose link anomalies and implement effective recovery, significantly improving the continuity and stability of the system under complex operating conditions.

[0010] In a first aspect, the present invention provides an Ethernet multi-link fault diagnosis and recovery method based on FPGA, characterized in that the method includes: The CPU loads the FPGA bitstream file and starts the periodic transmission of FPGA internal functional modules and probe messages. The internal functional modules of the FPGA perform self-tests during operation. When an error is detected, the corresponding internal functional module and its preceding modules are reset. The probe message is looped back through the virtual network port loopback channel inside the FPGA. When no loopback probe message is received within a consecutive preset probe period, the FPGA records the link timeout status. The CPU determines the faulty link based on the link timeout status. The CPU controls the FPGA to reset the faulty link; When the faulty link times out again within a consecutive preset probe period after the link is reset, the CPU reloads the FPGA bitstream file.

[0011] Secondly, the present invention also provides an Ethernet multi-link fault diagnosis and recovery system based on FPGA, characterized in that the system includes a CPU and an FPGA, the CPU and the FPGA are communicatively connected, and the FPGA includes an internal functional module, a probe message generation and detection module, a virtual network port loopback module and a status register. The CPU is used to load the FPGA bitstream file and start the internal functional module and the probe message generation and detection module to periodically send probe messages. The internal functional module is used to perform self-checks during operation. When an error is detected, it performs a reset on the corresponding internal functional module and its predecessor module. The probe message generation and detection module is used to enable the probe message to be detected through the virtual network port loopback channel formed by the virtual network port loopback module. When no loopback probe message is received within a continuous preset probe period, the link timeout status is recorded in the status register. The CPU is also used to determine the faulty link based on the link timeout status; The CPU is also used to perform a reset of the faulty link by controlling the FPGA; When the faulty link times out again within a consecutive preset probe period after the link is reset, the CPU is also used to reload the FPGA bitstream file.

[0012] This invention provides an FPGA-based method and system for Ethernet multi-link fault diagnosis and recovery: First, this invention employs a three-tiered fault recovery mechanism—module, link, and chip—to achieve layered recovery from FPGA internal functional module self-testing and link-level reset to FPGA bitstream reload. Compared to existing technologies that only perform module self-testing or overall reload, this invention can take the most appropriate recovery measures for different fault types. This mechanism can handle most transient faults with minimal cost and maximum speed, only performing overall reload on the most severe persistent faults, thereby minimizing communication interruption time and significantly reducing the risk of communication interruption caused by link failures.

[0013] Secondly, a virtual self-test channel (i.e., a virtual network port loopback channel) independent of external physical links is constructed within the FPGA. Through periodic probe messages and a virtual loopback detection mechanism, the FPGA can proactively and periodically inspect the entire internal message processing path (including logic, memory, interface timing, etc.) before any abnormalities occur in service communication. The virtual network port loopback channel establishes a closed loop between the virtual network port sending module and the virtual network port receiving module at the FPGA logic level. This allows probe messages to completely traverse all logic units of the sending and receiving links without passing through external PHY chips and physical network cables, achieving comprehensive early diagnosis without blind spots. This completely eliminates the limitations of traditional Ethernet devices that rely on external physical links or passively wait for upper-layer protocol errors. Compared with traditional methods that rely on service messages or passive judgment of upper-layer communication anomalies, this invention can significantly improve the timeliness and accuracy of fault detection.

[0014] Third, this invention can distinguish between transmission link and reception link failures. The FPGA sets a first detection point and a second detection point on the transmission link and the reception link, respectively. When a probe message fails to return to the corresponding detection point within a consecutive preset period, the timeout flag for the corresponding link is set. The CPU periodically reads the FPGA status register and determines the fault location through the flag bits, thus performing a targeted reset operation only on the transmission link or the reception link. This not only avoids blindly reloading the entire FPGA bitstream but also improves link recovery efficiency while minimizing the impact on normal links and service communication.

[0015] Fourth, this invention directly integrates fault diagnosis and recovery logic into the FPGA, with the CPU only responsible for reading the status register and executing decision control, achieving rapid response without relying on upper-layer software polling or periodic checks. This is particularly suitable for industrial control scenarios with high real-time requirements. Under complex operating conditions such as strong ionizing radiation and electromagnetic interference, the method of this invention can quickly diagnose and recover link anomalies, improving the continuity and stability of industrial Ethernet multi-link communication systems and ensuring the reliable operation of DCS systems in critical industrial scenarios.

[0016] Fifth, the probe sending cycle and the number of consecutive preset probe cycles can both be set by the CPU through the FPGA configuration register, allowing for flexible adjustment of the detection strategy according to different industrial environments and performance requirements, thereby improving the applicability of the solution.

[0017] Sixth, this invention is compatible with multiple Ethernet physical layer interfaces (such as RGMII, RMII, etc.) and supports flexible expansion of the number of network ports. It can adapt to the redundant communication architecture of different industrial control systems, making it convenient to deploy or upgrade in existing DCS systems and improving the versatility and scalability of the solution. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of an Ethernet multi-link fault diagnosis and recovery method based on FPGA provided in an embodiment of the present invention; Figure 2 This is a block diagram of an Ethernet multi-link fault diagnosis and recovery system based on FPGA provided in an embodiment of the present invention; Figure 3 This is a complete flowchart of the FPGA-based Ethernet multi-link fault diagnosis and recovery method provided in this embodiment of the invention; Figure 4 This is a structural block diagram of the FPGA internal RGMII interface module provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. SUMMARY As mentioned above, this invention provides an Ethernet multi-link fault diagnosis and recovery method and system based on FPGA. Through a three-level progressive reset mechanism of modules, links and chips and periodic virtual loopback probes, it realizes active monitoring, accurate location and hierarchical recovery of multi-link faults, which significantly improves the reliability and real-time performance of industrial Ethernet communication.

[0022] Exemplary method Figure 1This is a flowchart of an Ethernet multi-link fault diagnosis and recovery method based on FPGA provided in an embodiment of the present invention. In this embodiment, the CPU is responsible for communicating with the host computer, receiving control commands and feeding back relevant operating data; loading the FPGA bitstream file and completing the initialization configuration of the FPGA; configuring the internal registers of the FPGA and monitoring the working status of the FPGA in real time; and sending and receiving Ethernet service packets, detecting the timeout status of probe packets, and performing corresponding fault recovery operations according to the fault situation.

[0023] The FPGA is responsible for providing configuration registers and status registers to realize interactive control between the CPU and the FPGA; distributing service messages issued by the CPU to the corresponding network ports, and summarizing the messages received by each network port and sending them to the CPU; verifying the structure and content of the messages, filtering abnormal or erroneous messages; and realizing the link self-test function through the virtual network port loopback channel, and triggering a hierarchical reset mechanism based on the test results.

[0024] This embodiment includes the following steps: S101: Power-on initialization, the CPU loads the FPGA bitstream file, configures the relevant registers, and starts the FPGA internal function modules and periodic transmission of probe messages.

[0025] Specifically, the probe message generation and detection module in the FPGA periodically generates the probe messages according to a preset probe sending cycle, which are then distributed by the message exchange and processing core and injected into the virtual network port sending module of the FPGA. For example... Figure 2 As shown, Gen (Generate) is integrated into the probe packet generation and detection module. It is used to periodically generate probe packets and inject them into the virtual network port loopback channel, providing a detection data source for Ethernet link fault diagnosis.

[0026] The probe message has the same structure as the service message and includes a specific identification field for identifying the probe message, which is generated by a timer inside the CPU or FPGA.

[0027] The probe transmission period is a configurable parameter, and the probe transmission period is set by the CPU by writing to the configuration register of the FPGA.

[0028] S102: The internal functional modules of the FPGA perform self-tests during operation. When a correctable local error is detected, the corresponding internal functional module and its predecessor module are automatically triggered to perform a reset, i.e., the first-level recovery: module-level reset recovery.

[0029] S103: The probe message is looped back through the virtual network port loopback channel inside the FPGA. When no loopback probe message is received within a consecutive preset probe period, the FPGA records the link timeout status.

[0030] The link timeout status includes a first timeout flag and / or a second timeout flag; Specifically, a first detection point and a second detection point are set in the transmitting link and the receiving link, respectively; The probe message sequentially passes through the sending link controlled by the message exchange and processing core, the virtual network port sending module of the FPGA, the virtual network port loopback channel, the virtual network port receiving module of the FPGA, and the receiving link, before returning to the first detection point and the second detection point.

[0031] like Figure 2 As shown, the probe message inspection path is illustrated by dashed arrows. The probe message is sent to the FPGA's message switching and processing core (including the RGMII interface module, sending-related functional modules, message distribution module, receiving-related functional modules, and message merging module), undergoes the entire processing of the sending link like a service message, enters the FPGA's virtual network port sending module, and is immediately looped back to the FPGA's virtual network port receiving module. It then undergoes the entire processing of the receiving link and finally returns to the detection point. The virtual network port sending module and the virtual network port receiving module form a closed loop through a direct internal connection. The probe message is immediately looped back to the virtual network port receiving module after being sent from the virtual network port sending module. The first detection point Chk1 and the second detection point Chk2 are shown. The first detection point Chk1 is located near the output of the virtual network port sending module and is used to monitor the sending link and loopback path; the second detection point Chk2 is located after the receiving-related functional modules and is used to monitor the receiving link.

[0032] In summary, the virtual Ethernet loopback channel is a virtual self-test channel within the FPGA that does not rely on external physical links. It periodically generates and sends probe messages with specific identifiers, which are transmitted within the FPGA along a data processing path consistent with the actual service messages. This path sequentially passes through key processing stages such as the sending link logic, data buffer and storage unit, interface control module, and receiving link logic. In this way, the probe messages can completely traverse the entire logical path of the Ethernet data path within the FPGA and ultimately return to the detection point for verification via the virtual loopback path. If no corresponding loopback probe message is detected within a preset period, an anomaly can be determined for the corresponding path.

[0033] Through the aforementioned virtual loopback detection mechanism, this invention enables continuous and periodic proactive inspection of the FPGA's internal message processing path without relying on external PHY devices or physical network links. This allows for comprehensive monitoring of key aspects such as the status of internal logic units, memory units, and interface timing. Compared to traditional methods that rely on passive judgment based on service message transmission status or upper-layer communication anomalies, this mechanism can detect potential faults or abnormal states in real time during system operation, achieving comprehensive fault detection and early warning, thereby significantly improving system reliability and self-diagnostic capabilities.

[0034] If no probe message is received at the first detection point within the preset probe cycle, the first timeout flag is set and recorded in the FPGA status register; If no probe message is received at the second detection point within the preset probe cycle, the second timeout flag is set and recorded in the FPGA status register.

[0035] That is, if a module-level reset fails to recover from the fault, or if the fault occurs at a lower level, the virtual network interface loopback will be interrupted. When the probe packet generation and detection module does not receive a loopback probe packet within the preset probe period, it triggers a link-level timeout flag and writes it to the status register.

[0036] In summary, based on the precise location results described above, the CPU can perform targeted, tiered recovery operations: for transmit link failures, only the transmit link enable bit is reset; for receive link failures, only the receive link enable bit is reset, without requiring a full reset of the entire FPGA logic or all network ports. This precise recovery strategy significantly shortens fault recovery time and avoids unnecessary service interruptions; furthermore, it reduces the impact of reset operations on the system and mitigates secondary risks caused by full resets.

[0037] S104: The CPU determines the faulty link based on the link timeout status.

[0038] Specifically, the CPU periodically reads the status register of the FPGA; When only the first timeout flag is set, the faulty link is determined to be a transmission link; When only the second timeout flag is set, the faulty link is determined to be a receiving link; When both the first timeout flag and the second timeout flag are set, the faulty links are determined to be the transmitting link and the receiving link.

[0039] This invention precisely pinpoints the fault range to the transmitting or receiving link, avoiding the drawbacks of traditional solutions that cannot distinguish the fault location and can only blindly perform a whole reset. It provides a reliable basis for the CPU to perform a targeted link-level reset, which not only improves the fault recovery efficiency but also minimizes the impact of the reset operation on normal services.

[0040] S105: The CPU controls the FPGA to perform a reset on the faulty link, thereby achieving the second-layer recovery: transmit / receive link reset recovery. The FPGA records this link reset event.

[0041] The CPU writes control bits to the configuration register of the FPGA, first clearing the transmit link enable tx_en or receive link enable rx_en of the corresponding faulty link to zero, and then setting it to valid. After detecting the falling edge of the transmit link enable tx_en or the receive link enable rx_en, the FPGA automatically sets the transmit link enable falling edge detection bit tx_en_f or the receive link enable falling edge detection bit rx_en_f. If probe messages are correctly received in a continuous probe cycle (10 consecutive probe cycles), the FPGA automatically sets the falling edge detection bit tx_en_f of the transmit link enable or the falling edge detection bit rx_en_f of the receive link enable to zero.

[0042] Configure parameters related to link enabling, probe message sending, and fault detection by configuring registers.

[0043] The functions of each bit in the configuration register are as follows: Bit 0 is the transmit link enable bit (tx_en), with read / write (RW) mode. A value of 1 indicates that the transmit link is enabled, and 0 indicates that the transmit link is disabled. Bit 1 is the receive link enable bit (rx_en), with read / write (RW) mode. A value of 1 indicates that the receive link is enabled, and 0 indicates that the receive link is disabled. Bit 2 is the transmit link enable falling edge detection bit (tx_en_f), with read-only (R) mode. A value of 1 indicates that the transmit link has been reset by the CPU, and 0 indicates that it has not. If probe messages are correctly received for 10 consecutive probe cycles, this bit will automatically reset to zero. Bit 3 is the receive link enable falling edge detection bit (rx_en_f), with read-only (R) mode. A value of 1 indicates that the receive link has been reset by the CPU, and 0 indicates that it has not. If probe messages are correctly received for 10 consecutive probe cycles, this bit will automatically reset to zero. If the probe message is received correctly, this bit will automatically reset to zero; Bit 4 is the first detection point timeout flag (timeout_1), which is read-only (R). It indicates that no probe message was received at Chk1 for two consecutive probe cycles. When this bit is 1, it indicates a timeout, and when it is 0, it indicates no timeout; Bit 5 is the second detection point timeout flag (timeout_2), which is read-only (R). It indicates that no probe message was received at Chk2 for two consecutive probe cycles. When this bit is 1, it indicates a timeout, and when it is 0, it indicates no timeout; Bit 6 is the probe message cycle transmission enable bit (frm_en), which is read-write (RW). When this bit is 1, it indicates that probe message cycle transmission is enabled, and when it is 0, it indicates that it is disabled; Bits 8 to 31 are probe message transmission cycle configuration bits (frm_cycle), which are read-write (RW) and are used to configure the probe message transmission cycle.

[0044] S106: When the faulty link times out again within a consecutive preset probe period after the link is reset, the CPU determines that the link-level reset is invalid and the fault may be caused by the disorder of the FPGA configuration memory. At this time, the CPU triggers the third-level recovery: the CPU reloads the FPGA bitstream file.

[0045] Specifically, the CPU reads the configuration register of the FPGA to obtain the status of the falling edge detection bit of the transmit link enable or the falling edge detection bit of the receive link enable, as well as the link timeout status. When the falling edge detection bit of the transmit link enable or the falling edge detection bit of the receive link enable is still active, and the faulty link timeout is detected again within a consecutive preset probe period, the CPU reloads the FPGA bitstream file.

[0046] More specifically, the CPU reads the configuration register of the FPGA to obtain the status of the transmit link enable falling edge detection bit tx_en_f or the receive link enable falling edge detection bit rx_en_f, as well as the corresponding link timeout status (timeout_1 or timeout_2). When tx_en_f is still valid (1) and a transmit link timeout is detected again within a consecutive preset probe period (timeout_1 is 1), or when rx_en_f is still valid (1) and a receive link timeout is detected again within a consecutive preset probe period (timeout_2 is 1), the CPU determines that the link-level reset is invalid and reloads the FPGA bitstream file.

[0047] This invention introduces a joint judgment of the tx_en_f / rx_en_f flag bit and the link timeout status to quickly identify deep configuration anomaly-type faults. When tx_en_f / rx_en_f and the corresponding timeout status are set at the same time, it indicates that the root cause of the fault has exceeded the scope of the local link logic and is likely due to FPGA configuration memory disorder or underlying timing abnormality. At this time, the system can directly skip repeated link-level resets and upgrade to chip-level bit stream reloading, fundamentally reconstructing the FPGA logic configuration and effectively preventing small faults from accumulating and evolving into system-level crashes.

[0048] The number of consecutive preset probe cycles is a configurable parameter; In this invention, the number of consecutive preset probe cycles can be set by writing the CPU into the configuration register of the FPGA.

[0049] The method may further include: when a link timeout is still detected after reloading the bitstream file, the CPU outputs a hardware fault alarm, reports an unrecoverable fault to the host computer or operation and maintenance system, and prompts the operation and maintenance personnel to check or replace the FPGA chip, related hardware circuits and interfaces to avoid the system from continuing to run in a faulty state, which could lead to service interruption or further expansion of the fault scope.

[0050] As an optional embodiment, such as Figure 3 As shown, the CPU first writes the configuration parameters into the FPGA's configuration register, completes system initialization, and starts the periodic transmission of various functional modules and probe messages within the FPGA. At this time, the FPGA enters normal working state, the internal functional modules continuously perform self-tests, and the probe message generation and detection module begins periodic inspection of the virtual network port loopback channel.

[0051] When a functional module within the FPGA fails, that module will automatically trigger a reset of itself and its upstream associated modules. If the module-level reset is successful, the system returns to normal operation; if the module-level reset fails to recover from the fault, it will inevitably cause probe message detection at Chk1 and / or Chk2 to time out.

[0052] Fault location is determined based on the timeout status of Chk1 and Chk2: when Chk1 times out (or when Chk1 and Chk2 time out simultaneously), it is determined to be a transmission link failure; when Chk1 is normal but Chk2 times out, it is determined to be a reception link failure.

[0053] For a transmit link failure, the FPGA first checks if the transmit link enable falling edge detection bit (tx_en_f) is set. If tx_en_f is 1, it means the transmit link was recently reset but failed again within 10 probe cycles. In this case, the CPU detects that tx_en_f and timeout_1 are both valid and directly triggers the reloading of the FPGA bitstream file. If tx_en_f is 0, the CPU performs a reset operation on the transmit link, that is, first clears the transmit link enable to zero and then sets it to valid. After the FPGA detects the falling edge of the enable, it automatically sets tx_en_f to 1. Subsequently, if probe messages are correctly received for 10 consecutive probe cycles, it automatically returns tx_en_f to zero.

[0054] For receiver link failures, the handling logic is similar: The FPGA first checks whether the receiver link enable falling edge detection bit (rx_en_f) has been set. If rx_en_f is 1, the CPU detects that rx_en_f and timeout_2 are both valid and directly reloads the FPGA bitstream file; if rx_en_f is 0, the CPU performs a reset operation on the receiver link (first clearing the receiver link enable to zero, then setting it to valid). The FPGA automatically sets rx_en_f after detecting the falling edge, and if probe messages are correctly received for 10 consecutive probe cycles, rx_en_f is automatically returned to zero.

[0055] After the CPU reloads the bitstream file of the FPGA, if the reload conditions are met again during subsequent operation (i.e., the reset flag of the corresponding link is still valid and the link timeout occurs again), the CPU determines that the FPGA cannot be recovered by software means, internally sets the load flag and outputs a hardware fault alarm, prompting the system to replace the FPGA device.

[0056] In summary, this invention employs a three-layer recovery mechanism that escalates according to the severity of the fault, enabling graded handling from minor anomalies to deep faults, thus improving system reliability while ensuring recovery efficiency. The first layer is functional module reset recovery. Various functional modules within the FPGA, such as the message verification module and message distribution module, possess autonomous detection capabilities. When they detect an error in their own operation, they can automatically perform a reset operation on the currently faulty module and its upstream related modules without CPU intervention, achieving the fastest local fault recovery. The second layer is transmit / receive link reset recovery. When the autonomous recovery of a functional module fails, causing link transmission anomalies and probe message timeouts, the FPGA feeds back the fault location to the CPU in real time through the timeout_1 and timeout_2 register bits. The CPU performs a precise reset on the transmit or receive link based on the judgment result, i.e., first setting the tx_en or rx_en signal to 0 and then to 1. Simultaneously, the FPGA automatically sets the tx_en_f or rx_en_f flag to record the reset status. If messages can be received normally for the next 10 consecutive probe cycles, the link recovery is deemed effective, and the corresponding flag bit is automatically cleared. The third layer is the FPGA bitstream file reload recovery. If a timeout fault occurs again within 10 probe cycles after the link reset is completed, and tx_en_f / rx_en_f and the corresponding timeout bit remain at 1, it indicates that the fault has escalated to FPGA bitstream configuration disorder or deep hardware abnormality. At this time, the CPU directly triggers FPGA bitstream file reload to reinitialize the FPGA as a whole. If the fault still exists after bitstream reload, the CPU will output an FPGA failure alarm to prompt the maintenance personnel to check and replace the FPGA device.

[0057] Through the above processing flow, this embodiment constructs a progressive fault recovery mechanism within the FPGA, from the module level, link level to the chip level, enabling the system to adopt different recovery strategies based on the severity of the fault. For most faults caused by transient interference or local logic anomalies, rapid recovery can be achieved through module-level self-reset or link-level reset, thereby avoiding direct reloading of the entire bitstream of the FPGA, significantly reducing system communication interruption time, and improving the continuity and stability of industrial Ethernet communication links.

[0058] Meanwhile, by setting independent detection points on the sending and receiving links and combining them with the timeout detection mechanism of probe messages, this embodiment can achieve precise location of faulty links, enabling the CPU to perform corresponding reset operations for specific faulty links without blindly resetting all links or the entire FPGA system, thereby further improving fault recovery efficiency and reducing the impact on normal communication links.

[0059] Furthermore, by setting falling edge detection bits (tx_en_f, rx_en_f) for the transmitting and receiving links and a probe period counting mechanism, this embodiment can record whether the link has recently been reset and determine whether the fault will reappear shortly after the reset. When the link repeatedly experiences anomalies within a short period, the system can automatically upgrade the recovery strategy and directly trigger FPGA bitstream reloading, thereby avoiding performance jitter caused by repeated link resets and improving the stability of system operation.

[0060] Furthermore, when the same fault recurs after the FPGA bitstream is reloaded, the CPU can automatically determine that the FPGA device may have an unrecoverable hardware-level fault based on the loading flag, and output hardware alarm information to provide clear fault indications for system maintenance personnel, thereby improving the maintainability and fault handling efficiency of the system.

[0061] Exemplary system Accordingly, this invention also provides an FPGA-based Ethernet multi-link fault diagnosis and recovery system. Figure 2 This is a block diagram of an FPGA-based Ethernet multi-link fault diagnosis and recovery system provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the system 100 provided in this embodiment includes: The system includes a CPU 101, an FPGA 102, and multiple PHY chips. The CPU 101 is communicatively connected to the FPGA 102, and the PHY chips are connected to the physical network transceiver module of the FPGA 102.

[0062] The FPGA 102 includes internal functional modules, a probe message generation and detection module, a virtual network port loopback module, and a hierarchical fault diagnosis and status register module.

[0063] The internal functional modules include a message switching and processing core and multiple physical network port transceiver modules.

[0064] The hierarchical fault diagnosis and status register module includes multiple status registers and configuration registers.

[0065] The CPU 101 is used to load the bitstream file of the FPGA 102 and start the internal functional module and the probe message generation and detection module to periodically send probe messages.

[0066] The internal functional module is used to perform self-checks during operation. When an error is detected, it resets the corresponding internal functional module and its preceding module.

[0067] The probe message generation and detection module is used to enable the probe message to be detected through the virtual network port loopback channel formed by the virtual network port loopback module. When no loopback probe message is received within a consecutive preset probe period, the link timeout status is recorded in the status register.

[0068] The virtual network port loopback module includes a virtual network port sending module, a virtual network port loopback channel, and a virtual network port receiving module. The virtual network port sending module and the virtual network port receiving module are directly connected inside the FPGA 102 to form a virtual diagnostic channel (i.e., a virtual network port loopback channel) that is not physically connected to the outside, providing a path for probe message loopback detection.

[0069] The message switching and processing core is responsible for routing, distributing, merging, and verifying Ethernet messages among CPU 101, each physical network port transceiver module, and the virtual network port loopback module. It also includes the following sub-functional modules: 1) RGMII interface module, which completes the timing conversion between RGMII dual-edge 4-bit data and FPGA single-edge 8-bit byte stream; The RGMII interface (Reduced Gigabit Media Independent Interface) is an interface standard between the PHY and the data link layer (MAC / FPGA) specifically designed for Gigabit Ethernet (1000Mbps) communication. Among them, such as Figure 4 As shown, the RGMII interface module is the communication interface unit between the FPGA and the external Ethernet PHY chip, and is internally divided into the RGMII_TX module and the RGMII_RX module: The RGMII_TX module is responsible for verifying the message structure and content of the byte stream converted by the RGMII interface module, and storing the correct messages in RAM for subsequent modules to read; the RGMII_RX module is responsible for verifying the data stream of the preceding module and sending the correct messages to the RGMII interface module.

[0070] The configuration register is connected to the CPU through the register configuration interface. On the one hand, it receives control parameters such as link enable and probe cycle from the CPU. On the other hand, it records the operating status of the RGMII_TX and RGMII_RX modules (such as link reset flags and timeout status) for the CPU to read and monitor in real time. This enables the CPU to configure and control the RGMII modules and perceive their status, providing hardware support for Ethernet multi-link fault diagnosis and recovery.

[0071] 2) Functional modules related to the transmission stage: Read the message from the front-end RAM and verify the correctness of the message structure and content. Write the message that passes the verification into the back-end FIFO to realize the conversion from RAM to FIFO.

[0072] 3) Message distribution module: Based on the network port number attached to the message, the message is read from the FIFO and distributed to the corresponding network port sending module.

[0073] 4) Receiving stage related functional modules: Implementing functions such as RAM to FIFO conversion, whitelist filtering, storm suppression, and flow control; among which: Whitelist filtering: Ethernet packets carry destination MAC address information. The whitelist processing module extracts the destination MAC information from the packet and compares it with its own configured MAC address. If the comparison results match, the packet is accepted; otherwise, the packet is discarded. Storm suppression: Used to avoid receiving duplicate packets. There are two detection methods: a. If the same packet appears within a set time (e.g., 10ms), it is considered a network storm; b. If the same packet appears within 32 consecutive received packets, it is considered a network storm. If either of the above situations occurs, the latest received packet is discarded; otherwise, it is received normally. Flow control: Flow control is applied to broadcast, multicast, and unicast messages respectively. There are two flow control checking methods: a. If the number of bits of a received message exceeds the maximum limit within a set statistical period, messages after that frame will no longer be received and will wait for the next period to start receiving again; b. If the number of received message frames exceeds the maximum limit within a set statistical period, messages after that frame will no longer be received and will wait for the next period to start receiving again. If either of the above situations occurs, the flow control conditions are considered to have been met.

[0074] 5) Message merging module: It summarizes the messages received from each network port and encapsulates the network port number in the message format for CPU 101 to distinguish.

[0075] The physical network port transceiver module is connected to an external PHY chip and is responsible for sending and receiving Ethernet packets; wherein: Each network port transmitting module performs message verification and converts the byte timing inside the FPGA 102 into the receiving timing of the external PHY chip. Common PHY chip interfaces include RGMII and RMII. Each network port receiving module restores the transmission timing from the external PHY chip to the byte stream processing timing inside the FPGA 102 and stores the correct message in the subsequent RAM.

[0076] The status register is used to record local errors reported by each internal functional module, as well as link timeout status reported by the probe message generation and detection module.

[0077] In addition, configuration registers are used to configure parameters related to link enabling, probe message transmission, and fault detection.

[0078] The PHY chip is used to realize the physical layer conversion between the digital signals output by FPGA 102 and the analog signals transmitted via Ethernet, and supports standard interfaces such as RGMII and RMII.

[0079] The CPU 101 is also used to determine the faulty link based on the link timeout status.

[0080] The CPU 101 is also used to perform a reset on the faulty link by controlling the FPGA 102.

[0081] When the faulty link times out again within a consecutive preset probe period after the link is reset, the CPU 101 is also used to reload the bitstream file of the FPGA 102.

[0082] It should be noted that although the operation of the FPGA-based Ethernet multi-link fault diagnosis and recovery method of the present invention is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0083] Furthermore, although several devices, units, or modules of the FPGA-based Ethernet multi-link fault diagnosis and recovery system have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.

[0084] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for fault diagnosis and recovery of Ethernet multi-links based on FPGA, characterized in that, The method includes: The CPU loads the FPGA bitstream file and starts the periodic transmission of FPGA internal functional modules and probe messages. The internal functional modules of the FPGA perform self-tests during operation. When an error is detected, the corresponding internal functional module and its preceding modules are reset. The probe message is looped back through the virtual network port loopback channel inside the FPGA. When no loopback probe message is received within a consecutive preset probe period, the FPGA records the link timeout status. The CPU determines the faulty link based on the link timeout status. The CPU controls the FPGA to reset the faulty link; When the faulty link times out again within a consecutive preset probe period after the link is reset, the CPU reloads the FPGA bitstream file.

2. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to claim 1, characterized in that, The link timeout status includes a first timeout flag and / or a second timeout flag; The probe message is loopback detected via the FPGA's internal virtual network port loopback channel. When no loopback probe message is received within a consecutive preset probe period, the FPGA records the link timeout status in the following steps: A first detection point and a second detection point are set on the transmitting link and the receiving link, respectively; If no probe message is received at the first detection point within the preset probe cycle, the first timeout flag is set and recorded in the FPGA status register; If no probe message is received at the second detection point within the preset probe cycle, the second timeout flag is set and recorded in the FPGA status register.

3. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to claim 2, characterized in that, The step of the CPU determining the faulty link based on the link timeout status includes: The CPU periodically reads the status register of the FPGA; When only the first timeout flag is set, the faulty link is determined to be a transmission link; When only the second timeout flag is set, the faulty link is determined to be a receiving link; When both the first timeout flag and the second timeout flag are set, the faulty links are determined to be the transmitting link and the receiving link.

4. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to claim 3, characterized in that, The specific steps for periodically sending the probe messages are as follows: The FPGA periodically generates the probe message according to the preset probe transmission period and injects it into the virtual network port transmission module of the FPGA. The step of performing loopback detection on the probe message via the FPGA's internal virtual network port loopback channel also includes: The probe message sequentially passes through the sending link, the virtual network port sending module of the FPGA, the virtual network port loopback channel, the virtual network port receiving module of the FPGA, and the receiving link, before returning to the first detection point and the second detection point.

5. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to any one of claims 1-4, characterized in that, The step of the CPU controlling the FPGA to reset the faulty link includes: The CPU writes control bits to the configuration register of the FPGA, first clearing the transmit link enable or receive link enable of the corresponding faulty link to zero, and then setting it to valid. After detecting the falling edge of the transmit link enable or the receive link enable, the FPGA automatically sets the transmit link enable falling edge detection bit or the receive link enable falling edge detection bit. If a probe message is received during a continuous probe cycle, the FPGA automatically resets the falling edge detection bit of the transmit link enable or the falling edge detection bit of the receive link enable to zero.

6. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to claim 5, characterized in that, When the faulty link times out again within a consecutive preset probe period after the link is reset, the step of the CPU reloading the FPGA bitstream file further includes: The CPU reads the configuration register of the FPGA to obtain the status of the falling edge detection bit of the transmit link enable or the falling edge detection bit of the receive link enable, as well as the link timeout status. When the falling edge detection bit of the transmit link enable or the falling edge detection bit of the receive link enable is still active, and the faulty link timeout is detected again within a consecutive preset probe period, the CPU reloads the FPGA bitstream file.

7. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to claim 5, characterized in that, The probe transmission period and / or the number of consecutive preset probe cycles are configurable parameters. The probe sending cycle and / or the number of consecutive preset probe cycles are set by the CPU by writing to the configuration register of the FPGA.

8. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to any one of claims 1-4, characterized in that, The probe message has the same structure as the service message and includes a specific identification field for identifying the probe message.

9. The FPGA-based Ethernet multi-link fault diagnosis and recovery method according to any one of claims 1-4, characterized in that, The method further includes: If a link timeout is still detected after reloading the bitstream file, the CPU outputs a hardware fault alarm.

10. An Ethernet multi-link fault diagnosis and recovery system based on FPGA, characterized in that, The system includes a CPU and an FPGA. The CPU is communicatively connected to the FPGA. The FPGA includes internal functional modules, a probe message generation and detection module, a virtual network port loopback module, and a status register. The CPU is used to load the FPGA bitstream file and start the internal functional module and the probe message generation and detection module to periodically send probe messages. The internal functional module is used to perform self-checks during operation. When an error is detected, it performs a reset on the corresponding internal functional module and its predecessor module. The probe message generation and detection module is used to enable the probe message to be looped back through the virtual network port loopback channel formed by the virtual network port loopback module. When no loopback probe message is received within a consecutive preset probe period, the link timeout status is recorded in the status register. The CPU is also used to determine the faulty link based on the link timeout status; The CPU is also used to perform a reset of the faulty link by controlling the FPGA; When the faulty link times out again within a consecutive preset probe period after the link is reset, the CPU is also used to reload the FPGA bitstream file.

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