Packet forwarding chip processing system and method

Abstract

Embodiments of the present application provide a packet forwarding chip processing system and method, and relate to the field of communication technology, the system comprises: a plurality of matching units MU and a plurality of action units AU, each matching unit MU and action unit AU are arranged in a set order on a chip pipeline and are connected by a main BUS communication, the input information entering the packet forwarding chip processing system enters the matching unit MU or the action unit AU in turn according to the set order for searching, processing and writing back. Thus, the MU+AU architecture with separated MU and AU is realized to replace the traditional MAU, and the overall processing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to a packet forwarding chip processing system and method. Background Technology

[0002] In communication chip message processing architectures that support programmable Match Action Units (MAUs), multi-level Arithmetic Logic Units (ALUs) are typically included. The configuration index relationship of the ALUs is determined by the preceding configuration entries in the MAU. However, in related technologies, the overall performance of ALU processing within the MAU needs optimization. Summary of the Invention

[0003] One of the objectives of this invention includes, for example, providing a packet forwarding chip processing system and method to at least partially improve the overall performance of ALU processing in a MAU.

[0004] The embodiments of the present invention can be implemented as follows: In a first aspect, the present invention provides a packet forwarding chip processing system, comprising: a plurality of matching units MU and a plurality of action units AU, wherein each of the matching units MU and action units AU is arranged in a predetermined order on a chip pipeline and is connected via a main BUS communication, and input information entering the packet forwarding chip processing system enters the matching unit MU or action unit AU sequentially in the predetermined order for processing; The matching unit MU and the action unit AU both include a pre-lookup unit, a processing component, and a field write-back unit; The matching unit MU is used to search, process and write back the input information according to the first strategy based on the pre-search unit, processing component and field write-back unit in the MU; The action unit AU is used to search, process, and write back the input information according to a second strategy based on the pre-lookup unit, processing component, and field write-back unit in the AU. The processing of the input information according to the second strategy includes ALU processing.

[0005] In an optional implementation, the pre-lookup unit in the matching unit MU is used to extract a specified set of fields from the input information for pre-lookup, and to determine whether the subsequent processing of the matching unit MU is effective and to configure the face index. The processing components in the matching unit MU include a lookup key generation unit, a main lookup unit, a BUS selection unit, a main BUS write-back instruction generation unit, and a write-back instruction merging unit. The lookup key generation unit is used to generate a key for lookup by combining the decision of the pre-lookup unit; The main search unit is used to perform a search based on the KEY obtained by the search KEY generation unit to obtain the search result; The BUS selection unit is used to determine the fields required for BUS write-back from the main BUS or configuration plane constants; The main BUS write-back instruction generation unit is used to generate a main BUS write-back instruction based on the search results and the fields required for BUS write-back. The write-back instruction merging unit is used to merge the main BUS write-back instructions according to a preset strategy when there are multiple main BUS write-back instructions in the same Stage. The field write-back unit is used to write back the fields of the main BUS according to the main BUS write-back instruction.

[0006] In an optional implementation, the lookup key generation unit generates a key for lookup by combining the decision of the pre-lookup unit through the following steps: The lookup key generation unit, in conjunction with the decision of the pre-lookup unit, calls several key generation containers to select fields from the main BUS according to the sel value, shifts according to the shift configuration, extracts the corresponding number of bits according to the len configuration, and writes them to the corresponding position of the lookup key according to the destPosA configuration, thereby obtaining the key used for lookup.

[0007] In an optional implementation, the main BUS write-back instruction generation unit generates the main BUS write-back instruction based on the search results and the fields required for BUS write-back through the following steps: A container is generated by calling several instructions. Based on the container generated by the instructions, fields are selected from the search results, fields required for BUS write-back, and configuration constants to generate write-back instructions. The write-back instruction includes the write-back position of destPosB, the value of val, and the valid bitmap of val.

[0008] In an optional implementation, the pre-lookup unit in the action unit AU is used to extract a specified set of fields from the input information for pre-lookup, and to decide whether the subsequent processing of the action unit AU is effective and to configure the face index. The processing components in the action unit AU include a BUS selection unit, a field processing unit, a main BUS write-back instruction generation unit, and a write-back instruction merging unit. The BUS selection unit is used to determine the fields needed for field processing from the main BUS or configuration constants to form a local BUS; The field processing unit is used to perform one or more levels of ALU processing on the local BUS and write back the result of each level of ALU processing to the local BUS. The main BUS write-back instruction generation unit is used to generate main BUS write-back instructions based on the results of the ALU processing. The write-back instruction merging unit is used to merge the main BUS write-back instructions according to a preset strategy when there are multiple main BUS write-back instructions in the same Stage. The field write-back unit is used to write back the fields of the main BUS according to the main BUS write-back instruction.

[0009] In an optional implementation, the write-back instruction merging unit merges the write-back instructions of each main BUS according to a preset strategy through the following steps: In the case of multiple main BUS write-back instructions in the same stage, the main BUS write-back instructions with the same destPosB position are merged.

[0010] In an optional implementation, the field write-back unit performs the field write-back of the main BUS according to the main BUS write-back instruction through the following steps: The merged instruction set of the write-back instruction merging unit is mapped according to the global configuration so that the mapped position is consistent with the order of the main BUS editable area. The number of containers consistent with the main BUS editable area is set, and the val value of the corresponding position is updated according to the bitmap value and val.

[0011] In an optional implementation, the field write-back unit performs the field write-back of the main BUS according to the main BUS write-back instruction through the following steps: Based on global configuration, the editable area of ​​the main BUS is mapped at the container granularity to ensure that the set area in the editable area of ​​the main BUS is consistent with the order of the local editable field set of the Stage. The number of containers consistent with the local editable field set of the Stage is set, and the val value of the corresponding position is updated according to the bitmap value and val.

[0012] In an optional implementation, the input information is obtained by the main BUS parsing and processing the input request, and the input request includes an initial request and a request processed by the matching unit MU or the action unit AU. The matching unit MU searches, processes, and writes back the input information according to the first strategy, including: direct write-back, conditional write-back, and if-else write-back logic; The action unit AU searches, processes, and writes back the input information according to the second strategy, including calculating relevant items that meet the complexity threshold.

[0013] In a second aspect, embodiments of the present invention provide a packet forwarding chip processing method, applied to the packet forwarding chip processing system described in any one of the first aspects; the method includes: According to the arrangement order of each matching unit MU and action unit AU, the input information is sequentially input into each matching unit MU or action unit AU; Based on the pre-lookup unit, processing component, and field write-back unit in the matching unit MU, the input information is searched, processed, and written back according to the first strategy; or, Based on the pre-lookup unit, processing component, and field write-back unit in the action unit AU, the input information is looked up, processed, and written back according to the second strategy. The processing of the input information in the second strategy includes ALU processing.

[0014] The beneficial effects of the embodiments of the present invention include, for example, that, unlike the traditional MAU architecture, a MU+AU chip architecture with separate MU and AU is adopted, with MU and AU being divided into hardware units respectively, and each unit of MU and AU being independent of each other, so that the setting of AU and its setting specifications are no longer bound to MU, and MU and AU can be flexibly combined in different scenarios, and AU can independently implement ALU functions, thereby optimizing the overall processing performance of ALU. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This diagram illustrates a pipeline architecture for processing in a conventional communication system, as provided by an embodiment of the present invention.

[0017] Figure 2 The diagram shows an architecture schematic of a packet forwarding chip processing system provided by an embodiment of the present invention.

[0018] Figure 3 A schematic diagram of the architecture of a MU provided by an embodiment of the present invention is shown.

[0019] Figure 4 A schematic diagram of an AU architecture provided by an embodiment of the present invention is shown.

[0020] Figure 5 The diagram shows an architecture schematic of a BUS selection unit provided by an embodiment of the present invention.

[0021] Figure 6 This diagram illustrates the architecture of a write-back instruction generation unit provided in an embodiment of the present invention.

[0022] Figure 7 The diagram shows an architecture schematic of a write-back instruction merging unit provided in an embodiment of the present invention.

[0023] Figure 8 This is one of the schematic diagrams of a position mapping provided by an embodiment of the present invention.

[0024] Figure 9 This is a second schematic diagram of a position mapping provided by an embodiment of the present invention.

[0025] Figure 10 This diagram illustrates the architecture of an ALU processing unit provided in an embodiment of the present invention.

[0026] Figure 11 The diagram shows a flowchart of a packet forwarding chip processing method provided by an embodiment of the present invention. Detailed Implementation

[0027] Definitions of some terms:

[0028] Please see Figure 1 This paper provides a processing pipeline architecture diagram for a communication system, illustrating the flow path of data in the main pipeline.

[0029] The Main Pipeline is responsible for transmitting instructions to each execution unit through the bus (main BUS) within each clock cycle for reading, writing, calculation, and other tasks.

[0030] The communication system's operating parameters or performance monitoring strategies are configured through the Profile. The lookup unit searches for corresponding data or instructions in an internal table based on the input address or index, and then passes the search results to subsequent processing units, such as ALUs, MAUs, and BUSs. Multiple ALUs 0..n perform addition, subtraction, multiplication, division, bitwise operations, etc., and read and write data in memory.

[0031] Figure 1The architecture shown is commonly found in high-performance computing chips and embedded processors. The MAU typically contains multiple levels of ALUs, and the configuration index relationship of the ALUs is determined by the configuration entries in the preceding levels of the MAU. By having multiple levels of ALUs work in parallel, data processing speed and throughput can be effectively improved.

[0032] However, research has found that the overall performance of ALU processing in MAU within related technologies needs optimization. Reasons include: At the hardware design level, the number of ALU levels is difficult to plan. If multiple ALU levels are planned for each lookup unit, the overall processing pipeline level will expand rapidly. If multiple ALU levels are planned in parallel with the lookup, the multiple ALU levels cannot be applied to the lookup results, or the ALU results cannot affect subsequent processing in real time.

[0033] In practice, ALU processing and table lookup are highly coupled. In the processing of the result fields of each lookup table, multiple tables may involve different fields in the same processing. In actual business deployment, it is often found that multiple places are configured with the same processing logic or that multi-stage serial processing must be performed.

[0034] The overall utilization rate of ALU configuration is not high. In the processing of the result fields of each lookup table, the proportion of complex logic is not large, but the hardware is often configured according to the profile, and the number of ALU levels in each stage is designed according to the most complex case, resulting in a high actual idle rate of ALU configuration.

[0035] Based on the above research, this invention provides a packet forwarding chip processing solution that uses a MU+AU architecture with separate MU and ALU to replace the traditional MAU. This decouples table lookup from the complex processing of results, thereby improving the overall business flexibility and utilization of ALU processing, reducing overall overhead, and significantly improving ALU energy efficiency.

[0036] The shortcomings of the above solutions are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present invention in the following text should be considered as contributions made by the inventors during the invention process.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0039] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0040] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0041] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0042] Please refer to the following: Figure 2 This is a schematic diagram of the architecture of a packet forwarding chip processing system provided in an embodiment of the present invention. The packet forwarding chip processing system includes: a plurality of matching units MU and a plurality of action units AU. Each of the matching units MU and action units AU is arranged in a set order on the chip pipeline and is connected to the main BUS for communication. Input information entering the packet forwarding chip processing system enters the matching unit MU or action unit AU for processing in the set order.

[0043] The matching unit MU and the action unit AU both include a pre-lookup unit, a processing component, and a field write-back unit.

[0044] The matching unit MU is used to search, process, and write back the input information according to a first strategy, based on the pre-search unit, processing component, and field write-back unit in the MU.

[0045] The action unit AU is used to search, process, and write back the input information according to a second strategy based on the pre-lookup unit, processing component, and field write-back unit in the AU. The processing of the input information according to the second strategy includes ALU processing.

[0046] By designing AU and MU separately, with each unit of MU and AU operating independently, the number, levels, and order of AU and MU can be flexibly configured according to the actual needs of the application scenario. Hardware units are divided separately for MU and AU, and ALU functions are implemented through AU. This ensures that the setting and specifications of AU are no longer tied to MU, guaranteeing the implementation of ALU functions and improving overall processing efficiency.

[0047] The input information can be obtained by parsing and processing the input request by the main BUS. The main BUS contains message parsing information and message processing information. The message parsing information usually exists in the form of a parsed header vector (PHV). The message processing information usually corresponds to metadata, with a typical width of 2K / 4K / 6K / 8K bits, and may be partially editable.

[0048] The processing components in MU and AU can be implemented flexibly, as long as MU and AU can be used to search, process and write back the input information, and AU can be used for ALU processing.

[0049] Please refer to the following: Figure 3 This provides an optional implementation architecture for the MU. For example... Figure 3 As shown, the MU includes a pre-lookup unit, a lookup key generation unit, a main lookup unit, a BUS selection unit, a main BUS write-back instruction generation unit, a write-back instruction merging unit, and a field write-back unit.

[0050] The pre-lookup unit in the matching unit MU is used to extract a specified set of fields from the input information for pre-lookup, and to determine whether the subsequent processing of the matching unit MU is effective and to configure the face index.

[0051] The lookup key generation unit is used to generate a key for lookup by combining the decision of the pre-lookup unit.

[0052] The main search unit is used to perform a search based on the KEY obtained by the search KEY generation unit to obtain the search result.

[0053] The BUS selection unit is used to determine the fields needed for BUS write-back from the main BUS or configuration plane constants.

[0054] The main BUS write-back instruction generation unit is used to generate main BUS write-back instructions based on the search results and the fields required for BUS write-back.

[0055] The write-back instruction merging unit is used to merge the main BUS write-back instructions according to a preset strategy when there are multiple main BUS write-back instructions in the same stage.

[0056] The field write-back unit is used to write back the fields of the main BUS according to the main BUS write-back instruction.

[0057] To more clearly illustrate the implementation of each unit in MU, the following examples illustrate the design of each unit in MU.

[0058] Pre-lookup unit: Selects a set of fields from the main BUS for pre-lookup to determine whether subsequent MU processing is valid and the configuration plane index A1 for subsequent MU processing. The pre-lookup unit can determine whether subsequent MU processing is valid in any way; it can be that the configuration plane directly outputs valid control bits, or that a specific A1 value represents invalidity, such as 0 or the maximum value representing invalidity.

[0059] The pre-lookup unit can be searched in a lookup table, which can be a linear table, a hash table, a CAM table, a TCAM table, etc.

[0060] Key generation unit: Based on the decision of the pre-lookup unit, several key generation containers are called to select fields from the main BUS according to the sel value, shift according to the shift configuration, extract the corresponding number of bits according to the len configuration, and write the key to the corresponding position of the lookup key according to the destPosA configuration, thereby obtaining the key for lookup.

[0061] For example, the lookup KEY generation unit can select fields from the main BUS to generate a lookup KEY. When looking up in the HASH / CAM / TCAM table, the KEY is the field set K1. When looking up in the direct index table, the KEY is the table index K2. The selection is completed by N1 key generation containers. Each key generation container supports selecting fields from the main BUS by the sel value, configuring shift by shift, configuring the number of bits to be truncated by the field len, and configuring writing to the corresponding position of the lookup KEY by destPosA. In the case of a short index K2 for a single key generation container, destPosA can be omitted. When there are multiple key generation containers, the relationship between the key generation containers can be the OR logic of the left shift result by destPosA.

[0062] Main search unit: Performs a search based on the search table type and the key, and returns the search results. The search table type can be a linear list, hash table, CAM table, TCAM table, etc.

[0063] BUS Selection Unit: Selects the fields needed for BUS write-back from the main BUS or configuration constants. Configuration constants can be set globally or according to index A1.

[0064] The main BUS write-back instruction generation unit: calls several instruction generation containers, and generates write-back instructions based on the fields selected from the search results, fields required for BUS write-back, and configuration constants. The write-back instruction includes the destPosB position to be written back, the val value, and the val valid bitmap.

[0065] For example, the main BUS write-back instruction generation unit can combine the BUS selection field and the search result field to generate the main BUS write-back instruction for the field. It contains N2 instruction generation containers. Each instruction generation container supports selecting fields from the BUS selection field, the search result field, or the configuration constant to enter the container. The write-back instruction is generated according to the configuration of the instruction generation container. The write-back instruction content includes: the destPosB position to be written back, the val value, and the val valid bitmap.

[0066] Write-back instruction merging unit: When there are multiple main BUS write-back instructions in the same Stage, the main BUS write-back instructions with the same destPosB position are merged.

[0067] For example, write-back instructions generated by multiple lookup instances in the same Stage can be merged according to their respective destPosB positions. When there is only one lookup instance, the write-back instruction merging unit does not need to be applied. The merging mode supports "priority mode", "OR mode", etc.

[0068] The typical width of the local total bit width for each Stage's editable field set can be 128 / 256 / 384 / 512 bits.

[0069] Field write-back unit: Performs field write-back of the main BUS according to the write-back instruction. Field write-back can be implemented in two ways.

[0070] Solution A: For the merged instruction set of the write-back instruction merging unit, perform position mapping according to the global configuration so that the mapped position is consistent with the order of the main BUS editable area, set the number of containers consistent with the main BUS editable area, and update the val value of the corresponding position according to the bitmap value and val.

[0071] For example, the merged instruction set is mapped to a position according to the global configuration so that it is consistent with the order of the main BUS editable area, the number of containers is set to be consistent with the main BUS editable area, and the old values ​​are updated according to the bitmap value and val.

[0072] Option B: Based on global configuration, the editable area of ​​the main BUS is mapped at the container granularity to ensure that the set area in the editable area of ​​the main BUS is consistent with the order of the local editable field set of the Stage. The number of containers consistent with the local editable field set of the Stage is set, and the val value of the corresponding position is updated according to the bitmap value and val.

[0073] For example, the editable area of ​​the main BUS can be pre-mapped at the container granularity according to the global configuration, so that the order of its specific area is consistent with the local editable field set of the Stage. The number of containers that are consistent with the local editable field set of the Stage can be set, and the old value can be updated according to the bitmap value and val.

[0074] Scheme A involves mapping the position from a small bit-width region to a large bit-width region, implemented using methods such as sorting / shifting or muxing / inserting bubbles. Scheme B, on the other hand, can be based on the main BUS's editable range. The field position changes every time a stage of the main BUS's editable range is reached. This requires configuration management, and the mapping implementation methods include sorting / shifting or muxing.

[0075] Please refer to the following: Figure 4 This provides an optional implementation architecture for AU. For example... Figure 4 As shown, the AU includes a pre-search unit, a BUS selection unit, a field processing unit, a main BUS write-back instruction generation unit, a write-back instruction merging unit, and a field write-back unit.

[0076] The pre-lookup unit in the action unit AU is used to extract a specified set of fields from the input information for pre-lookup, and to decide whether the subsequent processing of the action unit AU is valid and to configure the face index.

[0077] The BUS selection unit is used to determine the fields needed for field processing from the main BUS or configuration constants to form a local BUS.

[0078] The field processing unit is used to perform one or more levels of ALU processing on the local BUS and write back the result of each level of ALU processing to the local BUS.

[0079] The main BUS write-back instruction generation unit is used to generate main BUS write-back instructions based on the results of the ALU processing.

[0080] The write-back instruction merging unit is used to merge the main BUS write-back instructions according to a preset strategy when there are multiple main BUS write-back instructions in the same stage.

[0081] The field write-back unit is used to write back the fields of the main BUS according to the main BUS write-back instruction.

[0082] To more clearly illustrate the implementation of each unit in AU, the following examples illustrate the design of each unit in AU.

[0083] Pre-lookup unit: Selects a set of fields from the main BUS for pre-lookup to determine whether subsequent AU processing is valid and the configuration plane index A2 for subsequent AU processing. The pre-lookup unit can determine whether subsequent AU processing is valid in any way; it can be that the configuration plane directly outputs valid control bits, or that a specific value A2 represents invalidity, etc.

[0084] BUS Selection Unit: Select fields from the main BUS or configuration constants to form a local BUS. The configuration constants can be set globally or according to index A2.

[0085] Field processing unit: Performs complex processing on local BUS fields, including one or more levels of ALU processing. After each level of processing is completed, the result can be written back to the local BUS.

[0086] Main BUS write-back instruction generation unit: Generates main BUS write-back instructions for the processing result fields of the field processing unit, containing N3 instruction generation containers.

[0087] Write-back instruction merging unit: When there are multiple main BUS write-back instructions in the same Stage, the main BUS write-back instructions with the same destPosB position are merged.

[0088] For example, the write-back instruction merging unit merges write-back instructions generated by multiple lookup instances in the same Stage according to the same destPosB position. The write-back instruction merging unit may not exist when there is only one lookup instance.

[0089] Field write-back unit: Performs field write-back of the main BUS according to the write-back instruction, and supports two methods for field write-back.

[0090] Solution A: For the merged instruction set of the write-back instruction merging unit, perform position mapping according to the global configuration so that the mapped position is consistent with the order of the main BUS editable area, set the number of containers consistent with the main BUS editable area, and update the val value of the corresponding position according to the bitmap value and val.

[0091] For example, the merged instruction set is mapped to a position according to the global configuration so that it corresponds to the editable area of ​​the main BUS in sequence, the number of containers corresponding to the editable area of ​​the main BUS is set, and the old value is updated according to the bitmap value and val.

[0092] Option B: Based on global configuration, the editable area of ​​the main BUS is mapped at the container granularity to ensure that the set area in the editable area of ​​the main BUS is consistent with the order of the local editable field set of the Stage. The number of containers consistent with the local editable field set of the Stage is set, and the val value of the corresponding position is updated according to the bitmap value and val.

[0093] For example, the editable area of ​​the main BUS can be pre-mapped at the container granularity according to the global configuration, so that the specific area corresponds to the order of the local editable field set of the Stage, the number of containers corresponding to the local editable field set of the Stage can be set, and the old value can be updated according to the bitmap value and val.

[0094] Scheme A involves mapping positions from a small bit-width region to a large bit-width region. Implementation methods include sorting / shifting or muxing / inserting bubbles. Scheme B involves mapping positions based on the main BUS's editable range. The field positions change every time a stage of the main BUS's editable range is reached. This requires configuration management, and specific implementation methods include sorting / shifting or muxing.

[0095] Condition write-back can be completed through the field write-back unit that supports condition processing. Combined with the same destPos configuration in the instruction, it can complete the multi-choice logic for multi-way condition write-back.

[0096] Based on the above design, the granularity of the selection fields for KEY generation, BUS selection, ALU selection from local BUS, and main BUS write-back instruction generation unit in each Stage is not limited. It can be 1b / 4b / 8b / 16b / 32b / 64b or a combination of several granularities, and the mechanism is unified under each granularity.

[0097] In each stage, the ALU writes back to the local BUS and the main BUS. The granularity of various write-back fields is not limited and can be 1b / 4b / 8b / 16b / 32b / 64b or a combination of several granularities. The mechanism is consistent across all granularities.

[0098] The condition processing capability of the main BUS write-back instruction generation unit may not be reflected in every container.

[0099] In this embodiment, the structure of each unit in MU and AU can be flexibly designed. This embodiment provides examples of optional structures for some units.

[0100] Please refer to the following: Figure 5 This provides a basic structure for a BUS selection unit. The 8-bit width and number of containers are only examples. If the BUS is partitioned, then each partition contains... Figure 5 The basic structure shown. Based onFigure 5 The architecture shown shows that the BUS selection unit performs field extraction and bit manipulation, which is used to extract specific fields from the main BUS and perform displacement, truncation and splicing, and finally output them to the internal BUS.

[0101] For example, the data range is determined based on the field source location and field length configuration. The bit fields are aligned by left shift << and right shift >>, and bit truncation is performed using mask[7:0]. Then, the data is aligned by left shift with the field destination location, and finally, the result is written to the internal BUS. The entire process supports configurable offsets and lengths, enabling flexible field reorganization.

[0102] The structure of the KEY generation unit can be the same as the basic structure of the BUS selection unit, and the partitioning is also the same.

[0103] Please refer to the following: Figure 6 This paper presents a basic structure for a write-back instruction generation unit, used to generate precise field write-back instructions after processing such as lookup. Combining the lookup results and write-back configuration constants, target data is extracted from the internal BUS based on the write-back field source location and field length configuration. Data alignment and truncation are performed through offset (left / right shift), masking, and AND operations (&). Simultaneously, address mapping is performed based on the instruction destination location and byte alignment offset, ultimately generating a field write-back instruction containing the field ID, offset, and length, which is then output to subsequent units for execution.

[0104] Please refer to the following: Figure 7 This provides a working mechanism for a write-back instruction merging unit, which aggregates and merges independent write-back instructions from multiple processing instances to reduce bus load and improve system efficiency.

[0105] In the main BUS write-back unit, the order of instructions and BUS data corresponds one-to-one (maintained by global configuration). The value at the corresponding position is updated according to the bitmap in the instruction, and the old value is retained for bits in the bitmap that are not set to 1.

[0106] Please refer to the following: Figure 8 One method for achieving one-to-one correspondence is to map the instruction positions, which has the advantage of unified BUS planning. Control signals from configuration registers (such as 1D registers) are dynamically matched with a preset instruction storage structure to achieve precise location mapping of instructions in memory or logical space. Input configuration parameters such as m0 and m1 are decoded by the location mapping unit and used to select and activate the corresponding instruction block. Simultaneously, each instruction block is associated with an update unit responsible for generating corresponding output data such as B127[7:0]…B001[7:0] based on the mapping result, forming an ordered instruction stream output.

[0107] Please refer to the following: Figure 9A second method for achieving one-to-one location mapping is provided: location mapping of the BUS. This method hides the hardware latency of the mapping and requires fewer update units. The location mapping unit dynamically associates control signals from the configuration register with the instruction storage structure, achieving precise mapping of instructions in memory or logical space. The input configuration parameters are decoded by the mapping unit, selecting and activating the corresponding instruction block, and simultaneously triggering the corresponding update unit to generate output data. These mapped instructions are written to the target address through the BUS update unit and ultimately transmitted via the internal bus.

[0108] Please refer to the following: Figure 10 This provides the basic structure of each ALU processing unit. Each operand-fetching unit has the same structure as the preceding container. The arithmetic unit performs corresponding operations on the operands according to the opcode, which is obtained from the linear list retrieved from the configuration plane index A2. For example, with ab as the operand and c as the result, the opcode can represent c = a + b, c = a|b, c = |a,” and so on.

[0109] The result write-back instruction section inside the ALU processing unit has the same structure as the write-back instruction generation container, except that the write-back target is the internal BUS. Multi-level ALU processing units execute serially. The green configurations in the diagram, except for those marked as 1D registers, are all obtained from the linear list of configuration plane indices A1 / A2. The actual implementation may vary depending on the size and specifications, and could be either Static Random-Access Memory (SRAM) or a register (REG).

[0110] Based on the above, please refer to the following: Figure 11 This embodiment provides a packet forwarding chip processing method, applied to the packet forwarding chip processing system described above. The method includes steps S110, S120, and S130.

[0111] S110, according to the arrangement order of each matching unit MU and action unit AU, the input information is sequentially input into each matching unit MU or action unit AU.

[0112] S120: Based on the pre-lookup unit, processing component, and field write-back unit in the MU, the input information is looked up, processed, and written back according to the first strategy. Alternatively, S130 is executed.

[0113] S130, based on the pre-lookup unit, processing component and field write-back unit in the AU, the input information is looked up, processed and written back according to the second strategy, wherein the processing of the input information in the second strategy includes ALU processing.

[0114] The above-described solution in this embodiment of the invention abandons the traditional MAU structure and provides an optimized pipeline structure. By setting up MU and AU independent of MU, which contain one or more ALU pipelines, a balance can be achieved between business flexibility and hardware overhead such as pipeline number, number of ALU instances and their utilization.

[0115] From a hardware perspective, a significant portion of the overhead in a programmable architecture MAU is the MUX In and MUX Out operations of the main bus. Since field write-backs involving the MU are unavoidable, this embodiment of the invention reuses this MUX In and MUX Out overhead, enhancing flexibility at the write-back instruction generation container level. This allows the MU to handle most simple write-back logic, limiting the ALU's workload to complex logic, thereby reducing the scale of logic handled by the ALU. Basic direct write-back, conditional write-back, and simple if-else write-back logic in the table Action can be completed in the MU. The programmability of the MU is mainly reflected in the write-back instruction generation container level. Computational and complex processing in the table Action can be completed in the AU.

[0116] By dividing the MU and AU into hardware units, and making each unit of the MU and AU independent of each other, the setting of the AU and its specifications are no longer tied to the MU. This allows the MU and AU to be flexibly combined in different scenarios, and the AU can independently implement the ALU function, thereby optimizing the overall processing performance.

[0117] In the several embodiments provided by this invention, it should be understood that the disclosed systems and methods can also be implemented in other ways. The system embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0118] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0119] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0120] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A packet forwarding chip processing system, characterized in that, include: Several matching units MU and several action units AU are arranged in a set order on the chip pipeline and connected by the main BUS. Input information entering the packet forwarding chip processing system enters the matching unit MU or action unit AU in the set order for processing. The matching unit MU and the action unit AU both include a pre-lookup unit, a processing component, and a field write-back unit; The matching unit MU is used to search, process and write back the input information according to the first strategy based on the pre-search unit, processing component and field write-back unit in the MU; The action unit AU is used to search, process, and write back the input information according to a second strategy based on the pre-lookup unit, processing component, and field write-back unit in the AU. The processing of the input information according to the second strategy includes ALU processing.

2. The packet forwarding chip processing system according to claim 1, characterized in that, The pre-lookup unit in the matching unit MU is used to extract a specified set of fields from the input information for pre-lookup, and to determine whether the subsequent processing of the matching unit MU is effective and to configure the face index. The processing components in the matching unit MU include a lookup key generation unit, a main lookup unit, a BUS selection unit, a main BUS write-back instruction generation unit, and a write-back instruction merging unit. The lookup key generation unit is used to generate a key for lookup by combining the decision of the pre-lookup unit; The main search unit is used to perform a search based on the KEY obtained by the search KEY generation unit to obtain the search result; The BUS selection unit is used to determine the fields required for BUS write-back from the main BUS or configuration plane constants; The main BUS write-back instruction generation unit is used to generate a main BUS write-back instruction based on the search results and the fields required for BUS write-back. The write-back instruction merging unit is used to merge the main BUS write-back instructions according to a preset strategy when there are multiple main BUS write-back instructions in the same Stage. The field write-back unit is used to write back the fields of the main BUS according to the main BUS write-back instruction.

3. The packet forwarding chip processing system according to claim 2, characterized in that, The lookup key generation unit, in conjunction with the decision of the pre-lookup unit, generates a key for lookup through the following steps: The lookup key generation unit, in conjunction with the decision of the pre-lookup unit, calls several key generation containers to select fields from the main BUS according to the sel value, shifts according to the shift configuration, extracts the corresponding number of bits according to the len configuration, and writes them to the corresponding position of the lookup key according to the destPosA configuration, thereby obtaining the key used for lookup.

4. The packet forwarding chip processing system according to claim 3, characterized in that, The main BUS write-back command generation unit generates the main BUS write-back command based on the search results and the fields required for BUS write-back through the following steps: A container is generated by calling several instructions. Based on the container generated by the instructions, fields are selected from the search results, fields required for BUS write-back, and configuration constants to generate write-back instructions. The write-back instruction includes the write-back position of destPosB, the value of val, and the valid bitmap of val.

5. The packet forwarding chip processing system according to claim 1, characterized in that, The pre-lookup unit in the action unit AU is used to extract a specified set of fields from the input information for pre-lookup, and to decide whether the subsequent processing of the action unit AU is effective and to configure the surface index. The processing components in the action unit AU include a BUS selection unit, a field processing unit, a main BUS write-back instruction generation unit, and a write-back instruction merging unit. The BUS selection unit is used to determine the fields needed for field processing from the main BUS or configuration constants to form a local BUS; The field processing unit is used to perform one or more levels of ALU processing on the local BUS and write back the result of each level of ALU processing to the local BUS. The main BUS write-back instruction generation unit is used to generate main BUS write-back instructions based on the result of the ALU processing. The write-back instruction merging unit is used to merge the main BUS write-back instructions according to a preset strategy when there are multiple main BUS write-back instructions in the same Stage. The field write-back unit is used to write back the fields of the main BUS according to the main BUS write-back instruction.

6. The packet forwarding chip processing system according to any one of claims 2 to 5, characterized in that, The write-back instruction merging unit merges the write-back instructions of each main BUS according to a preset strategy through the following steps: In the case of multiple main BUS write-back instructions in the same stage, the main BUS write-back instructions with the same destPosB position are merged.

7. The packet forwarding chip processing system according to any one of claims 2 to 5, characterized in that, The field write-back unit performs the field write-back of the main BUS according to the main BUS write-back instruction through the following steps: The merged instruction set of the write-back instruction merging unit is mapped according to the global configuration so that the mapped position is consistent with the order of the main BUS editable area. The number of containers consistent with the main BUS editable area is set, and the val value of the corresponding position is updated according to the bitmap value and val.

8. The packet forwarding chip processing system according to any one of claims 2 to 5, characterized in that, The field write-back unit performs the field write-back of the main BUS according to the main BUS write-back instruction through the following steps: Based on global configuration, the editable area of ​​the main BUS is mapped at the container granularity to ensure that the set area in the editable area of ​​the main BUS is consistent with the order of the local editable field set of the Stage. The number of containers consistent with the local editable field set of the Stage is set, and the val value of the corresponding position is updated according to the bitmap value and val.

9. The packet forwarding chip processing system according to any one of claims 1 to 8, characterized in that, The input information is obtained by the main BUS parsing and processing the input request. The input request includes an initial request and a request processed by the matching unit MU or the action unit AU. The matching unit MU searches, processes, and writes back the input information according to the first strategy, including: direct write-back, conditional write-back, and if-else write-back logic; The action unit AU searches, processes, and writes back the input information according to the second strategy, including calculating relevant items that meet the complexity threshold.

10. A packet forwarding chip processing method, characterized in that, The method is applied to the packet forwarding chip processing system according to any one of claims 1 to 9; the method includes: According to the arrangement order of each matching unit MU and action unit AU, the input information is sequentially input into each matching unit MU or action unit AU; Based on the pre-lookup unit, processing component, and field write-back unit in the matching unit MU, the input information is searched, processed, and written back according to the first strategy; or, Based on the pre-lookup unit, processing component, and field write-back unit in the action unit AU, the input information is looked up, processed, and written back according to the second strategy. The processing of the input information in the second strategy includes ALU processing.

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