Calibration method and device of circuit, electronic equipment and storage medium

Abstract

The application provides a calibration method and device of a circuit, electronic equipment and a storage medium, and relates to the technical field of analog integrated circuit design. The method comprises the following steps: determining a reset level state of a reset signal, determining an initial adjustment signal in the case that the reset level state is a high level state; the reset signal is used for indicating whether to perform a clear reset on the circuit; the circuit comprises an operational amplifier; the operational amplifier is arranged with a first MOSFET and a second MOSFET; the initial adjustment signal is represented in the form of N-bit binary; according to the initial adjustment signal, the size of the first MOSFET and the size of the second MOSFET are adjusted to obtain a first target MOSFET and a second target MOSFET; wherein the difference between the size of the first target MOSFET and the size of the second target MOSFET is smaller than the difference between the size of the first MOSFET and the size of the second MOSFET; and according to the size of the first target MOSFET and the size of the second target MOSFET, a calibrated circuit is determined. The scheme provided by the application improves the brightness adjustment precision of the LED.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design technology, and in particular to a circuit calibration method, apparatus, electronic device, and storage medium. Background Technology

[0002] As the requirements for the precision and dimming capability of LED constant current driving become increasingly stringent in display devices, intelligent lighting systems, and industrial-grade light-emitting diode (LED) driver modules, LED constant current driving circuits are needed to achieve fine-grained LED brightness adjustment.

[0003] In related technologies, LED constant current drive circuits can achieve fine-grained brightness adjustment based on operational amplifiers and laterally diffused metal-oxide-semiconductor (LDMOS). Specifically, the LED constant current drive circuit can utilize the virtual short and virtual open characteristics of the operational amplifier to determine the voltage across the resistor in the LED constant current drive circuit, and determine the voltage across the resistor and the resistance value of the resistor to determine the drive current. Then, the LED constant current drive circuit, combined with pull-up and pull-down networks, adjusts the drive current to achieve high-bit pulse width modulation (PWM) dimming.

[0004] However, the voltage across the resistors in the LED constant current drive circuit includes the DC offset voltage of the operational amplifier, and due to the random stray nature of the DC offset voltage, the brightness adjustment accuracy of the LED is relatively low. Therefore, a circuit calibration method is urgently needed to reduce the DC offset voltage, thereby improving the accuracy of LED brightness adjustment. Summary of the Invention

[0005] This application provides a circuit calibration method, apparatus, electronic device, and storage medium to improve the brightness adjustment accuracy of LEDs.

[0006] In a first aspect, this application provides a circuit calibration method, the method comprising:

[0007] The reset level state of the reset signal is determined. When the reset level state is high, the initial adjustment signal is determined. The reset signal is used to indicate whether to clear the circuit. The circuit includes an operational amplifier. The operational amplifier has a first MOSFET and a second MOSFET. The initial adjustment signal is represented in N-bit binary form, where N is a positive integer greater than 1.

[0008] Based on the initial adjustment signal, the dimensions of the first MOSFET and the second MOSFET are adjusted to obtain the first target MOSFET and the second target MOSFET; wherein the difference between the dimensions of the first target MOSFET and the second target MOSFET is less than the difference between the dimensions of the first MOSFET and the second MOSFET.

[0009] The calibrated circuit is determined based on the dimensions of the first target MOSFET and the second target MOSFET.

[0010] In one possible implementation, the dimensions of the first MOSFET and the second MOSFET are adjusted according to an initial adjustment signal to obtain the first target MOSFET and the second target MOSFET, including:

[0011] Perform a first operation, which includes: adjusting the size of the first MOSFET and the size of the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment; determining the adjustment result of the i-th adjustment signal according to the operational amplifier after the i-th adjustment, and generating the (i+1)-th adjustment signal based on the adjustment result of the i-th adjustment signal;

[0012] Repeat the first operation until i is greater than or equal to N, then determine the first MOSFET after the Nth adjustment as the first target MOSFET, and determine the second MOSFET after the Nth adjustment as the second target MOSFET;

[0013] Where i is a positive integer; when i=1, the first adjustment signal is the initial adjustment signal; the operational amplifier after the i-th adjustment includes the first MOSFET after the i-th adjustment and the second MOSFET after the i-th adjustment.

[0014] In one possible implementation, the first MOSFET is connected in parallel with M third MOSFETs, and the second MOSFET is connected in parallel with M fourth MOSFETs; wherein the M third MOSFETs and the M fourth MOSFETs are all binary weighted MOSFETs, and the binary weight of each third MOSFET is the same as the binary weight of each fourth MOSFET.

[0015] In one possible implementation, adjusting the dimensions of the first MOSFET and the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment includes:

[0016] Based on the i-th adjustment signal and M third MOSFETs, adjust the size of the first MOSFET to obtain the first MOSFET after the i-th adjustment;

[0017] Based on the i-th adjustment signal and M fourth MOSFETs, the size of the second MOSFET is adjusted to obtain the second MOSFET after the i-th adjustment.

[0018] In one possible implementation, adjusting the size of the first MOSFET based on the i-th adjustment signal and M third MOSFETs to obtain the first MOSFET after the i-th adjustment includes:

[0019] Based on the i-th adjustment signal, determine the state of each of the M third MOSFETs; wherein, the state of each third MOSFET is either on or off.

[0020] Based on the states of the M third MOSFETs, the size of the first MOSFET is adjusted to obtain the first MOSFET after the i-th adjustment; wherein, the size of the first MOSFET after the i-th adjustment is the sum of the inherent size of the first MOSFET and the inherent size of at least one fifth MOSFET; each fifth MOSFET is a MOSFET in the on state among the M third MOSFETs.

[0021] In one possible implementation, determining the adjustment result of the i-th adjustment signal based on the operational amplifier after the i-th adjustment includes:

[0022] The same voltage is applied to the first MOSFET and the second MOSFET after the i-th adjustment;

[0023] Input current into the operational amplifier after the i-th adjustment to determine the first output current and the second output current after the i-th adjustment; the first output current after the i-th adjustment is the output current of the first MOSFET after the i-th adjustment, and the second output current after the i-th adjustment is the output current of the second MOSFET after the i-th adjustment;

[0024] If the i-th current difference between the first output current after the i-th adjustment and the second output current after the i-th adjustment is less than the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be an effective adjustment.

[0025] If the i-th current difference is greater than or equal to the (i-1)-th current difference, the regulation result of the i-th regulation signal is determined to be invalid regulation.

[0026] In one possible implementation, generating the (i+1)th adjustment signal based on the adjustment result of the i-th adjustment signal includes:

[0027] If the adjustment result of the i-th adjustment signal is effective, the binary state of the (i+1)-th bit in the i-th adjustment signal is determined as the state to be verified, and the (i+1)-th adjustment signal is obtained.

[0028] If the adjustment result of the i-th adjustment signal is invalid, the binary state of the i-th bit in the i-th adjustment signal is determined as the default state, and the binary state of the (i+1)-th bit is determined as the state to be verified, thus obtaining the (i+1)-th adjustment signal.

[0029] Secondly, this application provides a circuit calibration device, comprising:

[0030] The first determining module is used to determine the reset level state of the reset signal. When the reset level state is high, it determines the initial adjustment signal. The reset signal is used to indicate whether to clear the circuit. The circuit includes an operational amplifier. The operational amplifier has a first MOSFET and a second MOSFET. The initial adjustment signal is represented in N-bit binary form, where N is a positive integer greater than 1.

[0031] An adjustment module is used to adjust the size of the first MOSFET and the second MOSFET according to an initial adjustment signal to obtain a first target MOSFET and a second target MOSFET; wherein the difference between the size of the first target MOSFET and the size of the second target MOSFET is less than the difference between the size of the first MOSFET and the size of the second MOSFET.

[0032] The second determining module is used to determine the calibrated circuit based on the dimensions of the first target MOSFET and the second target MOSFET.

[0033] In one possible implementation, the adjustment module is specifically used for:

[0034] Perform a first operation, which includes: adjusting the size of the first MOSFET and the size of the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment; determining the adjustment result of the i-th adjustment signal according to the operational amplifier after the i-th adjustment, and generating the (i+1)-th adjustment signal based on the adjustment result of the i-th adjustment signal;

[0035] Repeat the first operation until i is greater than or equal to N, then determine the first MOSFET after the Nth adjustment as the first target MOSFET, and determine the second MOSFET after the Nth adjustment as the second target MOSFET;

[0036] Where i is a positive integer; when i=1, the first adjustment signal is the initial adjustment signal; the operational amplifier after the i-th adjustment includes the first MOSFET after the i-th adjustment and the second MOSFET after the i-th adjustment.

[0037] In one possible implementation, the first MOSFET is connected in parallel with M third MOSFETs, and the second MOSFET is connected in parallel with M fourth MOSFETs; wherein the M third MOSFETs and the M fourth MOSFETs are all binary weighted MOSFETs, and the binary weight of each third MOSFET is the same as the binary weight of each fourth MOSFET.

[0038] In one possible implementation, the adjustment module is specifically used for:

[0039] Based on the i-th adjustment signal and M third MOSFETs, adjust the size of the first MOSFET to obtain the first MOSFET after the i-th adjustment;

[0040] Based on the i-th adjustment signal and M fourth MOSFETs, the size of the second MOSFET is adjusted to obtain the second MOSFET after the i-th adjustment.

[0041] In one possible implementation, the adjustment module is specifically used for:

[0042] Based on the i-th adjustment signal, determine the state of each of the M third MOSFETs; wherein, the state of each third MOSFET is either on or off.

[0043] Based on the respective states of the M third MOSFETs, the size of the first MOSFET is adjusted to obtain the first MOSFET after the i-th adjustment; wherein, the size of the first MOSFET after the i-th adjustment is the sum of the inherent size of the first MOSFET and the inherent size of at least one fifth MOSFET; each fifth MOSFET is a MOSFET in the on state among the M third MOSFETs.

[0044] In one possible implementation, the adjustment module is specifically used for:

[0045] The same voltage is applied to the first MOSFET and the second MOSFET after the i-th adjustment;

[0046] Input current into the operational amplifier after the i-th adjustment to determine the first output current and the second output current after the i-th adjustment; the first output current after the i-th adjustment is the output current of the first MOSFET after the i-th adjustment, and the second output current after the i-th adjustment is the output current of the second MOSFET after the i-th adjustment;

[0047] If the i-th current difference between the first output current after the i-th adjustment and the second output current after the i-th adjustment is less than the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be an effective adjustment.

[0048] If the i-th current difference is greater than or equal to the (i-1)-th current difference, the regulation result of the i-th regulation signal is determined to be invalid regulation.

[0049] In one possible implementation, the adjustment module is specifically used for:

[0050] If the adjustment result of the i-th adjustment signal is effective, the binary state of the (i+1)-th bit in the i-th adjustment signal is determined as the state to be verified, and the (i+1)-th adjustment signal is obtained.

[0051] If the adjustment result of the i-th adjustment signal is invalid, the binary state of the i-th bit in the i-th adjustment signal is determined as the default state, and the binary state of the (i+1)-th bit is determined as the state to be verified, thus obtaining the (i+1)-th adjustment signal.

[0052] Thirdly, this application provides an electronic device, comprising:

[0053] At least one processor; and

[0054] A memory that is communicatively connected to at least one processor; wherein,

[0055] The memory stores instructions that can be executed by at least one processor to cause the at least one processor to perform the methods involved in the first aspect and any possible implementation.

[0056] Fourthly, this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods involved in the first aspect and any possible implementation.

[0057] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the methods involved in the first aspect and any possible implementation.

[0058] In a sixth aspect, this application provides a chip including at least one processor for executing program instructions to perform the methods involved in the first aspect and any possible implementation.

[0059] The calibration method, apparatus, electronic device, and storage medium provided in this application, through an ordered calibration process triggered by a reset signal, adjust the dimensions of the first MOSFET and the second MOSFET using an N-bit binary initial adjustment signal, reducing the size difference between the first MOSFET and the second MOSFET, thereby reducing the DC offset voltage caused by MOSFET manufacturing mismatch. Therefore, when adjusting the brightness of an LED through the calibrated circuit, the brightness adjustment accuracy of the LED can be improved, thereby realizing the fusion of high-bit PWM dimming and high-bit DC dimming, further improving the adjustment accuracy of LED brightness. Attached Figure Description

[0060] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0061] Figure 1 A schematic diagram of an LED constant current drive circuit provided for related technologies;

[0062] Figure 2 This is a schematic diagram of the system architecture provided for an embodiment of this application;

[0063] Figure 3 A schematic flowchart illustrating a circuit calibration method provided in an embodiment of this application;

[0064] Figure 4 A schematic diagram illustrating a first MOSFET and a second MOSFET that do not have mismatch, provided for an embodiment of this application;

[0065] Figure 5 A schematic diagram illustrating a mismatch between a first MOSFET and a second MOSFET provided in an embodiment of this application;

[0066] Figure 6 A schematic flowchart for determining a first target MOSFET and a second target MOSFET is provided for embodiments of this application;

[0067] Figure 7 A schematic diagram of a circuit provided for an embodiment of this application;

[0068] Figure 8 A timing diagram for calibrating a circuit is provided as an embodiment of this application;

[0069] Figure 9 This is a schematic diagram of the structure of a circuit calibration device provided in an embodiment of this application;

[0070] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0071] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0072] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0073] The collection, storage, use, processing, transmission, provision, and disclosure of financial data or user data involved in the technical solution of this application all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0074] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0075] As the requirements for the precision and dimming capability of LED constant current driving become increasingly stringent in display devices, intelligent lighting systems, and industrial-grade LED driver modules, LED constant current driving circuits are needed to achieve fine-grained LED brightness adjustment.

[0076] In related technologies, LED constant current drive circuits can achieve fine-grained brightness adjustment based on operational amplifiers and LDMOS. This can be combined with... Figure 1 To understand, Figure 1 This is a schematic diagram of an LED constant current drive circuit provided for related technologies. Figure 1 As shown, the LED constant current drive circuit includes a digital-to-analog converter (DAC), an operational amplifier, resistors, a P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET), an LDMOS, and an LED.

[0077] Among them, the DAC is the core reference signal generation module in the LED constant current drive circuit. The DAC can convert digital control signals into continuously changing analog voltage signals, which serve as the reference voltage for the operational amplifier.

[0078] Operational amplifiers are the core amplification and comparison devices in LED constant current drive circuits to achieve constant current control. They have the characteristics of high gain, high input impedance, and low output impedance. Their working principle is based on the ideal characteristics of virtual short and virtual open.

[0079] One end of the resistor is connected to the source of the LDMOS, and the other end is grounded. The resistance value of the resistor is fixed.

[0080] PMOSFETs are auxiliary switches or bias adjustment devices in LED constant current drive circuits. PMOSFETs can receive output signals from operational amplifiers and adjust the voltage signal at the gate of LDMOS by changing their own on and off states.

[0081] LDMOS is a power switching device that directly drives the LED load in LED constant current drive circuits. The gate of the LDMOS receives a control signal regulated by the PMOSFET, and regulates the driving current ILED flowing through the LED by controlling its own conduction level (equivalent resistance change).

[0082] The LED is the load device in the LED constant current drive circuit and the core component that ultimately achieves brightness output. When the LDMOS is turned on, the drive current ILED flows through the LED, and the LED converts electrical energy into light energy and emits light; the brightness is positively correlated with the magnitude of the current flowing through it, and the greater the current, the higher the brightness.

[0083] In some embodiments, when the PWM is high, the LDMOS is in the on state. At this time, the LDMOS provides high-voltage protection, and utilizing the virtual short / virtual open principle of the operational amplifier, the voltage at the negative terminal of the operational amplifier is equal to the voltage at the positive terminal. Therefore, the voltage across resistor R is the superposition of the input voltage of the DAC and the DC offset voltage. Thus, the current generated in this LED constant current drive circuit = (input voltage + DC offset voltage) / resistance value. Therefore, the negative feedback mechanism of the operational amplifier can linearly adjust the gate voltage of the PMOSFET, thereby ensuring the linear constant current drive characteristics of this LED constant current drive circuit.

[0084] In addition, the LED constant current drive circuit also includes pull-up and pull-down networks. The pull-up network, consisting of a pull-up resistor and the power supply voltage, quickly provides a drive voltage to the LDMOS gate when the PWM signal is high, accelerating the LDMOS conduction process and avoiding current build-up delay caused by a slow gate voltage rise. The pull-down network, consisting of a pull-down resistor and ground, quickly discharges residual charge on the LDMOS gate when the PWM signal is low, causing the LDMOS to turn off rapidly and preventing current tailing caused by incomplete turn-off.

[0085] Therefore, LED constant current drive circuits can be combined with pull-up and pull-down networks to achieve rapid switching of LEDs, and achieve a wide range of brightness adjustment by adjusting the duty cycle of the conduction time.

[0086] However, when the PWM signal is high, the current generated in the LED constant current drive circuit is equal to (input voltage + DC offset voltage) / the resistance value. The DC offset voltage is caused by manufacturing process mismatch in the differential pair metal-oxide-semiconductor field-effect transistor (MOSFET) of the operational amplifier, and it exhibits random stray characteristics, meaning its magnitude and polarity cannot be predicted or eliminated in advance through hardware design.

[0087] Furthermore, since the drain of the LDMOS is directly connected to an external LED, the power at this node affects the port temperature. If the drain voltage is too high and the power is excessive, the port temperature will rise sharply, potentially burning out the chip. Therefore, to reduce the port temperature, the drain voltage of the LDMOS needs to be reduced, which means reducing the sum of the input voltage and the DC offset voltage. For example, the sum of the input voltage and the DC offset voltage needs to be less than or equal to 300mV.

[0088] However, the magnitude of the DC offset voltage cannot be predicted or eliminated in advance, making it impossible to accurately determine the voltage value. For example, when the input voltage is less than or close to the DC offset voltage, the DC offset voltage accounts for a large proportion of the resistor voltage, which may cause problems such as current misalignment and dimming errors. This limits the granularity of DAC dimming, preventing the LED constant current drive circuit from achieving the integration of high-bit PWM and DC dimming, thus reducing the accuracy of LED brightness adjustment.

[0089] Based on this, this application provides a circuit calibration method. Through an ordered calibration process triggered by a calibration enable signal, the size of the first MOSFET and the second MOSFET is adjusted using an N-bit binary initial adjustment signal. This reduces the slight size difference between the artificially manufactured first MOSFET and the second MOSFET, thereby complementing the difference in equivalent input pair transistors caused by the manufacturing process, and further reducing the equivalent DC offset voltage caused by MOSFET manufacturing mismatch and other reasons.

[0090] To facilitate understanding, the following will be combined with... Figure 2 The system architecture applicable to the embodiments of this application will be described.

[0091] Figure 2 This is a schematic diagram of the system architecture provided for an embodiment of this application. Figure 2 As shown, it includes an LED constant current driving circuit 21 and a control device 22. The control device 22 can be, for example, a mobile phone, a computer, or other similar device. The LED constant current driving circuit 21 can be, for example, as shown in the diagram. Figure 1 As shown, the LED constant current drive circuit 21 includes LED 23.

[0092] In practical applications, the control device 22 can communicate with the LED constant current drive circuit 21 to instruct the LED constant current drive circuit 21 to adjust the brightness of the LED 23. For example, the control device 22 can send a digital input voltage to the LED constant current drive circuit 21. Upon receiving the digital input voltage, the DAC in the LED constant current drive circuit 21 converts the digital input voltage into an analog input voltage. The LED constant current drive circuit 21 then adjusts the brightness of the LED 23 based on the analog input voltage.

[0093] It should be noted that, Figure 2 This is merely an example to illustrate a system architecture diagram, and is not a limitation on system architecture diagrams.

[0094] It should be noted that the execution subject in each embodiment of this application can be a chip, chip module, processor, microprocessor, etc., or it can be a device integrating the above-mentioned chips, chip modules, processors, or microprocessors, such as a server. The specific execution subject in each embodiment of this application is not limited, and it can be selected and set according to actual needs. In the following embodiments, a server integrating the above-mentioned chips, chip modules, processors, or microprocessors is used as an example for description, which does not constitute a limitation on the actual execution subject.

[0095] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0096] Figure 3 This is a schematic flowchart illustrating a circuit calibration method provided in an embodiment of this application. Figure 3 As shown, the method may include the following steps:

[0097] S301. Determine the reset level state of the reset signal. When the reset level state is high, determine the initial adjustment signal. The reset signal is used to indicate whether to clear the circuit. The circuit includes an operational amplifier. The operational amplifier has a first MOSFET and a second MOSFET. The initial adjustment signal is represented in N-bit binary form, where N is a positive integer greater than 1.

[0098] A reset signal is a control signal used to trigger a circuit to return to its initial state. The reset signal is generated by an external control unit or an internal reset module of the chip.

[0099] The reset signal's reset level indicates whether the circuit performs a clear reset operation. When the reset level is high, the reset signal indicates that the circuit performs a clear reset operation; when the reset level is low, the reset signal indicates that the circuit does not perform a clear reset operation. This circuit can be, for example, an LED constant current drive circuit.

[0100] An operational amplifier is an analog integrated circuit with high voltage gain, high input impedance, and low output impedance. An operational amplifier includes an input differential MOSFET, which comprises a first MOSFET and a second MOSFET. The first and second MOSFETs are integrated in a symmetrical structure within the operational amplifier, sharing the same bias circuitry and signal nodes, forming the core differential amplification unit of the operational amplifier.

[0101] The first MOSFET is based on a three-layer structure of metal, oxide, and semiconductor, and the conduction current between the source and drain is controlled by the gate voltage. The second MOSFET is also based on a three-layer structure of metal, oxide, and semiconductor, and the conduction current between the source and drain is controlled by the gate voltage. The first MOSFET and the second MOSFET can be, for example, PMOSFETs.

[0102] In some embodiments, when the reset level is high, the reset signal is used to indicate a zero-reset operation on the circuit. At this time, the circuit can be corrected to obtain a corrected circuit, and then the circuit can operate based on the corrected circuit when the reset level is low.

[0103] The initial adjustment signal is the signal that initiates the first adjustment of the input differential MOSFET in the operational amplifier. The initial adjustment signal can be, for example, a binary control signal.

[0104] In some embodiments, the circuit stores the highest number of bits of a binary control signal. The circuit can generate an initial adjustment signal based on this highest number of bits and a preset rule. For example, assuming the highest number of bits is 8, and the preset rule is to set the value of the highest bit to 1 and the values ​​of the remaining bits to 0, the initial adjustment signal can be determined to be 10000000 based on the highest number of bits and the preset rule.

[0105] S302. According to the initial adjustment signal, the size of the first MOSFET and the size of the second MOSFET are adjusted to obtain the first target MOSFET and the second target MOSFET; wherein, the difference between the size of the first target MOSFET and the size of the second target MOSFET is less than the difference between the size of the first MOSFET and the size of the second MOSFET.

[0106] Operational amplifiers can be single-stage or multi-stage. For a single-stage operational amplifier, the DC offset voltage is primarily caused by the mismatch between the input differential MOSFETs in the single-stage amplifier; mismatches in other components are equivalently superimposed on the input differential MOSFETs. The DC offset voltage of a multi-stage operational amplifier attenuates the gain of the preceding stage. Therefore, the DC offset voltage of a multi-stage operational amplifier is still primarily caused by the mismatch between the input differential MOSFETs in the first stage operational amplifier, and mismatches in other components are still equivalently superimposed on the input differential MOSFETs. Thus, the DC offset voltage of the operational amplifier can be equated to the size mismatch between the first and second MOSFETs, and is mainly caused by the mismatch between the first and second MOSFETs.

[0107] Can be combined Figure 4 and Figure 5 To understand, Figure 4 This is a schematic diagram illustrating a first MOSFET and a second MOSFET that do not exhibit mismatch, as provided in an embodiment of this application. Figure 4As shown, the voltage connected to the first MOSFET is VIP, and the voltage connected to the second MOSFET is VIN, with VIP and VIN having the same value. When there is no mismatch between the first and second MOSFETs, the same input current is applied to both MOSFETs. In this case, the output current of the first MOSFET is the same as the output current of the second MOSFET, and the sum of their output currents equals the input current.

[0108] Taking the input current as I as an example, assuming the output current of the first MOSFET is I1 and the output current of the second MOSFET is I2, then I1 = I2 = I / 2.

[0109] Figure 5 This is a schematic diagram illustrating a mismatch between a first MOSFET and a second MOSFET, as provided in an embodiment of this application. Figure 5 As shown, the voltage connected to the first MOSFET is VIP, and the voltage connected to the second MOSFET is VIN, with VIP and VIN having the same value. When there is a mismatch between the first and second MOSFETs, and the same input current I is applied to both, the output currents of the first and second MOSFETs will differ. To make the output currents I1 and I2 of the first and second MOSFETs the same, a DC offset voltage VOS can be added to the first MOSFET to increase its connection voltage, thereby generating the DC offset voltage VOS.

[0110] Based on this, M third MOSFETs and M fourth MOSFETs can be added to the LED constant current drive circuit. The first MOSFET is connected in parallel with the M third MOSFETs, and the second MOSFET is connected in parallel with the M fourth MOSFETs. All M third MOSFETs and M fourth MOSFETs are binary-weighted MOSFETs, and the binary weight of each third MOSFET is the same as the binary weight of each fourth MOSFET.

[0111] In some embodiments, two sets of dynamically configurable auxiliary size adjustment units are constructed by connecting M third MOSFETs in parallel with the first MOSFET of the operational amplifier input differential pair, and connecting M fourth MOSFETs in parallel with the second MOSFET of the input differential pair. Specifically, both the M third and M fourth MOSFETs adopt a binary weighting design rule, that is, the width-to-length ratio of each third MOSFET is set according to a power of 2, and each fourth MOSFET also follows the exact same binary weighting ratio, with a one-to-one correspondence between the weights of the third and fourth MOSFETs. In this way, each binary bit of the adjustment signal can be precisely matched with a set of MOSFETs with fixed weights. By controlling the on and off states of the corresponding MOSFETs, the dimensions of the first and second MOSFETs can be finely adjusted, resulting in a smaller size difference between the first and second target MOSFETs, thereby reducing the DC offset voltage caused by manufacturing mismatch between the first and second MOSFETs.

[0112] S303. Determine the calibrated circuit based on the dimensions of the first target MOSFET and the second target MOSFET.

[0113] In some embodiments, the calibrated circuit includes an adjusted operational amplifier, and the input differential MOSFET in the adjusted operational amplifier includes a first target MOSFET and a second target MOSFET.

[0114] The calibrated circuit refers to an LED constant current drive circuit with high-precision constant current drive capability. Because the size difference between the first and second target MOSFETs is small, the DC offset voltage of the calibrated circuit is lower than that of the original circuit.

[0115] exist Figure 3 In the illustrated embodiment, an ordered calibration process triggered by a reset signal is used to adjust the dimensions of the first and second MOSFETs using an N-bit binary initial adjustment signal. This reduces the size difference between the first and second MOSFETs, thereby decreasing the DC offset voltage caused by MOSFET manufacturing mismatch. Therefore, when the brightness of the LED is adjusted using the calibrated circuit, the brightness adjustment accuracy of the LED can be improved. This achieves the fusion of high-bit PWM dimming and high-bit DC dimming, further enhancing the accuracy of LED brightness adjustment.

[0116] exist Figure 3 Based on the illustrated embodiment, the following is combined with Figure 6The method of adjusting the size of the first MOSFET and the second MOSFET to obtain the first target MOSFET and the second target MOSFET will be further explained.

[0117] Figure 6 This is a schematic diagram illustrating a process for determining a first target MOSFET and a second target MOSFET, provided as an embodiment of this application. Figure 6 As shown, the process may include the following steps:

[0118] S601. Adjust the size of the first MOSFET and the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment.

[0119] Where i is a positive integer; when i=1, the first adjustment signal is the initial adjustment signal.

[0120] In some embodiments, the dimensions of the first MOSFET and the second MOSFET can be adjusted as follows: the dimensions of the first MOSFET are adjusted according to the i-th adjustment signal and M third MOSFETs to obtain the first MOSFET after the i-th adjustment; the dimensions of the second MOSFET are adjusted according to the i-th adjustment signal and M fourth MOSFETs to obtain the second MOSFET after the i-th adjustment.

[0121] In some embodiments, the size of the first MOSFET can be adjusted according to the i-th adjustment signal and the M third MOSFETs as follows: the state of each of the M third MOSFETs is determined according to the i-th adjustment signal; wherein the state of each third MOSFET is either on or off; the size of the first MOSFET is adjusted according to the state of each of the M third MOSFETs to obtain the first MOSFET after the i-th adjustment; wherein the size of the first MOSFET after the i-th adjustment is the sum of the inherent size of the first MOSFET and the inherent size of at least one fifth MOSFET; each fifth MOSFET is a MOSFET in the on state among the M third MOSFETs.

[0122] The i-th adjustment signal is a binary control signal that adjusts the dimensions of the first MOSFET and the second MOSFET for the i-th time. For each of the M third MOSFETs, a state where the third MOSFET is in the on-state indicates that a conductive channel is formed between its source and drain, allowing current to flow. A state where the third MOSFET is in the off-state indicates that there is no conductive channel between its source and drain, preventing current from flowing. In some embodiments, when a third MOSFET is in the on-state, it can be designated as the fifth MOSFET.

[0123] In some embodiments, M can be a positive integer greater than or equal to N. When M and N are the same, the N bits in the i-th adjustment signal correspond one-to-one with each of the M third MOSFETs; when M is greater than N, the N bits in the i-th adjustment signal correspond one-to-one with each of the N third MOSFETs out of the M third MOSFETs. For each bit in the i-th adjustment signal, the value of the bit is used to indicate the adjustment of the state of the third MOSFET corresponding to that bit. For example, when the value of the bit is 1, it indicates that the state of the third MOSFET corresponding to that bit is adjusted to the on state; when the value of the bit is 0, it indicates that the state of the third MOSFET corresponding to that bit is adjusted to the off state.

[0124] In some embodiments, the LED constant current driving circuit controls the state of each of the M third MOSFETs connected in parallel with the first MOSFET bit by bit through the i-th adjustment signal. The more third MOSFETs in the M-th MOSFET that are in the on state, the larger the size of the first MOSFET.

[0125] For example, assuming M is 2, that is, the third MOSFET connected in parallel with the first MOSFET includes the third MOSFET1 and the third MOSFET2, the i-th adjustment signal is 10, and the first bit of the adjustment signal corresponds to the third MOSFET1, and the second bit of the adjustment signal corresponds to the third MOSFET2.

[0126] Based on the i-th adjustment signal of 10, the third MOSFET1 and the third MOSFET2 are adjusted to determine that the state of the third MOSFET1 is in the on state and the state of the third MOSFET2 is in the off state. At this time, the size of the first MOSFET is the sum of the size of the first MOSFET and the size of the third MOSFET2.

[0127] The size of the second MOSFET is adjusted according to the i-th adjustment signal and the M fourth MOSFETs in the same way as the size of the first MOSFET is adjusted according to the i-th adjustment signal and the M third MOSFETs, and will not be described again here.

[0128] S602. Determine the adjustment result of the i-th adjustment signal based on the operational amplifier after the i-th adjustment.

[0129] The operational amplifier after the i-th adjustment includes the first MOSFET after the i-th adjustment and the second MOSFET after the i-th adjustment.

[0130] In some embodiments, the adjustment result of the i-th adjustment signal can be determined as follows: the same voltage is applied to the first MOSFET and the second MOSFET after the i-th adjustment; current is input into the operational amplifier after the i-th adjustment to determine the first output current and the second output current after the i-th adjustment; the first output current after the i-th adjustment is the output current of the first MOSFET after the i-th adjustment, and the second output current after the i-th adjustment is the output current of the second MOSFET after the i-th adjustment; if the i-th current difference between the first output current and the second output current after the i-th adjustment is less than the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be effective adjustment; if the i-th current difference is greater than or equal to the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be ineffective adjustment.

[0131] For example, assuming that after inputting current into the operational amplifier after the i-th adjustment, the first output current after the i-th adjustment is determined to be 5A and the second output current after the i-th adjustment is 6A, then the i-th current difference between the first output current and the second output current after the i-th adjustment is 1A. Assuming the (i-1)-th current difference is 2A, then the adjustment result of the i-th adjustment signal is determined to be effective adjustment.

[0132] S603. Generate the (i+1)th adjustment signal based on the adjustment result of the i-th adjustment signal.

[0133] In some embodiments, the (i+1)th adjustment signal can be generated as follows: if the adjustment result of the i-th adjustment signal is an effective adjustment, the binary state of the (i+1)-th bit in the i-th adjustment signal is determined as a state to be verified, thus obtaining the (i+1)-th adjustment signal; if the adjustment result of the i-th adjustment signal is an invalid adjustment, the binary state of the i-th bit in the i-th adjustment signal is determined as a default state, and the binary state of the (i+1)-th bit is determined as a state to be verified, thus obtaining the (i+1)-th adjustment signal.

[0134] In some embodiments, if the adjustment result of the i-th adjustment signal is an effective adjustment, it indicates that the current bit state selection of the i-th bit in the i-th adjustment signal is reasonable, and there is no need to modify the state of the traversed bits. In this case, the next bit of the i-th adjustment signal can be set to a state to be verified. The state to be verified is a preset state; for example, to determine the state of the next bit as the state to be verified, the value of the next bit can be set to 1.

[0135] For example, suppose i is 3, the third adjustment signal is 10100000, and the adjustment result of the third adjustment signal is effective. In this case, there is no need to modify the state of the third bit in the third adjustment signal, and the state of the fourth bit in the third adjustment signal is set to the state to be verified, so that the fourth adjustment signal is 10110000.

[0136] In some embodiments, if the adjustment result of the i-th adjustment signal is invalid, it indicates that the current position state selection of the i-th bit in the i-th adjustment signal is unreasonable. Since the current position state of the i-th bit is a state to be verified, the current position state of the i-th bit can be modified to the default state. For example, the value of the i-th bit in the i-th adjustment signal is modified from 1 to 0, and then the value of the (i+1)-th bit is determined to be 1, thus obtaining the (i+1)-th adjustment signal.

[0137] For example, suppose i is 3, the third adjustment signal is 10100000, and the adjustment result of the third adjustment signal is invalid. In this case, the bit state of the third bit in the third adjustment signal can be changed from the unverified state to the default state, and the bit state of the fourth bit in the third adjustment signal can be set to the unverified state, so that the fourth adjustment signal is 10010000.

[0138] S604. Determine whether i is greater than or equal to N.

[0139] If not, then execute S605;

[0140] If so, then execute S606.

[0141] S605, Update i to i+1, and execute S601.

[0142] If i is less than N, it means that the current calibration process has not yet reached the upper limit of the number of binary bits of the adjustment signal, and there are still untraversed binary bits that need to be verified for validity. In this case, i can be updated to i+1, and S601 can be executed again.

[0143] S606. The first MOSFET after the Nth adjustment is determined as the first target MOSFET, and the second MOSFET after the Nth adjustment is determined as the second target MOSFET.

[0144] If i is greater than or equal to N, it indicates that the current calibration process has reached the upper limit of the number of binary bits of the adjustment signal. At this point, the first MOSFET after the Nth adjustment can be determined as the first target MOSFET, and the second MOSFET after the Nth adjustment can be determined as the second target MOSFET.

[0145] exist Figure 6 In the illustrated embodiment, the equivalent size of the operational amplifier input differential pair MOSFETs is controlled through iterative adjustment logic based on successive approximation, combined with a parallel fine-tuning structure of a binary weighted MOSFET array. Furthermore, based on the adjustment result determination rule according to the current difference, the optimal MOSFET conduction combination can be efficiently selected, reducing the size mismatch of the differential pair transistors and decreasing the op-amp DC offset voltage.

[0146] The above embodiments describe a calibration method for the circuit provided in this application. Below, in conjunction with... Figure 7 and Figure 8 The calibration method for the circuit provided in the embodiments of this application will be further described.

[0147] Figure 7 This is a schematic diagram of a circuit provided in an embodiment of this application. (For example...) Figure 7 As shown, the calibration circuit includes a DAC, a first control module, an operational amplifier, a second control module, a pull-up network, a pull-down network, resistors, a PMOSFET, an LDMOS, and an LED. For descriptions of the DAC, operational amplifier, pull-up network, pull-down network, resistors, PMOSFET, LDMOS, and LED, please refer to [link to relevant documentation]. Figure 1 The illustrated embodiment will not be described in detail here. The first control module is the core control module of the operational amplifier calibration process, mainly responsible for the initiation of calibration logic, signal interaction, and status management. The second control module is the power stage control module of the LED constant current drive circuit, and is primarily responsible for ensuring the switching and current accuracy of the LDMOS.

[0148] Figure 8 This is a timing diagram for calibrating a circuit, provided as an embodiment of this application. For example... Figure 8 As shown, at time T1, the LED constant current drive circuit determines that the reset signal's reset level is high, triggering the circuit to perform a reset operation. At this time, both the calibration enable signal and the operating enable signal are at low levels, and the LED constant current drive circuit is in standby mode.

[0149] At time T2, the calibration enable signal is at a high level, and the LED constant current drive circuit initiates the calibration operation. At this time, the operational amplifier does not amplify the constant current; instead, it acts as an active comparator to determine the difference between the output current of the first MOSFET and the output current of the second MOSFET.

[0150] It should be noted that, in order to make the output of the active comparator of the operational amplifier more stable, the LED constant current drive circuit can wait for a period of time after the calibration enable signal is in a high-level state before performing the calibration operation.

[0151] Therefore, at time T3, the LED constant current drive circuit begins to perform circuit calibration operations, which continue until time T4. The method by which the LED constant current drive circuit begins to perform circuit calibration operations can be found in [link to documentation]. Figure 6 The embodiments shown will not be described in detail here.

[0152] At time T4, the LED constant current drive circuit finishes the calibration operation of the execution circuit, and the calibration enable signal returns to a low level. In some embodiments, after the LED constant current drive circuit finishes the calibration operation of the execution circuit, N adjustment signals can be sealed.

[0153] At time T5, the enable signal is at a high level, indicating that the LED constant current drive circuit has started to adjust the LED brightness. It should be noted that because the DC offset voltage in the LED constant current drive circuit is at its minimum at this time, the brightness adjustment accuracy is higher when adjusting the LED after time T5.

[0154] Figure 9 This is a schematic diagram of the structure of a circuit calibration device provided in an embodiment of this application. Figure 9 As shown, the circuit calibration device 90 includes: a first determining module 91, an adjusting module 92, and a second determining module 93, wherein,

[0155] The first determining module 91 is used to determine the reset level state of the reset signal. When the reset level state is high, the initial adjustment signal is determined. The reset signal is used to indicate whether to clear the circuit. The circuit includes an operational amplifier. The operational amplifier has a first MOSFET and a second MOSFET. The initial adjustment signal is represented in N-bit binary form, where N is a positive integer greater than 1.

[0156] The adjustment module 92 is used to adjust the size of the first MOSFET and the second MOSFET according to the initial adjustment signal to obtain the first target MOSFET and the second target MOSFET; wherein the difference between the size of the first target MOSFET and the size of the second target MOSFET is less than the difference between the size of the first MOSFET and the size of the second MOSFET.

[0157] The second determining module 93 is used to determine the calibrated circuit based on the dimensions of the first target MOSFET and the second target MOSFET.

[0158] In one possible implementation, the adjustment module 92 is specifically used for:

[0159] Perform a first operation, which includes: adjusting the size of the first MOSFET and the size of the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment; determining the adjustment result of the i-th adjustment signal according to the operational amplifier after the i-th adjustment, and generating the (i+1)-th adjustment signal based on the adjustment result of the i-th adjustment signal;

[0160] Repeat the first operation until i is greater than or equal to N, then determine the first MOSFET after the Nth adjustment as the first target MOSFET, and determine the second MOSFET after the Nth adjustment as the second target MOSFET;

[0161] Where i is a positive integer; when i=1, the first adjustment signal is the initial adjustment signal; the operational amplifier after the i-th adjustment includes the first MOSFET after the i-th adjustment and the second MOSFET after the i-th adjustment.

[0162] In one possible implementation, the first MOSFET is connected in parallel with M third MOSFETs, and the second MOSFET is connected in parallel with M fourth MOSFETs; wherein the M third MOSFETs and the M fourth MOSFETs are all binary weighted MOSFETs, and the binary weight of each third MOSFET is the same as the binary weight of each fourth MOSFET.

[0163] In one possible implementation, the adjustment module 92 is specifically used for:

[0164] Based on the i-th adjustment signal and M third MOSFETs, adjust the size of the first MOSFET to obtain the first MOSFET after the i-th adjustment;

[0165] Based on the i-th adjustment signal and M fourth MOSFETs, the size of the second MOSFET is adjusted to obtain the second MOSFET after the i-th adjustment.

[0166] In one possible implementation, the adjustment module 92 is specifically used for:

[0167] Based on the i-th adjustment signal, determine the state of each of the M third MOSFETs; wherein, the state of each third MOSFET is either on or off.

[0168] Based on the respective states of the M third MOSFETs, the size of the first MOSFET is adjusted to obtain the first MOSFET after the i-th adjustment; wherein, the size of the first MOSFET after the i-th adjustment is the sum of the inherent size of the first MOSFET and the inherent size of at least one fifth MOSFET; each fifth MOSFET is a MOSFET in the on state among the M third MOSFETs.

[0169] In one possible implementation, the adjustment module 92 is specifically used for:

[0170] The same voltage is applied to the first MOSFET and the second MOSFET after the i-th adjustment;

[0171] Input current into the operational amplifier after the i-th adjustment to determine the first output current and the second output current after the i-th adjustment; the first output current after the i-th adjustment is the output current of the first MOSFET after the i-th adjustment, and the second output current after the i-th adjustment is the output current of the second MOSFET after the i-th adjustment;

[0172] If the i-th current difference between the first output current after the i-th adjustment and the second output current after the i-th adjustment is less than the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be an effective adjustment.

[0173] If the i-th current difference is greater than or equal to the (i-1)-th current difference, the regulation result of the i-th regulation signal is determined to be invalid regulation.

[0174] In one possible implementation, the adjustment module 92 is specifically used for:

[0175] If the adjustment result of the i-th adjustment signal is effective, the binary state of the (i+1)-th bit in the i-th adjustment signal is determined as the state to be verified, and the (i+1)-th adjustment signal is obtained.

[0176] If the adjustment result of the i-th adjustment signal is invalid, the binary state of the i-th bit in the i-th adjustment signal is determined as the default state, and the binary state of the (i+1)-th bit is determined as the state to be verified, thus obtaining the (i+1)-th adjustment signal.

[0177] The circuit calibration device 90 provided in this application embodiment can execute the technical solution of the circuit calibration method in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0178] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 100 includes:

[0179] At least one processor 102; and

[0180] Memory 101 is communicatively connected to at least one processor 102; wherein,

[0181] The memory 101 stores instructions that can be executed by at least one processor 102, which, when executed by at least one processor 102, causes the at least one processor 102 to perform the calibration method of the circuit involved in the above method embodiment.

[0182] Optionally, the aforementioned processor can be a central processing unit (CPU), or it can be a GPU, other general-purpose processors, a digital signal processor (DSP), or an application-specific integrated circuit (ASIC), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0183] The electronic device 100 provided in this application embodiment can perform the calibration method of the circuit involved in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0184] This application provides a non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, which are used to cause a computer to execute the calibration method of the circuit involved in the above method embodiments.

[0185] This application provides a computer program product, including a computer program that, when executed by an electronic device, implements the circuit calibration method involved in the above method embodiments.

[0186] This application provides a chip, which includes at least one processor. The processor is used to run program instructions to perform the calibration method of the circuit involved in the above method embodiments.

[0187] This application provides a chip module on which a computer program is stored. When the computer program is executed by the chip module, it implements the circuit calibration method involved in the above method embodiments.

[0188] All or part of the steps in the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), RAM, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof.

[0189] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable terminal device to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0190] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable terminal device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0191] These computer program instructions can also be loaded onto a computer or other programmable terminal device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0192] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0193] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for calibrating a circuit, characterized in that, The method includes: The reset level state of the reset signal is determined. When the reset level state is high, an initial adjustment signal is determined. The reset signal is used to indicate whether to clear the circuit. The circuit includes an operational amplifier. A first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET are deployed in the operational amplifier. The initial adjustment signal is represented in N-bit binary form, where N is a positive integer greater than 1. According to the initial adjustment signal, the dimensions of the first MOSFET and the second MOSFET are adjusted to obtain a first target MOSFET and a second target MOSFET; wherein the difference between the dimensions of the first target MOSFET and the second target MOSFET is less than the difference between the dimensions of the first MOSFET and the second MOSFET. The calibrated circuit is determined based on the dimensions of the first target MOSFET and the second target MOSFET.

2. The method according to claim 1, characterized in that, The step of adjusting the dimensions of the first MOSFET and the second MOSFET according to the initial adjustment signal to obtain the first target MOSFET and the second target MOSFET includes: Perform a first operation, the first operation including: adjusting the size of the first MOSFET and the size of the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment; determining the adjustment result of the i-th adjustment signal according to the operational amplifier after the i-th adjustment, and generating the (i+1)-th adjustment signal based on the adjustment result of the i-th adjustment signal; Repeat the first operation until i is greater than or equal to N, then determine the first MOSFET after the Nth adjustment as the first target MOSFET, and determine the second MOSFET after the Nth adjustment as the second target MOSFET; Where i is a positive integer; when i=1, the first adjustment signal is the initial adjustment signal; the operational amplifier after the i-th adjustment includes the first MOSFET after the i-th adjustment and the second MOSFET after the i-th adjustment.

3. The method according to claim 2, characterized in that, The first MOSFET is connected in parallel with M third MOSFETs, and the second MOSFET is connected in parallel with M fourth MOSFETs; wherein the M third MOSFETs and the M fourth MOSFETs are all binary weighted MOSFETs, and the binary weight of each third MOSFET is the same as the binary weight of each fourth MOSFET.

4. The method according to claim 3, characterized in that, The step of adjusting the dimensions of the first MOSFET and the second MOSFET according to the i-th adjustment signal to obtain the first MOSFET and the second MOSFET after the i-th adjustment includes: Based on the i-th adjustment signal and the M third MOSFETs, the size of the first MOSFET is adjusted to obtain the first MOSFET after the i-th adjustment. Based on the i-th adjustment signal and the M fourth MOSFETs, the size of the second MOSFET is adjusted to obtain the second MOSFET after the i-th adjustment.

5. The method according to claim 4, characterized in that, The step of adjusting the size of the first MOSFET according to the i-th adjustment signal and the M third MOSFETs to obtain the first MOSFET after the i-th adjustment includes: Based on the i-th adjustment signal, the state of each of the M third MOSFETs is determined; wherein, the state of each third MOSFET is either on or off. Based on the respective states of the M third MOSFETs, the size of the first MOSFET is adjusted to obtain the first MOSFET after the i-th adjustment; wherein, the size of the first MOSFET after the i-th adjustment is the sum of the inherent size of the first MOSFET and the inherent size of at least one fifth MOSFET; each fifth MOSFET is a MOSFET among the M third MOSFETs that is in the on state.

6. The method according to claim 4 or 5, characterized in that, Determining the adjustment result of the i-th adjustment signal based on the operational amplifier after the i-th adjustment includes: The same voltage is applied to the first MOSFET and the second MOSFET after the i-th adjustment; Input a current into the operational amplifier after the i-th adjustment to determine the first output current and the second output current after the i-th adjustment; the first output current after the i-th adjustment is the output current of the first MOSFET after the i-th adjustment, and the second output current after the i-th adjustment is the output current of the second MOSFET after the i-th adjustment; If the i-th current difference between the first output current after the i-th adjustment and the second output current after the i-th adjustment is less than the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be an effective adjustment. If the i-th current difference is greater than or equal to the (i-1)-th current difference, the adjustment result of the i-th adjustment signal is determined to be invalid adjustment.

7. The method according to claim 6, characterized in that, The process of generating the (i+1)th adjustment signal based on the adjustment result of the i-th adjustment signal includes: If the adjustment result of the i-th adjustment signal is the effective adjustment, the binary bit state of the (i+1)-th bit in the i-th adjustment signal is determined as the state to be verified, and the (i+1)-th adjustment signal is obtained. If the adjustment result of the i-th adjustment signal is the invalid adjustment, the binary state of the i-th bit in the i-th adjustment signal is determined as the default state, and the binary state of the (i+1)-th bit is determined as the state to be verified, thus obtaining the (i+1)-th adjustment signal.

8. A circuit calibration device, characterized in that, The method includes: The first determining module is used to determine the reset level state of the reset signal, and when the reset level state is high, it determines the initial adjustment signal; the reset signal is used to indicate whether to clear the circuit; the circuit includes an operational amplifier; the operational amplifier has a first MOSFET and a second MOSFET deployed in it; the initial adjustment signal is represented in N-bit binary form, where N is a positive integer greater than 1. An adjustment module is configured to adjust the dimensions of the first MOSFET and the second MOSFET according to the initial adjustment signal to obtain a first target MOSFET and a second target MOSFET; wherein the difference between the dimensions of the first target MOSFET and the second target MOSFET is less than the difference between the dimensions of the first MOSFET and the second MOSFET. The second determining module is used to determine the calibrated circuit based on the dimensions of the first target MOSFET and the second target MOSFET.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to cause the at least one processor to perform the method of any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, in, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 7.

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