Solar cell and method of manufacturing the same
By printing and removing grid line protection patterns in solar cells, the linewidth of the polycrystalline silicon layer is narrowed, solving the problem of limited conversion efficiency in Poly Finger technology and improving cell efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TONGWEI SOLAR ENERGY (CHENGDU) CO LID
- Filing Date
- 2026-04-03
- Publication Date
- 2026-07-07
AI Technical Summary
Existing Poly Finger technology limits cell conversion efficiency in solar cells because it requires retaining a Poly layer to ensure the printing of screen grid lines, thus preventing further improvement.
By spraying a protective grid pattern onto the grid pattern, making its line width larger than the grid pattern, and combining it with an acid and alkali resistant material pattern, the pattern is then heated to peel off. Excess polycrystalline silicon material is then cleaned to remove it, forming a narrowed polycrystalline silicon layer.
It effectively reduces the linewidth of the polycrystalline silicon layer, compensates for printing accuracy deviation, and improves the conversion efficiency of solar cells.
Smart Images
Figure CN122349263A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for its fabrication. Background Technology
[0002] With the photovoltaic industry's continuous exploration of high-efficiency battery technology, tunnel oxide passivated contact (TOPCon) cells have gradually become one of the mainstream solar cells due to their high efficiency potential and relatively low process difficulty.
[0003] Currently, the introduction of Poly Finger (polycrystalline silicon finger electrode) technology, a key component in TOPCon battery structure optimization, has significantly improved battery conversion efficiency and mass production feasibility. Poly Finger technology specifically refers to a laser-modified process on the back of the battery that forms a poly layer below the metal grid lines, while other areas below the metal grid lines lack a poly layer, effectively reducing parasitic light absorption by the poly layer on the back of the battery.
[0004] However, Poly Finger technology requires a laser process to pattern the passivation material on the back after annealing, followed by cleaning to remove the modified areas of the passivation material and the corresponding Poly portions to ensure that the subsequent screen printing of the grid lines can be applied to the retained Poly. Therefore, the retained Poly needs to have sufficient linewidth, which is detrimental to further improving the battery's conversion efficiency. Summary of the Invention
[0005] Based on this, embodiments of this application provide a solar cell and a method for fabricating the same, which can effectively reduce the linewidth of the pattern in the polycrystalline silicon layer to further improve the conversion efficiency of the solar cell.
[0006] To achieve the above objectives, some embodiments of this application provide a method for preparing a solar cell, comprising:
[0007] A substrate is provided, and a polycrystalline silicon material layer and a first passivation material layer are stacked on at least one side of the substrate;
[0008] A grid pattern is printed onto the first passivation material layer;
[0009] Print a grid line protection pattern on the grid line pattern; the grid line protection pattern is the same as the grid line pattern, and the printing line width of a single protective pattern in the grid line protection pattern is greater than the printing line width of a single grid line in the grid line pattern.
[0010] Based on the gate line protection pattern, the first passivation material layer and the polysilicon material layer are patterned to form the first passivation layer and the polysilicon layer;
[0011] Remove the grid line protection pattern.
[0012] In some embodiments of this application, before removing the gate line protection pattern, the preparation method further includes forming a second passivation layer in the removal area of the first passivation material layer and the polysilicon material layer.
[0013] In some embodiments of this application, a single protective graphic in the grid line protection pattern covers the corresponding grid line in the grid line pattern. The printing linewidth of a single protective graphic in the grid line protection pattern is 20% to 30% of the spacing between two adjacent grid lines in the grid line pattern.
[0014] In some embodiments of this application, the printing thickness of the grid line protection pattern is 1 to 5 times the printing thickness of the grid line pattern.
[0015] In some embodiments of this application, the protective pattern in the grid protection pattern includes a pattern of acid and alkali resistant materials.
[0016] Accordingly, a grid line protection pattern is printed on the grid line pattern, including:
[0017] Acid and alkali resistant material solutions are sprayed onto each grid line of the grid pattern;
[0018] The acid and alkali resistant material solution is dried to form an acid and alkali resistant material pattern.
[0019] In some embodiments of this application, removing the grid line protection pattern includes: heating to a first temperature to soften and remove the acid and alkali resistant material pattern.
[0020] Accordingly, the method for fabricating a solar cell also includes: heating to a second temperature and sintering the resulting structure after removing the grid line protection pattern; wherein the second temperature is greater than the first temperature.
[0021] In some embodiments of this application, the acid and alkali resistant material pattern includes a polyimide pattern or a UV-curable adhesive pattern.
[0022] In some embodiments of this application, a first passivation material layer and a polysilicon material layer are patterned based on a gate line protection pattern to form a first passivation layer and a polysilicon layer, including:
[0023] The portion of the first passivation material layer not covered by the gate line protection pattern is cleaned and removed using hydrofluoric acid solution and / or hydrochloric acid solution to form the first passivation layer;
[0024] A sodium hydroxide solution is used to clean and remove the portion of the polycrystalline silicon material layer not covered by the first passivation layer, thus forming a polycrystalline silicon layer.
[0025] On the other hand, some embodiments of this application also provide a solar cell prepared using the fabrication method described in the above embodiments. This solar cell includes: a substrate; a polycrystalline silicon layer, a first passivation layer, and a grid pattern stacked on at least one side of the substrate; and a second passivation layer. The orthographic projection of the grid pattern onto the substrate lies within the orthographic projection of the polycrystalline silicon layer onto the substrate. The polycrystalline silicon layer and the first passivation layer have the same window pattern. The second passivation layer fills the window patterns of the polycrystalline silicon layer and the first passivation layer.
[0026] In some embodiments of this application, the gate pattern includes multiple gate lines. The polysilicon layer includes polysilicon finger electrodes disposed in a one-to-one correspondence with the gate lines. The linewidth of the polysilicon finger electrodes is 20% to 30% of the spacing between two adjacent gate lines in the gate pattern.
[0027] In some embodiments of this application, ...
[0028] The embodiments of this application may have, or at least have, the following advantages:
[0029] In this embodiment, after the polycrystalline silicon material layer and the first passivation material layer are stacked and the grid line pattern is printed, a grid line protection pattern is printed on the grid line pattern. The grid line protection pattern is identical to the grid line pattern, and the printing line width of a single protective pattern in the grid line protection pattern is greater than the printing line width of a single grid line in the grid line pattern. Under the protection of the grid line pattern, the excess width of polycrystalline silicon material in the polycrystalline silicon material layer is removed to the maximum extent, effectively narrowing the pattern line width in the polycrystalline silicon layer. This achieves the effect of increasing the proportion of width removed in the polycrystalline silicon material layer, thereby further improving the conversion efficiency of the solar cell while compensating for the grid line offset caused by printing accuracy.
[0030] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic flowchart of a method for fabricating a solar cell provided in some embodiments;
[0033] Figure 2 This is a schematic flowchart of another method for fabricating a solar cell provided in some embodiments;
[0034] Figure 3 This is a schematic flowchart illustrating yet another method for fabricating a solar cell provided in some embodiments;
[0035] Figure 4 This is a schematic flowchart of step S400 in a method for fabricating a solar cell provided in some embodiments;
[0036] Figure 5 This is a schematic cross-sectional view of a solar cell provided in some embodiments;
[0037] Figure 6 This is a schematic diagram illustrating the relative positions between grid lines and polycrystalline silicon finger electrodes in a solar cell provided in some embodiments.
[0038] Explanation of reference numerals in the attached figures:
[0039] 1-Substrate, 2-Polycrystalline silicon layer, 21-Polycrystalline silicon finger electrode, 3-First passivation layer, 4-Gate line pattern, 41-Gate line, 5-Second passivation layer, 6-Tunnel oxide layer, 7-P+ emitter, 8-Dielectric layer, 9-Third passivation layer. Detailed Implementation
[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0042] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various signals or spectra, these signals or spectra should not be limited by these terms. These terms are merely used to distinguish one signal or spectrum from another. Therefore, without departing from the teachings of this application, the first signal or spectrum discussed below may be referred to as the second signal or spectrum.
[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0044] Please see Figure 1 Some embodiments of this application provide a method for preparing a solar cell, including the following steps S100~S600.
[0045] S100 provides a substrate, on which a polycrystalline silicon material layer and a first passivation material layer are stacked at least on one side.
[0046] S200, a grid pattern is printed on the first passivation material layer.
[0047] The term "printing" as used herein and herein includes any patterning process capable of directly forming a thin film pattern, such as spraying, printing, or coating. This application does not limit this to specific examples.
[0048] S300, printing a grid line protection pattern on the grid line pattern; the grid line protection pattern is the same as the grid line pattern, and the printing line width of a single protective pattern in the grid line protection pattern is greater than the printing line width of a single grid line in the grid line pattern.
[0049] S400, based on the gate line protection pattern, patterns a first passivation material layer and a polysilicon material layer to form a first passivation layer and a polysilicon layer.
[0050] S600, remove the grid line protection pattern.
[0051] In this embodiment, after the polycrystalline silicon material layer and the first passivation material layer are stacked and the grid line pattern is printed, a grid line protection pattern is printed on the grid line pattern. The grid line protection pattern is identical to the grid line pattern, and the printing line width of a single protective pattern in the grid line protection pattern is greater than the printing line width of a single grid line in the grid line pattern. Under the protection of the grid line pattern, the excess width of polycrystalline silicon material in the polycrystalline silicon material layer is removed to the maximum extent, effectively narrowing the pattern line width in the polycrystalline silicon layer. This achieves the effect of increasing the proportion of width removed in the polycrystalline silicon material layer, thereby further improving the conversion efficiency of the solar cell while compensating for the grid line offset caused by printing accuracy.
[0052] Please see Figure 2In some embodiments of this application, before performing step S500 to remove the gate line protection pattern, the preparation method further includes the following step S500.
[0053] S500, a second passivation layer is formed in the removal region of the first passivation material layer and the polysilicon material layer.
[0054] In some embodiments of this application, a single protective graphic in the grid line protection pattern covers the corresponding grid line in the grid line pattern, that is, the protective graphic can at least cover the surface and sidewalls of the corresponding grid line.
[0055] Optionally, the printing line width of a single protective graphic in the grid line protection pattern is 20% to 30% of the spacing between two adjacent grid lines in the grid line pattern, for example, it can be 20%, 22%, 25%, 28% or 30%.
[0056] In some examples, the printed line width of a single protective graphic in the grid protection pattern is 25% of the spacing between two adjacent grid lines in the grid protection pattern.
[0057] In some embodiments of this application, the printing thickness of the grid line protection pattern is 1 to 5 times the printing thickness of the grid line pattern, for example, it can be 1, 2, 3, 4, or 5 times. This not only avoids the situation where the printing thickness of the grid line protection pattern is too thin, making it difficult to ensure that the protective pattern in the grid line protection pattern completely covers the corresponding grid lines, but also avoids the problem of increasing the overall thickness of the solar cell due to the printing thickness of the grid line protection pattern being too thick, thus preventing increased costs and difficulties in removing the grid line protection pattern.
[0058] For example, the printing thickness of the grid line pattern ranges from 10 μm to 20 μm. Correspondingly, the printing thickness of the grid line protection pattern ranges from 20 μm to 50 μm.
[0059] In some examples, the printing thickness of the grid line protection pattern is 30 μm.
[0060] In some embodiments of this application, the protective pattern in the grid protection pattern includes a pattern of acid and alkali resistant material, such as a polyimide (PI) pattern or a UV-curable adhesive pattern.
[0061] Accordingly, please refer to Figure 3 Step S300, which involves printing a grid line protective pattern on the grid line pattern, includes the following steps S310 and S320.
[0062] S310, acid and alkali resistant material solution is sprayed onto each grid line of the grid pattern.
[0063] S320, drying the acid and alkali resistant material solution to form an acid and alkali resistant material pattern.
[0064] In some examples, the drying process of the acid and alkali resistant material solution in step S320 is an over-drying process, that is, the drying temperature can be kept too high or the drying time can be kept too long so that the acid and alkali resistant material solution is over-dried into an acid and alkali resistant material pattern.
[0065] Optionally, the acid and alkali resistant material solution is a polyamic acid solution. Accordingly, the polyamic acid solution is over-dried at a drying temperature of 350°C to thermally imidize the polyamic acid, thereby obtaining an acid and alkali resistant polyimide (PI) pattern. Furthermore, the polyimide (PI) pattern can withstand temperatures up to 500°C to 600°C.
[0066] In some examples, the front side of the substrate has a velvety texture. A grid pattern is formed on the back side of the substrate.
[0067] Optionally, before performing step S310, which involves spraying polyamic acid solution onto each grid line of the grid pattern, the method for preparing a solar cell further includes: after spraying grid patterns onto both the front and back sides of the substrate and drying them, coating the entire front side of the substrate or a selected area with polyamic acid solution.
[0068] Alternatively, the polyamic acid solution can also be selectively coated onto one or more sides of the substrate.
[0069] Please refer to some embodiments of this application. Figure 3 Step S600, removing the grid line protective pattern, includes heating to a first temperature to soften and remove the acid and alkali resistant material pattern. Correspondingly, the method for fabricating a solar cell also includes step S700.
[0070] S700, heated to the second temperature, sintering the resulting structure after removing the grid line protection pattern.
[0071] For example, the second temperature is greater than the first temperature.
[0072] In some examples, the first temperature includes, but is not limited to, 650°C ± 50°C.
[0073] In some examples, the second temperature ranges from 750°C to 820°C, for example, it can be 750°C, 760°C, 780°C, 790°C, 795°C, 800°C, 810°C or 820°C.
[0074] In some examples, the second temperature is 795°C.
[0075] Please refer to some embodiments of this application. Figure 3 In step S400, based on the gate line protection pattern, the first passivation material layer and the polysilicon material layer are patterned to form the first passivation layer and the polysilicon layer, including the following steps S420 and S440.
[0076] S420 uses hydrofluoric acid solution and / or hydrochloric acid solution to clean and remove the portion of the first passivation material layer not covered by the gate line protection pattern, forming the first passivation layer.
[0077] S440 uses a sodium hydroxide solution to clean and remove the portion of the polycrystalline silicon material layer not covered by the first passivation layer, forming a polycrystalline silicon layer.
[0078] Optionally, the cleaning process in steps S420 and S440 is carried out using a tank-type equipment.
[0079] In some examples, please refer to Figure 4 In step S400, based on the gate line protection pattern, the first passivation material layer and the polysilicon material layer are patterned to form the first passivation layer and the polysilicon layer, which can be performed according to the following steps S410~S480.
[0080] S410, the resulting structure after forming the grid line protection pattern is first washed with water to clean the surface particles of the resulting structure.
[0081] Optionally, the first wash may last for up to 120 seconds.
[0082] Optionally, the washing temperature for the first water wash may include, but is not limited to, room temperature (RT), for example, 15°C to 25°C.
[0083] Optionally, the cleaning solution for the first water rinse is deionized (DI) water to clean the surface of the resulting structure.
[0084] S420 uses hydrofluoric acid solution and / or hydrochloric acid solution to clean and remove the portion of the first passivation material layer not covered by the gate line protection pattern, forming the first passivation layer.
[0085] Optionally, the first passivation material layer includes, but is not limited to, a silicon nitride material layer.
[0086] Optionally, the cleaning time of the first passivation material layer includes, but is not limited to, 2000s ± 200s.
[0087] Optionally, the cleaning temperature of the first passivation material layer includes, but is not limited to, room temperature.
[0088] Optionally, when cleaning and removing the portion of the first passivation material layer not covered by the gate line protection pattern using a hydrofluoric acid solution, the concentration of hydrofluoric acid in the hydrofluoric acid solution is not limited to 20% to 60%, and the volume ratio of hydrofluoric acid in the hydrofluoric acid solution is not limited to 50%.
[0089] Optionally, when using hydrochloric acid solution to clean and remove the portion of the first passivation material layer not covered by the gate line protection pattern, the concentration of hydrochloric acid in the hydrochloric acid solution is not limited to 5% to 10%, and the volume ratio of hydrochloric acid in the hydrochloric acid solution is not limited to 8%.
[0090] S430, the structure obtained after the formation of the first passivation layer is subjected to a second water wash.
[0091] Optionally, the second wash may last for up to 120 seconds.
[0092] Optionally, the washing temperature for the second wash may include, but is not limited to, room temperature.
[0093] Optionally, the cleaning solution for the second water rinse is deionized (DI) water, to clean the resulting structure surface and dilute the chemicals.
[0094] S440 uses a sodium hydroxide solution to clean and remove the portion of the polycrystalline silicon material layer not covered by the first passivation layer, forming a polycrystalline silicon layer.
[0095] Optionally, when using a sodium hydroxide solution to clean and remove the portions of the polycrystalline silicon material layer not covered by the first passivation layer, the concentration of sodium hydroxide in the solution is, but not limited to, 2% to 5%, and the volume ratio of sodium hydroxide in the solution is, but not limited to, 3.3%. Alternatively, when cleaning and removing the portions of the polycrystalline silicon material layer not covered by the first passivation layer, a diluted sodium hydroxide solution can also be used, for example, the concentration of sodium hydroxide in the diluted solution is, but not limited to, 0.5% to 2%, and the volume ratio of sodium hydroxide in the diluted solution is, but not limited to, 0.7%.
[0096] S450, the structure obtained after the formation of the polycrystalline silicon layer is subjected to a third water wash.
[0097] Optionally, the third wash may last for up to 120 seconds.
[0098] Optionally, the washing temperature for the third wash may include, but is not limited to, room temperature.
[0099] Optionally, the cleaning solution for the third rinse is deionized (DI) water to clean the resulting structure surface and dilute the chemicals.
[0100] S460 uses hydrofluoric acid solution to clean the structure obtained after forming a polycrystalline silicon layer and performing a third water wash to remove the surface silicon oxide of the obtained structure and dehydrate the obtained structure.
[0101] Optionally, the cleaning time with hydrofluoric acid solution may include, but is not limited to, 150 seconds.
[0102] Optionally, the concentration of hydrofluoric acid in the hydrofluoric acid solution is, but not limited to, 2% to 6%, and the volume ratio of hydrofluoric acid in the hydrofluoric acid solution is, but not limited to, 3%.
[0103] S470, the structure obtained after cleaning with hydrofluoric acid solution is subjected to a fourth water wash.
[0104] Optionally, the fourth wash may last for up to 120 seconds.
[0105] Optionally, the fourth wash may be performed at a temperature including but not limited to room temperature.
[0106] Optionally, the cleaning solution for the fourth rinse is deionized (DI) water to clean the resulting structure surface and dilute the chemicals.
[0107] S480, the structure obtained after drying and the fourth water wash.
[0108] Optionally, step S480 includes, but is not limited to, steps S481 and S482.
[0109] S481 uses deionized water and performs a slow hot water lift for 60 seconds on the structure obtained after the fourth water wash at a process temperature of 65°C to reduce residual water on the surface of the obtained structure.
[0110] S482, the structure obtained after hot water slow lifting is dried at a process temperature of 95°C for a drying time including but not limited to 900s.
[0111] Therefore, after forming the second passivation layer, removing the grid line protection pattern, and sintering the obtained structure, the method for fabricating solar cells may also include: injecting light into the solar cell, performing laser-enhanced contact optimization (LECO) process, and conducting sorting tests.
[0112] Some embodiments of this application also provide a solar cell, which can be prepared using the preparation methods described in the above embodiments. This solar cell also possesses all the technical advantages of the aforementioned solar cell preparation methods. Furthermore, the technical solutions involved in this solar cell can be understood in conjunction with the relevant content in the aforementioned solar cell preparation methods, and will not be detailed here.
[0113] Please see Figure 5The solar cell includes: a substrate 1; a polycrystalline silicon layer 2, a first passivation layer 3, and a grid pattern 4 stacked on at least one side of the substrate 1; and a second passivation layer 5. The orthographic projection of the grid pattern 4 onto the substrate 1 lies within the orthographic projection of the polycrystalline silicon layer 2 onto the substrate 1. The polycrystalline silicon layer 2 and the first passivation layer 3 have the same window pattern. The second passivation layer 5 fills the window patterns of the polycrystalline silicon layer 2 and the first passivation layer 3.
[0114] It should be added that the solar cells provided in the embodiments of this application can be tunnel oxide passivated contact (TOPCon) cells or back contact cells (BC cells). Figure 5 The example provided uses TOPCon solar cells as a case study.
[0115] In some embodiments of this application, please refer to Figure 5 and Figure 6 It is understood that the gate pattern 4 includes multiple gate lines 41. The polysilicon layer 2 includes polysilicon finger electrodes 21 that are disposed one-to-one with the gate lines 41. The linewidth D1 of the gate line 41 in the gate pattern 4 is smaller than the linewidth D2 of the corresponding polysilicon finger electrode 21, and the orthographic projection of each gate line 41 in the gate pattern 4 onto the substrate 1 lies within the orthographic projection of the corresponding polysilicon finger electrode 21 onto the substrate 1.
[0116] Optionally, the linewidth D2 of the polysilicon finger electrode 21 is 20% to 30% of the spacing D3 between two adjacent gate lines 41 in the gate pattern 4, for example, it can be 20%, 22%, 25%, 28% or 30%.
[0117] In some examples, the linewidth D2 of the polysilicon finger electrode 21 is 25% of the spacing D3 between two adjacent gate lines 41 in the gate pattern 4.
[0118] For example, the linewidth D1 of the gate line 41 ranges from 0.03 mm to 0.06 mm. The spacing D3 between any two adjacent gate lines 41 is 1.88 mm, and the linewidth D2 of the polysilicon finger electrode 21 is 0.47 mm.
[0119] It should be noted that, in some examples, please refer to [link / reference needed]. Figure 5 The substrate 1 includes, but is not limited to, a monocrystalline silicon substrate, such as an N-type monocrystalline silicon substrate.
[0120] In some examples, please refer to [link / reference]. Figure 5 The solar cell also includes a tunnel oxide layer 6 located between the substrate 1 and the polycrystalline silicon layer 2. The tunnel oxide layer 6 includes, but is not limited to, a silicon oxide layer.
[0121] In some examples, please refer to [link / reference]. Figure 5 The first passivation layer 3 includes, but is not limited to, a nitride layer, such as a silicon nitride layer.
[0122] In some examples, please refer to [link / reference]. Figure 5 The second passivation layer 5 can be a single-layer structure or a stacked structure.
[0123] Optionally, the second passivation layer 5 includes, but is not limited to, a stacked structure formed by sequentially stacking an aluminum oxide layer and a silicon nitride layer.
[0124] In some examples, please refer to [link / reference]. Figure 5 The oxide layer 6 and the polycrystalline silicon layer 2 are located on the back side of the substrate 1. The solar cell also includes a dielectric layer 8 and a third passivation layer 9 located on the front side of the substrate 1.
[0125] In some examples, please refer to [link / reference]. Figure 5 The front side of the substrate 1 has a textured structure, which forms a P+ emitter 7 through boron diffusion.
[0126] Optionally, the suede structure is a pyramid suede structure.
[0127] Optionally, dielectric layer 8 includes, but is not limited to, an aluminum oxide (AlOX) layer.
[0128] Optionally, the third passivation layer 9 includes, but is not limited to, a silicon nitride (SiNX) layer.
[0129] Furthermore, it can be understood that when the solar cell is a BC cell, the pattern of the polycrystalline silicon layer 2 can also be adapted to match the cross-finger distribution pattern of the BC cell.
[0130] In summary, the core principle of the solar cell and its fabrication method provided in this application is to first print and form grid lines 41, and then use an acid and alkali resistant material solution to coat and protect the grid lines 41 to perform reverse etching to form a polycrystalline silicon layer 2. This ensures that the pattern linewidth in the polycrystalline silicon layer 2 can be narrowed to the maximum extent. For example, the removal linewidth of the polycrystalline silicon layer 2 can be further increased from 50% to 70%~80% of the spacing between adjacent grid lines, thus having outstanding effects. This ensures the relative position of the grid lines and subsequent processes on the substrate 1, and helps to fundamentally solve a series of technical difficulties in the process, such as grid line printing offset, alignment, cleaning accuracy, and cleaning hygiene.
[0131] Compared to the conventional process flow of traditional solar cells: texturing → boron diffusion → alkaline polishing → POLY (polycrystalline silicon material layer) → annealing → polyfinger laser (laser-modified passivation material) → RCA → ALD → back film → positive film → screen printing → sintering → sorting, the process flow of the solar cell in this embodiment is: texturing → boron diffusion → alkaline polishing → POLY (polycrystalline silicon material layer) → annealing → RCA → ALD → back film → positive film → screen printing → coating and curing (forming gate protection pattern) → cleaning → secondary back film (forming second passivation layer) → sintering → sorting.
[0132] Using conventional solar cells prepared by the aforementioned conventional process as the baseline group, and solar cells prepared by the aforementioned grid reverse etching process as the experimental group in this application embodiment, the comparative data obtained are shown in the table below:
[0133]
[0134] As can be seen, compared with traditional solar cells, the solar cell provided in this application embodiment can achieve a current gain of 30mA in terms of short-circuit current and an efficiency gain of 0.05% in terms of photoelectric conversion efficiency.
[0135] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0136] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.
Claims
1. A method for preparing a solar cell, characterized in that, Comprising: Providing a substrate, and laminating a polysilicon material layer and a first passivation material layer on at least one side of the substrate; Printing a grid line pattern on the first passivation material layer; Printing a grid line protection pattern on the grid line pattern; the grid line protection pattern has the same pattern as the grid line pattern, and the printing line width of a single protection pattern in the grid line protection pattern is greater than the printing line width of a single grid line in the grid line pattern; Based on the grid line protection pattern, patterning the first passivation material layer and the polysilicon material layer to form a first passivation layer and a polysilicon layer; Removing the grid line protection pattern.
2. The method for preparing a solar cell according to claim 1, characterized in that, Before removing the grid line protection pattern, the preparation method further includes: Forming a second passivation layer in the removal area of the first passivation material layer and the polysilicon material layer.
3. The preparation method of the solar cell according to claim 1, wherein A single protection pattern in the grid line protection pattern covers the corresponding grid line in the grid line pattern; The printing line width of a single protection pattern in the grid line protection pattern is 20% - 30% of the distance between two adjacent grid lines in the grid line pattern.
4. The method for preparing a solar cell according to claim 1, characterized in that, The printing thickness of the grid line protection pattern is 1 - 5 times the printing thickness of the grid line pattern.
5. The method for preparing a solar cell according to claim 1, characterized in that, The protection pattern in the grid line protection pattern includes an acid and alkali resistant material pattern; wherein, printing the grid line protection pattern on the grid line pattern includes: Respectively printing an acid and alkali resistant material solution on each grid line of the grid line pattern; Drying the acid and alkali resistant material solution to form the acid and alkali resistant material pattern.
6. The preparation method of the solar cell according to claim 5, wherein Removing the grid line protection pattern includes: heating to a first temperature to soften and shed the acid and alkali resistant material pattern; The preparation method further includes: heating to a second temperature to sinter the obtained structure after removing the grid line protection pattern; wherein the second temperature is greater than the first temperature.
7. The method for preparing a solar cell according to claim 5, characterized in that, The acid and alkali resistant material pattern includes a polyimide pattern or an ultraviolet curable glue pattern.
8. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, Based on the grid line protection pattern, patterning the first passivation material layer and the polysilicon material layer to form a first passivation layer and a polysilicon layer includes: Using a hydrofluoric acid solution and / or a hydrochloric acid solution to clean and remove the part of the first passivation material layer not covered by the grid line protection pattern to form the first passivation layer; Using a sodium hydroxide solution to clean and remove the part of the polysilicon material layer not covered by the first passivation layer to form the polysilicon layer.
9. A solar cell, characterized in that, Comprising: A substrate; A polysilicon layer, a first passivation layer, and a grid line pattern laminated on at least one side of the substrate; the orthographic projection of the grid line pattern on the substrate is located within the orthographic projection of the polysilicon layer on the substrate; The polysilicon layer and the first passivation layer have the same window pattern; A second passivation layer filled in the window pattern of the polysilicon layer and the first passivation layer.
10. The solar cell according to claim 9, characterized in that, The grid line pattern includes a plurality of grid lines; The polysilicon layer includes polysilicon finger electrodes arranged corresponding to the grid lines one by one; Wherein, the line width of the polysilicon finger electrode is 20% - 30% of the distance between two adjacent grid lines in the grid line pattern.