Wafer dicing method

Abstract

A wafer dividing method includes: a step (S1) of forming a first dividing groove on at least one main surface of a wafer composed of a semiconductor having a crystal structure of a cubic system in a manner extending along a first non-dicing plane of the crystal structure; a step (S2) of forming an amorphous insulating layer on an inner peripheral surface of the first dividing groove; a step (S3) of supporting portions of the other main surface of the wafer located on both sides of the first dividing groove; and a step (S4) of pressing a tip portion of a cutting blade against the first dividing groove, thereby dividing the wafer in a fractured manner.

Description

Technical Field

[0001] This invention relates to a wafer dicing method. Background Technology

[0002] Semiconductor chips (hereinafter sometimes simply referred to as "chips") are manufactured by forming lattice-like sizing grooves between chip regions (regions that are formed into chips by dividing the wafer) that are formed in a matrix on a wafer, thereby separating the chip regions from each other at the sizing grooves. Thus, as a method for dividing the wafer at the sizing grooves to manufacture chips, for example, a roller sizing method is known to divide the wafer by pressing it with rollers (see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2002-124489

[0004] However, in the roll dicing method, a good dicing surface can be obtained if the wafer is diced along the cleavage plane, but a good dicing surface cannot be obtained if the wafer is diced along a non-cleavage plane. On the other hand, since the chip is manufactured by dividing chip regions formed in a matrix shape into dicing grooves formed in a lattice shape between these chip regions, if a dicing groove in one direction is formed along the cleavage plane, a dicing groove in the other direction must be formed along a non-cleavage plane. Therefore, there is a problem that a good dicing surface cannot be obtained at the dicing groove in the other direction. Summary of the Invention

[0005] The present invention was made to solve the problems mentioned above, and its object is to provide a wafer dicing method that can obtain good dicing surfaces in a wafer formed in a matrix shape in the chip region.

[0006] To achieve the above objectives, one aspect of the wafer dicing method disclosed herein includes: step (A), forming a first dicing groove on at least one main surface of a wafer composed of a semiconductor having a cubic crystal structure and having a semiconductor element formed thereon, extending along a first non-cleavage plane of the crystal structure; step (B), forming an amorphous insulating layer on the inner circumferential surface of the first dicing groove over the entire length of the first dicing groove; step (C), supporting portions of the other main surface of the wafer located on both sides of the first dicing groove; and step (D), pressing the tip of a cutting blade having a straight blade tip against the first dicing groove such that the tip tip extends overlapping with the first dicing groove when viewed from the pressing direction of the blade tip, thereby dicing the wafer in a cracking manner, wherein the straight blade tip is a length greater than or equal to the length of the first dicing groove.

[0007] The present invention achieves the following effect: it can obtain a good sizing surface in a wafer in which the chip area is divided into a matrix by grid-like sizing grooves. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating an example of a wafer dicing method according to Embodiment 1 of this disclosure.

[0009] Figure 2 This is a schematic diagram illustrating the process of forming the first dividing groove on a wafer formed in a matrix shape in the chip region.

[0010] Figure 3 This is a cross-sectional view showing the process of forming the first dividing groove on the two main surfaces of the wafer.

[0011] Figure 4 This is a cross-sectional view showing the process of forming an insulating layer in the first dividing groove.

[0012] Figure 5 This is a cross-sectional view showing the process of forming a dicing groove at the first dividing groove on the other side of the main surface of the wafer.

[0013] Figure 6 This is a cross-sectional view showing the process of supporting the portion on both sides of the first dividing groove on one side of the main surface of the wafer, and the process of dividing the wafer using a cutting blade.

[0014] Figure 7 It is shown in Figure 6 A schematic diagram of the cutting blade being pressed obliquely against the first dividing groove in the process.

[0015] Figure 8 It is shown Figure 6 A schematic diagram illustrating the mechanism of using a cutting blade to divide a wafer.

[0016] Figure 9A This is a photograph showing the state of the segmented surface obtained through the embodiment of implementation method 1.

[0017] Figure 9B yes Figure 9A A simplified sketch of the photograph.

[0018] Figure 10A This is a photograph showing the state of the segmented surface obtained through Comparative Example 1.

[0019] Figure 10B yes Figure 10A A simplified sketch of the photograph.

[0020] Figure 11A It is a diagram that schematically illustrates the situation of "neatly divided planes" when viewed from the side.

[0021] Figure 11B This diagram schematically illustrates the situation where "a segmented surface with longitudinal striped marks appears" when viewed from the side.

[0022] Figure 12 This is a cross-sectional view showing the process of dividing a wafer using a roller dicing method.

[0023] Figure 13A This is a photograph showing the state of the segmented surface obtained through Comparative Example 2.

[0024] Figure 13B yes Figure 13A A simplified sketch of the photograph.

[0025] Figure 14A This is a photograph showing the state of the segmented surface obtained through Comparative Example 3.

[0026] Figure 14B yes Figure 14A A simplified sketch of the photograph.

[0027] Figure 15 This is a cross-sectional view showing wafer dicing using a cutting blade with a 45-degree blade tip angle.

[0028] Figure 16A This is a photograph showing the state of the cut surface when a cutting blade with a 45-degree blade tip angle is used to cut along a non-cleavage surface.

[0029] Figure 16B yes Figure 16A A simplified sketch of the photograph.

[0030] Figure 17 This is a cross-sectional view showing wafer dicing using a cutting blade with a 90-degree blade tip angle.

[0031] Figure 18A This is a photograph showing the state of the cut surface when a cutting blade with a 90-degree blade tip angle is used to cut along a non-cleavage surface.

[0032] Figure 18B yes Figure 18A A simplified sketch of the photograph.

[0033] Figure 19 This is a cross-sectional view showing wafer dicing using a cutting blade with a 150-degree blade tip angle.

[0034] Figure 20A This is a photograph showing the state of the cut surface when a cutting blade with a 150-degree blade tip angle is used to cut along a non-cleavage surface.

[0035] Figure 20B yes Figure 20AA simplified sketch of the photograph.

[0036] Figure 21 This is a schematic diagram illustrating the process of forming a first dividing groove and a second dividing groove on a wafer formed in a matrix shape in the wafer dicing method of Embodiment 2 of this disclosure.

[0037] Figure 22 It is a cross-sectional view showing the process of forming the second dividing groove on the two main surfaces of the wafer.

[0038] Figure 23 This is a cross-sectional view showing the wafer dicing method according to Embodiment 3 of this disclosure, in which a cutting blade is used to dice the wafer.

[0039] Label Explanation

[0040] 1: Wafer; 1a: Main surface of one side; 1b: Main surface of the other side; 2: Chip area; 3: First dividing groove; 3A: First dividing groove of one side; 3B: First dividing groove of the other side; 4A, 4B: Insulating layer; 5: First dicing groove; 6: Support component; 7: Cutting blade; 7a: Blade tip; 8: Pressing direction; 10: Breakage at the tip; 11 13: Arrow; 21: Second dividing groove; 21A: Second dividing groove of one side; 21B: Second dividing groove of the other side; 22A, 22B: Insulating layer; 23: Second cutting groove; 31, 32: Dividing surface. Detailed Implementation

[0041] (Insights that led to this invention)

[0042] In order to solve the problem of the present invention, the inventors have conducted in-depth research and have obtained the following insights in the process.

[0043] The inventors attempted to cleave a wafer using a flat cutting tool. Specifically, first, a grid-like cleaving groove was formed on a wafer that was etched into a matrix pattern in the chip region. An insulating layer made of glass was formed on the inner circumferential surface of this cleaving groove along its entire length. Then, the wafer was cleaved along the cleaving grooves on its cleaving surface using a cutting tool. During cleaving, the two sides of the cleaving grooves on the wafer were supported relative to the pressure of the cutting tool. As a result, multiple longitudinal striations appeared on the cleaved surface of the wafer, making it impossible to obtain a neat cleaved surface (see reference). Figure 10A and Figure 10B Next, the wafer is cleaved along its non-cleavage plane using a cutting tool. The result is a neat (flat) cleavage surface (see reference). Figure 9A and Figure 9BThis is the exact opposite result of the roller-based segmentation method, and it was an unexpected discovery. Furthermore, the definition of "neat segmentation surface" will be described later.

[0044] The mechanism of using a cutting blade to divide a wafer is deduced as follows: The insulating layer, made of glass, is amorphous and has low toughness and strength. Therefore, when the tip of the cutting blade presses against the insulating layer at the bottom of the dicing groove, the insulating layer and the wafer flex together and break at the point of contact with the cutting blade tip. This breakage extends linearly along its direction of extension in the dicing groove as the cutting blade tip advances. Thus, the wafer is pulled and broken in a linear fashion by the extension of the broken insulating layer. The insulating layer breaks neatly (flatly), therefore the dicing groove is also pulled and broken neatly (flatly). Here, it is important that the cutting blade does not "cut" the wafer, but rather "breaks" it. Therefore, when the wafer is pulled by the neatly broken glass, the wafer also breaks neatly.

[0045] Additionally, when dicing wafers, ideally, the tip of the cutting blade should be pressed against the insulating layer located at the bottom of the dicing groove (see reference). Figure 15 and Figure 17 However, as inferred from the mechanism of this dicing, when dicing a wafer, even if only the tip of the cutting blade is pressed against the edge of the dicing groove (the upper end of the insulating layer) (see reference...). Figure 19 (If the cutting edge does not touch the insulating layer at the bottom of the dicing groove), the insulating layer will also bend along with the wafer, breaking cleanly along the edge of the dicing groove in the center, thus causing the wafer to break cleanly (see reference). Figure 20A and Figure 20B ).

[0046] The present invention was conceived based on the following insight. Therefore, one aspect of the wafer dicing method disclosed herein includes: step (A), forming a first dicing groove on at least one main surface of a wafer composed of a semiconductor having a cubic crystal structure, having a semiconductor element formed thereon, extending along a first non-cleavage plane of the crystal structure; step (B), forming an amorphous insulating layer on the inner circumferential surface of the first dicing groove over its entire length; step (C), supporting portions of the other main surface of the wafer located on either side of the first dicing groove; and step (D), pressing the tip of a cutting blade having a straight blade tip against the first dicing groove such that, when viewed from the pressing direction of the blade tip, the blade tip extends overlapping with the first dicing groove, thereby dicing the wafer in a cracking manner, the straight blade tip being a length exceeding the length of the first dicing groove.

[0047] According to this structure, since the insulating layer is amorphous and has low toughness, when the tip of the cutting tool presses against the first dicing groove, the insulating layer and the wafer flex together and break at the center. Because the tip of the cutting tool extends overlapping with the first dicing groove when viewed from the pressing direction of the tip, the fracture extends linearly along its extension direction within the first dicing groove as the cutting tool tip advances. Thus, the wafer is pulled and fractured linearly by the extension of the fractured insulating layer. In this case, even if the wafer is a semiconductor with a cubic crystal structure and the first dicing groove extends along the first non-cleavage plane, the wafer will fracture neatly (flatly). Therefore, according to this structure, even if the dicing groove is formed along the non-cleavage plane of the wafer, a neat dicing surface can be obtained, thus enabling the acquisition of a good dicing surface in wafers formed in a matrix pattern in the chip region.

[0048] Alternatively, in step (D), the tip of the cutting blade is pressed against one end of the first dividing groove in a state where the tip is inclined relative to the first dividing groove in the extension direction of the first dividing groove.

[0049] According to this structure, when the tip of the cutting blade is pressed against one end of the first dicing groove, the insulating layer at that end flexes and breaks along with the wafer. This breakage extends from one end of the first dicing groove towards the other as the cutting blade tip advances. The wafer is pulled apart from one end of the first dicing groove towards the other by the progression of the insulation layer's breakage. As a result, the insulating layer and the wafer are separated in a proper and neat manner.

[0050] Alternatively, in step (A), a first dividing groove, serving as one of the first dividing grooves, is formed on one of the main surfaces of the wafer, and a first dividing groove of the other side is formed on the other main surface of the wafer in a back-to-back manner with the first dividing groove of the first side; in step (B), an insulating layer is formed on the inner circumferential surfaces of the first dividing groove of the first side and the first dividing groove of the other side over their respective full lengths; and in step (C), a first dividing groove is formed at the bottom of the inner circumferential surface of the first dividing groove of the other side. A first cutting groove is formed by dividing the insulating layer of the first dividing groove of the other party in the width direction of the first dividing groove of the other party, and the first cutting groove extends along the extension direction of the first dividing groove of the other party. Then, the portions on both sides of the first dividing groove of the other party's main surface are supported. In the process (D), the tip of the cutting blade is pressed against the first dividing groove of the other party in such a way that the tip extends overlapping with the first dividing groove of the other party when viewed from the pressing direction of the tip, thereby dividing the wafer in a fracture manner.

[0051] According to this structure, first dicing grooves are formed on both main surfaces of the wafer. Therefore, compared to the case where the first dicing groove is formed only on one main surface of the wafer, it is easier to dice the wafer and thicker wafers can be diced. Furthermore, the insulating layer of the first dicing groove on the back side of one first dicing groove is separated by the first dicing groove. Therefore, when the tip of the cutting blade presses against one first dicing groove and the insulating layer breaks, the wafer is not affected by the insulating layer of the other first dicing groove; it is only broken by the pull of the broken insulating layer of that one first dicing groove. As a result, thicker wafers can be diced more easily by fracture.

[0052] Alternatively, in step (A), a plurality of first cleaving grooves are formed on at least one main surface of the wafer, extending along the first non-cleavage plane, and a plurality of second cleaving grooves are formed, extending along a second non-cleavage plane orthogonal to the first non-cleavage plane. In step (B), an amorphous insulating layer is formed on the inner circumferential surface of each of the plurality of first cleaving grooves over the entire length of each of the plurality of first cleaving grooves, and an amorphous insulating layer is formed on the inner circumferential surface of each of the plurality of second cleaving grooves over the entire length of each of the plurality of second cleaving grooves. Then, in step (C), the portions on both sides of a selected first cleaving groove in the other main surface of the wafer are supported. Then, in step (D), the tip of the cutting blade is cut towards the selected first cleaving groove. The blade tip is pressed against the first dividing groove in such a way that it extends overlapping with the first dividing groove when viewed from the pressing direction of the blade tip, thereby breaking the wafer in a crack manner. Then, for the wafer piece obtained in step (D), step (E) is performed: the portions on both sides of a selected second dividing groove among the plurality of second dividing grooves on the other main surface of the wafer are supported, and then, for the selected second dividing groove, step (F) is performed: the blade tip of the cutting blade is pressed against the second dividing groove in such a way that it extends overlapping with the second dividing groove when viewed from the pressing direction of the blade tip, thereby breaking the wafer in a crack manner.

[0053] According to this structure, for a semiconductor chip obtained by dividing a wafer at selected first and second dividing slots, the side of the wafer divided at the first dividing slot and the side of the wafer divided at the second dividing slot can be made into neatly broken surfaces.

[0054] Alternatively, the selection in step (C) can be performed on the unselected first dividing slots among the plurality of first dividing slots, and the selection in step (E) can be performed on the unselected second dividing slots among the plurality of second dividing slots, and these selections can be performed until all the first dividing slots and the second dividing slots are selected.

[0055] According to this structure, for all semiconductor chips obtained by dividing the wafer at multiple first dividing slots and multiple second dividing slots, the side surface of the wafer divided at the first dividing slot and the side surface of the wafer divided at the second dividing slot can be made into neatly broken surfaces.

[0056] Alternatively, in step (A), on one main surface of the wafer, a plurality of first dividing grooves, serving as one of the first dividing grooves, are formed extending along the first non-cleavage plane, and a plurality of second dividing grooves, serving as one of the second dividing grooves, are formed extending along the second non-cleavage plane orthogonal to the first non-cleavage plane. On the other main surface of the wafer, a plurality of first dividing grooves of the other side are formed back-to-back with the plurality of first dividing grooves of one side, and a plurality of second dividing grooves of the other side are formed back-to-back with the plurality of second dividing grooves of one side. In step (B), within each of the plurality of first dividing grooves of one side... An amorphous insulating layer is formed on the circumferential surface of each of the plurality of first dividing grooves along the entire length of each of the plurality of first dividing grooves. An amorphous insulating layer is also formed on the inner circumferential surface of each of the plurality of second dividing grooves along the entire length of each of the plurality of second dividing grooves. In step (C), a first cutting groove is formed at the bottom of each of the plurality of first dividing grooves. The dicing groove divides the insulating layer of the plurality of first dicing grooves of the other party in the width direction of each of the plurality of first dicing grooves of the other party, and the first dicing groove extends along the extension direction of each of the plurality of first dicing grooves of the other party. A second dicing groove is formed at the bottom of each of the plurality of second dicing grooves of the other party, the second dicing groove dividing the insulating layer of the plurality of second dicing grooves of the other party in the width direction of each of the plurality of second dicing grooves of the other party, and the second dicing groove extends along the extension direction of each of the plurality of second dicing grooves of the other party. Furthermore, the first dicing groove located on a selected one of the plurality of first dicing grooves of the other party's main surface is... The portions on both sides are supported. Then, in step (D), for the first dividing groove of the selected one side, the tip of the cutting blade is pressed against the first dividing groove of the selected one side in such a way that the tip extends overlapping with the first dividing groove of the selected one side when viewed from the pressing direction of the tip, thereby dividing the wafer in a fracture manner. And, for the wafer fragment obtained in step (D), the following step (E) is performed: the portions on both sides of the second dividing groove of the selected one side of the main surface of the other side of the wafer are supported. And then, for the second dividing groove of the selected one side...The following step (F) is performed: the tip of the cutting blade is pressed against the second dividing groove of one side, such that when viewed from the pressing direction of the tip, the tip extends overlapping with the second dividing groove of the other side, thereby breaking the fragment in a fracture manner.

[0057] According to this structure, for a semiconductor chip obtained by dicing a wafer at a selected first dicing groove and a selected second dicing groove, the side of the wafer diced at the first dicing groove and the side of the wafer diced at the second dicing groove can be made into neatly broken surfaces. Furthermore, since the first dicing groove and the second dicing groove are formed on both main surfaces of the wafer, and the insulating layers of the other dicing groove and the other dicing groove located on the back side of the first dicing groove and the second dicing groove are separated by the first dicing groove and the second dicing groove, respectively, it is easier to dice thicker wafers by fracture compared to the case where the first dicing groove and the second dicing groove are formed only on one main surface of the wafer.

[0058] Alternatively, the thickness of the insulating layer may be 5 μm or more and 100 μm or less.

[0059] Based on this structure, the wafer can be divided in a suitable manner by fracturing.

[0060] Alternatively, in step (D), at least the tip of the cutting blade is pressed against the insulating layer located at the bottom of the first dividing groove in such a way that the tip extends overlapping with the first dividing groove when viewed from the pressing direction of the tip, thereby dividing the wafer in a fracture manner.

[0061] According to this structure, the wafer can be divided in a manner that allows it to break appropriately at least at the first dividing groove.

[0062] Alternatively, the blade tip angle of the cutting blade may be less than 90 degrees.

[0063] Based on this structure, the wafer can be divided in a suitable manner by fracturing.

[0064] Alternatively, the wafer may be made of GaN grown on a Si, InP, or Si substrate via a buffer layer.

[0065] Based on this structure, the wafer can be divided in a suitable manner by fracturing.

[0066] Alternatively, the insulating layer may be made of glass.

[0067] Based on this structure, the wafer can be divided in a suitable manner by fracturing.

[0068] Hereinafter, specific embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, in all the drawings below, the same or equivalent elements will be labeled with the same reference numerals, and repeated descriptions will be omitted. Also, the following drawings are for the purpose of explaining the present disclosure, and therefore there may be omissions of elements unrelated to the present disclosure, inaccurate dimensions for exaggeration, simplifications, and inconsistencies in the shapes of corresponding elements in multiple drawings. Furthermore, the present disclosure is not limited to the following embodiments.

[0069] (definition)

[0070] In the specification and claims of this application, "pressing the tip of the cutting blade onto the dividing groove" includes both "pressing the tip of the cutting blade directly onto the dividing groove" and "pressing the tip of the cutting blade indirectly onto the dividing groove." As an example of pressing the tip of the cutting blade directly onto the dividing groove, one could cite the case where the tip of the cutting blade is pressed onto the edge of the dividing groove (the upper end of the dividing groove where no insulating layer is formed) (see [reference]). Figure 19 As an example of indirectly pressing the tip of the cutting blade against the dividing groove, one could illustrate the case where the tip of the cutting blade is pressed against the dividing groove through an insulating layer formed thereon (see [reference]). Figure 15 and Figure 17 ).

[0071] In the specification and claims of this application, "the first non-cleavage plane of the crystal structure of the semiconductor constituting the wafer" includes all non-cleavage planes parallel to any one of the first non-cleavage planes in the crystal structure of the semiconductor constituting the wafer. Furthermore, "the second non-cleavage plane of the crystal structure of the semiconductor constituting the wafer" includes all non-cleavage planes parallel to any one of the second non-cleavage planes in the crystal structure of the semiconductor constituting the wafer.

[0072] For convenience, "silicate glass" is sometimes simply referred to as "glass" in the specification and claims of this application.

[0073] In the specification of this application, the first dividing groove 3A formed on one side of the main surface of the wafer 1 is generally referred to as "the first dividing groove 3A of one side", and the first dividing groove 3B formed on the other side of the main surface of the wafer 1 is referred to as "the first dividing groove 3B of the other side". However, for convenience, the first dividing groove 3A of one side is sometimes simply referred to as "the first dividing groove 3A", and the first dividing groove 3B of the other side is sometimes simply referred to as "the first dividing groove 3B".

[0074] Furthermore, in the specification of this application, the second dividing groove 21A formed on one side of the main surface of the wafer 1 is generally referred to as "the second dividing groove 21A of one side", and the second dividing groove 21B formed on the other side of the main surface of the wafer 1 is referred to as "the second dividing groove 21B of the other side". However, for convenience, the second dividing groove 21A of one side is sometimes simply referred to as "the second dividing groove 21A", and the second dividing groove 21B of the other side is sometimes simply referred to as "the second dividing groove 21B".

[0075] Furthermore, in the specification and claims of this application, "the portion located on both sides of the first or second dividing groove in the main surface of the other side of the wafer" refers to the portion located on both sides of the first or second dividing groove 21A in the main surface of the other side of the wafer when viewed from the pressing direction of the cutting blade.

[0076] (Summary of the implementation method)

[0077] In this disclosure, Embodiment 1 illustrates a configuration where the first dividing groove is formed on both main surfaces of the wafer. Embodiment 2 illustrates a configuration where the first dividing groove and the second dividing groove are formed on both main surfaces of the wafer. Embodiment 3 illustrates a configuration where the first dividing groove is formed only on one main surface of the wafer. Embodiment 4 illustrates a configuration where the first dividing groove and the second dividing groove are formed only on one main surface of the wafer.

[0078] (Implementation Method 1)

[0079] Figure 1 This is a flowchart illustrating an example of a wafer dicing method according to Embodiment 1 of this disclosure. (Refer to...) Figure 1 The wafer dicing method of Embodiment 1 includes the following steps: forming first dicing grooves 3A and 3B (refer to) such that they extend along the first non-cleavage plane of a wafer 1 made of a semiconductor having a cubic crystal structure. Figure 2 (Step S1); Amorphous insulating layers 4A and 4B are formed on the inner circumferential surfaces of the first dividing grooves 3A and 3B over the entire length of the first dividing grooves 3A and 3B (refer to...). Figure 4 (Step S2); using support component 6 (refer to) Figure 6 The portion located on both sides of the first dividing groove 3A, 3B in the main surface 1b of the other side of the wafer 1 is supported by a cutting blade 7 with a straight blade tip (see step S3). Figure 7 The wafer 1 is broken by means of a straight blade tip that is longer than or equal to the length of the first dividing grooves 3A and 3B (step S4). The following is a detailed description of each process.

[0080] Figure 2 This is a schematic diagram illustrating the process (step S1) of forming a first dividing groove 3A on one side and a first dividing groove 3B on the other side on a wafer 1 formed in a matrix shape in chip region 2. The schematic diagram is shown in a top view.

[0081] Reference Figure 2 In wafer 1, chip regions 2 are formed in a matrix shape. Wafer 1 is made of a semiconductor with a cubic crystal structure. Examples of semiconductors with a cubic crystal structure include Si, InP, and GaAs. Chip regions 2 refer to the regions formed by the first segmentation trenches 3A and 3B and the second segmentation trenches 21A and 21B of wafer 1 (see reference). Figure 21 The region 2 is divided into sections to form a semiconductor chip. The semiconductor chip is composed of a single semiconductor element such as a diode, thyristor, or transistor. In this embodiment 1, the semiconductor chip is composed of a thyristor. Electrodes and other terminals are formed on the main surface of the chip region 2, but these are omitted from the illustration in this embodiment 1.

[0082] In this embodiment 1, the chip region 2 is formed in a matrix such that the row direction is along the direction of the first non-cleavage plane of the cubic crystal structure constituting the wafer 1 and the column direction is along the direction of the second non-cleavage plane orthogonal to the first non-cleavage plane, respectively. Moreover, for example, first dividing grooves 3A and 3B are formed along the row direction of the matrix of chip region 2.

[0083] Figure 3 Is with Figure 2 A cross-sectional view is shown together with the process (step S1) of forming the first dividing grooves 3A and 3B on the two main surfaces 1a and 1b of wafer 1. Figure 3 The cross-sectional view only shows the chip regions 2 located on both sides of the first dividing grooves 3A and 3B, omitting other chip regions 2. Furthermore, terminals such as electrodes formed on the main surface of the chip regions 2 are omitted. Figure 3 In order to make the first dividing slots 3A and 3B easier to understand, the scale of wafer 1, etc., was exaggerated, and therefore inaccurate. These points are in Figures 3-7 , Figure 12 , Figure 15 , Figure 17 , Figure 19 , Figure 22 , Figure 23 The same applies to China.

[0084] Reference Figure 3A first sizing trench 3A formed on one main surface 1a of wafer 1 and a first sizing trench 3B formed on the other main surface 1b of wafer 1 are formed back-to-back. That is, the first sizing trench 3A of one side and the first sizing trench 3B of the other side are formed to overlap when viewed from a direction perpendicular to the main surface of wafer 1, and their opening surfaces face opposite directions. The first sizing trenches 3A and 3B are formed, for example, by wet etching with a mixture of hydrofluoric acid (HF) and nitric acid (HNO3). For example, to fabricate a thyristor, wafer 1 has a p+ layer, a p- layer, an n- layer, a p- layer, and a p+ layer sequentially from one main surface 1a to the other main surface 1b. The first sizing trenches 3A and 3B are formed, for example, to reach the depth of the n- layer. The first sizing trenches 3A and 3B formed in this way have a U-shaped cross-sectional shape, but the cross-sectional shape of the first sizing trenches 3A and 3B is not particularly limited.

[0085] Figure 4 This is a cross-sectional view showing the process (step S2) in which amorphous insulating layers 4A and 4B are formed in the first dividing groove 3A on one side and the first dividing groove 3B on the other side, respectively.

[0086] Reference Figure 4 An amorphous insulating layer 4A is formed on the inner circumferential surface of one first dividing groove 3A along its entire length, and an amorphous insulating layer 4B is formed on the inner circumferential surface of the other first dividing groove 3B along its entire length. The amorphous insulator only needs to be able to break under excessive bending when formed in a layered or film-like state. Examples of such amorphous insulators include so-called glass layers, silicon oxide films (SiO2), silicon oxynitride films (SiON), and silicon nitride films (SiN). Examples of glasses include soda glass, crystal glass, borosilicate glass, and quartz glass. Typically, silicate glasses with silicon dioxide (SiO2) as the main component are examples. In the specification and claims of this application, "silicate glass" is sometimes simply referred to as "glass." In this embodiment 1, glass (silicate glass) is used as the amorphous insulator.

[0087] The amorphous insulating layer (hereinafter, sometimes simply referred to as "insulating layer") 4A is formed, for example, by coating a molten amorphous insulating material onto one of the main surfaces 1a of the wafer 1, using a scraper to accumulate the coated amorphous insulating material in layers on the inner surface of one of the first sizing grooves 3A, and then heating the wafer 1 to a predetermined temperature to sinter the layered amorphous insulating material. Similarly, the insulating layer 4B is formed, for example, by coating a molten amorphous insulating material onto the other main surface 1b of the wafer 1, using a scraper to accumulate the coated amorphous insulating material in layers on the inner surface of the other first sizing groove 3B, and then heating the wafer 1 to a predetermined temperature to sinter the layered amorphous insulating material. Through this formation, the insulating layers 4A and 4B have a U-shaped cross-sectional shape that thins from the center to both ends, but the cross-sectional shape of the insulating layers 4A and 4B is not particularly limited.

[0088] The thickness of insulating layers 4A and 4B is preferably 5 μm or more and 100 μm or less. Here, the thickness of the portion of insulating layers 4A and 4B located at the bottom of the first dividing grooves 3A and 3B is defined as the thickness of insulating layers 4A and 4B. If the thickness of insulating layers 4A and 4B is less than 5 μm, even if the bottom of the first dividing grooves 3A and 3B is covered by insulating layers 4A and 4B, the coverage of the sides of the first dividing grooves 3A and 3B is insufficient, and the wafer 1 is partially exposed on the sides of the first dividing grooves 3A and 3B. On the other hand, if the thickness of insulating layers 4A and 4B exceeds 100 μm, the large stress of insulating layers 4A and 4B will prevent the wafer 1 from breaking in the pressing direction of the cutting blade 7, resulting in breakage in various directions.

[0089] Alternatively, a first dividing groove 3A can be formed on one side, followed by the formation of an insulating layer 4A, and then the formation of a first dividing groove 3B on the other side, followed by the formation of an insulating layer 4B.

[0090] Figure 5 This is a cross-sectional view showing the process of forming the first dicing groove 5 at the first dicing groove 3B on the other side of the main surface 1b of the wafer 1. (Refer to...) Figure 5 The first dicing groove 5 is formed at the center of the amorphous insulating layer 4B to the depth of the wafer 1 and along the entire length of the other first dicing groove 3B. As a result, the insulating layer 4B of the other first dicing groove 3B is divided by the first dicing groove 5 in the width direction of the first dicing groove 3B.

[0091] Figure 6 This is a cross-sectional view showing the process of supporting the portion on both sides of the first dividing groove 3A on one side of the main surface 1b of the wafer 1 (step S3) and the process of dividing the wafer 1 using the cutting blade 7 (step S4). Figure 7 It is shown in Figure 6 A schematic diagram showing the cutting blade 7 being pressed obliquely against the first dividing groove 3A during the process.

[0092] Reference Figure 6 In the process of supporting the portions on both sides of the first dividing groove 3A on one side of the main surface 1b of the other side of wafer 1 (step S3), the portions on both sides of the first dividing groove 3A on one side of the main surface 1b of the other side of wafer 1 are supported by a pair of support members 6, 6. Here, the portions on both sides of the first dividing groove 3A on one side of the main surface 1b of the other side of wafer 1 refer to the portions on both sides of the first dividing groove 3A on one side of the main surface 1b of the other side of wafer 1 when viewed from the pressing direction 8 of the cutting blade 7. The pair of support members 6, 6 have a length greater than or equal to the length of the first dividing groove 3A on one side. The pair of support members 6, 6 are arranged in a parallel manner with a predetermined interval. The construction of the pair of support members 6, 6 is not particularly limited as long as they can horizontally support wafer 1 using parallel linear support portions. For example, the pair of support members 6, 6 can be a pair of elongated rod-shaped members with triangular or quadrilateral cross-sections arranged in parallel. Alternatively, the pair of support members 6, 6 can also be a pair of support portions formed on the upper surface of a stage. Specifically, for example, it can be as follows: The stage has a flat upper surface on which a straight groove with a rectangular cross-section is formed. The width of the groove is slightly wider than the width of one of the first dividing grooves 3A. The edges of the groove form a pair of support members 6, 6. The wafer 1 is placed on the stage with the center line of one of the first dividing grooves 3A aligned with the center line of the groove, and is divided using a cutting blade 7. Here, the pair of support members 6, 6 are composed of a pair of slender cuboid rod-shaped members arranged parallel to each other, and the upper corners 6a, 6a of their respective inner sides form parallel straight support portions. The predetermined interval of the pair of support members 6, 6 is determined based on experiments, simulations, calculations, etc.

[0093] In the process of dividing the wafer 1 using the cutting blade 7 (step S4), firstly, the wafer 1 is placed horizontally on a pair of support members 6, 6 with one main surface 1a on top and the other main surface 1b on the bottom, and the first dividing grooves 3A and 3B located in the middle of a pair of support members 6, 6.

[0094] Next, the cutting blade 7 is pressed downwards onto the wafer 1. Specifically, the tip of the cutting blade 7a is pressed against the insulating layer 4A located at the bottom of the first dicing groove 3A, such that the tip extends overlapping with the first dicing groove 3A when viewed from the pressing direction (vertical direction) 8. In this case, preferably, the tip of the cutting blade 7a is pressed against the insulating layer 4A at a distance from the bottom of the first dicing groove 5 (at... Figure 6 The middle part (the upper end) is the closest part. This allows for more neat division of the insulating layer 4A, and consequently, more neat division of the wafer 1. The cutting blade 7 needs to be a plate-shaped blade with a straight blade tip extending beyond the length of the first dividing grooves 3A and 3B (see reference). Figure 7 As the cutting blade 7, for example, a cutting blade commonly used for cutting wafer 1 can be used. Of course, the cutting blade 7 can also be a special cutting blade with a specified blade tip angle, as described later (see [reference]). Figure 15 and Figure 17 The cutting blade 7 is mounted on the actuating part of the cutting device (not shown), and moves in the vertical direction by means of the actuating part.

[0095] Reference Figure 7 The cutting blade 7 has its tip 7a pressed against one end of the first dividing groove 3A in an inclined state relative to the first dividing groove 3A in the extending direction of the first dividing groove 3A. The angle of inclination of the cutting blade 7 is determined through experiments, simulations, calculations, etc. Alternatively, the cutting blade 7 may not be inclined, and the cutting blade may uniformly abut against the first dividing groove 3A.

[0096] Refer again Figure 6 When the tip 7a of the cutting blade 7 presses against one of the first dicing grooves 3A, the insulating layer 4 flexes together with the wafer 1. Since the insulating layer 4A is amorphous and has low toughness, it fractures at its center. Because the tip 7a of the cutting blade 7 extends overlapping with one of the first dicing grooves 3A when viewed from the pressing direction 8 of the tip 7a, the fracture extends linearly along its extension direction within one of the first dicing grooves 3A as the tip 7a advances. Thus, the wafer 1 is pulled and fractured linearly by the extension of the fractured insulating layer 4A. Figure 6 The arrow indicates the fracture of wafer 1. In this case, since wafer 1 is a semiconductor with a cubic crystal structure, and one of the first cleaving grooves 3A extends along the first non-cleavage plane, wafer 1 fractures neatly (flatly). Furthermore, since the insulating layer 4B of the other first cleaving groove 3B of wafer 1 is separated by the first cutting groove 5 in the width direction of the first cleaving groove 3B, when the tip 7a of the cutting blade 7 presses against one of the first cleaving grooves 3A and the insulating layer 4A fractures, wafer 1 is not affected by the insulating layer 4B of the other first cleaving groove 3B, but is only fractured by the pull of the fractured insulating layer 4A of the first cleaving groove 3A. As a result, thicker wafers 1 can be divided by fracture.

[0097] Figure 8 It is shown schematically. Figure 6 A schematic diagram illustrating the mechanism by which the wafer 1 is divided using the cutting blade 7. Furthermore, Figure 8The mechanism shown is deduced by the inventors, therefore Figure 8 It's a concept diagram. Figure 8 schematically shown Figure 6 The portion enclosed by the dashed line in chip 1. Figure 8 The image shows the area near fracture 8 of wafer 1 and fracture 9 of insulating layer 4A, with double-dotted lines used for perspective view. Figure 8 The right side of the image. Additionally, label 10 indicates the starting point of the fracture in wafer 1 (the fracture at the beginning), and arrow 11... 13 indicates the direction of fracture extension, arrow 11 The number 1 within 13 3 indicates the order in which the fractures occurred.

[0098] Reference Figure 8 When the wafer 1 flexes beyond the allowable range due to the pressure of the cutting blade 7, a fracture 10 is generated at the lower end of the wafer 1 (upper end of the first cutting groove 5) located below the cutting blade 7. This fracture 10 extends upwards as shown by arrow 11, reaching the upper end of the insulating layer 4A. During this process, fractures 8 and 9 are generated in the wafer 1 and insulating layer 4A, respectively. Thus, because the insulating layer 4A has low toughness, it is prone to fracture, and fracture 9 progresses rapidly as shown by arrow 12. On the other hand, because the wafer 1 has high toughness, it is not easily fractured, and fracture 8 does not easily extend as shown by arrow 13. Therefore, fracture 8 of the wafer 1 is stretched by the rapidly advancing fracture 9 of the insulating layer 4A. Here, since the tip 7a of the cutting blade 7 extends overlapping with one of the first dividing grooves 3A when viewed from the pressing direction 8 of the tip 7a, the fracture 9 extends linearly along its extension direction in one of the first dividing grooves 3A as the tip 7a of the cutting blade 7 advances. Thus, the wafer 1 is pulled and fractured linearly by the linear fracture 9 of the insulating layer 4A.

[0099] {Example}

[0100] The effects of the wafer dicing method of Embodiment 1 will be explained using examples and comparative examples. In the examples, wafer 1 is diced using the wafer dicing method of Embodiment 1. In Comparative Example 1, wafer 1 is diced at the first dicing grooves 3A and 3B formed along its cleavage plane using a cutting blade 7. Other points are the same as in the embodiment. In Comparative Example 2, wafer 1 is diced at the first dicing grooves 3A and 3B formed along its non-cleavage plane using a roller dicing method. In Comparative Example 3, wafer 1 is diced at the first dicing grooves 3A and 3B formed along its cleavage plane using a roller dicing method. Through these dicings, the cross-sections of wafer 1 and insulating layer 4A at the first dicing grooves 3A and 3B appear as dicing surfaces. These dicing surfaces were observed by photographing them using a digital microscope.

[0101] <Example>

[0102] Figure 9A This is a photograph showing the state of the segmented surface obtained through the embodiment. Figure 9B yes Figure 9A A simplified sketch of the photograph. Figure 9B The sketch is to clearly show Figure 9A It was added to the darker and less discernible parts of the photo. Figure 9A In the diced surface of wafer 1, the black portion represents the recess. Figure 9B The sketch mainly shows Figure 9A The light and dark boundaries of the photograph. Furthermore, these are relevant to what will be discussed later. Figure 10A , Figure 10B , Figures 13A to 14B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 20A , Figure 20B The same applies.

[0103] Reference Figure 9A and Figure 9B In the embodiment, although the cleavage surface of wafer 1 has tiny longitudinal stripe-like scratches at the lower end, it is substantially neat (flat).

[0104] <Comparative Example 1>

[0105] Figure 10A This is a photograph showing the state of the segmented surface obtained through Comparative Example 1. Figure 10B yes Figure 10A A simplified sketch of the photograph.

[0106] Reference Figure 10A and Figure 10BIn Comparative Example 1, the cleavage surface of wafer 1 exhibited longitudinal striations due to surface misalignment, resulting in a rough surface. It is inferred that this surface misalignment was caused by the misalignment between the fracture surface of the insulating layer 4A and the cleavage surface of wafer 1. It is further inferred that this surface misalignment caused edge chipping.

[0107] Definition of "neatly divided facets"

[0108] Here, the definition of "neatly divided facets" in this disclosure is explained. Figure 11A It is a diagram that schematically illustrates the situation of "neatly divided planes" when viewed from the side. Figure 11B This diagram schematically illustrates the situation where "the dicing surface with longitudinal stripe marks appears" when viewed from the side. The "neat dicing surface" was obtained by dicing the wafer 1 using a cutting blade 7 with a cutting blade tip angle of 45 degrees, as described later in the "study on the blade tip angle of the cutting blade 7". Figure 16A A photograph of it is shown. The "splitting surface with longitudinal striations" was revealed by dividing the wafer 1 along the cleavage surface using a cutting tool 7. In the above... Figure 10A An example of this photograph is shown in the image.

[0109] Reference Figure 11A In the neatly divided surface 31, the divided surface of the amorphous insulating layer 4A and the divided surface of the wafer 1 are roughly flush broken surfaces. In this divided surface 31, although the divided surface of the wafer 1 is... Figure 11A The wafer 1 is not crystallographically free of steps in the depth direction of the paper (the extension direction of the dividing surface 31), but it is formed in a state where large steps cannot be identified under an optical microscope. The dividing surface of the wafer 1 in such a state is defined as a "neat dividing surface" in this disclosure.

[0110] On the other hand, an "irregular cleavage surface" is a cleavage surface that does not conform to this definition. A typical example is the surface obtained by cutting wafer 1 along a cleavage plane using a cutting blade 7. (See reference...) Figure 11B In this cleaving plane, although the amorphous insulating layer 4A fractures in the pressing direction of the cutting blade 7 (the direction perpendicular to the insulating layer 4A), the wafer 1 is intended to fracture on a cleavage plane offset from the direction perpendicular to the wafer 1. As a result, the fracture direction changes at the interface between the insulating layer 4A and the wafer 1, and the cleaving plane does not become a flush surface. In this cleaving, in the fracture direction... Figure 11B When traveling in the depth direction (inward direction of the paper), in wafer 1, the cleavage surface of wafer 1 is pulled by the fracture direction of insulating layer 4A, locally producing a surface offset from the cleavage surface, and the cleavage surface 32 of wafer 1 becomes an uneven rough surface with longitudinal stripe marks (see reference). Figure 10A ).

[0111] <Comparative Example 2>

[0112] Figure 12 This is a cross-sectional view showing the process of dividing wafer 1 using a roller dicing method. (Refer to...) Figure 12 In Comparative Examples 2 and 3, wafer 1, which was produced in the same manner as in Example 1, was divided at the first dividing grooves 3A and 3B by pressing wafer 1 with roller 107.

[0113] Figure 13A This is a photograph showing the state of the segmented surface obtained through Comparative Example 2. Figure 13B yes Figure 13A A simplified sketch of the photograph.

[0114] Reference Figure 13A and Figure 13B In Comparative Example 2, the dicing surface of wafer 1 has obvious longitudinal stripe marks, which is a clearly rough surface.

[0115] <Comparative Example 3>

[0116] Figure 14A This is a photograph showing the state of the segmented surface obtained through Comparative Example 3. Figure 14B yes Figure 14A A simplified sketch of the photograph.

[0117] Reference Figure 14A and Figure 14B In Comparative Example 3, the dicing surface of wafer 1 is completely flat and neat.

[0118] Summary

[0119] In the roller slitting method, it can be clearly seen from Comparative Example 2 that when the first slitting grooves 3A and 3B are formed along the non-cleavage surface of wafer 1, the slitting surface of wafer 1 becomes a noticeably rough surface, and a flat (neat) slitting surface cannot be obtained.

[0120] On the other hand, in the wafer dicing method of this embodiment 1, it can be clearly seen from the embodiments that even if the first dicing grooves 3A and 3B are formed along the non-cleavage surface of the wafer 1, a flat (neat) dicing surface can be obtained.

[0121] Therefore, this embodiment confirms that the wafer dicing method according to Embodiment 1 can obtain a good dicing surface in the wafer 1 in which the chip region 2 is formed in a matrix.

[0122] {Study on the tip angle of the cutting blade 7}

[0123] Next, the study of the blade tip angle of the cutting blade 7 will be explained. In this study, in the wafer dicing method of Embodiment 1 described above, the blade tip angle of the cutting blade 7 was changed to 45 degrees, 90 degrees, and 150 degrees, and the dicing surfaces of the first dicing grooves 3A and 3B were observed. This observation was performed by photographing the dicing surfaces using a digital microscope. The first dicing grooves 3A and 3B are formed along non-cleavage surfaces. In addition, the case where the first dicing grooves 3A and 3B are formed along cleavage surfaces was also studied, but the results were different from those obtained by using a digital microscope. Figure 10A and Figure 10B The dividing surface shown is also a rough and obvious dividing surface, so it will not be mentioned further here.

[0124] Figure 15 This is a cross-sectional view showing wafer dicing using a cutting blade 7 with a 45-degree blade tip angle. (Refer to...) Figure 15 The cutting blade 7 has a 45-degree blade tip angle. The width of the first dividing groove 3A is approximately 920 μm. The depth of the first dividing groove 3A to the bottom of the insulating layer 4A is approximately 140 μm. Other points are... Figure 6 The same method is used for wafer dicing.

[0125] Figure 16A This is a photograph showing the state of the cut surface when a cutting blade 7 with a cutting edge angle of 45 degrees is used to cut along a cutting groove on a non-cleavage surface. Figure 16B yes Figure 16A A simplified sketch of the photograph. (Refer to...) Figure 16A and Figure 16B The cleavage surface of wafer 1 is completely flat and neat.

[0126] Figure 17 This is a cross-sectional view showing wafer dicing using a cutting blade 7 with a 90-degree blade tip angle. (Refer to...) Figure 17 The cutting blade 7 has a 90-degree blade tip angle. The width of the first dividing groove 3A is approximately 920 μm. The depth of the first dividing groove 3A up to the bottom of the insulating layer 4A is approximately 140 μm. Other points are... Figure 6 The same method is used for wafer dicing.

[0127] Figure 18A This is a photograph showing the state of the cut surface when a cutting blade 7 with a 90-degree blade tip angle is used to cut along a cutting groove on a non-cleavage surface. Figure 18B yes Figure 18A A simplified sketch of the photograph. (Refer to...) Figure 18A and Figure 18B Although there are tiny longitudinal stripe-like scratches on the lower end of the dicing surface of wafer 1, it is actually neat (flat).

[0128] Figure 19This is a cross-sectional view showing wafer dicing using a cutting blade 7 with a 150-degree blade tip angle. (See reference...) Figure 19 The cutting blade 7 has a blade tip angle of 150 degrees. The width of the first dividing groove 3A is approximately 920 μm. The depth of the first dividing groove 3A to the bottom of the insulating layer 4A is approximately 140 μm. Therefore, it is inferred that the blade tip 7a of the cutting blade 7 abuts against the edge of the first dividing groove 3A (where there may be a portion where the insulating layer 4A is not formed), and the blade tip of the cutting blade 7 does not abut against the bottom of the insulating layer 4A.

[0129] Figure 20A This is a photograph showing the state of the cut surface when a cutting blade 7 with a cutting edge angle of 150 degrees is used to cut along a cutting groove on a non-cleavage surface. Figure 20B yes Figure 20A A simplified sketch of the photograph. (Refer to...) Figure 20A and Figure 20B Although there are tiny longitudinal stripe-like scratches on the lower end of the dicing surface of wafer 1, it is actually neat (flat).

[0130] Summary

[0131] The following points can be clearly identified from the above experimental results. First, the smaller the blade tip angle of the cutting blade 7, the flatter (neater) the dicing surface can be obtained. Second, the blade tip 7a of the cutting blade 7 abuts against the edge of the first dicing groove 3A, so even if the blade tip of the cutting blade 7 does not abut against the bottom of the insulating layer 4A, a good dicing surface can still be obtained. This is evidence that the wafer 1 is broken by the fracture of the insulating layer 4A in the wafer dicing method of Embodiment 1.

[0132] As can be clearly seen from the above description, according to the wafer dicing method of Embodiment 1, even if the dicing grooves 3A and 3B are formed along the non-cleavage surface of the wafer 1, a neat dicing surface can be obtained. Therefore, a good dicing surface can be obtained in the wafer 1 in which the chip region 2 is divided into a matrix by the grid-like dicing grooves.

[0133] (Implementation Method 2)

[0134] Embodiment 2 of this disclosure illustrates a manner in which first dividing grooves 3A and 3B and second dividing grooves 21A and 21B are formed on two main surfaces 1a and 1b of wafer 1.

[0135] Figure 21 This is a schematic diagram illustrating the process of forming first dividing grooves 3A, 3B and second dividing grooves 21A, 21B on a wafer formed in a matrix shape in chip region 2 according to the wafer dicing method of Embodiment 2 of this disclosure. The schematic diagram is shown in top view. (Refer to...) Figure 21In this embodiment 2, for example, first dividing slots 3A and 3B are formed along the row direction of the matrix of chip region 2, and second dividing slots 21A and 21B are formed along the column direction of the matrix of chip region 2. Other than this, it is the same as in embodiment 1.

[0136] Figure 22 This is a cross-sectional view showing the process of forming the second dividing grooves 21A and 21B on the two main surfaces 1a and 1b of wafer 1. (Refer to...) Figure 22 A second dividing groove 21A is formed on one main surface 1a of wafer 1, and a second dividing groove 21B is formed on the other main surface 1b of wafer 1.

[0137] The methods for forming the second dividing grooves 21A and 21B, forming insulating layers 22A and 22B in the second dividing grooves 21A and 21B, and dividing the second dividing grooves 21A and 21B of wafer 1 are the same as the methods for forming the first dividing grooves 3A and 3B, forming insulating layers 4A and 4B in the first dividing grooves 3A and 3B, and dividing the first dividing grooves 3A and 3B of wafer 1 in the wafer dividing method of Embodiment 1.

[0138] Specifically, for example, firstly, on one side of the main surface 1a of the wafer 1, a plurality of first dividing grooves 3A are formed along the row direction of the matrix of the chip region 2, and a plurality of second dividing grooves 21A are formed along the column direction of the matrix of the chip region 2.

[0139] Next, on the other main surface 1b of the wafer 1, a plurality of first dividing grooves 3B are formed along the row direction of the matrix of the chip region 2, and a plurality of second dividing grooves 21B are formed along the column direction of the matrix of the chip region 2.

[0140] Next, insulating layers 4A are formed in the first segments 3A of one of the plurality of wafers 1, and insulating layers 22B are formed in the second segments 21A of one of the plurality of wafers 1. Furthermore, insulating layers 4B are formed in the first segments 3B of the other of the plurality of wafers 1, and insulating layers 22B are formed in the second segments 21B of the other of the plurality of wafers 1.

[0141] Next, a first dicing groove 5 is formed at each of the plurality of other first dicing grooves 3B on the wafer 1, and a second dicing groove 23 is formed at each of the plurality of other second dicing grooves 21B. An amorphous insulating layer 22B is formed in the central portion of the second dicing groove 23 to the depth reaching the wafer 1 and along the entire length of the other second dicing groove 21B.

[0142] Next, the support member 6 is used to support the portions on both sides of the appropriate (selected) first dividing groove 3A of one of the plurality of first dividing grooves 3A on the other side of the main surface 1b of the wafer 1.

[0143] Next, the wafer 1 is divided at the appropriate (selected) first dividing groove 3A on one side using the cutting blade 7. Then, these support and dividing processes are performed sequentially on all the remaining first dividing grooves 3A on one side.

[0144] Next, the second dividing groove 21A of all the fragments of the wafer 1 obtained through these supporting and dividing processes is subjected to the same supporting and dividing processes as the first dividing groove 3A of the aforementioned process.

[0145] Thus, the wafer 1, which is formed in a matrix shape by the chip regions 2, is divided into semiconductor chips composed of individual chip regions 2. Moreover, the side of the wafer 1 divided at the first dividing groove 3A on one side and the side of the wafer 1 divided at the second dividing groove 21A on one side of the semiconductor chips obtained by this division become neatly broken surfaces.

[0146] As can be clearly seen from the above description, according to the wafer dicing method of this embodiment 2, for all semiconductor chips obtained by dicing wafer 1 at multiple first dicing grooves 3A, 3B and multiple second dicing grooves 21A, 21B, the side surface of wafer 1 diced at the first dicing grooves 3A, 3B and the side surface of wafer 1 diced at the second dicing grooves 21A, 21B can be made into neatly broken surfaces.

[0147] (Implementation Method 3)

[0148] Embodiment 3 of this disclosure illustrates a method in which the first dividing groove is formed only on one side of the wafer.

[0149] Figure 23 This is a cross-sectional view showing the wafer 1 being divided using a cutting blade 7 in the wafer dicing method of Embodiment 3 of this disclosure. (Refer to...) Figure 23 In this third embodiment, the first dividing groove 3A is formed only on one of the main surfaces 1a of the wafer 1. Therefore, in this embodiment, the first dividing groove 3A is not formed as in the third embodiment. Figure 5The first dicing groove 5 is formed on the other side of the main surface 1b of the wafer 1, as shown. In this embodiment 3, a pair of support members 6, 6 support the portions of the other side of the main surface 1b of the wafer 1 located on both sides of the first dicing groove 3. In this state, the wafer 1 is diced at the first dicing groove 3 using a cutting blade 7. In this case, since there is no insulating layer on the other side of the main surface 1b of the wafer 1, when the cutting blade 7 presses against the insulating layer 4 of the first dicing groove 3, the wafer 1 flexes and the insulating layer 4 breaks. The wafer 1 is pulled apart by the breakage of the insulating layer 4. As a result, a flat (neat) dicing surface is obtained. As a semiconductor element structure of such a wafer 1, for example, the structure of a diode can be listed. Other than this, it is the same as in embodiment 1.

[0150] According to this embodiment 3, a good partitioning surface can also be obtained in the wafer 1 in which the chip region 2 is divided into a matrix by grid-like partitioning grooves.

[0151] (Implementation Method 4)

[0152] In Embodiment 4 of this disclosure, the first dividing groove 3 and the second dividing groove 21 are formed only on one of the main surfaces 1a of the wafer 1. The wafer 1 of Embodiment 4 is the same as that of Embodiment 3. All other aspects are the same as those of Embodiment 2.

[0153] According to this embodiment 4, for a semiconductor chip obtained by slicing, the side surface of wafer 1 slicing at the first slicing groove 3 and the side surface of wafer 1 slicing at the second slicing groove 21 can also be made into neatly broken surfaces.

[0154] (Other implementation methods)

[0155] Any of the wafer dicing methods described in embodiments 1 to 4 above can also be used to dice wafer 1 for purposes other than semiconductor chip manufacturing.

[0156] In any of the embodiments 1 to 4 described above, the cutting blade 7 may be fixed, and a pair of support members 6 may move toward the cutting blade 7.

[0157] Based on the above description, many improvements or other implementations will be apparent to those skilled in the art. Therefore, the above description should be interpreted as illustrative only.

[0158] [Industry Applicability]

[0159] The wafer dicing method disclosed herein is useful as a wafer dicing method that can obtain good dicing surfaces in wafers where the chip regions are formed in a matrix shape.

Claims

1. A wafer dicing method, comprising: Step (A) involves forming a first dividing groove on at least one main surface of a wafer made of a semiconductor with a cubic crystal structure, in which a semiconductor element is formed, in such a way that it extends along a first non-cleavage plane of the crystal structure. Step (B) involves forming an amorphous insulating layer on the inner circumferential surface of the first dividing groove over the entire length of the first dividing groove. Step (C) involves supporting the portions of the wafer located on either side of the first dividing groove on the other main surface; and In process (D), the tip of a cutting blade with a straight blade tip is pressed against the first dividing groove in such a way that the tip tip extends overlapping with the first dividing groove when viewed from the pressing direction of the blade tip, thereby dividing the wafer in a fracture manner. The straight blade tip is a length greater than or equal to the length of the first dividing groove.

2. The wafer dicing method according to claim 1, wherein, In step (D), the tip of the cutting blade is pressed against one end of the first dividing groove in a state where the tip is inclined relative to the first dividing groove in the extension direction of the first dividing groove.

3. The wafer dicing method according to claim 1 or 2, wherein, In process (A), a first dividing groove, serving as one of the first dividing grooves, is formed on one of the main surfaces of the wafer, and a first dividing groove of the other side is formed on the other main surface of the wafer in a back-to-back manner with the first dividing groove of the first side. In step (B), an insulating layer is formed on the inner circumferential surface of the first dividing groove of one party and the first dividing groove of the other party over the entire length of the first dividing groove of each party. In step (C), a first dicing groove is formed at the bottom of the inner peripheral surface of the first dicing groove on the other side. This first dicing groove divides the insulating layer of the first dicing groove on the other side in the width direction of the first dicing groove on the other side, and the first dicing groove extends along the extension direction of the first dicing groove on the other side. Then, the portions on both sides of the first dicing groove on the other side of the main surface of the wafer are supported. In the process (D), the tip of the cutting blade is pressed against the first dividing groove of one side in such a way that the tip extends overlapping with the first dividing groove of the other side when viewed from the pressing direction of the tip, thereby dividing the wafer in a fracture manner.

4. The wafer dicing method according to claim 1 or 2, wherein, In process (A), a plurality of first dividing grooves are formed on at least one main surface of the wafer, extending along the first non-cleavage plane, and a plurality of second dividing grooves are formed extending along a second non-cleavage plane orthogonal to the first non-cleavage plane. In step (B), an amorphous insulating layer is formed on the inner circumferential surface of each of the plurality of first dividing grooves over the entire length of each of the plurality of first dividing grooves; and an amorphous insulating layer is formed on the inner circumferential surface of each of the plurality of second dividing grooves over the entire length of each of the plurality of second dividing grooves. Subsequently, in step (C), the portions on both sides of a selected first dividing groove among the plurality of first dividing grooves on the other main surface of the wafer are supported. Subsequently, in step (D), for the selected first dividing groove, the tip of the cutting blade is pressed against the first dividing groove such that it extends overlapping with the first dividing groove when viewed from the pressing direction of the tip, thereby dividing the wafer in a fracture manner. For the wafer fragment obtained in process (D), process (E) is performed as follows: The portions on both sides of a selected second dividing groove among the plurality of second dividing grooves on the other main surface of the wafer are supported, and... Then, for the selected second dividing groove, the following step (F) is performed: the tip of the cutting blade is pressed against the second dividing groove in such a way that the tip extends overlapping with the second dividing groove when viewed from the pressing direction of the tip, thereby dividing the fragment in a fracture manner.

5. The wafer dicing method according to claim 4, wherein, The selection process in step (C) is performed on the unselected first partition slots among the plurality of first partition slots, and the selection process in step (E) is performed on the unselected second partition slots among the plurality of second partition slots, and these selections are performed until all the first partition slots and the second partition slots are selected.

6. The wafer dicing method according to claim 4, wherein, In process (A), on one main surface of the wafer, a plurality of first dividing grooves, serving as one of the first dividing grooves, are formed extending along the first non-cleavage plane, and a plurality of second dividing grooves, serving as one of the second dividing grooves, are formed extending along the second non-cleavage plane orthogonal to the first non-cleavage plane. On the other main surface of the wafer, a plurality of first dividing grooves of the other side are formed back-to-back with the plurality of first dividing grooves of the other side, and a plurality of second dividing grooves of the other side are formed back-to-back with the plurality of second dividing grooves of the other side. In step (B), an amorphous insulating layer is formed on the inner circumferential surface of each of the plurality of first dividing grooves along the entire length of each of the plurality of first dividing grooves; an amorphous insulating layer is also formed on the inner circumferential surface of each of the plurality of second dividing grooves along the entire length of each of the plurality of second dividing grooves; and an amorphous insulating layer is formed on the inner circumferential surface of each of the plurality of other first dividing grooves along the entire length of each of the plurality of other first dividing grooves; and an amorphous insulating layer is also formed on the inner circumferential surface of each of the plurality of other second dividing grooves along the entire length of each of the plurality of other second dividing grooves. In step (C), a first dicing groove is formed at the bottom of each of the plurality of other first dicing grooves, the first dicing groove dividing the insulating layer of each of the plurality of other first dicing grooves in the width direction of each of the plurality of other first dicing grooves, and the first dicing groove extends along the extension direction of each of the plurality of other first dicing grooves. Furthermore, a second dicing groove is formed at the bottom of each of the plurality of other second dicing grooves, the second dicing groove dividing the insulating layer of each of the plurality of other second dicing grooves in the width direction of each of the plurality of other second dicing grooves, and the second dicing groove extends along the extension direction of each of the plurality of other second dicing grooves. The portion of the main surface of the other side of the wafer located on both sides of a selected portion of the plurality of other first dicing grooves is supported. Subsequently, in step (D), for the first dividing groove of one of the selected sections, the tip of the cutting blade is pressed against the first dividing groove of the other section so that, when viewed from the pressing direction of the tip, the tip extends overlapping with the first dividing groove of the other section, thereby dividing the wafer in a fracture manner. For the wafer fragment obtained in process (D), process (E) is performed as follows: The portions on both sides of a selected second dividing groove in one of the plurality of second dividing grooves on the other main surface of the wafer are supported, and... Then, for the second dividing groove of the selected one, the following step (F) is performed: the tip of the cutting blade is pressed against the second dividing groove of the one side in such a way that the tip extends overlapping with the second dividing groove of the one side when viewed from the pressing direction of the tip, thereby dividing the fragment in a fracture manner.

7. The wafer dicing method according to claim 6, wherein, The selection in step (C) is performed on the first partition slot of one of the plurality of parties that has not yet been selected, and the selection in step (E) is performed on the second partition slot of one of the plurality of parties that has not yet been selected, and these selections are performed until all the first partition slots and the second partition slots of the parties are selected.

8. The wafer dicing method according to claim 1, wherein, The thickness of the insulating layer is greater than 5 μm and less than 100 μm.

9. The wafer dicing method according to claim 1, wherein, In the process (D), at least the tip of the cutting blade is pressed against the insulating layer located at the bottom of the first dividing groove in such a way that the tip extends overlapping with the first dividing groove when viewed from the pressing direction of the tip, thereby dividing the wafer in a fracture manner.

10. The wafer dicing method according to claim 1, wherein, The blade tip angle of the cutting blade is less than 90 degrees.

11. The wafer dicing method according to claim 1, wherein, The wafer is made of GaN grown on a Si, InP, or Si substrate via a buffer layer.

12. The wafer dicing method according to claim 1, wherein, The insulating layer is made of glass.

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