Single transistor reservoir computer using bti

Abstract

A reservoir computing method (700) and related system (100) are disclosed. The reservoir computing system includes at least one non-linear computing node (103) with a computing node MOSFET (113), a drive circuit (110) coupled with the at least one non-linear computing node (103), and a readout unit (104) for acquiring an output sequence associated with the at least one non-linear computing node (103). The MOSFET has charge trapping sites positioned in a gate dielectric that exhibit a bias temperature instability when subjected to a voltage stress and exhibit a threshold voltage recovery after removal of the voltage stress. The drive circuit is configured to apply an input pulse and a readout pulse to a gate of the MOSFET. The readout unit (104) is configured to detect a current flowing through a channel region of the MOSFET when the drive circuit is applying the readout pulse. The readout pulse has a smaller voltage amplitude than the input pulse.

Description

Technical Field

[0001] This invention relates to the field of time series processing and related processing systems, and more specifically to a transistor-based reservoir calculation method and system.

[0002] Background of the Invention

[0003] Pool computing is an alternative computing scheme that leverages the transient behavior of complex dynamic systems. In a traditional pool computer, a large number of interconnected nonlinear computing nodes form a computing network, or pool, where complex spatiotemporal patterns are stimulated by time-dependent input data. Readout layers are trained to predict future inputs or classify inputs based on patterns observed in the pool (which are elements of a high-dimensional feature space). Unlike most neural networks (such as deep neural networks, convolutional neural networks, or recurrent neural networks), the internal connections between the computing nodes in a pool computer are stochastic and untrained. Due to their large number of computing nodes, traditional pool computers lack resource efficiency and compactness. Furthermore, truly random connections between computing nodes are difficult to implement in hardware.

[0004] In the article by Appeltant, L. et al., " Information processing using a single dynamic node as complex system ( Using a single dynamic node as the information processing method for complex systems A single-node reservoir computer with delayed dynamics has been described in *Nature Communications* (2:468 (2011)). In this model, the time input is first multiplied by a sequence of column input weights (masks), then time-multiplexed to form an input stream leading to a single nonlinear node (analog electronic oscillator circuit). The outputs from the nonlinear node are placed as virtual nodes (time slots) on the delayed feedback line and retrieved from there by a linear readout layer. More precisely, the readout layer combines information from many virtual nodes, similar to how the readout layer of a conventional reservoir computer combines the outputs of many physical nodes. This delayed-feedback single-node reservoir computer is more resource-friendly than conventional reservoir computers but requires a complex, dedicated analog electronic oscillator as the nonlinear node. Digital-to-analog and analog-to-digital conversions are applied before and after the nonlinearity, respectively. More energy-efficient and area-efficient computing nodes are still needed.

[0005] The article by Du, C. et al. Reservoir computing using dynamic memristors for temporal information processingA reservoir computer using dynamic memristors for time-domain information processing is disclosed in Nature Communications (8:2204 (2017)). WOx memristors are selected from a 32×32 cross array fabricated on a custom PCB. A drawback of memristor-based reservoir computers is their use of non-standard components and materials, making them more difficult to integrate with mainstream CMOS technologies.

[0006] Therefore, there is a need for energy-efficient storage pool computers that can be easily integrated with existing manufacturing technologies. Summary of the Invention

[0007] The purpose of this invention is to provide an energy-efficient nonlinear computing node for a reservoir computer that can be easily integrated with existing manufacturing technologies.

[0008] The above objectives are achieved by the method and apparatus according to the present invention.

[0009] Bias temperature instability (BTI) effects (negative or positive bias) are well-known transistor aging and degradation effects that negatively impact transistor performance and can disrupt the proper functioning of transistor-based integrated circuits, including signal processing circuits. Therefore, BTI is generally considered a reliability issue in the design and operation of metal-oxide-semiconductor field-effect transistors (MOSFETs) and related computer hardware, including signal processing circuits. Extensive research has been conducted to mitigate or suppress this effect, both through improvements in device fabrication and material selection, and by adding dedicated circuitry designed to compensate for or restore BTI. Surprisingly, the inventors found that bias temperature instability effects can be beneficial in unconventional computing methods and related systems, where the cycle history-dependent threshold voltage offset provides MOSFETs with both short-term memory and enhanced output nonlinearity—two fundamental characteristics of reservoir computing.

[0010] On one hand, the present invention relates to a method for calculating a storage pool, comprising the following steps: A MOSFET is provided as a nonlinear computing node in a reservoir computing system. The MOSFET includes a channel region, a gate stack formed above the channel region, and charge trapping sites in the gate dielectric of the gate stack. The MOSFET exhibits bias temperature instability when subjected to voltage stress and threshold voltage recovery when the voltage stress is removed, wherein the relaxation time constant spectrum characterizing the threshold voltage recovery spans multiple orders of magnitude. Provides a pulse waveform representation of the time-related input signal to be processed, the pulse waveform representation including the input pulse sequence; The input pulse sequence is applied to the gate terminal of the MOSFET, each input pulse having a voltage amplitude greater than the threshold voltage of the MOSFET, thereby causing a cycle history-dependent offset in the threshold voltage in response to the input pulse sequence; An output sequence associated with the nonlinear computing node is acquired by repeatedly applying readout pulses to the gate terminal of the MOSFET while simultaneously detecting the current flowing through the MOSFET channel region, wherein the readout pulses have a smaller amplitude compared to the input pulses.

[0011] In embodiments of the invention, the readout pulse can bias the MOSFET in the subthreshold region. The readout pulse can be applied at regular time intervals.

[0012] In embodiments, a read pulse can be applied after each write pulse or after a predetermined number of consecutive write pulses. A read pulse can be applied after a predetermined delay relative to the first write pulse, for example, after the nth (where n>1) write pulse. Write pulses can be applied at regular time intervals, for example, at an input / write pulse rate that keeps the MOSFET-based computing node in transient mode. This means that the write pulses continuously perturb the MOSFET threshold dynamics and prevent the MOSFET-based computing node from reaching an equilibrium state (e.g., an equilibrium threshold voltage). This is typically achieved by applying write pulses consecutively, such that the time interval between any two write pulses is shorter than one of the relaxation time constants of the MOSFET threshold voltage dynamics. Conversely, typical read pulses are selected such that the reservoir state (e.g., MOSFET threshold dynamics) is not perturbed or is only minimally perturbed, thus preventing the read pulse from acting in the same way as the write pulse. This means that the application of each read pulse does not cause a substantial change in the MOSFET threshold dynamics. This is typically achieved by reducing the amplitude and / or duration of the read pulse relative to the write pulse.

[0013] In embodiments of the invention, each MOSFET-based computing node of the reservoir computing system can be reset before transmitting a pulse sequence corresponding to a new time-dependent input signal. The reset can be a hard reset, which drives the MOSFET's threshold voltage back to its equilibrium (e.g., steady-state value). Alternatively, a reset can be performed for a different threshold voltage.

[0014] In other embodiments, a reset is not performed before transmitting the pulse sequence corresponding to the new time-dependent input signal. In fact, due to the well-known decaying memory characteristics of reservoir computing systems, the reservoir state (e.g., MOSFET threshold voltage) depends only on the most recent past input, not on the initial conditions. Therefore, the readout pulse can be applied with a time delay relative to the start time of the write pulse sequence, making the MOSFET threshold voltage independent of the initial conditions. Alternatively, the current measurements obtained for each readout pulse can be accumulated or time-averaged, such that for a sufficiently long write pulse sequence, the contribution of the initial conditions to the accumulated or time-averaged current becomes very small.

[0015] In another embodiment, a pre-established and fixed initialization write pulse sequence is applied before each new input write pulse sequence, and no reset is performed before transmitting the pulse sequence corresponding to the new time-dependent input signal. The effects of the initialization conditions have disappeared by the time the initialization sequence has been applied to the MOSFET-based computing node of the reservoir.

[0016] In another aspect, the present invention relates to a reservoir computing system comprising at least one nonlinear computing node, a driving circuit coupled to the at least one nonlinear computing node, and a readout unit for acquiring an output sequence associated with the at least one nonlinear computing node. Each of the one or more nonlinear computing nodes includes a computing node MOSFET having a channel region, a gate stack formed over the channel region, and charge trapping sites located in the gate dielectric of the gate stack. Therefore, the computing node MOSFET exhibits bias temperature instability under voltage stress and threshold voltage recovery after the voltage stress is removed. The relaxation time constant spectrum characterizing the threshold voltage recovery spans multiple orders of magnitude. The driving circuit is configured to encode a time-dependent input signal to be processed by the at least one nonlinear computing node into an input pulse sequence (e.g., a pulse train), and apply each input pulse in the input pulse sequence to the gate terminal of the computing node MOSFET. Each generated input pulse has a voltage amplitude greater than the threshold voltage of the computing node MOSFET. The input pulse sequence thereby causes a cycle history-dependent offset in the threshold voltage. The threshold voltage offset is typically bounded and occurs between the minimum and maximum values ​​of the threshold voltage. The drive circuit is also configured to repeatedly generate and apply readout pulses to the gate terminal of the computing node MOSFET. The readout unit is configured to detect the current flowing through the channel region of the computing node MOSFET when the drive circuit is applying the readout pulse to the gate terminal of the computing node MOSFET. The readout pulse has a smaller voltage amplitude compared to the input pulse.

[0017] Embodiments of the present invention allow for the implementation of resource-friendly computing nodes in reservoir computing systems. Using standard field-effect transistors (e.g., CMOS-MOSFETs or CMOS-compatible MOSFETs) as computing nodes in reservoir computing systems according to embodiments of the present invention can achieve significant improvements in energy efficiency and area efficiency. Embodiments of the present invention have the advantage of being easily integrated with existing manufacturing technologies (e.g., mainstream CMOS).

[0018] According to embodiments of the invention, a computing node can cause the MOSFET to operate in subthreshold or near-subthreshold mode by applying a low-voltage pulse to the MOSFET gate, while being advantageously read out in low-power mode.

[0019] Computing nodes according to embodiments of the present invention inherently possess short-term memory. Therefore, fewer computing nodes are required in embodiments of the present invention compared to large networks of computing nodes in conventional reservoir computing systems. In some embodiments of the present invention, the reservoir computing method can be executed using only a single computing node.

[0020] The advantage of the embodiments of the present invention is that it does not require random connections between the computing nodes of the reserve pool, which is difficult to implement in hardware.

[0021] Another advantage of embodiments of the present invention is that the MOSFET, as a computing node, provides strong nonlinearity in its output. The readout current of a MOSFET operating in or near subthreshold mode depends in a highly nonlinear manner on the instantaneous threshold voltage of the transistor, which is offset due to the bias temperature instability (BTI) effect.

[0022] Embodiments of the present invention that use write pulses with constant voltage amplitude have the additional advantage of eliminating the need to design dedicated analog electronic circuitry for computing nodes.

[0023] The advantage of embodiments of the present invention is that it can process time information that evolves on very different time scales. The time series or time sequence of the input signal can be sampled and processed at different rates, for example, sampling intervals from nanoseconds to hours or even days. This is a result of the wide range of time constants present in the threshold voltage offset decay characteristics under the BTI effect.

[0024] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claims and other dependent claims, not merely as expressly set forth in the claims.

[0025] For the purpose of summarizing the invention and its advantages over the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all such objects or advantages may be achieved according to any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention can be embodied or practiced in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0026] The above and other aspects of the invention will be apparent from the embodiments described below and will be illustrated with reference to the embodiments.

[0027] Brief description of the attached figures

[0028] The invention will now be further described by way of example with reference to the accompanying drawings, in which: Figure 1 A reservoir calculation system according to a first embodiment is shown.

[0029] Figure 2 This is a schematic cross-sectional view of a computing node MOSFET according to an embodiment of the present invention.

[0030] Figure 3 The electrical IV behavior of a computing node MOSFET according to an embodiment of the present invention is illustrated under different threshold voltage offsets.

[0031] Figure 4 A reservoir calculation system according to a second embodiment is shown.

[0032] Figure 5 A reservoir calculation system according to a third embodiment is shown.

[0033] Figure 6 A reservoir calculation system according to a fourth embodiment is shown.

[0034] Figure 7 and Figure 8 The steps of a reservoir calculation method according to an embodiment of the present invention are shown.

[0035] These accompanying drawings are merely illustrative and not restrictive. In the drawings, some elements may be enlarged and not drawn to scale for illustrative purposes. Scale and relative scale do not necessarily correspond to an actual simplification of the practice of this invention.

[0036] Any reference numerals in the claims should not be construed as limiting the scope.

[0037] In different accompanying drawings, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0038] The invention will be described with respect to specific embodiments and with reference to certain accompanying drawings, but the invention is not limited thereto, but is defined only by the claims.

[0039] It should be noted that the term "comprising" as used in the claims should not be construed as limiting itself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the features, integers, steps, or components stated as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of the statement "an apparatus comprising means A and B" should not be limited to an apparatus consisting solely of components A and B. This means that for the present invention, the only relevant components of the apparatus are A and B.

[0040] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in an embodiment" or "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, as will be apparent to those skilled in the art from this disclosure, particular features, structures, or characteristics may be combined in any suitable manner.

[0041] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this approach of the disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive aspect lies in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the appended claims are thus explicitly incorporated into this detailed description, wherein each claim itself represents a separate embodiment of the invention.

[0042] Furthermore, although some embodiments described herein include some features included in other embodiments but not all other features included in those other embodiments, as will be understood by those skilled in the art, combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments.

[0043] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention can be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0044] In the context of this invention, reservoir computation relates to an unconventional computational method that uses a fixed nonlinear physical system (referred to as a reservoir or reservoir layer) to map input signals to a higher-dimensional state space for subsequent computation. The input signals are time-dependent signals that continuously perturb the nonlinear physical system, driving it from a stable point to transient patterns. Subsequent computation typically involves training the parameters of the readout layer to perform signal recognition, classification, or prediction tasks, or to generate rhythmic output patterns. Transient signals from the reservoir are used as observation data (training data) during readout layer training. The reservoir typically comprises one or more nonlinear units, hereinafter referred to as nonlinear computation nodes.

[0045] The transient computation aspect of reservoir computing systems is well-known. Reservoir computing systems are dynamic, typically nonlinear systems, operating far from equilibrium (e.g., under unsteady conditions). Clearly, meaningful readout signals can only be obtained when a readout pulse is applied to the computing node of a MOSFET-based reservoir computing system while it is in transient mode.

[0046] Another known aspect of reservoir computing systems is the "decay memory" property, meaning that the reservoir state (i.e., the instantaneous threshold voltage of each MOSFET-based computing node) depends on recent past inputs (i.e., write pulses) and is independent of inputs from the distant past. In other words, the reservoir has a persistent tendency to forget its distant history, and of course, its initial conditions. Technically, the reservoir response signal x(t) at time t is uniquely defined by the decay history of the input sequence u(t), rather than by the initial condition x(0) of the reservoir. Although reservoirs can operate on the "edge of chaos," they do not exhibit chaotic behavior. In this sense, reservoirs differ from truly chaotic systems, where small perturbations to the input can have dramatic consequences for the system state. In contrast to chaotic systems, reservoir computing systems remain predictable.

[0047] When referring to a "relaxation time constant spectrum characterizing threshold voltage recovery," it means that the recovery of the MOSFET threshold voltage exhibits a definite dynamic behavior, which can be described by multiple relaxation time constants (e.g., a relaxation time constant spectrum) that appear at multiple time scales or are distributed within a certain range. The range or distribution of relaxation time constants associated with MOSFET threshold recovery kinetics is described as "spanning multiple orders of magnitude." This means that the range or distribution of relaxation time constants associated with MOSFET threshold recovery kinetics is increased by multiple factors of ten, such as 0.1–10, 1–100, 10–1000, which is consistent with the common technical meaning of "order of magnitude." In other words, the range of relaxation time constants associated with MOSFET threshold recovery kinetics makes the ratio of the longest relaxation time constant to the shortest relaxation time constant a multiple of ten. That is to say, "order of magnitude" does not refer to a ten-year timeframe, as that would be too long for a reservoir computing system to produce useful computational results in everyday life.

[0048] Regarding the higher-dimensional state space used for subsequent calculations, there are various ways to obtain the feature vector representing the reservoir state. In a single-node reservoir system, different readouts over time (e.g., the reservoir response sequence x[k]) can be organized into a feature vector. For example, each term of the response sequence can be used as a different entry / component of the feature vector, thereby obtaining a high-dimensional feature vector. In embodiments of the present invention, current measurements for different readout pulses can be arranged into a feature vector.

[0049] Furthermore, input masking techniques are known in the art, which create numerous virtual nodes for a reservoir consisting of only a single physical node. Physical nodes are spatial nodes where nonlinearity exists, while virtual nodes are temporal nodes based on time-multiplexed inputs using different mask weights. Nonlinearity and decaying memory on the spatial nodes couple to adjacent virtual nodes. Similarly, in these types of reservoirs, high-dimensional feature vectors can be obtained by reading the reservoir response signal of each virtual node and arranging the virtual node signals into a feature vector. For feedback loops including spatial nodes, time averaging of the virtual node readouts obtained over multiple loop round-trip times can be performed. In embodiments of the present invention, a single MOSFET-based computing node can be selected as the spatial computing node, and numerous temporal / virtual nodes can be created using input masks, which can be read out individually to obtain high-dimensional feature vectors.

[0050] Ultimately, in a multi-node (spatial node) reservoir, the reservoir response can be read out over time at each spatial reservoir node. The response sequences from different reservoir nodes can be concatenated into a high-dimensional feature vector. Alternatively, the reservoir response can be read out at each spatial node and accumulated or averaged over time. The accumulated or time-averaged readout signals for different spatial nodes can be used as entries / components of the high-dimensional feature vector. In embodiments of the invention, the multiple computing nodes of the reservoir computing system can be MOSFET-based, and the readout current measurements obtained for the MOSFET-based computing nodes can be assembled into a high-dimensional feature vector, optionally accumulated or averaged over time for each MOSFET-based computing node.

[0051] In a first aspect, the present invention relates to a reservoir computing system for processing time information, comprising at least one MOSFET-based nonlinear computing node. Here, the time information typically relates to any type of time-dependent signal, continuous-time or discrete-time signal, which can be represented as a time series, a time sequence, or a data stream. This includes static spatial data that has been serialized into a data stream, such as image or video frames, for example, a bitstream representing pixels from a raster scan of an image or video frame.

[0052] Figure 1 A reservoir computing system 100 according to a first embodiment is shown. The reservoir computing system 100 includes a nonlinear computing node 103, a drive circuit 110 coupled to the nonlinear computing node 103, a readout unit 104 coupled to the nonlinear computing node 103, and a control unit 105 coupled to the drive circuit 110 and the readout unit 104. The control unit is capable of setting the operating mode of the drive circuit via appropriate control signals, which can switch between a write mode and a read mode.

[0053] The output of the drive circuit 110 is coupled to the gate terminal of the computing node MOSFET 113, while the readout unit 105 is connected to one of the source / drain terminals of the computing node MOSFET 113. The drive circuit 110 receives time-dependent signals (e.g., time series, time data sequences, or time-varying data streams) as system input and, when operating in write mode, is configured to encode the system input as a sequence of pulses, such as a pulse-based digital representation of the input data by means of pulses in a pulse wave or a pulse-based digital representation of features extracted from the input data. Existing pre-trained feature extractors can be used to extract a set of features from the input data, and can even be fine-tuned for the specific application of the MOSFET-based computing node. Furthermore, the drive circuit 110 is adapted to generate voltage pulses based on the pulse-encoded input data and delivers the generated voltage pulses to the gate of the computing node MOSFET 113 when operating in write mode. Conversely, the drive circuit 110 is configured to repeatedly generate readout pulses at regular time intervals when operating in read mode, such as at least one readout pulse after a predetermined number of sampling time steps of the input signal (e.g., one readout pulse after each sampling time step). As will be explained further below, the voltage amplitude of the input pulse (also known as the write pulse) must exceed the instantaneous threshold voltage of the compute node MOSFET 113, causing the MOSFET to turn on and the threshold voltage to begin drifting due to the BTI effect. This can be ensured by boosting the write pulse to a sufficiently high voltage level “VP” greater than the expected maximum value of the threshold voltage offset under the BTI effect. Compared to the read pulse, the input pulse has a larger voltage amplitude and / or duration. The drive circuit 110 can generate a read pulse with a voltage amplitude less than or slightly higher than the threshold voltage of the compute node MOSFET 113, for example, less than or slightly higher than the minimum achievable threshold voltage of the compute node MOSFET 113 (e.g., the initial or minimum threshold voltage of the MOSFET that can be recovered after a very long relaxation time). This allows for a significant reduction in the amount of read current flowing through the channel of the compute node MOSFET 113, resulting in energy savings. This is especially true if the voltage amplitude of the read pulse is lower than the threshold voltage of the compute node MOSFET 113, causing the MOSFET 113 to operate in subthreshold mode.

[0054] Time-related information contained in the system input can be encoded as at least one of the following variables characterizing the pulse sequence: pulse amplitude, pulse duration, pulse interval, pulse position, pulse shape (e.g., triangular and trapezoidal), or pulse density. In some embodiments of the invention, time-related information is encoded as multiple variables of the pulse sequence, such as pulse amplitude and pulse duration. For digital implementation, an encoding scheme with a constant write pulse amplitude is preferred. However, an encoding scheme using pulse amplitude modulation combined with analog drive circuitry is also feasible. The amplitude of the system input data points is represented wholly or partially by the amplitude of the write pulse. Furthermore, the selection of the write pulse voltage has the added advantage of allowing controlled modification of the time constant of the response defects in the gate dielectric, thereby allowing tuning of the BTI effect for a specific input sequence. Each dataset type of interest can be associated with an optimal voltage for the corresponding write pulse. In this way, the same reservoir computing hardware can be used for many different applications.

[0055] Continuous-time signals can be sampled and quantized by the drive circuit 110 before being converted into pulse sequences, or discrete-time signals can be resampled. Alternatively, separate sampling and / or quantization units can be provided. In this embodiment, the drive circuit includes an encoder unit 101 and a pulse generator unit 102 as sub-components, but this distinction may not be necessary in alternative embodiments. The encoder unit 101 is configured to encode the system input into a digital pulse train, and the pulse generator unit is configured to drive the compute node MOSFET 113 according to the digital pulse train when the compute node 103 is operating in write mode, for example by generating a corresponding voltage pulse sequence and applying each voltage pulse to the gate terminal of the compute node MOSFET 113. During read mode, the pulse generator unit 102 is configured to generate one or more read pulses at a corresponding read voltage level and apply the read pulses to the gate of the compute node MOSFET 113. In alternative embodiments of the invention, a separate pulse generator or drive circuit may be provided in addition to the drive circuit 110 as a means of providing read pulses in read mode. In embodiments of the invention where the system input is provided in the form of a burst of pulses, the encoder unit 101 may be omitted or skipped. The readout mode may be repeatedly triggered by the control unit 105 at regular time intervals, for example, generating a read interrupt signal if a clock counter reaches a predetermined count. The hardware implementation of the drive circuitry includes, but is not limited to, existing control circuitry for pulse width modulation and / or pulse code modulation.

[0056] The readout unit 104 is configured to detect the current flowing through the channel region of the computing node MOSFET 113 when the drive circuit 110 is applying a readout pulse to the gate terminal of the computing node MOSFET 113 (e.g., during readout mode). The readout cycle can be initiated by a timely interrupt signal issued by the control unit 105. Through repeated current measurements, the readout unit 104 acquires an output sequence associated with at least one nonlinear computing node 103. This output sequence corresponds to a processed version of the input signal, the processing of which is performed by the nonlinear electrical characteristics of the computing node MOSFET 113, which are directly dependent on the threshold voltage offset and indirectly dependent on the input history due to the dependence of the threshold voltage offset on the cycle history. During the readout cycle, the computing node MOSFET 113 experiences negligible voltage stress, or no voltage stress at all. Therefore, the instantaneous threshold voltage of the computing node MOSFET 113 remains almost unaffected or not shifted at all. The hardware implementation of the readout unit includes, but is not limited to, existing circuitry for current sensing, such as a current sense amplifier. Alternatively or additionally, the readout unit 104 may also include a current-to-voltage converter (e.g., a transimpedance amplifier) ​​and / or an analog-to-digital converter. Therefore, the output sequence obtained by the readout unit can be a current or voltage signal in the digital or analog domain.

[0057] The specific output format (current or voltage, digital or analog) can be determined based on the requirements of any optional neural network layer (such as a readout layer (linear regression, ridge regression, logistic regression) or a hidden layer of a subsequent neural network). The data points of the output sequence—calculated by nonlinear computation nodes in response to the system input signal—are components of the state-space vector of the reservoir computation system. This state-space vector can be interpreted as a higher-dimensional feature vector in the reservoir computation space. The output sequence can be output directly or optionally further processed, for example, used as input to a readout layer or a hidden neural network layer.

[0058] refer to Figure 2A schematic cross-sectional view of a computing node MOSFET according to an embodiment of the present invention is shown. MOSFET 213 includes a source region and a drain region and associated contact terminals, a channel region 21, and a gate stack 22 formed over the channel region 21. In the inversion mode of MOSFET 213, the channel region 21 is induced by an applied gate voltage "VG" exceeding the threshold voltage "VT" of the transistor device. The conductive channel region 21 may be located near the interface with the gate stack 22 or may be buried in the substrate 25. Charge trapping sites 24, as defects, are located in the gate dielectric 23 of the gate stack 22 (e.g., within the volume of the gate dielectric and / or at the interface between the gate dielectric 22 and the substrate 25). Therefore, the computing node MOSFET 213 is subject to bias temperature instability (BTI) effects under voltage stress and undergoes threshold voltage recovery after the voltage stress is removed. In embodiments of the present invention, the relaxation time constant spectrum characterizing the threshold voltage recovery spans multiple orders of magnitude. In fact, different defects are associated with different trapping and emission rates, and therefore with different timescales; the sum of all defects produces a wide range of relaxation spectra. The different trapping and emission rates are determined by the structural characteristics of the defects and their position relative to the channel region. This wide timescale range typically stems from the amorphous nature of the gate dielectric (e.g., oxide). Here, the relaxation spectrum range, spanning multiple orders of magnitude, can range from nanoseconds or microseconds to seconds, hours, or even months, for example, including six or more orders of magnitude, such as ten or more orders of magnitude, such as twelve or more orders of magnitude.

[0059] In a preferred embodiment of the invention, MOSFET 213 is pMOS type. The positive BTI effect in pMOS MOSFETs is very significant in shrinking manufacturing techniques, especially those using high-k gate dielectrics, and when the gate voltage is slightly above the nominal operating voltage. This enhances the short-term memory capability and nonlinear behavior of the MOSFET, both of which are important in the framework of reservoir calculations. However, the BTI effect can also be obtained in nMOS MOSFETs. It should be understood that in the case of pMOS-MOSFETs, the write pulse voltage level “VP” and the read pulse voltage level “VRO” are negative, while for nMOS-MOSFETs they are positive, and the absolute value of the threshold voltage increases under voltage stress (i.e., the amplitude increases regardless of the sign). The gate dielectric of the gate stack can include oxides (e.g., thermal SiOx), high-k materials (e.g., HfOx), nitrides (e.g., SiN), or oxide nitrides. Unlike FETs, which require thin sheets (e.g., monolayer sheets) of unconventional semiconductor materials such as graphene or dichalcogenides and are therefore difficult to integrate with existing manufacturing technologies such as mainstream CMOS, the channel region of a computing node MOSFET includes bulk (i.e., 3D) semiconductor material.

[0060] Figure 3 The electrical IV behavior of a computational node MOSFET is illustrated at three different threshold voltage offsets. The horizontal axis represents the gate voltage (arbitrary units), while the vertical axis represents the source-drain current flowing through the MOSFET channel region (logarithmic scale; arbitrary units). All three curves show that as the applied gate voltage “VG” approaches the instantaneous threshold voltage “Vth”, the on-state source-drain current increases sharply and begins to saturate above this threshold voltage. The increase in current flowing through the MOSFET channel is accompanied by an increase in MOSFET conductance; the MOSFET switches from a low-conductance state to a high-conductance state. In the context of this invention, the voltage pulse that causes the switch from a low-conductance state to a high-conductance state is also referred to as a write pulse or a switching pulse. For example, in a typical pMOS MOSFET, the offset threshold voltage can be in the range of -0.1V to -0.5V, while the write pulse is applied with an amplitude of -1.5V. When the gate voltage is reduced below the instantaneous threshold voltage “Vth”, the source-drain current amplitude decreases exponentially rapidly. In the subthreshold region, the MOSFET conducts only a very small amount of leakage current through the channel region, for example, less than 10 nA, less than 1 nA, or between 1 nA and a few picoamps. The MOSFET is a volatile switch because the information stored in the conductance state is inevitably lost in the absence of a gate voltage. Multiple charged defects in or at the gate dielectric determine the magnitude of the instantaneous threshold voltage and the size of the source-drain current in readout mode. Under the constant readout voltage “VRO” of the readout pulse applied during the readout cycle, even a small shift in the MOSFET threshold voltage will cause a substantial change in the amount of subthreshold current “Iread” detected during readout operation. Therefore, the cycle history-dependent variation of the threshold voltage of the MOSFET in a computing node enhances the nonlinear output behavior of the computing node and enables the differentiation of different system input signals, even with small differences. The specific value of the readout voltage “VRO” depends on the details of the MOSFET and the speed and sensitivity requirements of the readout cell, which may vary from application to application. A typical readout current “Iread” will be in the nanoamp range, for example, about 10 nA.

[0061] from Figure 3The electrical characteristics of a MOSFET are understandable. When a write pulse is applied to the MOSFET gate, it exhibits switching behavior from a low-conductance state to a high-conductance state, and returns to a low-conductance state if the applied voltage signal is removed again or becomes insignificant relative to the threshold voltage. This completes one switching cycle, during which the MOSFET is subjected to voltage stress, and defect sites in the gate dielectric trap mobile carriers attracted from the underlying channel region. Between successive switching cycles, at least some of the trapped charge is released, and the charged defect sites become neutral again, resulting in relaxation of the threshold voltage. This means that the value of the threshold voltage drifts as a function of the relaxation time. Here, the relaxation time refers to the period of time during which the MOSFET is not subjected to any voltage stress above the threshold, such as the time interval between successive switching cycles determined by the individual switching pulses. At the end of each relaxation time interval, the MOSFET's threshold voltage moves to a new instantaneous threshold voltage level "Vth," which is then raised again by the next write pulse. For MOSFETs, as the relaxation time interval becomes longer, a decrease in the threshold voltage towards its initial value is observed. Interestingly, threshold voltage relaxation is observable over a very wide range of relaxation time intervals—from short intervals of a few nanoseconds to longer intervals in the range of milliseconds and seconds, and even very long intervals of hours to days or even months. In other words, the timescale of threshold voltage relaxation dynamics spans many orders of magnitude. The advantage of this is that readily available MOSFETs can handle input data sequences with very different timescales. Furthermore, the relaxation dynamics of the threshold voltage also depend on the cycle history, i.e., the number, timing, and duration of all past write pulses.

[0062] In embodiments of the invention, the pulse amplitude and / or duration are preferably selected to be sufficiently small to prevent or minimize any permanent damage to the MOSFET gate dielectric, and thus prevent any permanent shift in the threshold voltage. Nevertheless, initial and / or periodically performed calibration steps also allow for the elimination of any persistent shift in the threshold voltage within the MOSFET device.

[0063] Threshold voltage relaxation and cycle history dependence in MOSFETs are generally considered reliability issues because they impair optimal switching operation. There is a constant search for ways to reduce or eliminate them. The inventors have discovered that, contrary to popular prejudice, these phenomena can be advantageously used in the computational nodes of reservoir computing systems that operate on time series, such as sequential input data or time sequences. Notably, MOSFET threshold voltage relaxation provides short-term memory to reservoir computing nodes, while the cycle history dependence of threshold voltage offset gives them the ability to distinguish between different input data sequences. Furthermore, during the readout cycle, the source-drain current in the MOSFET subthreshold region is a nonlinear function (e.g., an exponential function) of the difference between the instantaneous threshold voltage and the applied readout voltage. This advantageously amplifies the differences that exist between separable input data sequences. Here, the nonlinearity of the readout in the subthreshold region further enhances the inherent nonlinearity and random behavior of the threshold voltage offset. The readout voltage pulse can be sufficiently short (e.g., about 1 µs or less, or about 1 ns or less) and has a lower amplitude than the write pulse. Therefore, the stress applied to the MOSFET is minimized, and the application of the readout pulse only minimally interferes with or has no effect on the threshold voltage relaxation dynamics. The aforementioned properties—short-term memory, input separability, and output nonlinearity—are often referred to as fundamental computational properties in the context of transient signal computation, reservoir computation, and echo state networks. In this sense, every readily available MOSFET can be used in computational nodes for time-signal processing, where the internal dynamics of the threshold voltage are state variables affecting the nonlinear input-output behavior (transfer function) of the computational node. As described above, input data sequences with very different time scales can be processed.

[0064] Figure 4 A reservoir calculation system 400 according to a second embodiment is shown.

[0065] The reservoir system 400 differs from the reservoir system of the first embodiment in that a delay line 106 is connected between the output of the readout unit 104 and the gate terminal of the computing node MOSFET. This additional delay feedback has the advantage of enriching the dynamic behavior of the nonlinear computing node and the entire reservoir computer. Furthermore, the delay feedback can be combined with the input masking taught in the article “Information processing using a single dynamical node as complex system” by Appeltant, L. et al., Nature Communications (Nature Communications 68 (2011)). In this case, the delay time interval is attributed to the delay line 106 and subdivided into multiple virtual nodes (i.e., physical nodes that have been mapped to the time domain). The output sequence obtained by the readout unit 104 is converted into a sequence of virtual nodes propagating on the delay line 106, from which these virtual nodes can be extracted. The pattern generator 108 is configured to repeatedly generate terms of the mask sequence M[t] (here, bits of the binary mask sequence), which are used by the modulator or multiplier unit 107 to modulate each pulse of the pulse train. This has the effect of mapping each data point of the input signal... The effect is projected into a higher-dimensional input space. The time slot allocated to each item in the mask sequence corresponds to the time length of a virtual node. The resulting mask pulse sequence is processed per time slot by a nonlinear computation node, and the corresponding output is placed on delay line 106 to fill the virtual nodes. Although shown as a digital mask sequence in this embodiment, an analog masking scheme can be implemented in alternative embodiments of the invention to modulate data points of the system input signal instead of the pulse sequence derived from them. Delay line 106 can be implemented using buffered or unbuffered delay lines, data buffers (e.g., FIFO buffers), or other delay circuitry.

[0066] Figure 5An extended reservoir computing system 500 according to a third embodiment is illustrated. The extended reservoir computing system 500 includes a reservoir subsystem 51, which can be selected from any of the foregoing embodiments or variations thereof. Furthermore, the extended reservoir computing system 500 includes an output buffer 54 that stores a portion or all of the output sequence obtained by the readout unit for further processing by a readout layer 52. The readout layer 52 includes one or more output neurons 53 and trainable weighted connections to each element of the output sequence currently stored in the output buffer 54. In embodiments of the invention, the output buffer may be a FIFO-type buffer, a shift register, or a buffered delay line. The output buffer 54 may be refreshed at regular time intervals to allow the storage of new output sequences or portions of output sequences, or stored elements may be popped from the output buffer 54 whenever a newly obtained readout element of the output sequence arrives. The readout layer 52 may be a regression layer. In a variation of this embodiment, an additional neural network layer may be appended after the readout layer 52.

[0067] The reservoir computing system according to embodiments of the present invention accepts scalar time data or signals carrying data. Vector-valued signals can be serialized in embodiments of the invention either by concatenating vector signal components (i.e., appending the time signal to each component to obtain a longer scalar time signal), by time multiplexing the vector signal components, or by processing them component by component in parallel. In the latter case, the scalar implementation components of the reservoir computing system described above can be replicated to provide full support for vector input signals.

[0068] Figure 6 A multi-node reservoir computing system 600 according to a fourth embodiment is illustrated. The extended reservoir computing system 600 includes multiple independent reservoir subsystems 61a-61c, which can be selected as... Figure 1 and Figure 4The foregoing embodiments or variations thereof. Components of multiple input signals or vector input signals can be provided in parallel to the respective input units 63 of the input layer 62. Each input unit 63 of the input layer 62 can be connected to exactly one reservoir subsystem 61a-61c for independently processing multiple input signals or input signal components. Alternatively, the input units 63 of the input layer 62 can be connected to multiple reservoir subsystems 61a-61c, for example, to obtain a linear combination of multiple input signals or input signal components before performing nonlinear computation node processing. Similarly, a readout layer 62 including one or more output neurons 63 can be provided to combine and further process the respective output sequences obtained by the reservoir subsystems 61a-61c. A readout weight is associated with each connection in the readout layer 62 for weighting corresponding data points of the output sequence to obtain a weighted output sequence, and the respective output neurons 63 combine the multiple weighted outputs in the weighted output sequence into one or more output variables. Readout layer 62 can combine the output sequences of the reservoir subsystems on a data point-by-data-point basis, or it can combine sets of data points (e.g., subsequences) from each reservoir subsystem, as described above. Figure 5 As illustrated in the examples. Depending on the desired application, the output variables can be used for regression, prediction, or classification tasks.

[0069] In an embodiment of the invention comprising a set of independently operating MOSFET-based computing nodes, each computing node can receive a digital representation in the form of a pulse wave with different characteristics. If the input data to the reservoir computing system does not represent the extracted features but is closer to the original data format, the driving circuitry of the corresponding MOSFET-based computing node can include a hardware implementation of a trained feature extractor, such as a hardware-implemented neural network. This advantageously increases the readout dimension, thereby increasing the signal separation capability of the reservoir computing system.

[0070] In a preferred embodiment, the reservoir computing system is provided as a single electronic device, such as an integrated circuit or semiconductor chip. Nevertheless, a portion of the drive circuitry and / or any further processing units associated with the output sequence can be implemented on different devices, such as on a server or dedicated hardware of an external service provider (e.g., cloud computing hardware). For example, an encoder unit can be implemented remotely to accelerate the encoding of system inputs into digital pulse trains, or to acquire and store digital pulse trains corresponding to many input signals to create training datasets for faster processing. Similarly, output sequences from many different distributed nonlinear computing nodes can be transmitted to an external computer, where they are combined to train readout layers or subsequent layers of a neural network. The advantage of providing a single device is that it eliminates the need to transmit the encoded input signals of the training dataset to a remote server via a vulnerable network. This is particularly relevant for training data containing private or sensitive information. Furthermore, communication overhead and network latency are avoided in this case.

[0071] The embodiments described so far relate to enhancement-mode computing node MOSFETs. However, anyone skilled in the art will recognize that the same beneficial effects can be achieved in depletion-mode MOSFETs without any inventive skill.

[0072] In another aspect of the invention, a reservoir calculation method is disclosed, which uses a computing node MOSFET according to the foregoing embodiments.

[0073] Figure 7 and Figure 8 The steps of a reservoir calculation method 700 according to an embodiment of the present invention are illustrated. In a first step 701, a MOSFET is provided as a nonlinear computing node of the reservoir calculation system, comprising a channel region, a gate stack formed above the channel region, and charge trapping defect sites located in the gate dielectric of the gate stack. Therefore, the MOSFET exhibits bias temperature instability when subjected to voltage stress and exhibits threshold voltage recovery after the voltage stress is removed. The relaxation time constant spectrum characterizing the threshold voltage recovery spans multiple orders of magnitude.

[0074] Next, in step 702, a pulse waveform representation of the time-dependent input signal to be processed is provided. Here, the pulse waveform representation includes or consists of an input pulse sequence representing the time information contained in the input signal. This step may further include at least one of the following sub-steps: encoding the time-dependent input signal into an input pulse sequence, sampling the continuous-time input signal or resampling the discrete-time input signal, and converting the analog input signal into a digital input signal. Figure 8The bottom and middle sections show the time-dependent input signal and its pulse waveform representation, respectively. Long arrows indicate the presence of a write pulse at a given time step (e.g., the sampling time step) of the input signal, while short arrows indicate the absence of a write pulse. The input signal can be represented as a pulse wave using known pulse coding techniques.

[0075] Then, in step 703, an input pulse sequence is applied to the gate terminal of the MOSFET, where the voltage amplitude of each input pulse is greater than the threshold voltage of the MOSFET. The delivery of each input pulse constitutes a write cycle, during which the MOSFET is subjected to voltage stress. When there are no input pulses at a specific time step or within a certain time step, the threshold voltage of the MOSFET begins to relax towards its initial value. This results in a threshold voltage offset that depends on the cycle history, such as... Figure 8 As shown in the upper part. Preferably, the input signal sequence is a digital signal, so that analog circuitry is not required when driving the gate terminal of the MOSFET, since analog circuitry is more difficult to design and implement than digital circuitry. During this step, the source / drain terminals of the MOSFET can be grounded to avoid power dissipation in the MOSFET. Alternatively, a small voltage difference can be applied between the drain and source terminals to induce a small current in the channel region of the MOSFET, which can be used for monitoring purposes.

[0076] Next, during step 704, the output sequence associated with the nonlinear computing node is acquired by repeatedly applying a readout pulse to the gate terminal of the MOSFET while simultaneously detecting the current flowing through the MOSFET channel region. The readout pulse has a smaller amplitude than the input pulse and is preferably shorter than the write pulse. In some embodiments, the readout pulse amplitude biases the MOSFET in a subthreshold state, and the detected channel current is a subthreshold current. In other embodiments, the readout pulse amplitude biases the MOSFET slightly above the subthreshold state. The readout pulse can be applied at regular time intervals, such as after each sampling time step or after a predetermined number of time steps. The readout cycle can be timed short enough to provide a readout pulse between two consecutive write pulses, but the write cycle can also be interrupted at any time by a programmed readout pulse. During this step, a small voltage difference, such as V(DS) ≈ 0.05 V, is applied between the drain and source terminals to induce a small readout current (e.g., about 10 nA) in the MOSFET channel region.

[0077] Optionally, the reservoir calculation method may include an initialization step for the MOSFET, during which the threshold voltage offset and relaxation time constant are adjusted to desired values. For this purpose, positive and / or negative voltage pulses of varying durations and / or amplitudes can be applied to the MOSFET gate.

[0078] Furthermore, as an optional step, readout weights can be applied to the output sequence to obtain a weighted output sequence. Multiple weighted outputs from this weighted output sequence can then be combined into one or more output variables. This enables the learning and execution of regression or classification tasks based on the detected output current.

[0079] In some embodiments of the present invention, the reservoir calculation method may include additional steps related to the input masking scheme: - Sample the input signal to obtain multiple sampled data points, or provide the input signal as a discrete time series including multiple sampled data points, wherein two consecutive data points are separated by a sampling time interval; - Multiply the mask weights in the alternating pattern of mask weights with each sampled data point of the input signal or the pulse sequence derived from the input signal to obtain a masked input signal or a masked pulse sequence, wherein each mask weight is assigned a fixed time slot, which is a portion of the sampling time interval.

[0080] The reservoir calculation method according to embodiments of the present invention may further include the step of feeding the obtained output sequence back to the gate terminal of the MOSFET of the computing node or a different computing node, and may include a previous current-to-voltage conversion step if necessary.

[0081] By studying the accompanying drawings, this disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plural. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be advantageously used. Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A method for calculating a reserve pool (700), comprising the following steps: A MOSFET (701) is provided as a nonlinear computing node in a reservoir computing system. The MOSFET includes a channel region, a gate stack formed above the channel region, and charge trapping sites in the gate dielectric of the gate stack. The MOSFET exhibits bias temperature instability when subjected to voltage stress and threshold voltage recovery after the voltage stress is removed. The relaxation time constant characterizing the threshold voltage recovery spans multiple orders of magnitude. A pulse waveform representation (702) of the time-related input signal to be processed is provided, the pulse waveform representation including the input pulse sequence; The input pulse sequence is applied to the gate terminal (703) of the MOSFET, each input pulse having a voltage amplitude greater than the threshold voltage of the MOSFET, thereby causing a cycle history-dependent offset in the threshold voltage in response to the input pulse sequence; An output sequence (704) associated with the nonlinear computing node is acquired by repeatedly applying readout pulses to the gate terminal of the MOSFET while simultaneously detecting the current flowing through the MOSFET channel region, wherein the readout pulses have a smaller amplitude than the input pulses.

2. The method as described in claim 1, characterized in that, The readout pulse biases the MOSFET in the subthreshold region.

3. The method as described in any one of the preceding claims, characterized in that, The readout pulses are applied at regular time intervals.

4. The method as described in any one of the preceding claims, characterized in that, During the application of the input pulse, the source / drain terminals of the MOSFET are grounded, while during the application of the readout pulse, a voltage difference is applied between the source / drain terminals.

5. The method of any of the preceding claims, further comprising: Readout weights are applied to the output sequence to obtain a weighted output sequence, and multiple weighted outputs in the weighted output sequence are combined into one or more output variables.

6. The method of any of the preceding claims further comprises: The input signal is sampled to obtain multiple sampled data points, or the input signal is provided as a discrete time series including multiple sampled data points, wherein two consecutive data points are separated by a sampling time interval; The mask weights in the alternating pattern of mask weights are multiplied by each sampled data point of the input signal to obtain the masked input signal, wherein each mask weight is assigned a fixed time slot, which is a portion of the sampling time interval.

7. The method as described in any one of the preceding claims, characterized in that, The step of providing a pulse waveform representation of the time-correlated input signal includes: encoding the time-correlated input signal into a digital pulse train.

8. A reservoir calculation system (100; 400; 500; 600), comprising: At least one nonlinear computing node (103) including a computing node MOSFET (113), the computing node MOSFET including a channel region, a gate stack formed over the channel region, and charge trapping sites in the gate dielectric of the gate stack, such that the computing node MOSFET exhibits bias temperature instability when subjected to voltage stress and exhibits threshold voltage recovery after the voltage stress is removed, wherein the relaxation time constant characterizing the threshold voltage recovery spans multiple orders of magnitude; A driving circuit (110) coupled to the at least one nonlinear computing node (103) and configured to: encode a time-dependent input signal to be processed by the at least one nonlinear computing node into an input pulse sequence, and apply each input pulse in the input pulse sequence to the gate terminal of the computing node MOSFET (113), each input pulse being generated with a voltage amplitude greater than a threshold voltage of the computing node MOSFET, thereby causing a cycle history-dependent offset in the threshold voltage in response to the input pulse sequence; the driving circuit (110) is also configured to repeatedly generate readout pulses and apply the readout pulses to the gate terminal of the computing node MOSFET (113); A readout unit (104) for acquiring an output sequence associated with the at least one nonlinear computing node (103), the readout unit (104) being configured to detect the current flowing through the channel region of the computing node MOSFET (113) when the drive circuit (110) is applying the readout pulse to the gate terminal of the computing node MOSFET, wherein the readout pulse has a smaller voltage amplitude than the input pulse.

9. The reservoir calculation system as described in claim 8, characterized in that, The drive circuit (110) is also configured to generate the readout pulse at a subthreshold voltage amplitude to bias the computing node MOSFET (113) in the subthreshold region.

10. The reservoir calculation system as described in claim 8 or 9, characterized in that, The computing node MOSFET (113) is PMOS type and / or includes a high-k material as the gate dielectric.

11. The reservoir computing system (400) as claimed in any one of claims 8 to 10, further comprising a delay line (106) disposed between the readout unit (104) and the nonlinear computing node (103).

12. The reservoir calculation system (400) of any one of claims 8 to 11, further comprising a masking unit (107, 108) configured to multiply a masking weight in an alternating pattern of masking weights with each of a plurality of sampled data points derived from the input signal, wherein the masking unit is further configured to assign a fixed time slot to each masking weight, the fixed time slot being a portion of a sampling time interval separating two consecutive data points of the plurality of sampled data points.

13. The reservoir computing system (500) of any one of claims 8 to 12 further includes a readout layer (52) configured to apply readout weights to an output sequence associated with the at least one nonlinear computing node to obtain a weighted output sequence, and to combine a plurality of weighted outputs in the weighted output sequence into one or more output variables.

14. The reservoir computing system (600) of claim 13, comprising a plurality of MOSFET-based nonlinear computing nodes, wherein the readout layer (62) is configured to: apply readout weights to the output sequences of the plurality of nonlinear computing nodes and combine the weighted outputs of the plurality of weighted output sequences into one or more output variables.

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