Pixel circuit, driving method and display device

Abstract

This disclosure provides a pixel circuit, a driving method, and a display device. The pixel circuit includes a driving circuit, a first energy storage circuit, a second energy storage circuit, an on / off control circuit, a compensation control circuit, and a writing circuit. A first terminal of the first energy storage circuit is electrically connected to a first node, and a second terminal of the first energy storage circuit is electrically connected to a fourth node. The second energy storage circuit is electrically connected to a fifth node. Under the control of an on / off control signal, the on / off control circuit controls the connection or disconnection between the fourth node and the fifth node. Under the control of a compensation control signal, the compensation control circuit controls the connection or disconnection between the first node and a third node. Under the control of a writing control signal, the writing circuit writes data voltage to the fifth node. This disclosure can separate threshold voltage compensation and data voltage writing, and can fully charge the pixel circuit through data voltage while ensuring display uniformity, thus ensuring display effect.

Description

Pixel circuits, driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0002] With the rapid development of AMOLED (Active-matrix organic light-emitting diode), medium and large-sized tablet computers and laptops have become important future development directions. Customers have increasingly strong demands for high-frequency displays. Existing pixel circuits perform threshold voltage compensation and data voltage writing simultaneously. High-frequency technology leads to line time compression, which cannot effectively compensate for the threshold voltage of the driving transistor in the driving circuit, and thus cannot achieve high-frequency driving.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a first energy storage circuit, a second energy storage circuit, an on / off control circuit, a compensation control circuit, and a writing circuit.

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0006] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node.

[0007] The first terminal of the second energy storage circuit is electrically connected to the fifth node, and the second terminal of the second energy storage circuit is electrically connected to the first voltage terminal.

[0008] The on / off control circuit is electrically connected to the on / off control terminal, the fourth node, and the fifth node, respectively, and is used to control the connection or disconnection between the fourth node and the fifth node under the control of the on / off control signal provided by the on / off control terminal;

[0009] The compensation control circuit is electrically connected to the compensation control terminal, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal.

[0010] The writing circuit is electrically connected to the writing control terminal, the data line and the fifth node, respectively, and is used to write the data voltage provided by the data line to the fifth node under the control of the writing control signal provided by the writing control terminal.

[0011] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit and a first reset circuit;

[0012] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the second voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0013] The first reset circuit is electrically connected to the first reset control terminal, the first reference voltage terminal, and the second node, respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the second node under the control of the first reset control signal provided by the first reset control terminal.

[0014] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a second light-emitting control circuit, and a second reset circuit;

[0015] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0016] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal;

[0017] The second electrode of the light-emitting element is electrically connected to the third voltage terminal.

[0018] In at least one embodiment of this disclosure, the write control signal and the second reset control signal are provided by different levels of GOA circuits included in the same GOA module.

[0019] The pixel circuit described in at least one embodiment of this disclosure further includes a third reset circuit;

[0020] The third reset circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the third reset control signal provided by the third reset control terminal.

[0021] In at least one embodiment of this disclosure, the compensation control signal and the third reset control signal are provided by different levels of GOA circuits included in the same GOA module.

[0022] The pixel circuit described in at least one embodiment of this disclosure further includes a setting circuit;

[0023] The set circuit is electrically connected to the set control terminal, the second reference voltage terminal and the fifth node respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the fifth node under the control of the set control signal provided by the set control terminal.

[0024] In at least one embodiment of this disclosure, the on / off control signal and the set control signal are provided by different levels of GOA circuits included in the same GOA module.

[0025] In at least one embodiment of this disclosure, the driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the on / off control circuit includes a first transistor, the compensation control circuit includes a second transistor, and the writing circuit includes a third transistor.

[0026] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0027] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node.

[0028] The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the first voltage terminal.

[0029] The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the fifth node.

[0030] The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the third node.

[0031] The gate of the third transistor is electrically connected to the write control terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the fifth node.

[0032] Optionally, the first transistor and the second transistor are dual-gate transistors; and / or, the first transistor and the second transistor are oxide transistors.

[0033] Optionally, the first light-emitting control circuit includes a fourth transistor, and the first reset circuit includes a fifth transistor;

[0034] The gate of the fourth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

[0035] The gate of the fifth transistor is electrically connected to the first reset control terminal, the first terminal of the fifth transistor is electrically connected to the first reference voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

[0036] Optionally, the second light-emitting control circuit includes a sixth transistor, and the second reset circuit includes a seventh transistor;

[0037] The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the third node, and the second terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting element.

[0038] The gate of the seventh transistor is electrically connected to the second reset control terminal, the first terminal of the seventh transistor is electrically connected to the first initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0039] Optionally, the third reset circuit includes an eighth transistor;

[0040] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0041] Optionally, the set circuit includes a ninth transistor;

[0042] The gate of the ninth transistor is electrically connected to the set control terminal, the first terminal of the ninth transistor is electrically connected to the second reference voltage terminal, and the second terminal of the ninth transistor is electrically connected to the fifth node.

[0043] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, wherein the refresh frame includes a compensation phase and a writing phase; the driving method includes:

[0044] During the compensation phase, the compensation control circuit, under the control of the compensation control signal, controls the connection between the first node and the third node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node.

[0045] During the writing phase, the writing circuit writes the data voltage to the fifth node under the control of the writing control signal.

[0046] Optionally, the pixel circuit further includes a setting circuit; the refresh frame further includes a first control stage and a second control stage set sequentially after the write stage; the driving method further includes:

[0047] In the first control phase, the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node to write the data voltage to the fourth node.

[0048] In the second control phase, the set circuit, under the control of the set control signal, writes the second reference voltage into the fifth node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node.

[0049] Optionally, the pixel circuit further includes a first light-emitting control circuit and a first reset circuit; the refresh frame further includes a refresh reset stage and a refresh light-emitting stage; the refresh reset stage is disposed between the compensation stage and the first control stage; the refresh light-emitting stage is disposed after the second control stage; the driving method further includes:

[0050] During the refresh reset phase, the first reset circuit, under the control of the first reset control signal, writes the first reference voltage into the second node;

[0051] During the compensation phase and the refresh light emission phase, the first light emission control circuit, under the control of the first light emission control signal, controls the connection between the second voltage terminal and the second node;

[0052] During the refresh and reset phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second voltage terminal to disconnect from the second node, and the on / off control circuit, under the control of the on / off control signal, controls the fourth node to disconnect from the fifth node.

[0053] Optionally, the pixel circuit further includes a light-emitting element, a second light-emitting control circuit, a second reset circuit, and a third reset circuit; the refresh frame further includes a first reset stage, a second reset stage, and a refresh light-emitting stage; the first reset stage is set before the compensation stage, the refresh light-emitting stage is set after the second control stage, and the second reset stage is set before the refresh light-emitting stage; the driving method includes:

[0054] In the first reset phase, the third reset circuit, under the control of the third reset control signal, writes the second initial voltage into the first node so that at the beginning of the compensation phase, the drive circuit can control the connection between the second node and the third node under the control of the potential of the first node.

[0055] During the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0056] During the refresh light emission stage, the second light emission control circuit, under the control of the second light emission control signal, controls the connection between the third node and the first electrode of the light emission element.

[0057] Optionally, the holding frame includes a holding reset phase and a holding light emission phase set sequentially; the driving method includes:

[0058] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0059] During the light-emitting phase, the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

[0060] Optionally, the pixel circuit further includes a first light-emitting control circuit and a first reset circuit; the holding frame includes a holding set phase, which is set before the holding light-emitting phase; the driving method includes:

[0061] During the hold-set phase, the first reset circuit, under the control of the first reset control signal, writes the first reference voltage into the second node; the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second voltage terminal to disconnect from the second node.

[0062] During the light-emitting phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the connection between the second voltage terminal and the second node.

[0063] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0064] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] Figure 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] Figure 8A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 7 of this disclosure during a refresh frame.

[0072] Figure 8B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 7 of this disclosure in the operation of a holding frame;

[0073] Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] Figure 10A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure during the operation of a refresh frame;

[0075] Figure 10B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure in the operation of a holding frame;

[0076] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] Figure 12A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure during a refresh frame.

[0078] Figure 12B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure in the operation of a holding frame;

[0079] Figure 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] Figure 14A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13 of this disclosure during a refresh frame.

[0081] Figure 14B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13 of this disclosure in the operation of a holding frame. Detailed Implementation

[0082] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0083] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0084] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0085] As shown in Figure 1, the pixel circuit described in this embodiment includes a driving circuit 10, a first energy storage circuit 11, a second energy storage circuit 12, an on / off control circuit 13, a compensation control circuit 14, and a writing circuit 15.

[0086] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1; the second node N2 is electrically connected to the second voltage terminal V2.

[0087] The first terminal of the first energy storage circuit 11 is electrically connected to the first node N1, and the second terminal of the first energy storage circuit 11 is electrically connected to the fourth node N4.

[0088] The first terminal of the second energy storage circuit 12 is electrically connected to the fifth node N5, and the second terminal of the second energy storage circuit 12 is electrically connected to the first voltage terminal V1.

[0089] The on / off control circuit 13 is electrically connected to the on / off control terminal ST, the fourth node N4 and the fifth node N5 respectively, and is used to control the connection or disconnection between the fourth node N4 and the fifth node N5 under the control of the on / off control signal provided by the on / off control terminal ST.

[0090] The compensation control circuit 14 is electrically connected to the compensation control terminal GT, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the compensation control signal provided by the compensation control terminal GT.

[0091] The writing circuit 15 is electrically connected to the writing control terminal GAT, the data line DL, and the fifth node N5, respectively, and is used to write the data voltage provided by the data line DL into the fifth node N5 under the control of the writing control signal provided by the writing control terminal GAT.

[0092] At least one embodiment of the pixel circuit shown in Figure 1 of this disclosure can separate threshold voltage compensation and data voltage writing, requiring less scan time per line. This ensures that the data voltage writing time is guaranteed during high-frequency display, and that the pixel circuit is fully charged by the data voltage while ensuring display uniformity, thus guaranteeing the display effect.

[0093] Optionally, the first voltage terminal can be a DC voltage terminal, for example, the first voltage terminal can be a high voltage terminal.

[0094] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit and a first reset circuit;

[0095] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the second voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0096] The first reset circuit is electrically connected to the first reset control terminal, the first reference voltage terminal, and the second node, respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the second node under the control of the first reset control signal provided by the first reset control terminal.

[0097] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit and a first reset circuit. Under the control of the first light-emitting control signal, the first light-emitting control circuit controls the connection or disconnection between the second voltage terminal and the second node. Under the control of the first reset control signal, the first reset circuit writes the first reference voltage into the second node to improve the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0098] Optionally, the second voltage terminal can be a high voltage terminal.

[0099] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first light-emitting control circuit 21 and a first reset circuit 22.

[0100] The first light-emitting control circuit 21 is electrically connected to the first light-emitting control terminal EM1, the second voltage terminal V2 and the second node N2 respectively, and is used to control the connection or disconnection between the second voltage terminal V2 and the second node N2 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0101] The first reset circuit 22 is electrically connected to the first reset control terminal R1, the first reference voltage terminal REF1 and the second node N2 respectively, and is used to write the first reference voltage Vref1 provided by the first reference voltage terminal REF into the second node N2 under the control of the first reset control signal provided by the first reset control terminal R1.

[0102] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a second light-emitting control circuit, and a second reset circuit;

[0103] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0104] The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal;

[0105] The second electrode of the light-emitting element is electrically connected to the third voltage terminal.

[0106] Optionally, the third voltage terminal can be a low voltage terminal.

[0107] In a specific implementation, the pixel circuit may further include a second light-emitting control circuit and a second reset circuit; the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection or disconnection between the third node and the first electrode of the light-emitting element; the second reset circuit, under the control of the second reset control signal, resets the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0108] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1, a second light-emitting control circuit 31, and a second reset circuit 32.

[0109] The second light-emitting control circuit 31 is electrically connected to the second light-emitting control terminal EM2, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0110] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1, and the first pole of the light-emitting element E1, respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first pole of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0111] The second electrode of the light-emitting element E1 is electrically connected to the third voltage terminal V3.

[0112] In at least one embodiment of this disclosure, the write control signal and the second reset control signal are provided by different levels of GOA circuits included in the same GOA (Gate On Array, gate drive circuit disposed on array substrate) module.

[0113] In practice, the write control signal and the second reset control signal can be provided by the same GOA module to reduce the number of GOA modules used, which is beneficial for achieving a narrow bezel.

[0114] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1, a second light-emitting control circuit 31, and a second reset circuit 32.

[0115] The second light-emitting control circuit 31 is electrically connected to the second light-emitting control terminal EM2, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0116] The second reset circuit 32 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1, and the first pole of the light-emitting element E1, respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first pole of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0117] The second electrode of the light-emitting element E1 is electrically connected to the third voltage terminal V3.

[0118] In at least one embodiment of the pixel circuit shown in Figure 4, the first reset control terminal and the second reset control terminal can be the same control terminal to reduce the number of reset control terminals used.

[0119] The pixel circuit described in at least one embodiment of this disclosure further includes a third reset circuit;

[0120] The third reset circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the third reset control signal provided by the third reset control terminal.

[0121] In a specific implementation, the pixel circuit may further include a third reset circuit, which, under the control of a third reset control signal, writes a second initial voltage into the first node to reset the potential of the first node.

[0122] In at least one embodiment of this disclosure, the compensation control signal and the third reset control signal are provided by different levels of GOA circuits included in the same GOA module.

[0123] In practice, the compensation control signal and the third reset control signal can be provided by the same GOA module to reduce the number of GOA modules used, which is beneficial for achieving a narrow bezel.

[0124] The pixel circuit described in at least one embodiment of this disclosure further includes a setting circuit;

[0125] The set circuit is electrically connected to the set control terminal, the second reference voltage terminal and the fifth node respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the fifth node under the control of the set control signal provided by the set control terminal.

[0126] In a specific implementation, the pixel circuit may further include a setting circuit, which, under the control of a setting control signal, writes a second reference voltage into the fifth node to set the potential of the fifth node.

[0127] In at least one embodiment of this disclosure, the on / off control signal and the set control signal are provided by different levels of GOA circuits included in the same GOA module.

[0128] In practical implementation, the on / off control signal and the set control signal can be provided by the same GOA module to reduce the number of GOA modules used and facilitate the achievement of a narrow bezel.

[0129] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a third reset circuit 33;

[0130] The third reset circuit 33 is electrically connected to the third reset control terminal R3, the second initial voltage terminal I2 and the first node N1 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I3 into the first node N1 under the control of the third reset control signal provided by the third reset control terminal R3.

[0131] The pixel circuit described in at least one embodiment of this disclosure further includes a setting circuit 34;

[0132] The set circuit 34 is electrically connected to the set control terminal SZ, the second reference voltage terminal REF2 and the fifth node N5 respectively, and is used to write the second reference voltage Vref2 provided by the second reference voltage terminal REF2 into the fifth node N5 under the control of the set control signal provided by the set control terminal SZ.

[0133] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit of at least one embodiment of this disclosure further includes a third reset circuit 33;

[0134] The third reset circuit 33 is electrically connected to the third reset control terminal R3, the second initial voltage terminal I2 and the first node N1 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I3 into the first node N1 under the control of the third reset control signal provided by the third reset control terminal R3.

[0135] The pixel circuit described in at least one embodiment of this disclosure further includes a setting circuit 34;

[0136] The set circuit 34 is electrically connected to the set control terminal SZ, the second reference voltage terminal REF2 and the fifth node N5 respectively, and is used to write the second reference voltage Vref2 provided by the second reference voltage terminal REF2 into the fifth node N5 under the control of the set control signal provided by the set control terminal SZ.

[0137] Optionally, the driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the on / off control circuit includes a first transistor, the compensation control circuit includes a second transistor, and the writing circuit includes a third transistor.

[0138] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0139] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node.

[0140] The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the first voltage terminal.

[0141] The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the fifth node.

[0142] The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the third node.

[0143] The gate of the third transistor is electrically connected to the write control terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the fifth node.

[0144] Optionally, the first light-emitting control circuit includes a fourth transistor, and the first reset circuit includes a fifth transistor;

[0145] The gate of the fourth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

[0146] The gate of the fifth transistor is electrically connected to the first reset control terminal, the first terminal of the fifth transistor is electrically connected to the first reference voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

[0147] Optionally, the second light-emitting control circuit includes a sixth transistor, and the second reset circuit includes a seventh transistor;

[0148] The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the third node, and the second terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting element.

[0149] The gate of the seventh transistor is electrically connected to the second reset control terminal, the first terminal of the seventh transistor is electrically connected to the first initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0150] Optionally, the third reset circuit includes an eighth transistor;

[0151] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

[0152] Optionally, the set circuit includes a ninth transistor;

[0153] The gate of the ninth transistor is electrically connected to the set control terminal, the first terminal of the ninth transistor is electrically connected to the second reference voltage terminal, and the second terminal of the ninth transistor is electrically connected to the fifth node.

[0154] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 5, the driving circuit includes a driving transistor DT, the first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, the on / off control circuit includes a first transistor T1, the compensation control circuit includes a second transistor T2, and the writing circuit includes a third transistor T3.

[0155] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the high voltage terminal VDD, and the drain of the driving transistor DT is electrically connected to the third node N3.

[0156] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the fourth node N4.

[0157] The first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and the second terminal of the second capacitor C2 is electrically connected to the high voltage terminal VDD.

[0158] The gate of the first transistor T1 is electrically connected to the third light-emitting control terminal EM3-n of the nth stage, the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the fifth node N5; n is a positive integer;

[0159] The gate of the second transistor T2 is electrically connected to the compensation control terminal GT, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0160] The gate of the third transistor T3 is electrically connected to the write control terminal GAT, the source of the third transistor T3 is electrically connected to the data line DL, and the drain of the third transistor T3 is electrically connected to the fifth node N5.

[0161] The second light-emitting control circuit includes a sixth transistor T6, and the second reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0162] The gate of the sixth transistor T6 is electrically connected to the second light-emitting control terminal EM2, the source of the sixth transistor T6 is electrically connected to the third node N3, and the drain of the sixth transistor T6 is electrically connected to the anode of O1.

[0163] The gate of the seventh transistor T7 is electrically connected to the second reset control terminal R2, the source of the seventh transistor T7 is electrically connected to the first initial voltage terminal I1, the drain of the seventh transistor T7 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0164] The third reset circuit includes an eighth transistor T8;

[0165] The gate of the eighth transistor T8 is electrically connected to the third reset control terminal R3, the source of the eighth transistor T8 is electrically connected to the second initial voltage terminal I2, and the drain of the eighth transistor T8 is electrically connected to the first node N1.

[0166] The setting circuit includes a ninth transistor T9;

[0167] The gate of the ninth transistor T9 is electrically connected to the third light-emitting control terminal EM3-n+1 of the (n+1)th stage, the source of the ninth transistor T9 is electrically connected to the second reference voltage terminal REF2, and the drain of the ninth transistor T9 is electrically connected to the fifth node N5.

[0168] In at least one embodiment of the pixel circuit shown in Figure 7, all transistors are p-type transistors, and T8 and T2 are dual-gate transistors to reduce the risk of leakage current and improve the stability of the potential of the first node N1 and the brightness retention rate within a frame; the other transistors are single-gate transistors.

[0169] In at least one embodiment of the pixel circuit shown in Figure 7, the data voltage range can be adjusted by adjusting the capacitance values ​​of C1 and C2, and by adjusting the ratio of the capacitance values ​​of C1 to C2.

[0170] In at least one embodiment of the pixel circuit shown in Figure 7, the on / off control terminal is the nth level third light emission control terminal EM3-n, the set control terminal is the (n+1)th level third light emission control terminal EM3-n+1, ​​and EM2 is the nth level second light emission control terminal.

[0171] In at least one embodiment shown in Figure 7, the write control signal provided by GAT and the second reset control signal provided by R2 can be provided by different levels of GOA circuits included in the same GOA module, so as to reduce the number of GOA modules used and facilitate the realization of narrow bezels.

[0172] In at least one embodiment of this disclosure, the voltage value of the high voltage signal provided by VDD can be greater than or equal to 2V and less than or equal to 6V. For example, the voltage value of the high voltage signal can be 2.8V or 4.6V; the difference between the voltage value of the high voltage signal and the voltage value of the low voltage signal provided by VSS is greater than or equal to 6V and less than or equal to 22V.

[0173] When the light-emitting element is a single-layer light-emitting element, the difference between the voltage value of the first initial voltage provided by I1 and the voltage value of the low voltage signal is less than 1V;

[0174] When the light-emitting element is a stacked light-emitting element, the difference between the voltage value of the first initial voltage provided by I1 and the voltage value of the low voltage signal is greater than or equal to 0.5V and less than or equal to 2.5V.

[0175] The difference between the voltage value of the high voltage signal and the voltage value of the second initial voltage provided by I2 is greater than or equal to 6.5V and less than or equal to 10V;

[0176] The second initial voltage provided by REF2 is greater than or equal to 2V and less than or equal to 6V.

[0177] As shown in FIG8A, when at least one embodiment of the pixel circuit shown in FIG7 of this disclosure is in operation, the refresh frame includes a first reset stage S1, a compensation stage S2, a writing stage S3, a second reset stage S4, a first control stage S5, a second control stage S6 and a refresh light emission stage S7, which are set sequentially.

[0178] In the first reset phase S1, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a low voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, T1 and T9 are both turned on, N4 and N5 are connected, REF2 provides the second reference voltage Vref2 to N5; T8 is turned on, I2 provides the second initial voltage Vinit2 to N1; the gate-source voltage of DT is Vinit2-Vdd, where Vdd is the voltage value of the high voltage signal provided by VDD. DT is in a bias state, which can improve the hysteresis effect of DT.

[0179] By increasing the duration of the first reset phase S1, or by increasing the interval between the first reset phase S1 and the compensation phase S2, the hysteresis effect of DT can be effectively improved.

[0180] During compensation phase S2, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a high voltage signal, GT provides a low voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, T1 and T9 are both open, N4 and N5 are connected, REF2 provides the second reference voltage Vref2 to N5; T2 is open, N1 and N3 are connected;

[0181] At the start of the compensation phase S2, DT is turned on, and the high voltage signal provided by VDD charges the capacitor through DT and T2, changing the potential of N1 until DT is turned off to perform threshold voltage compensation; at this time, the potential of N1 is Vdd + Vth, and Vth is the threshold voltage of DT; by using the high voltage signal provided by VDD to perform threshold voltage compensation, the influence of VDD's IR Drop can be eliminated.

[0182] The threshold voltage compensation time can be controlled by adjusting the duration of the compensation phase S2, thereby improving the image quality of high-frequency displays. T1 and T9 remain on until the threshold voltage compensation ends.

[0183] During the time interval between the compensation phase S2 and the writing phase S3, T1 and T9 are turned off in sequence. During the process of T1 being turned off, the potentials of N4 and N1 are raised due to device coupling. However, after T1 is turned off, N4 and N1 are in a floating state. At the same time, the threshold voltage information is still stored in the capacitor. Meanwhile, the potential of N5 is also related to Vref2.

[0184] During the write phase S3, EM2 provides a high voltage signal, EM3-n provides a high voltage signal, EM3-n+1 provides a high voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a low voltage signal, R2 provides a high voltage signal, T3 is turned on, DL provides the data voltage Vdata to N5, and writes Vdata into C2;

[0185] In the second reset phase S4, EM2 provides a high voltage signal, EM3-n provides a high voltage signal, EM3-n+1 provides a high voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a low voltage signal, T7 is turned on, and I1 provides the first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1.

[0186] In the first control phase S5, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a high voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, T1 is turned on, and Vdata stored in C2 is written to N4 through T1. The potential of N4 is the same as the potential of N5.

[0187] In the second control phase S6, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, T1 and T9 are both in the on state, the potential of N4 and the potential of N5 jump from Vdata to Vref2. Since N1 is in the floating state at this time, the signal related to the data voltage jump in N4 is coupled to N1. At this time, the jump signal related to Vdata is recorded in N1, the potential of N4 is maintained at Vref2, and N1 simultaneously stores the voltage signals related to Vth and Vdata.

[0188] During the refresh emission stage S7, EM2 provides a low voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, T1, T6 and T9 are all in the on state, and DT drives O1 to emit light;

[0189] During the refresh emission stage S7, the emission current Id of O1 is equal to 0.5K×((C1z / (C1z+C2z))×(Vref2-Vdata)). 2 Where K is the current coefficient of DT, C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0190] As shown in FIG8B, in operation, at least one embodiment of the pixel circuit shown in FIG7 of this disclosure includes a hold-reset phase S0 and a hold-light phase SE that are set sequentially.

[0191] During the reset phase S0, R2 provides a low voltage signal, T7 is turned on, and I1 provides the first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1.

[0192] During the light-emitting phase SE, EM2 provides a low voltage signal, T6 is in the on state, and DT drives O1 to emit light.

[0193] In at least one embodiment of the pixel circuit shown in Figure 7 of this disclosure, the high-low frequency conversion can be performed using a frame skipping method during operation. During the hold frame, except for T7 being turned on to reset the anode of O1, all other control terminals except EM2 provide invalid voltage signals. As shown in Figure 8B, since the write control signal provided by GAT and the second reset control signal provided by R2 are provided by the same GOA module, GAT provides a low voltage signal for a period of time before the hold reset phase S0, causing T3 to turn on. However, since T1 is in the off state during the hold frame, the potential fluctuation of N1 is very small. The potential of the data line DL can remain constant during the hold frame, and the fluctuation of N1 will be removed due to charge conservation and will not affect the light-emitting current of O1 during the hold light-emitting phase SE.

[0194] In at least one embodiment shown in Figure 7, the third reset control signal provided by R3 and the compensation control signal provided by GT can be provided by different levels of GOA circuits in the same GOA module.

[0195] The difference between at least one embodiment of the pixel circuit shown in FIG. 9 of this disclosure and at least one embodiment of the pixel circuit shown in FIG. 7 of this disclosure is as follows: T8 and T2 are n-type transistors and oxide transistors, in order to reduce the leakage current of N1, and high and low frequency display from 1Hz to 300Hz can be realized.

[0196] Figure 10A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure during the refresh frame. Figure 10B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure during the hold frame.

[0197] The difference between at least one embodiment of the pixel circuit shown in FIG11 of this disclosure and at least one embodiment of the pixel circuit shown in FIG7 of this disclosure is as follows: it further includes a first light-emitting control circuit and a first reset circuit;

[0198] The first light-emitting control circuit includes a fourth transistor T4, and the first reset circuit includes a fifth transistor T5;

[0199] The gate of the fourth transistor T4 is electrically connected to the first light-emitting control terminal EM1, the source of the fourth transistor T4 is electrically connected to the high voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the second node N2.

[0200] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal R2, the source of the fifth transistor T5 is electrically connected to the first reference voltage terminal REF1, and the drain of the fifth transistor T5 is electrically connected to the second node N2.

[0201] Optionally, the voltage value of the first reference voltage provided by REF1 can be greater than or equal to 3V and less than or equal to 7V.

[0202] Figure 12A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure in a refresh frame. Figure 12B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure in a hold frame.

[0203] In at least one embodiment shown in Figure 11, the first reset control terminal and the second reset control terminal are the same reset control terminal to reduce the number of reset control terminals used. In specific implementations, the first reset control terminal and the second reset control terminal can be different control terminals.

[0204] As shown in Figure 12A, at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure operates as follows:

[0205] The refresh frame includes the first reset phase S1, the compensation phase S2, the writing phase S3, the second reset phase S4, the first control phase S5, the second control phase S6, and the refresh and light emission phase S7, which are set sequentially.

[0206] In the first reset phase S1, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a low voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, EM1 provides a high voltage signal, T1 and T9 are both turned on, N4 and N5 are connected, REF2 provides the second reference voltage Vref2 to N5; T8 is turned on, I2 provides the second initial voltage Vinit2 to N1; the gate-source voltage of DT is Vinit2-Vdd, where Vdd is the voltage value of the high voltage signal provided by VDD. DT is in a bias state, which can improve the hysteresis effect of DT.

[0207] By increasing the duration of the first reset phase S1, or by increasing the interval between the first reset phase S1 and the compensation phase S2, the hysteresis effect of DT can be effectively improved.

[0208] During compensation phase S2, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a high voltage signal, GT provides a low voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, EM1 provides a low voltage signal, T4 is on, T1 and T9 are both on, N4 and N5 are connected, REF2 provides the second reference voltage Vref2 to N5; T2 is on, N1 and N3 are connected;

[0209] At the start of the compensation phase S2, DT is turned on, and the high voltage signal provided by VDD charges the capacitor through DT and T2, changing the potential of N1 until DT is turned off to perform threshold voltage compensation; at this time, the potential of N1 is Vdd + Vth, and Vth is the threshold voltage of DT; by using the high voltage signal provided by VDD to perform threshold voltage compensation, the influence of VDD's IR Drop can be eliminated.

[0210] The threshold voltage compensation time can be controlled by adjusting the duration of the compensation phase S2, thereby improving the image quality of high-frequency displays. T1 and T9 remain on until the threshold voltage compensation ends.

[0211] During the time interval between the compensation phase S2 and the writing phase S3, T1 and T9 are turned off in sequence. During the process of T1 being turned off, the potentials of N4 and N1 are raised due to device coupling. However, after T1 is turned off, N4 and N1 are in a floating state. At the same time, the threshold voltage information is still stored in the capacitor. Meanwhile, the potential of N5 is also related to Vref2.

[0212] During the write phase S3, EM2 provides a high voltage signal, EM3-n provides a high voltage signal, EM3-n+1 provides a high voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a low voltage signal, R2 provides a high voltage signal, EM1 provides a high voltage signal, T3 is turned on, DL provides the data voltage Vdata to N5, and writes Vdata into C2;

[0213] In the second reset phase S4, EM2 provides a high voltage signal, EM3-n provides a high voltage signal, EM3-n+1 provides a high voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a low voltage signal, EM1 provides a high voltage signal, T7 is turned on, I1 provides the first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1; T5 is turned on, REF1 provides the first reference voltage Vref1 to N2 to improve the hysteresis phenomenon of DT;

[0214] In the first control phase S5, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a high voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, EM1 provides a high voltage signal, T1 is turned on, and Vdata stored in C2 is written to N4 through T1. The potential of N4 is the same as the potential of N5.

[0215] In the second control phase S6, EM2 provides a high voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, and EM1 provides a high voltage signal. T1 and T9 are both in the on state. The potentials of N4 and N5 jump from Vdata to Vref2. Since N1 is in a floating state at this time, the signal related to the data voltage jump in N4 is coupled to N1. At this time, the jump signal related to Vdata is recorded in N1, and the potential of N4 is maintained at Vref2. N1 simultaneously stores the voltage signals related to Vth and Vdata.

[0216] During the refresh emission stage S7, EM2 provides a low voltage signal, EM3-n provides a low voltage signal, EM3-n+1 provides a low voltage signal, R3 provides a high voltage signal, GT provides a high voltage signal, GAT provides a high voltage signal, R2 provides a high voltage signal, EM1 provides a low voltage signal, T1, T4, T6 and T9 are all in the on state, and DT drives O1 to emit light;

[0217] During the refresh emission stage S7, the emission current Id of O1 is equal to 0.5K×((C1z / (C1z+C2z))×(Vref2-Vdata)). 2 Where K is the current coefficient of DT, C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0218] In at least one embodiment of the pixel circuit shown in FIG11 of this disclosure, the gate of T5 may be electrically connected to the first reset control terminal R1. When R1 provides a low voltage signal, T5 is turned on during the refresh reset phase. The refresh reset phase may be set between the compensation phase and the first control phase. During the refresh reset phase, T4 is turned off and T1 is turned off.

[0219] The difference between at least one embodiment of the pixel circuit shown in FIG. 13 of this disclosure and at least one embodiment of the pixel circuit shown in FIG. 9 of this disclosure is as follows: it further includes a first light-emitting control circuit and a first reset circuit;

[0220] The first light-emitting control circuit includes a fourth transistor T4, and the first reset circuit includes a fifth transistor T5;

[0221] The gate of the fourth transistor T4 is electrically connected to the first light-emitting control terminal EM1, the source of the fourth transistor T4 is electrically connected to the high voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the second node N2.

[0222] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal R2, the source of the fifth transistor T5 is electrically connected to the first reference voltage terminal REF1, and the drain of the fifth transistor T5 is electrically connected to the second node N2.

[0223] Figure 14A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13 of this disclosure during a refresh frame. Figure 14B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13 of this disclosure during a hold frame.

[0224] The driving method described in this embodiment is applied to the pixel circuit described above, and the refresh frame includes a compensation stage and a writing stage; the driving method includes:

[0225] During the compensation phase, the compensation control circuit, under the control of the compensation control signal, controls the connection between the first node and the third node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node.

[0226] During the writing phase, the writing circuit writes the data voltage to the fifth node under the control of the writing control signal.

[0227] The driving method described in this embodiment can separate threshold voltage compensation and data voltage writing, requiring less scanning time per line. This ensures that the data voltage writing time is guaranteed during high-frequency display, and that the pixel circuit is fully charged by the data voltage while ensuring display uniformity, thus guaranteeing the display effect.

[0228] In at least one embodiment of this disclosure, the pixel circuit further includes a setting circuit; the refresh frame further includes a first control stage and a second control stage set sequentially after the write stage; the driving method further includes:

[0229] In the first control phase, the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node to write the data voltage to the fourth node.

[0230] In the second control phase, the set circuit, under the control of the set control signal, writes the second reference voltage into the fifth node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node.

[0231] In at least one embodiment of this disclosure, the pixel circuit further includes a first light-emitting control circuit and a first reset circuit; the refresh frame further includes a refresh reset stage and a refresh light-emitting stage; the refresh reset stage is disposed between the compensation stage and the first control stage; the refresh light-emitting stage is disposed after the second control stage; the driving method further includes:

[0232] During the refresh reset phase, the first reset circuit, under the control of the first reset control signal, writes the first reference voltage into the second node to improve the hysteresis phenomenon of the drive transistors included in the drive circuit.

[0233] During the compensation phase and the refresh light emission phase, the first light emission control circuit, under the control of the first light emission control signal, controls the connection between the second voltage terminal and the second node;

[0234] During the refresh and reset phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second voltage terminal to disconnect from the second node, and the on / off control circuit, under the control of the on / off control signal, controls the fourth node to disconnect from the fifth node.

[0235] In at least one embodiment of this disclosure, the pixel circuit further includes a light-emitting element, a second light-emitting control circuit, a second reset circuit, and a third reset circuit; the refresh frame further includes a first reset stage, a second reset stage, and a refresh light-emitting stage; the first reset stage is disposed before the compensation stage, the refresh light-emitting stage is disposed after the second control stage, and the second reset stage is disposed before the refresh light-emitting stage; the driving method includes:

[0236] In the first reset phase, the third reset circuit, under the control of the third reset control signal, writes the second initial voltage into the first node so that at the beginning of the compensation phase, the drive circuit can control the connection between the second node and the third node under the control of the potential of the first node.

[0237] In the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element;

[0238] During the refresh light emission stage, the second light emission control circuit, under the control of the second light emission control signal, controls the connection between the third node and the first electrode of the light emission element.

[0239] In at least one embodiment of this disclosure, the holding frame includes a holding reset phase and a holding light emission phase that are set sequentially; the driving method includes:

[0240] During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0241] During the light-emitting phase, the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

[0242] In at least one embodiment of this disclosure, the pixel circuit further includes a first light-emitting control circuit and a first reset circuit; the holding frame includes a holding set phase, which is set before the holding light-emitting phase; the driving method includes:

[0243] During the hold-set phase, the first reset circuit, under the control of the first reset control signal, writes the first reference voltage into the second node to improve the hysteresis phenomenon of the driving transistor included in the driving circuit; the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second voltage terminal to disconnect from the second node.

[0244] During the light-emitting phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the connection between the second voltage terminal and the second node.

[0245] The display device described in this disclosure includes the pixel circuit described above.

[0246] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a first energy storage circuit, a second energy storage circuit, an on / off control circuit, a compensation control circuit, and a writing circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node. The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node. The first terminal of the second energy storage circuit is electrically connected to the fifth node, and the second terminal of the second energy storage circuit is electrically connected to the first voltage terminal. The on / off control circuit is electrically connected to the on / off control terminal, the fourth node, and the fifth node, respectively, and is used to control the connection or disconnection between the fourth node and the fifth node under the control of the on / off control signal provided by the on / off control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal. The writing circuit is electrically connected to the writing control terminal, the data line and the fifth node, respectively, and is used to write the data voltage provided by the data line to the fifth node under the control of the writing control signal provided by the writing control terminal.

2. The pixel circuit as described in claim 1, wherein, It also includes a first light-emitting control circuit and a first reset circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the second voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal. The first reset circuit is electrically connected to the first reset control terminal, the first reference voltage terminal, and the second node, respectively, and is used to write the first reference voltage provided by the first reference voltage terminal into the second node under the control of the first reset control signal provided by the first reset control terminal.

3. The pixel circuit as described in claim 1, wherein, It also includes a light-emitting element, a second light-emitting control circuit, and a second reset circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; The second reset circuit is electrically connected to the second reset control terminal, the first initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal; The second electrode of the light-emitting element is electrically connected to the third voltage terminal.

4. The pixel circuit as described in claim 3, wherein, The write control signal and the second reset control signal are provided by different levels of GOA circuits included in the same GOA module.

5. The pixel circuit as described in claim 1, wherein, It also includes a third reset circuit; The third reset circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the third reset control signal provided by the third reset control terminal.

6. The pixel circuit as described in claim 5, wherein, The compensation control signal and the third reset control signal are provided by different levels of GOA circuits included in the same GOA module.

7. The pixel circuit as described in claim 1, wherein, It also includes a set circuit; The set circuit is electrically connected to the set control terminal, the second reference voltage terminal and the fifth node respectively, and is used to write the second reference voltage provided by the second reference voltage terminal into the fifth node under the control of the set control signal provided by the set control terminal.

8. The pixel circuit as described in claim 7, wherein, The on / off control signal and the set control signal are provided by different levels of GOA circuits included in the same GOA module.

9. The pixel circuit as described in claim 1, wherein, The driving circuit includes a driving transistor, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, the on / off control circuit includes a first transistor, the compensation control circuit includes a second transistor, and the writing circuit includes a third transistor. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node. The first terminal of the second capacitor is electrically connected to the fifth node, and the second terminal of the second capacitor is electrically connected to the first voltage terminal. The gate of the first transistor is electrically connected to the on / off control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the fifth node. The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the write control terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the fifth node.

10. The pixel circuit as claimed in claim 9, wherein, The first transistor and the second transistor are dual-gate transistors; and / or, the first transistor and the second transistor are oxide transistors.

11. The pixel circuit as claimed in claim 2, wherein, The first light-emitting control circuit includes a fourth transistor, and the first reset circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the first light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the first reset control terminal, the first terminal of the fifth transistor is electrically connected to the first reference voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

12. The pixel circuit as claimed in claim 3, wherein, The second light-emitting control circuit includes a sixth transistor, and the second reset circuit includes a seventh transistor; The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the third node, and the second terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting element. The gate of the seventh transistor is electrically connected to the second reset control terminal, the first terminal of the seventh transistor is electrically connected to the first initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

13. The pixel circuit as claimed in claim 5, wherein, The third reset circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first node.

14. The pixel circuit as claimed in claim 7, wherein, The set circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the set control terminal, the first terminal of the ninth transistor is electrically connected to the second reference voltage terminal, and the second terminal of the ninth transistor is electrically connected to the fifth node.

15. A driving method applied to a pixel circuit as described in any one of claims 1 to 14, wherein refreshing a frame includes a compensation phase and a writing phase; the driving method includes: During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the compensation control signal; The on / off control circuit controls the connection between the fourth node and the fifth node under the control of the on / off control signal; During the writing phase, the writing circuit writes the data voltage to the fifth node under the control of the writing control signal.

16. The driving method as described in claim 15, wherein, The pixel circuit further includes a setting circuit; the refresh frame further includes a first control stage and a second control stage set sequentially after the write stage; the driving method further includes: In the first control phase, the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node to write the data voltage to the fourth node. In the second control phase, the set circuit, under the control of the set control signal, writes the second reference voltage into the fifth node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the fourth node and the fifth node.

17. The driving method as described in claim 16, wherein, The pixel circuit further includes a first light-emitting control circuit and a first reset circuit; the refresh frame further includes a refresh reset stage and a refresh light-emitting stage; the refresh reset stage is disposed between the compensation stage and the first control stage; the refresh light-emitting stage is disposed after the second control stage; the driving method further includes: During the refresh reset phase, the first reset circuit, under the control of the first reset control signal, writes the first reference voltage into the second node; During the compensation phase and the refresh light emission phase, the first light emission control circuit, under the control of the first light emission control signal, controls the connection between the second voltage terminal and the second node. During the refresh and reset phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second voltage terminal. The connection between the second node and the fourth node is broken. Under the control of the on / off control signal, the on / off control circuit controls the connection between the fourth node and the fifth node to be broken.

18. The driving method as described in claim 16 or 17, wherein, The pixel circuit further includes a light-emitting element, a second light-emitting control circuit, a second reset circuit, and a third reset circuit; the refresh frame further includes a first reset stage, a second reset stage, and a refresh light-emitting stage; the first reset stage is set before the compensation stage, the refresh light-emitting stage is set after the second control stage, and the second reset stage is set before the refresh light-emitting stage; the driving method includes: In the first reset phase, the third reset circuit, under the control of the third reset control signal, writes the second initial voltage into the first node so that at the beginning of the compensation phase, the drive circuit can control the connection between the second node and the third node under the control of the potential of the first node. During the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first electrode of the light-emitting element; During the refresh light emission stage, the second light emission control circuit, under the control of the second light emission control signal, controls the connection between the third node and the first electrode of the light emission element.

19. The driving method as described in claim 18, wherein, The holding frame includes a holding reset phase and a holding light phase set sequentially; the driving method includes: During the reset phase, the second reset circuit, under the control of the second reset control signal, writes the first initial voltage into the first electrode of the light-emitting element; During the light-emitting phase, the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

20. The driving method as described in claim 19, wherein, The pixel circuit further includes a first light-emitting control circuit and a first reset circuit; the holding frame includes a holding set phase, which is set before the holding light-emitting phase; the driving method includes: During the hold-set phase, the first reset circuit, under the control of the first reset control signal, writes the first reference voltage into the second node; the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second voltage terminal to disconnect from the second node. During the light-emitting phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the connection between the second voltage terminal and the second node.

21. A display device comprising a pixel circuit as claimed in any one of claims 1 to 14.

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