An impedance detection circuit, impedance matcher and semiconductor process equipment

Abstract

This invention discloses an impedance detection circuit, an impedance matching device, and a semiconductor process apparatus, including a center conductor, a first winding, a second winding, a capacitor, and a processing circuit. The center conductor is connected in series between the RF power supply and the load. The first end of the capacitor is connected to the center conductor, and the second end is connected to both the first and second windings. The first end of the first winding and the first end of the second winding are both connected to a first node, and the second end of both the first and second windings are both connected to a second node. The winding direction of the first winding is opposite to that of the second winding, and the loop circuit formed by the first and second windings is arranged circumferentially around the center conductor. The processing circuit is connected to the first and second nodes respectively and is used to obtain the current and voltage signals of the center conductor based on the first voltage signal of the first node and the second voltage signal of the second node. Therefore, it can accurately identify and sample the current and voltage of the RF power supply over a wider range.

Description

Technical Field

[0001] This invention relates to the field of radio frequency technology, and more specifically to an impedance detection circuit, an impedance matching device, and semiconductor process equipment. Background Technology

[0002] In semiconductor process equipment, because the output impedance of the RF power supply does not match the input impedance of the process chamber, an impedance matching device needs to be connected between the RF power supply and the process chamber. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of an impedance matching device, which includes an impedance detection circuit 10, a matching controller 11, an actuator 12, and an impedance matching network 13. The impedance detection circuit 10 samples the voltage and current signals of the RF power supply and feeds them back to the matching controller 11. The matching controller 11 calculates an adjustment signal from the voltage and current signals and feeds it back to the actuator 12. The actuator 12 adjusts the impedance of the impedance matching network 13 according to the adjustment signal to achieve impedance matching between the RF power supply and the process chamber. However, the signal sampling range of the current impedance detection circuit 10 needs further improvement. Summary of the Invention

[0003] This invention discloses an impedance detection circuit, an impedance matching device, and a semiconductor process apparatus to improve the signal sampling range of the impedance detection circuit.

[0004] In a first aspect, the present invention discloses an impedance detection circuit, comprising: a center conductor, a first winding, a second winding, a capacitor, and a processing circuit; wherein: the center conductor is connected in series between an RF power supply and a load; a first end of the capacitor is connected to the center conductor, and a second end of the capacitor is connected to both the first winding and the second winding; a first end of the first winding and a first end of the second winding are both connected to a first node, and a second end of both the first winding and the second winding are both connected to a second node; the winding direction of the first winding is opposite to that of the second winding, and the loop formed by the first winding and the second winding surrounds the center conductor in a circular arrangement; the processing circuit is connected to both the first node and the second node, and is used to obtain the current signal and voltage signal of the center conductor based on the first voltage signal of the first node and the second voltage signal of the second node.

[0005] In some embodiments of the present invention, the first winding and the second winding are arranged symmetrically.

[0006] In some embodiments of the present invention, a printed circuit board is further included; the printed circuit board includes a central opening; the central conductor passes through the central opening; both the first winding and the second winding include multi-turn coils; each turn includes a first via, a first trace, a second via, and a second trace; the first via and the second via penetrate the printed circuit board; the first trace and the second trace are located on opposite sides of the printed circuit board; the first trace is used to electrically connect the first via and the second via of the same turn, and the second trace is used to electrically connect the second via of the same turn and the first via of different turns; the capacitor includes multiple third vias and multiple third traces; the third vias penetrate the printed circuit board; the third traces are located on one side of the printed circuit board; each third trace is used to electrically connect one third via and one first via.

[0007] In some embodiments of the present invention, all the first vias are arranged sequentially on a first circumference surrounding the central opening; all the second vias are arranged sequentially on a second circumference surrounding the central opening; and all the third vias are arranged sequentially on a third circumference surrounding the central opening; the radius of the first circumference is smaller than the radius of the second circumference; and the radius of the third circumference is smaller than the radius of the first circumference.

[0008] In some embodiments of the present invention, the orthographic projection of the third via on the printed circuit board is an arc-shaped pattern, and the orthographic projections of all the third vias on the printed circuit board are located on the same circumference.

[0009] In some embodiments of the present invention, the number of third vias electrically connected to the first winding is the same as the number of third vias electrically connected to the second winding.

[0010] In some embodiments of the present invention, the processing circuit includes: an analog-to-digital converter and a signal controller; the analog-to-digital converter is connected to the first node and the second node respectively, and is used to convert the first voltage signal into a first digital signal and convert the second voltage signal into a second digital signal; the signal controller is connected to the analog-to-digital converter and is used to obtain the voltage signal of the center conductor according to the sum of the first digital signal and the second digital signal, and to obtain the current signal of the center conductor according to the difference between the first digital signal and the second digital signal.

[0011] In some embodiments of the present invention, the signal controller is used to obtain the voltage signal on the central conductor based on the sum of the product of the first digital signal and the first coupling coefficient and the product of the second digital signal and the second coupling coefficient, and to obtain the current signal on the central conductor based on the difference between the product of the first digital signal and the third coupling coefficient and the product of the second digital signal and the fourth coupling coefficient.

[0012] In some embodiments of the present invention, the signal controller is used to convert the first digital signal into a first data signal and a second data signal, wherein the first data signal is the amplitude component of the first digital signal and the second data signal is the phase component of the first digital signal; to convert the second digital signal into a third data signal and a fourth data signal, wherein the third data signal is the amplitude component of the second digital signal and the fourth data signal is the phase component of the second digital signal; to obtain the voltage signal on the central conductor based on the sum of the product of the first data signal and the first coupling coefficient and the product of the third data signal and the second coupling coefficient; and to obtain the current signal on the central conductor based on the difference between the product of the second data signal and the third coupling coefficient and the product of the fourth data signal and the fourth coupling coefficient.

[0013] Secondly, the present invention discloses an impedance matching device, including a matching controller, an actuator, an impedance matching network, and the impedance detection circuit provided in any of the above embodiments of the present invention; the impedance detection circuit is used to sample the voltage signal and current signal output by the radio frequency power supply; the matching controller is used to obtain an adjustment signal based on the voltage sampling signal and current sampling signal output by the impedance detection circuit; the actuator is used to adjust the impedance of the impedance matching network based on the adjustment signal.

[0014] Thirdly, the present invention discloses a semiconductor process apparatus, including a radio frequency power supply, an impedance matching device as described above, and a process chamber, wherein the radio frequency power supply is used to provide radio frequency power to the process chamber, and the impedance matching device is used to match the impedance of the radio frequency power supply with that of the process chamber.

[0015] The impedance detection circuit, impedance matching device, and semiconductor process equipment disclosed in this invention obtain the current and voltage signals of the center conductor based on the first voltage signal of the first node and the second voltage signal of the second node. The first voltage signal of the first node and the second voltage signal of the second node are obtained based on the voltages of the first winding, the second winding, and the capacitor. Therefore, compared to voltage signals obtained solely based on the voltages of a single winding or coil and capacitor, the amplitudes of the first and second voltage signals are significantly increased. This increases the amplitude of the voltage signal input to the analog-to-digital converter (ADC), enabling the ADC to accurately identify and sample the current and voltage of a wider range of RF power supplies. For example, it accurately identifies and samples the current and voltage of the RF power supply when its output power is extremely high or low, or when its impedance is extremely high or low. This increases the signal sampling range of the impedance detection circuit, thereby improving the signal processing accuracy of the signal processing circuit where the ADC is located, and enhancing the impedance matching accuracy of the impedance matching device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0017] Figure 1 This is a schematic diagram of an impedance matching device.

[0018] Figure 2 This is a schematic diagram of the circuit structure of an impedance detection circuit.

[0019] Figure 3 This is a schematic diagram of an impedance detection circuit disclosed in an embodiment of the present invention.

[0020] Figure 4 for Figure 3 The equivalent circuit diagram of the impedance detection circuit shown is shown.

[0021] Figure 5 This is a schematic diagram of a series structure of a center conductor and a radio frequency power supply disclosed in an embodiment of the present invention.

[0022] Figure 6 This is an equivalent circuit diagram of a first winding and a second winding disclosed in an embodiment of the present invention.

[0023] Figure 7 This is an equivalent circuit diagram of a center conductor, a first winding, a second winding, and a capacitor disclosed in an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of another impedance detection circuit disclosed in an embodiment of the present invention.

[0025] Figure 9This is a schematic diagram of a traditional signal controller.

[0026] Figure 10 for Figure 9 The measured results of the voltage and current output by the signal controller are shown.

[0027] Figure 11 This is a schematic diagram of the structure of a signal controller disclosed in an embodiment of the present invention.

[0028] Figure 12 for Figure 11 The measured results of the voltage and current output by the signal controller are shown.

[0029] Figure 13 This is a schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] As described in the background section, a current impedance matching device includes an impedance detection circuit 10, a matching controller 11, an actuator 12, and an impedance matching network 13. The actuator 12 is typically a stepper motor, which drives the vacuum capacitors C10 and C11 in the impedance matching network 13 to adjust their capacitance values, thereby adjusting the impedance of the impedance matching network 13. In practical applications, the output power of RF power supplies often ranges from a few watts to several kilowatts. To achieve impedance matching for different output powers, the impedance detection circuit 10 must accurately identify and sample the current and voltage signals of RF power supplies with various output powers and impedances.

[0032] like Figure 2 As shown, Figure 2 This is a schematic diagram of an impedance detection circuit, which includes a current sampling circuit 20, a voltage sampling circuit 21, and a signal processing circuit 22. The current sampling circuit 20 includes an induction coil 200 and a load resistor 201; the voltage sampling circuit 21 includes a voltage divider capacitor 210; the signal processing circuit 22 includes an analog-to-digital converter 220 and a signal controller 221; and the equivalent circuit 23 of the main circuit containing the RF power supply includes an equivalent resistance 230, an equivalent inductance 231, and an equivalent capacitance 232.

[0033] In this circuit, the induction coil 200 and the equivalent inductance 231 generate a current-sensing signal using the transformer principle, which is then applied to the load resistor 201, representing the current signal of the main circuit, i.e., the current signal of the RF power supply. The voltage-dividing capacitor 210 and the equivalent capacitor 232 form a voltage-sensing signal through capacitive voltage division, representing the voltage signal of the main circuit, i.e., the voltage signal of the RF power supply. The analog signals sampled by the current sampling circuit 20 and the voltage sampling circuit 21 are converted into digital signals by the analog-to-digital converter 220 and output to the signal controller 221. The signal controller 221 processes and calculates the digital signals to obtain the impedance or output power of the main circuit, i.e., the RF power supply. This impedance or output power can be used for subsequent impedance matching calculations.

[0034] Among them, it can be determined according to the formula I = f(M) 231-200 R 201 )×i=m×i, calculate the current I in the main circuit, and then use the formula V=f(C)×i=m×i to calculate the current I in the main circuit. 232 C 210 )×u=n×u, calculate the voltage V of the main circuit. Where, M 231-200 R is the mutual inductance coefficient between induction coil 200 and equivalent inductance 231. 201 is the resistance value of load resistor 201, i is the amplitude of the current sampling signal output by current sampling circuit 20, m is the coupling coefficient between the equivalent circuit 23 of the main circuit and current sampling circuit 20, and C 210 It is the capacitance value of the voltage divider capacitor 210, C. 232 is the capacitance value of the equivalent capacitor 232, u is the amplitude of the voltage sampling signal output by the voltage sampling circuit 21, and n is the coupling coefficient between the equivalent circuit 23 of the main circuit and the voltage sampling circuit 21.

[0035] If the voltage of the main circuit is greater than the voltage threshold and the current of the main circuit is greater than the current threshold, then the RF power supply is considered to start outputting an RF signal. The signal controller 221 can calculate impedance and power, etc., based on the voltage and current of the main circuit. Wherein, impedance Z = (V / I) × e jθ =R + jX = (V / I) × cosθ + j × (V / I) × sinθ, power P = V × I, θ is the phase angle of the impedance, R is the real part of the impedance, X is the imaginary part of the impedance, and j is the imaginary unit, satisfying j 2 =-1.

[0036] Because the coupling coefficients m and n of the impedance detection circuit 10 are fixed, and the resolution of the analog-to-digital converter 220 is also fixed, the impedance detection circuit 10 can only sample the voltage and current of the main circuit within a specific range. For example, if n is 1000:1 and the resolution of the analog-to-digital converter 220 is 0.01V-1V, then the range of the voltage of the main circuit that can be sampled is 10V-1000V; if m is 50:1 and the resolution of the analog-to-digital converter 220 is 0.01V-1V, then the range of the current of the main circuit that can be sampled is 0.5A-50A.

[0037] When the output power of the RF power supply is extremely low or extremely high, for example, the voltage of the main circuit is less than 10V or greater than 1000V, or the current of the main circuit is less than 0.5A or greater than 50A, the resolution of the analog-to-digital converter 220 is insufficient, and it cannot sample the voltage and current signals of the main circuit. This results in poor signal processing accuracy of the signal processing circuit where the analog-to-digital converter is located, and poor impedance matching accuracy of the impedance matching device.

[0038] Furthermore, when the output power of the RF power supply is the same, the current and voltage of the main circuit change with the impedance of the RF power supply. When the impedance is extremely low, the voltage in the main circuit will be extremely low, resulting in a very small voltage sampling signal input to the analog-to-digital converter 220. As shown in Table 1, when the impedance is 0.5 + j * 0.5 ohms, the voltage sampling signal is less than 0.01V. The insufficient resolution of the analog-to-digital converter 220 will cause the impedance detection circuit 10 to fail to accurately identify and sample the voltage in the main circuit, leading to poor signal processing accuracy in the signal processing circuit where the analog-to-digital converter is located, and poor impedance matching accuracy of the impedance matching device. When the impedance is extremely high, the current in the main circuit will be extremely low, resulting in a very small current sampling signal input to the analog-to-digital converter 220. As shown in Table 1, when the impedance is 500 + j * 500 ohms, the current sampling signal is less than 0.01V. The insufficient resolution of the analog-to-digital converter 220 will also cause the impedance detection circuit 10 to fail to accurately identify and sample the current in the main circuit, leading to poor signal processing accuracy in the signal processing circuit where the analog-to-digital converter is located, and poor impedance matching accuracy of the impedance matching device.

[0039] Table 1

[0040] Power (W) Impedance (Ω) Voltage (V) Current (A) Voltage sampling (V) Current sampling (V) 50 50 70 1 0.07 0.02 50 0.5+j*0.5 1.98 1.980198 0.00198 0.039604 50 500+j*500 134 0.134371 0.134 0.002687

[0041] Based on this, the present invention discloses an impedance detection circuit that, by increasing the amplitude of the voltage signal input to the analog-to-digital converter, enables the analog-to-digital converter to accurately identify and sample the current and voltage of a wider range of radio frequency power supplies, thereby increasing the signal sampling range of the impedance detection circuit, improving the signal processing accuracy of the signal processing circuit where the analog-to-digital converter is located, and improving the impedance matching accuracy of the impedance matching device.

[0042] As an optional implementation of the disclosed content of this invention, an embodiment of this invention discloses an impedance detection circuit, such as... Figure 3 and Figure 4 As shown, Figure 3 This is a schematic diagram of an impedance detection circuit disclosed in an embodiment of the present invention. Figure 4 for Figure 3 The equivalent circuit diagram of the impedance detection circuit shown includes a center conductor 30, a first winding 310, a second winding 311, a capacitor 312, and a processing circuit.

[0043] The center conductor 30 is connected in series with the RF power supply 40 and the load R. L Between. In some embodiments, the center conductor 30 is a strip-shaped conductor.

[0044] The first end of capacitor 312 is connected to the center conductor 30, and the second end of capacitor 312 is connected to the first end of the first winding 310 and the first end of the second winding 311, respectively.

[0045] The first end of the first winding 310 and the first end of the second winding 311 are both connected to the first node A, and the second end of the first winding 310 and the second end of the second winding 311 are both connected to the second node B. The winding direction of the first winding 310 is opposite to that of the second winding 311, and the loop circuit formed by the first winding 310 and the second winding 311 is arranged in a circle around the central conductor 30.

[0046] The processing circuit is connected to the first node A and the second node B respectively, and is used to obtain the current signal and voltage signal of the center conductor 30 based on the first voltage signal of the first node A and the second voltage signal of the second node B.

[0047] In some embodiments of the present invention, the first winding 310 and the second winding 311 are symmetrically arranged.

[0048] The first winding 310 partially surrounds the central conductor 30. The first winding 310 is used to couple the current signal output from the radio frequency power supply 40 to the central conductor 30 to obtain the first sampling voltage signal V. MA According to the principle of electromagnetic induction, when current flows through the central conductor 30, a changing magnetic field is generated around the central conductor 30, and the first winding 310, which is in the changing magnetic field, will generate an induced voltage, i.e., the first sampling voltage signal V. MA Furthermore, the magnitude of the induced voltage generated by the first winding 310 is proportional to the magnitude of the current flowing through the center conductor 30.

[0049] The second winding 311 partially surrounds the center conductor 30. The second winding 311 is used to couple the current signal output from the RF power supply 40 to the center conductor 30 to obtain the third sampling voltage signal V.MB Similarly, the second winding 311, located in the changing magnetic field around the central conductor 30, will also generate an induced voltage, namely the third sampling voltage signal V. MB Furthermore, the magnitude of the induced voltage generated by the second winding 311 is proportional to the magnitude of the current flowing through the center conductor 30.

[0050] Capacitor 312 is connected in series between the center conductor 30 and the first winding 310 and the second winding 311. Specifically, one end of capacitor 312 is electrically connected to the center conductor 30, and the other end of capacitor 312 is electrically connected to the first winding 310 and the second winding 311. Capacitor 312 is used to couple the voltage signal output from the RF power supply 40 to the center conductor 30 to obtain the second sampling voltage signal V. E Specifically, by utilizing the voltage division effect between capacitor 312 and the equivalent capacitance of the central conductor 30, the voltage signal on the central conductor 30 can be sampled to obtain the second sampled voltage signal V. E Furthermore, the second sampled voltage signal V E The magnitude of the voltage is proportional to the magnitude of the voltage across the center conductor 30.

[0051] The first voltage signal V of the first node A A Equal to the first sampled voltage signal V MA Second sampled voltage signal V E The sum. The second voltage signal V at the second node B. B Equal to the third sampled voltage signal V MB With the second sampled voltage signal V E The sum. Wherein, the first voltage signal V of the first node A. A The second voltage signal V of the second node B B For input to an analog-to-digital converter, Z L This represents the input impedance of the analog-to-digital converter.

[0052] Because the first voltage signal V of the first node A A Equal to the first sampled voltage signal V MA Second sampled voltage signal V E The sum of the two voltage signals V at the second node B. B Equal to the third sampled voltage signal V MB With the second sampled voltage signal V E The sum of these, therefore, the first voltage signal V of the first node A. A The amplitude is greater than the first sampled voltage signal V. MA The amplitude or second sampled voltage signal V E The amplitude of the second voltage signal V at the second node B. B The amplitude is greater than that of the third sampled voltage signal V. MB The amplitude or second sampled voltage signal VE The range.

[0053] Even when the output power of the RF power supply is extremely small or extremely large, although the first sampled voltage signal V MA Second sampling voltage signal V EA Or the third sampled voltage signal V MB The amplitude is relatively small, but the first voltage signal V of the first node A is... A The second voltage signal V of the second node B B The amplitude is relatively large. When the output power of the RF power supply is the same but the impedance of the RF power supply is extremely small, although the second sampled voltage signal V... E The amplitude is small, but the first sampled voltage signal V MA and the third sampled voltage signal V MB The amplitude is relatively large, and the first voltage signal V of the first node A is large. A The second voltage signal V of the second node B B The amplitude is also relatively large. Even with the same output power from the RF power supply but with extremely high impedance, although the first sampled voltage signal V... MA and the third sampled voltage signal V MB The amplitude is small, however, the second sampled voltage signal V E The amplitude is relatively large, and the first voltage signal V of the first node A is large. A The second voltage signal V of the second node B B The range is also quite large.

[0054] Because the first voltage signal V of the first node A A The second voltage signal V of the second node B B Since the sampled voltage signal is input to the analog-to-digital converter, therefore, with Figure 2 Compared to the impedance detection circuit shown, this circuit can increase the amplitude of the sampling voltage signal input to the analog-to-digital converter (ADC), enabling the ADC to accurately identify and sample a wider range of RF power supply current and voltage. This increases the signal sampling range of the impedance detection circuit, thereby improving the signal processing accuracy of the signal processing circuit where the ADC is located and enhancing the impedance matching accuracy of the impedance matching device.

[0055] In some embodiments of the present invention, such as Figure 3 As shown, the impedance detection circuit also includes a printed circuit board 50. The printed circuit board 50 includes a central opening 500, through which a central conductor 30 passes. An insulating layer 504 is provided between the central conductor 30 and the interior of the central opening 500. The insulating layer 504 is used to fix the central conductor 30 in the central opening 500 and to insulate the central conductor 30 from other structures.

[0056] Both the first winding 310 and the second winding 311 include multi-turn coils. Each turn of the coil includes a first via 5010, a first trace 5011, a second via 5012, and a second trace 5013. The first via 5010 and the second via 5012 penetrate the printed circuit board 50. The first trace 5011 and the second trace 5013 are located on opposite sides of the printed circuit board 50, and their extension directions intersect. The first trace 5011 is used to electrically connect the first via 5010 and the second via 5012 of the same turn of the coil, and the second trace 5013 is used to electrically connect the second via 5012 of the same turn of the coil and the first via 5010 of different turns of the coil.

[0057] Each capacitor 312 includes multiple third vias 5014 and multiple third traces 5015. The third vias 5014 penetrate the printed circuit board 50. The third traces 5014 are located on one side of the printed circuit board 50, and each third trace 5015 is used to electrically connect a third via 5014 and a first via 5010.

[0058] In this capacitor 312, the sidewall of the center conductor 30 corresponds to one electrode plate, the multiple third vias 5014 correspond to the other electrode plate, and the insulating layer 504 corresponds to the insulating medium between the two electrode plates. It should be noted that insulating layers 504 made of different materials can achieve not only different insulation properties but also different capacitance values ​​for the capacitor 312.

[0059] In some embodiments of the present invention, all first vias 5010 are arranged sequentially on a first circumference surrounding the central opening 500, and all second vias 5012 are arranged sequentially on a second circumference surrounding the central opening 500, such that the first winding 310 and the second winding 311 at least partially surround the central conductor 30. All third vias 5014 are arranged sequentially on a third circumference surrounding the central opening 500, such that the plurality of third vias 5014 and the central conductor 30 form a capacitor 312. The radius of the first circumference is smaller than the radius of the second circumference, and the radius of the third circumference is smaller than the radius of the first circumference.

[0060] Of course, the present invention is not limited to this. In some other embodiments, all the first vias 5010 may be arranged sequentially on the boundary of the square pattern surrounding the central opening 500, all the second vias 5012 may be arranged sequentially on the boundary of the square pattern surrounding the central opening 500, and all the third vias 5014 may be arranged sequentially on the boundary of the square pattern surrounding the central opening 500. These will not be described in detail here.

[0061] In some embodiments of the present invention, the orthographic projection of the third via 5014 on the printed circuit board 50 is an arc-shaped pattern, so that the third via 5014 can be fully coupled with the center conductor 30 to form a capacitor 312. Furthermore, by making multiple discontinuous third vias 5014 constitute another electrode plate of the capacitor 312, the amplitude of the voltage signal obtained by the capacitor 312 can be guaranteed, and short circuits between coils of different turns can be avoided.

[0062] In some embodiments of the present invention, the printed circuit board 50 further includes a conductive layer 501 located around the first winding 310, the second winding 311, and the capacitor 312, and the conductive layer 501 is grounded through a fourth via 5015. In addition, other openings 502 on the printed circuit board 50 are used for mounting screws, etc.

[0063] Based on this, in some embodiments of the present invention, such as Figure 5 As shown, Figure 5 This is a schematic diagram of a series structure of a center conductor and a radio frequency power supply disclosed in an embodiment of the present invention. The radio frequency power supply 40 and the load R L The coaxial line 60 and the center conductor 30 are electrically connected. The coaxial line 60 includes a conductor 601 located at its center and an insulating layer 602 and a shielding layer 603 that are sequentially wrapped around the conductor. The center conductor 30 is electrically connected to the conductor 601, and the conductive layer 501 is electrically connected to the shielding layer 603 so that the shielding layer 603 is grounded.

[0064] In some embodiments of the present invention, the first winding 310 and the second winding 311 have the same structure (e.g., the number of turns of the coil) and the first winding 310 and the second winding 311 are symmetrically arranged on both sides of the center conductor 30, so that the third sampling voltage signal V MB With the first sampled voltage signal V MA They are equal in size and opposite in polarity.

[0065] The magnetic field generated by the central conductor 30 can be obtained according to the Biot-Sava theorem. Specifically, the magnetic flux density B can be obtained according to the formula B = μI / 2πR, where μ is the permeability, I is the current in the central conductor 30, and R is the distance from any magnetic field measurement point to the center of the central conductor 30. The magnetic flux of each turn of the coil can be obtained. Where b is the distance from the center of the second via 5012 to the center of the center conductor 30, a is the distance from the center of the first via 5010 to the center of the center conductor 30, and h is the thickness of the printed circuit board 50.

[0066] According to Lenz's law, when the amplitude of the current in the central conductor 30 is I and the frequency is f, the magnetic field around the central conductor 30 will induce a voltage in the first winding 310 or the second winding 311. N is the number of turns in the coil. Changing h, a, b, or N will change the induced voltage V. M The proportionality coefficient with the current in the center conductor 30.

[0067] When the first winding 310 and the second winding 311 have the same structure (e.g., the number of turns of the coil) and the first winding 310 and the second winding 311 are symmetrically arranged on both sides of the center conductor 30, such as Figure 6 As shown, Figure 6 The equivalent circuit diagram of the first winding and the second winding disclosed in this embodiment of the invention allows for the calculation of the voltage output from the first winding 310 to point A, i.e., the first sampled voltage signal. The voltage output from the second winding 311 to point B is the third sampled voltage signal. L is the inductance of the first winding 310 and the second winding 311. Let... V can be obtained MA =I×m,V MB =―I×m.

[0068] like Figure 7 As shown, Figure 7 The equivalent circuit diagram of the center conductor, first winding, and second winding disclosed in this embodiment of the invention allows for the calculation of the voltage output from capacitor 312 to the first node A and the second node B, i.e., the second sampled voltage signal V. E .in, V is the voltage across the center conductor 30, and C is... e Let be the capacitance value of capacitor 312. V can be obtained E =V×n, because capacitor 312 is connected in series with the first winding 310 and the second winding 311, therefore, the voltage at the first node A is the first voltage signal V. A =V E +V MA = V×n+I×m, where the voltage at the second node B is the second voltage signal V. B =V E +V MB =V×n―I×m.

[0069] With n = 1000:1 and m = 50:1, as shown in Table 2, the minimum voltage input to the analog-to-digital converter (ADC) changes from 0.00198 to 0.037624, and the ratio of the maximum voltage to the minimum voltage changes from 67 times to 3.6 times. This reduces the amplitude fluctuation range of the signal input to the ADC, enabling the ADC to accurately identify and sample the current and voltage of a wider range of RF power supplies. It also improves the signal sampling range and accuracy of the impedance detection circuit, enhances the signal processing accuracy of the signal processing circuit where the ADC is located, and improves the impedance matching accuracy of the impedance matching device.

[0070] Table 2

[0071]

[0072] In some embodiments of the present invention, such as Figure 8 As shown, Figure 8 This is a schematic diagram of another impedance detection circuit disclosed in an embodiment of the present invention. The impedance detection circuit further includes an analog-to-digital converter 220 and a signal controller 221. The analog-to-digital converter 220 is connected to the first node A and the second node B respectively, and is used to convert the first voltage signal V... A Converted to the first digital signal V A ', the second voltage signal V B Converted to a second digital signal V B The signal controller 221 is connected to the analog-to-digital converter 220 and is used to determine the signal based on the first digital signal V. A ' and second digital signal V B The sum of ' is used to obtain the voltage signal of the central conductor 30, based on the first digital signal V. A ' and second digital signal V B The difference between ' and ' is used to obtain the current signal of the center conductor 30.

[0073] In some embodiments of the present invention, such as Figure 8 As shown, the signal controller 221 is used to receive the first digital signal V output by the analog-to-digital converter 220. A ' and second digital signal V B ', and according to the first digital signal V A The product of ' and the first coupling coefficient with the second digital signal V B The sum of the product of the first digital signal and the second coupling coefficient is used to obtain the voltage sampling signal V of the voltage signal on the center conductor 30, based on the first digital signal V. A The product of ' and the third coupling coefficient with the second digital signal V B The difference between the product of the first and fourth coupling coefficients is used to obtain the current sampling signal I on the central conductor 30. The first coupling coefficient is not equal to the second, third, and fourth coupling coefficients.

[0074] Among them, the signal controller 221 can convert the first digital signal V A 'and the second digital signal V B The summation yields a signal V that is only related to voltage. sum The first digital signal V A 'and the second digital signal V B Subtraction yields a signal V that is only related to the current. diff Among them, V sum =V A '+V B '=2×V×n, V diff =V A '-V B ' = 2 × I × n. Then, the signal controller 221 can calculate with the coupling coefficient to obtain the accurate values ​​of the voltage and current of the radio frequency power supply.

[0075] like Figure 9 As shown, Figure 9 This is a schematic diagram of a traditional signal controller. The analog-to-digital converter 220 outputs the first digital signal V. A ' and second digital signal V B Afterwards, the signal controller 221 uses a multiplier, a low-pass filter, and a rectangular-to-polar coordinate conversion unit to convert the first digital signal V... A The signal is converted into a first data signal VAmag, represented by amplitude, and a second data signal VAphase, represented by phase, and the second digital signal V is converted into a second digital signal V. B The first data signal VAmag is converted into a third data signal VBmag, which is represented by amplitude, and a fourth data signal VBphase, which is represented by phase. The first data signal VAmag is the first digital signal V. A The amplitude component of ', the second data signal VAphase is the first digital signal V A The phase component of ', the third data signal VBmag is the second digital signal V B The amplitude component of ', the fourth data signal VBphase is the second digital signal V B The phase component of ' is obtained by adding the first data signal VAmag and the third data signal VBmag, subtracting the second data signal VAphase and the fourth data signal VBphase, and then respectively dividing the result by the voltage coupling coefficient n×e. jθn The coupling coefficient m×e with current jθm Multiplying them yields a vector voltage signal V and a current signal I, where V = (V0 + V1)2 + V3 + I4 + I5 + I6 + I7 + I8 + I9 + I1 + I2A '+V B ')×n×e jθn , I = (V A '-V B')×m×e jθm .

[0076] However, in practical applications, manufacturing errors on printed circuit boards can lead to circuit imbalances, resulting in discrepancies in the sampled first digital signal V. A ' and second digital signal V B The components of the first data signal VAmag, the second data signal VAphase, the third data signal VBmag, and the fourth data signal VBphase are unbalanced, resulting in V obtained by adding and subtracting the first data signal VAmag, the second data signal VAphase, the third data signal VBmag, and the fourth data signal VBphase, respectively. sum With V diff It cannot be completely decoupled, that is, V sum There will still be a contribution from the current, V diff The voltage will still contribute to the test, causing the error of the test results under different impedances to vary with the impedance, resulting in larger errors under some impedances.

[0077] like Figure 10 As shown, Figure 10 for Figure 9 The voltage and current measurement results output by the signal controller are shown. Z1, Z2, and Z3 represent three different impedances. It can be seen that the ratio of the voltage measurement value Vtest to the actual voltage value V varies with different impedances, and the ratio of the current measurement value Isit to the actual current value I also varies with different impedances, resulting in a large error between the measured voltage and current and the actual voltage and current.

[0078] like Figure 11 As shown, Figure 11 This is a schematic diagram of a signal controller disclosed in an embodiment of the present invention. Before the first data signal VAmag, the second data signal VAphase, the third data signal VBmag, and the fourth data signal VBphase are added and subtracted respectively, a vector multiplication module is added to each of them, so that the first data signal VAmag, the second data signal VAphase, the third data signal VBmag, and the fourth data signal VBphase are respectively multiplied by n1e. jθn1 m1e jθm1 n2e jθn2 and m2e jθm2 Multiplication is used to perform vector correction, resulting in the final V. sum With V diff Complete decoupling yields more accurate calibration results. Wherein, n1e jθn1 n2e jθn2 m1e jθm1 m2e jθm2These are the first coupling coefficient, the second coupling coefficient, the third coupling coefficient, and the fourth coupling coefficient, respectively.

[0079] In other words, in this embodiment of the invention, the signal controller 221 determines the first data signal VAmag and the first coupling coefficient n1e based on... jθn1 The product of the third data signal VBmag and the second coupling coefficient n2e jθn2 The sum of the products is used to obtain the voltage signal V on the central conductor 30, based on the second data signal VAphase and the third coupling coefficient m1e. jθm1 The product of the fourth data signal VBphase and the fourth coupling coefficient m2e jθm2 The difference between the products is used to obtain the current signal I on the central conductor 30.

[0080] In an ideal situation, n1e jθn1 =n2e jθn2 =0.5×n×e jθn m1e jθm1 =m2e jθm2 =0.5×m×e jθm V = V A ×0.5×n×e jθn +V B ×0.5×n×e jθn =(V A +V B )×0.5×n×e jθn I = V A ×0.5×m×e jθm +V B ×0.5×m×e jθm =(V A +V B )×0.5×m×e jθm However, in reality, due to circuit imbalance, interference, and parasitic parameters, n1e jθn1 ≠n2e jθn2 ≠0.5×n×e jθn m1e jθm1 ≠m2e jθm2 ≠0.5×m×e jθm Using n1e jθn1 n2e jθn2 m1e jθm1 and m2e jθm2 After correcting for the circuit imbalance, more accurate calibration results can be obtained. Where V = V A ×n1×e jθn1 +V B ×n2×e jθn2 I = V A ×m1×ejθm1 +V B ×m2×e jθm2 n1, n2, n3, and n4 are all different.

[0081] It should be noted that in actual measurements, n1e jθn1 and n2e jθn2 With 0.5×n×e jθn It's close, m1e jθm1 and m2e jθm2 With 0.5×m×e jθm It is close; it can be determined by measuring standard signals at multiple known impedances, specifically 0.5 × n × e. jθn and 0.5×m×e jθm It was obtained through fine-tuning.

[0082] like Figure 12 As shown, Figure 12 for Figure 11 The measured results of the voltage and current output by the signal controller shown are consistent with... Figure 10 Compared to the previous method, the ratio of the voltage measurement value Vtest to the actual voltage value V remains basically 1:1, and the ratio of the current measurement value Isit to the actual current value I remains basically 1:1. The measurement error is small, and the measurement accuracy is significantly improved.

[0083] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses an impedance matching device, such as... Figure 1 As shown, the impedance matching device includes an impedance detection circuit 10, a matching controller 11, an actuator 12, and an impedance matching network 13 as disclosed in any of the above embodiments.

[0084] Impedance detection circuit 10 is used to sample the voltage and current signals output by the RF power supply; matching controller 11 is used to obtain adjustment signals based on the voltage and current signals sampled by the impedance detection circuit; and actuator 12 is used to adjust the impedance of impedance matching network 13 according to the adjustment signals to perform impedance matching on the RF power supply.

[0085] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a semiconductor process apparatus, such as... Figure 13 As shown, Figure 13 This is a schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of the present invention. The semiconductor process equipment includes a radio frequency power supply, an impedance matching device, a process chamber 1, an air intake assembly 2, an air extraction assembly (not shown in the figure), an upper electrode assembly, a lower electrode assembly, and a controller (not shown in the figure).

[0086] The radio frequency (RF) power supply includes an upper RF power supply 31 and a lower RF power supply 41, and the impedance matching device includes a first matching device 32 and a second matching device 42. The RF power supply is used to provide power to the process chamber 1, and the impedance matching device is used to match the impedance of the RF power supply with that of the process chamber 1.

[0087] The air intake assembly 2 is used to introduce gas into the process chamber 1, including etching gas, etc. The controller is used to control the opening or closing of the electronic valve of the air intake assembly 2, so as to control the air intake assembly 2 to start or stop introducing gas into the process chamber 1.

[0088] The extraction assembly is used to extract gas from process chamber 1, including byproduct gases generated after the etching reaction. The controller can also control the opening and closing of the electronic valves of the extraction assembly to control the start or stop of gas extraction from process chamber 1. Furthermore, the controller can also control the valve size of both the electronic valves of the inlet assembly 2 and the extraction assembly to control the chamber pressure of process chamber 1.

[0089] The upper electrode assembly includes an upper RF power supply 31, a first matching unit 32 electrically connected to the upper RF power supply 31, and an RF coil 33 electrically connected to the first matching unit 32. The upper RF power supply 31 can be electrically connected to the RF coil 33 within the process chamber 1 via the first matching unit 32, thereby applying RF power to the RF coil 33. This allows the RF coil 33 to couple the RF power into the process chamber 1 through the dielectric window 5, ionizing the gas within the process chamber 1 into plasma 6. The controller can also be used to control the amount of RF power applied by the upper RF power supply 31 to the RF coil 33 via the first matching unit 32.

[0090] The lower electrode assembly includes a lower RF power supply 41, a second matching unit 42 electrically connected to the lower RF power supply 41, and a carrier device 43 electrically connected to the second matching unit 42. The carrier device 43 includes an electrostatic chuck, etc. The lower RF power supply 41 is electrically connected to the carrier device 43 via the second matching unit 42 and is used to apply bias power to the carrier device 43. The carrier device 43 is used to carry the device 7 to be fabricated and to heat or cool the device 7 to be fabricated according to the bias power.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the protection scope of this specification. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. An impedance detection circuit, characterized in that, include: The components include a center conductor, a first winding, a second winding, a capacitor, and a processing circuit; among which: The center conductor is used to connect in series between the RF power supply and the load; The first end of the capacitor is connected to the center conductor, and the second end of the capacitor is connected to the first winding and the second winding respectively; The first end of the first winding and the first end of the second winding are both connected to the first node, and the second end of the first winding and the second end of the second winding are both connected to the second node; The first winding is wound in the opposite direction to the second winding, and the loop circuit formed by the first winding and the second winding is arranged in a circle around the central conductor. The processing circuit is connected to the first node and the second node respectively, and is used to obtain the current signal and voltage signal of the central conductor based on the first voltage signal of the first node and the second voltage signal of the second node.

2. The impedance detection circuit according to claim 1, characterized in that, The first winding and the second winding are arranged symmetrically.

3. The impedance detection circuit according to claim 1, characterized in that, It also includes printed circuit boards; The printed circuit board includes a central opening; the central conductor passes through the central opening; Both the first winding and the second winding include multi-turn coils; each turn includes a first via, a first trace, a second via, and a second trace; the first via and the second via penetrate the printed circuit board; the first trace and the second trace are located on opposite sides of the printed circuit board; the first trace is used to electrically connect the first via and the second via of the same turn, and the second trace is used to electrically connect the second via of the same turn and the first via of different turns. The capacitor includes multiple third vias and multiple third traces; the third vias penetrate the printed circuit board; the third traces are located on one side of the printed circuit board; each third trace is used to electrically connect one third via and one first via.

4. The impedance detection circuit according to claim 3, characterized in that, All first vias are arranged sequentially on a first circumference surrounding the central opening; all second vias are arranged sequentially on a second circumference surrounding the central opening; all third vias are arranged sequentially on a third circumference surrounding the central opening; the radius of the first circumference is smaller than the radius of the second circumference; the radius of the third circumference is smaller than the radius of the first circumference.

5. The impedance detection circuit according to claim 3, characterized in that, The orthographic projection of the third via on the printed circuit board is an arc-shaped pattern, and the orthographic projections of all the third vias on the printed circuit board are located on the same circumference.

6. The impedance detection circuit according to claim 3, characterized in that, The number of third vias electrically connected to the first winding is the same as the number of third vias electrically connected to the second winding.

7. The impedance detection circuit according to claim 1, characterized in that, The processing circuit includes: an analog-to-digital converter and a signal controller; The analog-to-digital converter is connected to the first node and the second node respectively, and is used to convert the first voltage signal into a first digital signal and the second voltage signal into a second digital signal; The signal controller is connected to the analog-to-digital converter and is used to obtain the voltage signal of the center conductor based on the sum of the first digital signal and the second digital signal, and to obtain the current signal of the center conductor based on the difference between the first digital signal and the second digital signal.

8. The impedance detection circuit according to claim 7, characterized in that, The signal controller is used to obtain the voltage signal on the central conductor based on the sum of the product of the first digital signal and the first coupling coefficient and the product of the second digital signal and the second coupling coefficient, and to obtain the current signal on the central conductor based on the difference between the product of the first digital signal and the third coupling coefficient and the product of the second digital signal and the fourth coupling coefficient.

9. The impedance detection circuit according to claim 8, characterized in that, The signal controller is used to convert the first digital signal into a first data signal and a second data signal, wherein the first data signal is the amplitude component of the first digital signal and the second data signal is the phase component of the first digital signal; to convert the second digital signal into a third data signal and a fourth data signal, wherein the third data signal is the amplitude component of the second digital signal and the fourth data signal is the phase component of the second digital signal; to obtain the voltage signal on the central conductor based on the sum of the product of the first data signal and the first coupling coefficient and the product of the third data signal and the second coupling coefficient; and to obtain the current signal on the central conductor based on the difference between the product of the second data signal and the third coupling coefficient and the product of the fourth data signal and the fourth coupling coefficient.

10. An impedance matching device, characterized in that, Includes a matching controller, an actuator, an impedance matching network, and an impedance detection circuit as described in any one of claims 1 to 9; The impedance detection circuit is used to sample the voltage and current signals output by the RF power supply. The matching controller is used to obtain an adjustment signal based on the voltage signal and the current signal; The actuator is used to adjust the impedance of the impedance matching network according to the adjustment signal.

11. A semiconductor process apparatus, characterized in that, The device includes a radio frequency (RF) power supply, an impedance matching device as described in claim 10, and a process chamber, wherein the RF power supply is used to provide RF power to the process chamber, and the impedance matching device is used to match the impedance of the RF power supply to the process chamber.

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