Method and system for managing the service life of a driving chip based on digital twinning

Abstract

This invention discloses a method and system for managing the lifespan of a driver chip based on digital twins. The invention relates to the technical field of driver chips. By tracing the various deviations output by the driver chip twin, corresponding multi-source anomaly data is determined. This multi-source anomaly data is then mapped in multiple directions to the actual working content of the driver chip at the physical layer, thereby dynamically constructing a corresponding lifespan topology map. Furthermore, by combining a long short-term memory mechanism, corresponding temporal degradation features are extracted, improving the accuracy of the driver chip's temporal degradation features. Multi-level iterations are performed on each critical phase transition point to predict the driver chip's lifespan characteristic combination under current operating conditions, determining the remaining lifespan of the driver chip. This remaining lifespan is then integrated with the current usage history of the driver chip, improving the accuracy of the driver chip's lifespan management system.

Description

Technical Field

[0001] This invention relates to the technical field of driver chips, and in particular to a method and system for managing the lifespan of driver chips based on digital twins. Background Technology

[0002] As core actuators in modern power electronics and control systems, driver chips (such as motor driver chips and power management ICs) operate under extreme conditions of high-frequency switching, high current, and complex thermal interaction for extended periods. Their internal packaging materials and semiconductor structures inevitably undergo degradation phenomena such as electrothermal fatigue, bond wire detachment, or oxide layer breakdown. Once a driver chip fails, it often leads to the shutdown of the entire system or even causes catastrophic safety accidents. Accurate lifespan management and remaining useful life (RUL) prediction of driver chips are crucial to ensuring the high reliability of the system.

[0003] Meanwhile, the driver chip generates multi-physical field coupling effects such as electricity, heat, and vibration during operation. Existing technologies usually only perform simple synchronous splicing of parameters in each dimension, failing to eliminate the timestamp delay and spatial phase difference caused by the difference between signal transmission path and physical response speed. This results in distortion of the input data itself, affecting the accuracy of the timing degradation characteristics of the driver chip and leading to low accuracy of the driver chip's lifespan management system. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a method and system for lifespan management of driver chips based on digital twins.

[0005] This invention provides a method for managing the lifespan of a driver chip based on digital twins, comprising:

[0006] During the operation of the driver chip, multiple parameters of the driver chip in different dimensions are collected, the multiple parameters are spatiotemporally aligned, and the online data cluster of the driver chip is determined by combining the state detection signal of the driver chip. The online data cluster is input into the digital twin space, and the corresponding driver chip twin is determined by combining the preset digital twin mechanism.

[0007] The driver chip twin dynamically outputs multiple deviation contents, and determines the corresponding multi-source abnormal data by tracing each deviation content. The multi-source abnormal data is then mapped in multiple directions with the actual working content of the driver chip at the physical level, thereby dynamically constructing the corresponding lifespan topology map and extracting the corresponding temporal degradation features by combining the long short-term memory mechanism.

[0008] The corresponding nonlinear degradation trajectory is formed by sorting along the various time-series degradation features. Combined with the dynamic optimization mechanism of the driver chip, the critical phase transition point that triggers the abnormal situation in the driver chip is located. Multi-level iteration is performed on each critical phase transition point, and failure inference is performed during the iteration process to predict the combination of lifespan characteristics of the driver chip under the current working conditions, and further determine the remaining lifespan of the driver chip.

[0009] The remaining lifespan is integrated with the current usage history of the driver chip to dynamically build a lifespan management system for the driver chip. The system also determines emergency measures for the driver chip's operation based on the lifespan threshold and corresponding safety margin, and simultaneously triggers a re-inspection of the driver chip's remaining lifespan.

[0010] This invention provides a lifespan management system for a driver chip based on digital twins. The lifespan management system is applied to the aforementioned lifespan management method for driver chips based on digital twins. The lifespan management system for the driver chip based on digital twins includes:

[0011] The driver chip twin module is used to collect multiple parameters of the driver chip in different dimensions during the operation of the driver chip, perform spatiotemporal alignment of the multiple parameters, and determine the online data cluster of the driver chip by combining the status detection signal of the driver chip. The online data cluster is then input into the digital twin space, and the corresponding driver chip twin is determined by combining the preset digital twin mechanism.

[0012] The topology module is used to dynamically output multiple deviation contents of the driver chip twin, determine the corresponding multi-source abnormal data by tracing each deviation content, and perform multi-directional mapping between the multi-source abnormal data and the actual working content of the driver chip at the physical level, thereby dynamically constructing the corresponding lifespan topology map, and extracting the corresponding temporal degradation features by combining the long short-term memory mechanism.

[0013] The iterative module is used to form a corresponding nonlinear degradation trajectory by sorting along various temporal degradation features, and combined with the dynamic optimization mechanism of the driver chip, locate the critical phase transition point that triggers abnormal conditions in the driver chip. It performs multi-level iterations on each critical phase transition point and performs failure inference during the iteration process, thereby predicting the combination of lifespan characteristics of the driver chip under the current operating conditions, and further determining the remaining lifespan of the driver chip.

[0014] The emergency module is used to integrate the remaining lifespan with the current usage history of the driver chip, thereby dynamically constructing a lifespan management system for the driver chip. It also determines emergency measures for the operation of the driver chip by combining the lifespan threshold and the corresponding safety margin, and simultaneously triggers a re-inspection of the remaining lifespan of the driver chip.

[0015] Compared with the prior art, the beneficial effects of the present invention are:

[0016] (1) During the operation of the driver chip, multiple parameters of the driver chip in different dimensions are collected, the multiple parameters are spatiotemporally aligned, and the online data cluster of the driver chip is determined by combining the state detection signal of the driver chip. The online data cluster is input into the digital twin space, and the corresponding driver chip twin is determined by combining the preset digital twin mechanism. The driver chip twin dynamically outputs multiple deviation contents. The corresponding multi-source abnormal data is determined by tracing along each deviation content. The multi-source abnormal data is mapped to the actual working content of the driver chip at the physical level in multiple directions, thereby dynamically constructing the corresponding lifespan topology map. The corresponding time degradation features are extracted by combining the long short-term memory mechanism. The driver chip twin is introduced to further control the multi-source abnormal data and improve the accuracy of the time degradation features of the driver chip.

[0017] (2) The corresponding nonlinear degradation trajectory is formed by sorting the various time-series degradation characteristics, and the critical phase transition point that triggers the abnormal situation in the driver chip is located by combining the dynamic optimization mechanism of the driver chip. The critical phase transition point is iterated in multiple levels, and failure is deduced in the iteration process to predict the combination of the lifespan characteristics of the driver chip under the current working condition, and further determine the remaining lifespan of the driver chip. The remaining lifespan is integrated with the current usage history of the driver chip to dynamically construct the lifespan management system of the driver chip. The emergency measures for the operation of the driver chip are determined by combining the lifespan threshold and the corresponding safety margin, and the re-inspection of the remaining lifespan of the driver chip is triggered simultaneously. The combination of the lifespan characteristics of the driver chip under the current working condition is introduced, and the remaining lifespan and the current usage history of the driver chip are fully considered, which improves the accuracy of the lifespan management system of the driver chip. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the lifespan management method for a driver chip based on digital twins in an embodiment of the present invention.

[0019] Figure 2 This is a flowchart illustrating step S11 in the lifespan management method for driver chips based on digital twins in an embodiment of the present invention.

[0020] Figure 3 This is a flowchart illustrating step S12 in the lifespan management method for driver chips based on digital twins in an embodiment of the present invention.

[0021] Figure 4 This is a flowchart illustrating step S13 in the lifespan management method for driver chips based on digital twins in an embodiment of the present invention.

[0022] Figure 5 This is a flowchart illustrating step S14 of the lifespan management method for driver chips based on digital twins in an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the structural composition of the lifespan management system for a driver chip based on digital twins in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0025] Please see Figures 1 to 6 A lifespan management method for driver chips based on digital twins is applied to driver chip scenarios. The lifespan management method for driver chips based on digital twins includes:

[0026] Step S11: During the operation of the driver chip, multiple parameters of the driver chip in different dimensions are collected, the multiple parameters are spatiotemporally aligned, and the online data cluster of the driver chip is determined by combining the state detection signal of the driver chip. The online data cluster is input into the digital twin space, and the corresponding driver chip twin is determined by combining the preset digital twin mechanism.

[0027] Step S12: The driver chip twin dynamically outputs multiple deviation contents, and determines the corresponding multi-source abnormal data by tracing each deviation content. The multi-source abnormal data is mapped in multiple directions with the actual working content of the driver chip at the physical level, thereby dynamically constructing the corresponding lifespan topology map, and extracting the corresponding temporal degradation features by combining the long short-term memory mechanism.

[0028] Step S13: Form the corresponding nonlinear degradation trajectory by sorting the various time-series degradation features, and locate the critical phase transition point that triggers the abnormal situation in the driver chip by combining the dynamic optimization mechanism of the driver chip. Perform multi-level iteration on each critical phase transition point and perform failure inference during the iteration process to predict the combination of lifespan characteristics of the driver chip under the current working conditions, and further determine the remaining lifespan of the driver chip.

[0029] Step S14: Integrate the remaining lifespan with the current usage history of the driver chip to dynamically construct a lifespan management system for the driver chip. Combine the lifespan threshold and the corresponding safety margin to determine emergency measures for the operation of the driver chip, and simultaneously trigger a re-inspection of the remaining lifespan of the driver chip.

[0030] refer to Figure 2 In step S11, the specific steps are as follows:

[0031] S111: Real-time monitoring of the driver chip's operation process, marking the multi-dimensional sensing network deployed by the driver chip, and synchronously collecting multiple parameters of the driver chip, which cover multiple physical field dimensions such as electricity, heat, and vibration; at the same time, using the spatiotemporal alignment mechanism of edge computing nodes to perform timestamp calibration and spatial coordinate mapping on multiple parameters, eliminating data transmission delay and phase difference, and combining the state detection signal of the driver chip for initial feature screening, thereby determining the online data cluster of the driver chip;

[0032] S112: Input the online data cluster into the cloud-based digital twin space through the communication channel and trigger the preset digital twin mechanism. In this digital twin mechanism, based on the fusion technology of parametric modeling and physical mechanism model, adjust the corresponding boundary conditions and data attributes in real time, thereby generating a real-time synchronized driver chip twin in the digital twin space to realize the full-element digital reconstruction of the physical entity into the twin.

[0033] In the embodiments of this application, the working process of the driver chip is monitored in real time, the multi-dimensional sensing network deployed by the driver chip is marked, and multiple parameters of the driver chip are collected synchronously. These multiple parameters cover multiple physical field dimensions such as electricity, heat, and vibration. At the same time, the spatiotemporal alignment mechanism of the edge computing node is used to perform timestamp calibration and spatial coordinate mapping on the multiple parameters to eliminate data transmission delay and phase difference. Combined with the state detection signal of the driver chip, feature screening is performed to determine the online data cluster of the driver chip. This approach takes into account the overall state detection signal of the driver chip and ensures the accuracy of the online data cluster of the driver chip.

[0034] At this point, the system pre-calibrates the topological positions of the sensors on the physical entity of the driver chip and its surrounding key nodes, establishing a three-dimensional sensing system covering the three physical field dimensions of electricity, heat, and vibration. In the electric field dimension, the system focuses on collecting transient voltage and current waveforms at the chip's input and output terminals, as well as the amount of gate drive charge. In the thermal field dimension, the system collects the chip die junction temperature, package temperature, and fluid temperatures at the inlet and outlet of the heat sink. In the vibration field dimension, the system captures the micromechanical resonance signals of the package structure caused by high-frequency switching through microelectromechanical system sensors. The synchronous acquisition of these parameters must ensure an extremely high sampling rate to fully reproduce the details of stress changes in the driver chip during the switching transient process.

[0035] Because electrical signals propagate at or near the speed of light, thermal signals spread at milliseconds to seconds, and vibration signals conduct in solids at the speed of sound, these three types of heterogeneous data inevitably experience severe transmission delays and phase differences when they reach the data processing center. After receiving the raw data stream, the edge computing node uses the highest frequency control signal (such as a pulse width modulation clock) generated inside the driver chip as the absolute time reference. It then uses a hardware-level timestamp marking mechanism to resample and interpolate the thermal and vibration data, thereby achieving nanosecond-level or even microsecond-level timestamp calibration on the time axis. At the spatial level, the edge node maps the data captured by different sensors to the three-dimensional spatial grid coordinate system of the driver chip. For example, it accurately binds the local temperature rise data to a specific power switch unit area in the chip layout, completing the spatial coordinate mapping and ultimately eliminating the spatiotemporal disconnect between multi-physics data.

[0036] In actual operation, the driver chip will experience various working states such as startup, steady-state operation, light-load standby, and fault protection. The characteristics strongly correlated with chip aging and degradation are often only contained within specific dynamic stress ranges. The system will read the enable signal, overcurrent protection signal, and over-temperature alarm signal of the driver chip in real time. Based on this, the system will perform state masking operation on the spatiotemporally aligned multidimensional parameter sequence to accurately remove invalid static sleep data and stray noise interference, and retain only the effective data segments that reflect the substantial alternating thermal and electrical stresses that the chip is subjected to. These high-purity multidimensional time-series data are packaged and aggregated to finally form a structured online data cluster for the driver chip.

[0037] Specifically, taking the drive chip that undertakes the task of high-current inversion in the motor controller of new energy vehicles as an example, under extreme conditions such as rapid vehicle acceleration or high-speed climbing, the high-precision shunt in the multi-dimensional sensing network captures the hundreds of amperes of phase current (electric field) flowing through the drive chip at a megahertz sampling rate. At the same time, the temperature-sensing diode inside the chip records the steep slope (thermal field) as the junction temperature rises from 75°C to 150°C. Meanwhile, the piezoelectric sensor mounted on the back of the ceramic substrate monitors the micron-level high-frequency mechanical chatter (vibration field) caused by the mismatch of the thermal expansion coefficients between the silicon chip and the copper-clad laminate.

[0038] Due to the physical lag of heat conduction, the arrival times of the current peak and the temperature peak are misaligned by several milliseconds in the original data. At this time, the edge computing FPGA module deployed inside the motor controller immediately starts the spatiotemporal alignment mechanism, taking the rising edge of the gate drive PWM of the driver chip as the time zero point, shifting and phase compensating the thermal and vibration data curves backward, and accurately projecting them onto the heat hotspot grid of the upper left bridge arm inside the driver chip.

[0039] Meanwhile, the edge computing node detects that the PWM enable signal of the driver chip remains at a high level without any overcurrent cutoff or other protection actions, and determines that the chip is in a deep fatigue alternating load range. This filters out the soft-start noise at the moment of power-on and extracts the perfectly aligned electrical, thermal, and vibration coupled data segment full of degradation characterization information. It directly constructs an online data cluster dedicated to the current high-load operation cycle of the driver chip, providing absolutely clean underlying data support for the high-fidelity mapping of the subsequent cloud digital twin.

[0040] Furthermore, the online data cluster is input into the cloud-based digital twin space through a communication channel, triggering a preset digital twin mechanism. In this digital twin mechanism, based on the fusion technology of parametric modeling and physical mechanism model, the corresponding boundary conditions and data attributes are adjusted in real time, thereby generating a real-time synchronized driver chip twin in the digital twin space to achieve full-element digital reconstruction of the physical entity into the twin, thus introducing the driver chip twin.

[0041] At this point, since the online data cluster generated in the preceding steps has extremely high temporal resolution and multi-dimensional characteristics, the system needs to rely on a high-bandwidth, low-latency deterministic communication network (such as vehicle Ethernet or 5G private network) to reliably push it from the edge to the cloud platform. After capturing the data cluster, the cloud data receiving gateway will automatically match and wake up the pre-allocated twin computing container in the cloud memory according to the chip unique identifier and timestamp information encapsulated in the data packet, thereby successfully triggering the preset digital twin mechanism and preparing resource scheduling for the subsequent real-time calculation.

[0042] Traditional pure data-driven black-box models are prone to failure when faced with extreme operating conditions that the chip has not experienced, while pure physical models face the bottleneck of exploding computational load. This digital twin mechanism adopts a strategy of integrating the two, that is, pre-embedding a physical mechanism model based on partial differential equations (such as electrothermal coupling equations and thermoelasticity equations) in the cloud, and parameterizing its key parameters (such as material thermal conductivity, contact thermal resistance, parasitic capacitance, etc.). The system uses the real-time influx of online data clusters as input excitation, not only to update the external boundary conditions of the physical mechanism model (such as real-time coolant flow rate and ambient substrate temperature), but more importantly, to use the measured response values ​​in the data cluster (such as actual temperature rise slope and switching loss change) to iteratively correct the parameterized data attributes inside the mechanism model through parameter identification, so that the abstract physical equations can fit the current material property degradation state of the chip due to aging in real time.

[0043] After boundary condition loading and internal parameter attribute correction, the fusion model will be solved in a high-frequency iterative process in the cloud computing engine. The solution results surpass the limitations of physical sensors that can only measure surface or macroscopic parameters. It can deduce the precise physical field distribution of each grid node in the three-dimensional space inside the chip at the current moment (such as the location of hidden hot spots inside the junction layer, the distribution of microscopic shear stress at the root of the bonding line, etc.). These multi-dimensional physical field slices are continuously refreshed according to the time sequence. Finally, a driver chip twin that is strictly synchronized with the physical layer driver chip in terms of state, behavior and performance is rendered in the cloud virtual space, which completely completes the full-element digital reconstruction from external appearance data to internal deep physical mechanisms.

[0044] Specifically, when a vehicle is climbing a long slope on a continuous mountain road, the edge computing node reports the online data cluster of the driver chip, accompanied by rapid thermal fluctuations, to the cloud digital twin space in real time via the vehicle Ethernet, triggering the twin mechanism. The system not only inputs the real-time cooling water temperature and flow rate in the data cluster as dynamic boundary conditions into the electrothermal coupling physical mechanism model of the driver chip, but more importantly, the system finds that the measured case temperature is 2°C higher than the theoretically calculated case temperature. At this time, the parametric modeling technology comes into play. Through the least squares identification method, the data attribute of "thermal conductivity of the solder layer between the chip silicon substrate and the copper clad laminate" in the mechanism model is automatically corrected from the normal 60W / (m·K) to 52W / (m·K). This parameter adjustment accurately maps the physical reality of voids in the solder layer inside the driver chip caused by long-term thermal fatigue.

[0045] Based on these dynamically adjusted real boundaries and degradation attributes, the cloud model quickly completes high-dimensional calculations. In the digital twin space, it not only synchronously reproduces the voltage and current alternation process on the surface of the driver chip, but also presents and reconstructs the local thermal accumulation phenomenon caused by solder voids in the rightmost bridge arm region inside the chip, as well as the abnormal tensile stress distribution borne by the aluminum bonding wires in this region. This generates a real-time high-fidelity twin that can reflect the current fatigue damage state of the driver chip, laying an irreplaceable data foundation for the subsequent accurate location of the critical phase transition point of aging.

[0046] refer to Figure 3 In step S12, the specific steps are as follows:

[0047] S121: During the operation of the chip twin, the preset deviation monitoring process of the chip twin is monitored in real time, and multiple deviation contents between the actual working conditions and the ideal working conditions are dynamically output. The multiple deviation contents include temperature drift deviation, loss accumulation deviation, circuit deviation and vibration deviation; reverse trace along the logic chain of each deviation content, and locate the multi-source abnormal data source that causes the deviation in the reverse trace process.

[0048] S122: The multi-source anomaly data is mapped along different dimensions to the actual working content of the driver chip at the physical level, thereby dynamically constructing a lifespan topology map that reflects the evolution of the driver chip's health status. This lifespan topology map uses nodes to represent degraded parts and edges to represent failure propagation paths. Furthermore, by combining the long short-term memory mechanism, the time-series degradation features with long-term dependence are deeply extracted from the time-series data stream of the lifespan topology map, thereby presenting the degradation content that is hidden in the fluctuations and has a trend.

[0049] In the embodiments of this application, during the operation of the chip twin, the preset deviation monitoring process of the chip twin is monitored in real time, and multiple deviation contents between the actual working conditions and the ideal working conditions are dynamically output. The multiple deviation contents include temperature drift deviation, loss accumulation deviation, circuit deviation and vibration deviation. The logic chain of each deviation content is traced back, and the multi-source abnormal data source that causes the deviation is located in the reverse tracing process. The multi-source abnormal data source that causes the deviation is located in the reverse tracing process.

[0050] At this time, while the chip twin is continuously operating in the cloud, an ideal health response model that is completely synchronized with the input online data cluster is running in parallel within it. The system compares the actual physical field distribution mapped in the twin with the standard physical field distribution output by the ideal model in real time at an extremely high sampling frequency. Through difference calculation, it dynamically extracts multiple deviations that can characterize the degradation of chip performance. Among them, temperature drift deviation focuses on the difference between the actual junction temperature rise of a specific spatial grid inside the chip and the temperature rise calculated by theoretical thermal resistance; loss accumulation deviation measures the degree to which the energy dissipation trajectory deviates from the non-degradation reference curve during the actual switching transient process; circuit deviation is mainly reflected in the increase of on-resistance or the delay jitter of switching time; vibration deviation characterizes the mechanical resonant frequency shift and abnormal amplitude amplification caused by the decline in structural integrity.

[0051] The generation of a single deviation is often the result of the interplay of multiple underlying physical degradation mechanisms. Therefore, it is necessary to establish a directed causal tracing network from macroscopic manifestations to microscopic causes. The system takes a dynamically output deviation as the starting point and uses a tracing method based on graph neural networks or Bayesian causal inference to drill down along a pre-set physical failure logic chain. During the reverse tracing process, interference terms that are strongly correlated but belong to symbiotic phenomena are eliminated, the initial abnormal fluctuation point that caused the deviation is identified, and combined with the spatial coordinate mapping relationship of multidimensional data, the system can accurately pinpoint which batch of underlying original sensor data in which physical field dimension has undergone an abnormal change that violates physical common sense. Finally, the underlying data that caused the degradation phenomenon is clearly located as a multi-source abnormal data source.

[0052] Specifically, in the cloud-based twin monitoring during long-distance uphill operation, the deviation monitoring process keenly detected a significant "temperature drift deviation," namely, the actual local temperature rise in the upper left bridge arm region of the twin display driver chip was 15°C higher than the value extrapolated by the ideal model. Following this 15°C temperature drift deviation logic chain, the system initiated reverse tracing: excluding abnormal coolant flow rate (with normal boundary conditions), it traced back to the source of the thermal field and found that the thermal anomaly area completely overlapped with the area of ​​surged conduction loss in the "loss accumulation deviation" in spatial coordinates. Continuing to analyze downwards along the electrothermal coupling logic chain, the system captured a microsecond-level abnormal step in the conduction voltage drop of this bridge arm in the "circuit deviation" dimension.

[0053] The system penetrated the surface of the circuit and precisely located the multi-source abnormal data source that caused this series of chain reactions in the underlying time-series data slices. Specifically, a periodic micro-distortion appeared in a certain phase current waveform uploaded from the edge side, and abnormal high-frequency harmonics representing structural loosening appeared in the micromechanical vibration spectrum of the same area acquired simultaneously. Through reverse tracing, the system clearly pointed out that it was these two multi-source abnormal data sources that revealed that the aluminum bonding wires in the bridge arm area inside the driver chip had peeled off due to long-term thermomechanical fatigue, leading to a sudden change in contact resistance and precursors to local thermal runaway.

[0054] Furthermore, the multi-source anomaly data is mapped along different dimensions to the actual working content of the driver chip at the physical layer, thereby dynamically constructing a lifespan topology map that reflects the evolution of the driver chip's health status. This lifespan topology map uses nodes to represent degraded parts and edges to represent failure propagation paths. In addition, by combining the long short-term memory mechanism, long-term dependent temporal degradation features are deeply extracted from the time-series data stream of the lifespan topology map, thus presenting those degradation contents that are hidden in fluctuations and have trends. This introduces degradation contents that are fluctuating and have trends. At the same time, the multi-source anomaly data is further controlled, which improves the accuracy of the driver chip's temporal degradation features.

[0055] At this point, the system removes the locked multi-source abnormal data from the pure data space and forcibly maps it back to the actual physical packaging layer of the driver chip (such as the active area of ​​the silicon wafer, metallization layer, bonding interface, molding compound layer, and heat sink). During this mapping process, the system uses the spatial coordinates of each physical layer as nodes of the graph and the physical interfaces crossed by the abnormal data as edges of the graph. It uses complex network theory to dynamically construct a lifespan topology graph. This topology graph is essentially a multi-dimensional causal transmission graph. The nodes are assigned weight values ​​that represent the current degree of degradation of that part, while the edges are defined as the transmission rate and coupling strength of the failure mechanism between adjacent physical layers. This integrates the scattered aging phenomena of the chip into a spatial topology structure with clear physical semantics.

[0056] Because driver chips are subject to frequent start-stop cycles and load fluctuations during actual operation, their performance parameters are subject to high-frequency fluctuations, and the true degradation trend is often submerged in the huge dynamic operating noise. The system inputs the weight sequence of each node and the transmission coefficient sequence of the edge in the lifespan topology graph as a multi-channel time-series data stream into the Long Short-Term Memory (LSTM) network. Through the synergistic effect of the forget gate and the input gate inside the LSTM, the network can automatically filter out reversible state fluctuations caused by short-term operating condition changes, retain and amplify those parameter drifts that occur slowly and are irreversible across extremely long operating time windows, thereby deeply extracting the time-series degradation features with long-term dependence and accurately presenting the substantial degradation content hidden behind the violent operating fluctuations, which has monotonically increasing or accelerated deterioration characteristics.

[0057] Specifically, for the multi-source abnormal data caused by the micro-detachment of aluminum bonding wires traced in the previous step, the system performs multi-directional mapping along the physical hierarchy. In the dynamically constructed lifespan topology map, a local subnet is generated with "metallization layer above silicon wafer" as the parent node and "interface of aluminum bonding wire root" as the child node. At this time, the weight of the child node increases sharply due to the increase in contact resistance, and the "edge" connecting the two nodes represents the thermal stress conduction path caused by the current crowding effect.

[0058] Faced with the drastic current fluctuations caused by the frequent acceleration and deceleration of the driver chip in urban road conditions, the system utilizes the Long Short-Term Memory (LSTM) mechanism to deeply mine the temporal weight data stream of the sub-node in the topology graph. The LSTM network effectively forgets reversible noise such as the temperature drop caused by the brief coasting of the vehicle, and firmly grasps the phenomenon of "step-like increase in bond line contact voltage drop" that has accumulated over the past three months and spanned tens of thousands of thermal cycles. This extracted long-term dependent temporal degradation feature clearly and monotonously outlines the irreversible fatigue evolution trend of the bridge arm region of the driver chip from the initiation of microcracks to their gradual expansion, completely eliminating the interference of operating fluctuations.

[0059] refer to Figure 4 In step S13, the specific steps are as follows:

[0060] S131: Mark the priority of each timing degradation feature and sort each timing degradation feature according to the priority order, so as to perform the corresponding nonlinear fitting to form the corresponding nonlinear degradation trajectory. The nonlinear degradation trajectory depicts the dynamic path of the driver chip evolving from a healthy state to a failed state. Combined with the dynamic optimization mechanism of the driver chip, the critical phase transition point that triggers the abnormal situation in the driver chip is located in the nonlinear degradation trajectory. The critical phase transition point presents the moment when a sudden change or a sharp increase in the risk of failure can occur.

[0061] S132: Real-time monitoring of each critical phase transition point, and multi-level iterative analysis of each critical phase transition point. During the iteration process, failure physics mechanisms are introduced to perform failure deduction, simulate the degradation acceleration effect under different stress conditions, thereby predicting the lifespan characteristic combination of the driver chip under the current working condition, and then determining the remaining lifespan of the driver chip based on the dynamic identification of this characteristic combination.

[0062] In the embodiments of this application, the priority of each timing degradation feature is marked, and each timing degradation feature is sorted according to the priority order, thereby performing corresponding nonlinear fitting to form a corresponding nonlinear degradation trajectory. The nonlinear degradation trajectory depicts the dynamic path of the driver chip evolving from a healthy state to a failed state. Combined with the dynamic optimization mechanism of the driver chip, the critical phase transition point that triggers the abnormal situation in the driver chip is located in the nonlinear degradation trajectory. The critical phase transition point presents the moment when a sudden change or a sharp increase in the risk of failure can occur. The introduction of the critical phase transition point presents the moment when a sudden change or a sharp increase in the risk of failure can occur.

[0063] At this point, since the contribution of degradation features caused by different physical mechanisms to the final failure of the chip varies significantly, the system assigns a global priority label to each time-series degradation feature based on the strength of the causal relationship between the feature and the loss of the chip's core functions, as well as the rate of change of the feature itself. The system uses the dominant degradation feature as the main variable and the auxiliary degradation feature as the constraint variable in descending order of priority. It introduces a nonlinear fitting method based on exponential decay or piecewise polynomials to perform curve fitting. This process abandons the traditional linear lifetime assumption and truly restores the nonlinear evolution law of "slow change-acceleration-drastic change" exhibited by the driving chip in long-term operation due to fatigue accumulation, defect propagation and stress interaction. Thus, a dynamic nonlinear degradation trajectory that spans the entire service life and clearly depicts the chip's evolution from the initial healthy state to the final failure state is generated.

[0064] In terms of locating the critical phase transition point that triggers abnormal situations using a dynamic optimization mechanism, the degradation of the driver chip is not a uniform process, but rather a sudden change in physical state occurs when internal damage accumulates to the material's tolerance limit. The system deploys a dynamic optimization mechanism (such as extreme value optimization based on derivative changes or heuristic curve inflection point search) on this nonlinear degradation trajectory to calculate the rate of curvature change and the first and second derivatives of the trajectory curve in real time. When the optimization method captures a non-smooth increase in curvature or an exponential divergence trend in slope that exceeds a preset threshold on the trajectory, it marks this point. This marked point is precisely located as the critical phase transition point, which profoundly reveals the critical time node at which the microstructure inside the chip (such as crack penetration or thermal runaway initiation) is about to undergo a macroscopic physical mutation and the risk of system failure rises sharply.

[0065] Specifically, after extracting two temporal degradation features, namely "stepwise increase in bonding wire contact voltage drop" and "gradual increase in local thermal resistance", the system determines that the former is directly related to the risk of disconnection of the conductive path, and therefore assigns it the highest priority and places it on the fitting axis.

[0066] The system uses a nonlinear fitting method to fit this feature into a nonlinear degradation trajectory based on data from tens of thousands of thermal cycles. This trajectory clearly shows that the drive chip is in a slow and gradual degradation period in the first 80,000 kilometers, while in recent mileage the curve begins to show an upward-curving, accelerating parabolic shape.

[0067] Based on this, the dynamic optimization mechanism scans the slope change of the trajectory in real time and accurately locates a critical phase transition point with a sudden increase in curvature. At the physical level, this point means that the residual metal cross-section of a certain main aluminum bonding wire inside the driver chip has shrunk to the limit of being unable to withstand the thermal shock of subsequent current. Once a large current is injected during the next rapid acceleration of the vehicle, the bonding wire will inevitably melt and arc. The accurate location of this phase transition point directly indicates that the driver chip has officially entered the highly dangerous period of sudden failure from the state of controllable aging.

[0068] Furthermore, each critical phase transition point is monitored in real time, and multi-level iterative analysis is performed on each critical phase transition point. During the iteration process, failure physics mechanisms are introduced to perform failure inference and simulate the degradation acceleration effect under different stress conditions. This allows the driver chip to predict the combination of lifespan characteristics under the current operating conditions. Based on the dynamic identification of this combination of characteristics, the remaining lifespan of the driver chip is determined. This approach incorporates the overall consideration of dynamic identification of characteristic combinations and ensures the accuracy of the remaining lifespan of the driver chip.

[0069] At this point, the system sets the critical phase transition point located in the previous steps as the initial anchor point for lifetime estimation and initiates a progressively iterative calculation loop. In each iteration, the system directly calls the failure physics mechanism model that is deeply bound to the microscopic damage mechanism of the chip material, such as the electrothermal coupling aging model based on the Coxon-Miller law, the crack propagation model based on the Paris formula, or the thermal activation degradation model based on the Arrhenius equation. The system uses the current actual operating parameters as the iterative input and solves the problem through multi-level finite element coupling, gradually estimating how internal damage undergoes a cross-scale malignant evolution under the alternating effects of thermodynamics, electric field, and mechanical stress, starting from the critical phase transition point, until it reaches the predefined physical criteria for complete hardware failure (such as complete breakage of the bonding wire or local thermal runaway causing silicon wafer melt-through).

[0070] Since extreme high-stress conditions occur infrequently in actual vehicle operation, linear extrapolation based solely on the current mild conditions would lead to overly optimistic life predictions. Therefore, in iterative simulations, the system dynamically superimposes virtual extreme stress pulses to simulate the degradation acceleration effect under different degrees of severity, testing the tolerance margin of the twin from the critical phase transition point to complete failure.

[0071] The system performs massive sampling and statistical analysis on these accelerated simulation results, and finally outputs a combination of lifespan characteristics that includes multiple dimensions. This combination not only covers the expected median of the remaining lifespan, but also includes the upper and lower bounds of the lifespan, the failure probability density distribution, and the probability proportion of the most vulnerable failure mode under specific confidence intervals (such as 90% or 95%). Based on the dynamic drift characteristics of this combination of characteristics as the latest data flows in, the system performs intelligent identification and weighted fusion to remove uncertainty interference, thereby accurately locking in and outputting the remaining lifespan of the driver chip under the current real working state.

[0072] Specifically, once the system detects a phase transition point representing the "bonded wire cross-section approaching the critical value of melting," it immediately initiates a multi-level iterative failure simulation. In the first iteration, the system introduces the physical mechanism of Paris crack propagation, using the current high-speed ramp-up and high-current operating conditions to simulate how the bond wire will rapidly tear apart during the subsequent dozens of thermal cycles. In the next iteration, in order to test the ultimate bearing capacity, the system actively injects virtual "summer continuous ejection start" extreme electrothermal stress into the twin to simulate the extremely rapid degradation acceleration effect.

[0073] After thousands of cross-iteration simulations, the system discovered that the driver chip has an extremely high probability of bond wire breakage failure when encountering the next extreme stall condition. Based on these simulation results, the system dynamically generated a combination of lifespan characteristics: indicating that the median expected lifespan of the chip is only 1500 kilometers, but the lower limit within the 95% confidence interval is sharply shortened to 400 kilometers, and the failure probability density curve shows a steep peak at 400 kilometers. Based on the extremely low fault tolerance revealed by this combination of characteristics, the system finally determined and output the specific value of the driver chip's current extremely critical lifespan, providing a quantitative basis for subsequent emergency intervention.

[0074] refer to Figure 5 In step S14, the specific steps are as follows:

[0075] S141: Based on the traversal of the driver chip's database, the current usage history of the driver chip is determined. The remaining lifespan data and the current usage history of the driver chip are input into the same data space and deeply integrated in this data space. During the integration process, the lifespan management system of the driver chip is constructed step by step by combining the previous lifespan management content of the driver chip. The lifespan management system of the driver chip presents the working cycle content of the driver chip.

[0076] S142: Obtain the preset lifespan threshold of the driver chip, compare the lifespan threshold with the lifespan information output by the lifespan management system in multiple dimensions, and dynamically construct the corresponding lifespan management framework. Further combine the corresponding safety margin to determine the graded early warning content of the driver chip, and then determine the emergency measures for the driver chip to ensure that the driver chip is in a safe and controllable state before critical failure. These emergency measures include frequency reduction operation, switching to backup channels, or triggering safety shutdown measures. At the same time, trigger the re-inspection mechanism of the remaining lifespan of the driver chip, and use the re-inspection data to reverse correct the driver chip twin to form a closed-loop management ecosystem, and finally realize the proactive early warning of the driver chip.

[0077] In the embodiments of this application, the current usage history of the driver chip is determined by traversing the driver chip's database. The remaining lifespan data and the current usage history of the driver chip are input into the same data space and deeply integrated in this data space. During the integration process, the lifespan management system of the driver chip is constructed step by step by combining the driver chip's previous lifespan management content. This lifespan management system of the driver chip presents the working cycle content of the driver chip, is compatible with the overall consideration of the driver chip's database, and ensures the accuracy of the current usage history of the driver chip.

[0078] At this point, the system skips the current real-time calculation cycle and goes back in depth, triggering a traversal search of the entire historical database of the driver chip. This process aims to accurately extract and reconstruct the complete current usage history of the chip since it was powered on at the factory from massive logs. This history covers macroscopic statistical features such as the cumulative actual runtime, the number of cycles experienced, and the distribution density of historical extreme operating conditions. The system opens a high-dimensional data space in the cloud memory and projects the "remaining lifespan data" representing the future life boundary output by the previous steps and the "current usage history" representing the past consumption accumulation as two core feature tensors into this space at the same time, realizing zero-latency alignment and isomorphic expression of past and future data under the same mathematical dimension.

[0079] In building a lifespan management system by combining previous lifespan control content, simply overlaying historical and predictive data can only reflect physical fatigue and cannot reflect the continuity at the management level. Therefore, in the fusion calculation of the data space, the system will simultaneously retrieve lifespan control content that has been executed at different lifespan stages in the past, such as historical de-rated operation trigger records, preventive maintenance logs, and early health status adjustment instructions.

[0080] The system uses a timeline as its framework, historical control actions as intervention nodes, usage history as a baseline, and remaining lifespan as a dynamic endpoint. It sequentially connects and generates multi-level association rules, ultimately dynamically constructing a lifespan management system for the driver chip. This system is not only a data set but also a logical graph with causal traceability capabilities, presenting a complete and macroscopic view of the driver chip's entire working cycle from its commissioning, experiencing various stress consumptions, receiving adaptive control interventions, to its current predicted lifespan endpoint.

[0081] Specifically, when the system predicts that its remaining service life is only a very short mileage, it immediately traverses the vehicle's onboard cloud database to accurately identify that the drive chip has accumulated 25,000 thermal cycles in the past eighteen months and has undergone continuous high-power ice and snow climbing challenges in frigid regions. These constitute an extremely harsh current usage history.

[0082] The system injects the historical fatigue consumption of these 25,000 cycles and the current extremely critical remaining lifespan prediction into the high-dimensional fusion data space. During spatial fusion, the system retrieves the "past lifespan management content" of the chip, which was forced to reduce the switching frequency by the vehicle controller when the chip was driven to 10,000 kilometers due to high junction temperature.

[0083] Based on this, the lifespan management system built step by step clearly presents the complete working cycle of the driver chip: from the initial healthy service, to the mid-term derating control triggered by high load to delay aging, to the exhaustion of control margin, the resonance between historical accumulated damage and current micro-crack propagation, and finally to the end of the lifespan.

[0084] Furthermore, the preset lifespan threshold of the driver chip is obtained, and the lifespan threshold is compared with the lifespan information output by the lifespan management system from multiple dimensions. A corresponding lifespan management framework is dynamically constructed, and the graded early warning content of the driver chip is determined in combination with the corresponding safety margin. Then, the emergency measures for the driver chip are determined to ensure that the driver chip is in a safe and controllable state before critical failure. The emergency measures include frequency reduction, switching to backup channels, or triggering safety shutdown. At the same time, the remaining lifespan of the driver chip is re-examined, and the re-examined data is used to correct the driver chip twin to form a closed-loop management ecosystem. Ultimately, the driver chip's proactive early warning is realized, which is compatible with the overall consideration of the corresponding safety margin and ensures the accuracy of the graded early warning content of the driver chip. At the same time, the combination of the driver chip's lifespan characteristics under the current operating conditions is introduced, which fully considers the remaining lifespan and the current usage history of the driver chip, improving the accuracy of the driver chip's lifespan management system.

[0085] At this point, the system extracts the absolute life-end red line, i.e., the life-end threshold, from the underlying chip design specifications or vehicle functional safety requirements. This threshold not only includes a single lower limit for remaining time or number of cycles, but also extends horizontally to include multi-dimensional threshold vectors such as temperature tolerance limit and maximum parameter drift tolerance. The system performs a matrix-style cross-comparison between the real-time prediction information output by the life-end management system and these multi-dimensional threshold vectors. Based on the interval in which the comparison results are located, it dynamically activates and constructs life-end management frameworks with different levels of strictness, thereby setting the overall control tone for subsequent decisions.

[0086] Because digital twin simulations inevitably involve uncertainties, the system backs out by a preset buffer zone, or safety margin, based on the lifetime threshold. According to the depth to which the current lifetime indicator penetrates the safety margin, the system accurately defines the graded warning content: when the indicator approaches the outer edge of the safety margin, an early warning is triggered; when the indicator enters the middle of the margin, a downgrade warning is triggered; when the indicator completely breaks through the margin and approaches the absolute threshold, an extreme crisis alarm is triggered.

[0087] With different levels of warnings, the system directly issues corresponding emergency measures to the underlying hardware. For example, during the degradation warning stage, it implements frequency reduction measures to reduce thermal stress by lowering the switching frequency. In extreme crises and when the system has redundant hardware, it implements seamless switching to backup channels. When facing irreversible thermal runaway or short circuit risks, it decisively triggers hard-wired level safety shutdown measures to forcibly cut off the energy input of the physical circuit, ensuring that the chip is anchored in an absolutely safe and controllable physical state before critical failure.

[0088] Any pre-emptive emergency measures will instantly change the chip's boundary conditions, causing the foundation of the preceding lifetime prediction to be shaken. At the same clock tick when the emergency measures are triggered, the system forcibly wakes up the re-examination mechanism for the remaining lifetime. This mechanism captures high-frequency transient data at the moment of emergency state switching with the highest priority and performs cross-weighted re-examination using a lightweight verification method or a backup twin model. The system uses the actual response deviation obtained from the re-examination as a penalty factor or correction term, which is fed back into the driver chip twin in the cloud to perform online adaptive calibration of its internal parameterized physical mechanism model, thereby correcting the subsequent prediction trajectory and completely opening up the data closed loop of "perception-prediction-execution-re-examination-calibration", realizing an uninterrupted proactive early warning ecosystem.

[0089] Specifically, the system obtains the lifespan threshold of the chip model under the ASIL-D functional safety level, which requires "at least 500 thermal cycles before complete failure", and compares it with the "remaining lifespan is extremely critical" information output by the current management system to dynamically construct the highest-risk lifespan management framework.

[0090] Based on a safety margin of 200 cycles, the system determines that the driver chip has breached the safety threshold, immediately determines the highest level of warning content, and bypasses the conventional logic to directly issue a hardware-level instruction to the motor controller to "trigger safety shutdown measures," forcibly shutting down the PWM drive signal of the driver chip, so that it is in a passive, absolutely safe and controllable state before the internal aluminum bonding wire completely melts and causes the electrical control box to explode.

[0091] At the same time, the re-examination mechanism is activated simultaneously at the microsecond instant the shutdown command takes effect. It captures re-examination data such as the parasitic inductance reverse voltage spike at the moment of shutdown and finds that the stray inductance inside the actual chip is higher than the initial set value of the twin. The system immediately uses this re-examination data to reverse correct the electromagnetic parasitic parameter model of the cloud driver chip twin. This closed-loop correction not only verifies the absolute correctness of the safety shutdown decision just now, but also ensures that if the redundant channel is activated, the twin system can continue to provide highly reliable active warning services for the whole vehicle based on a more accurate model.

[0092] Please see Figure 6 , Figure 6 This is a schematic diagram of the structural composition of the lifespan management system for a driver chip based on digital twins according to an embodiment of the present invention; the lifespan management system for the driver chip based on digital twins is applied to the above-described lifespan management method for the driver chip based on digital twins; the lifespan management system for the driver chip based on digital twins includes:

[0093] The driver chip twin module 21 is used to collect multiple parameters of the driver chip in different dimensions during the operation of the driver chip, perform spatiotemporal alignment on the multiple parameters, and determine the online data cluster of the driver chip in combination with the state detection signal of the driver chip. The online data cluster is input into the digital twin space, and the corresponding driver chip twin is determined in combination with the preset digital twin mechanism.

[0094] The topology module 22 is used to dynamically output multiple deviation contents of the driver chip twin, determine the corresponding multi-source abnormal data by tracing each deviation content, and perform multi-directional mapping between the multi-source abnormal data and the actual working content of the driver chip at the physical level, thereby dynamically constructing the corresponding lifespan topology map, and extracting the corresponding temporal degradation features by combining the long short-term memory mechanism.

[0095] The iteration module 23 is used to form a corresponding nonlinear degradation trajectory by sorting along each time-series degradation feature, and combined with the dynamic optimization mechanism of the driver chip, locate the critical phase transition point that triggers the abnormal situation in the driver chip, perform multi-level iteration on each critical phase transition point, and perform failure inference during the iteration process, thereby predicting the combination of lifespan characteristics of the driver chip under the current working condition, and further determining the remaining lifespan of the driver chip.

[0096] Emergency module 24 is used to integrate the remaining service life with the current usage history of the driver chip, thereby dynamically constructing a service life management system for the driver chip, and determining emergency measures for the operation of the driver chip by combining the service life threshold and the corresponding safety margin, and simultaneously triggering a re-inspection of the remaining service life of the driver chip.

[0097] It should be noted that although multiple modules are mentioned in the detailed description above, this division is not mandatory; in fact, according to the embodiments of this disclosure, the features and functions of two or more modules or described above can be embodied in one module; conversely, the features and functions of one module described above can be further divided into multiple modules to be embodied.

[0098] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein; this application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein; the specification and embodiments are to be considered exemplary only.

[0099] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for lifespan management of a driver chip based on digital twins, characterized in that, include: During the operation of the driver chip, multiple parameters of the driver chip in different dimensions are collected, the multiple parameters are spatiotemporally aligned, and the online data cluster of the driver chip is determined by combining the state detection signal of the driver chip. The online data cluster is input into the digital twin space, and the corresponding driver chip twin is determined by combining the preset digital twin mechanism. The driver chip twin dynamically outputs multiple deviation contents, and determines the corresponding multi-source abnormal data by tracing each deviation content. The multi-source abnormal data is then mapped in multiple directions with the actual working content of the driver chip at the physical level, thereby dynamically constructing the corresponding lifespan topology map and extracting the corresponding temporal degradation features by combining the long short-term memory mechanism. The corresponding nonlinear degradation trajectory is formed by sorting along the various time-series degradation features. Combined with the dynamic optimization mechanism of the driver chip, the critical phase transition point that triggers the abnormal situation in the driver chip is located. Multi-level iteration is performed on each critical phase transition point, and failure inference is performed during the iteration process to predict the combination of lifespan characteristics of the driver chip under the current working conditions, and further determine the remaining lifespan of the driver chip. The remaining lifespan is integrated with the current usage history of the driver chip to dynamically build a lifespan management system for the driver chip. The system also determines emergency measures for the driver chip's operation based on the lifespan threshold and corresponding safety margin, and simultaneously triggers a re-inspection of the driver chip's remaining lifespan.

2. The lifespan management method for driver chips based on digital twins according to claim 1, characterized in that, During the operation of the driver chip, multiple parameters of the driver chip in different dimensions are collected, the multiple parameters are spatiotemporally aligned, and the online data cluster of the driver chip is determined by combining the state detection signal of the driver chip. The online data cluster is input into the digital twin space, and the corresponding driver chip twin is determined by combining it with a preset digital twin mechanism, including: The system monitors the operation of the driver chip in real time, marks the multi-dimensional sensing network deployed on the driver chip, and synchronously collects multiple parameters of the driver chip, which cover multiple physical field dimensions such as electricity, heat, and vibration. At the same time, the system uses the spatiotemporal alignment mechanism of the edge computing node to perform timestamp calibration and spatial coordinate mapping on the multiple parameters, eliminates data transmission delay and phase difference, and combines the state detection signal of the driver chip to perform initial feature screening, thereby determining the online data cluster of the driver chip.

3. The lifespan management method for driver chips based on digital twins according to claim 2, characterized in that, The process of collecting multiple parameters of the driver chip in different dimensions during the operation of the driver chip, performing spatiotemporal alignment on the multiple parameters, and determining the online data cluster of the driver chip by combining the state detection signal of the driver chip, inputting the online data cluster into the digital twin space, and determining the corresponding driver chip twin by combining the preset digital twin mechanism, also includes: The online data cluster is input into the cloud-based digital twin space through a communication channel, triggering a preset digital twin mechanism. In this mechanism, based on the fusion technology of parametric modeling and physical mechanism model, the corresponding boundary conditions and data attributes are adjusted in real time, thereby generating a real-time synchronized driver chip twin in the digital twin space to achieve full-element digital reconstruction of the physical entity into the twin.

4. The lifespan management method for driver chips based on digital twins according to claim 1, characterized in that, The driver chip twin dynamically outputs multiple deviation contents, and by tracing each deviation content, it determines the corresponding multi-source anomaly data. This multi-source anomaly data is then mapped in multiple directions to the actual working content of the driver chip at the physical layer, thereby dynamically constructing a corresponding lifespan topology map. Furthermore, it incorporates a long short-term memory mechanism to extract corresponding temporal degradation features, including: During the operation of the chip twin, the preset deviation monitoring process of the chip twin is monitored in real time, and multiple deviation contents between the actual working conditions and the ideal working conditions are dynamically output. The multiple deviation contents include temperature drift deviation, loss accumulation deviation, circuit deviation and vibration deviation. The logic chain of each deviation content is traced back, and the multi-source abnormal data sources that cause the deviation are located in the process of tracing back.

5. The lifespan management method for driver chips based on digital twins according to claim 4, characterized in that, The driver chip twin dynamically outputs multiple deviation contents, and determines the corresponding multi-source abnormal data by tracing each deviation content. This multi-source abnormal data is then mapped in multiple directions to the actual working content of the driver chip at the physical layer, thereby dynamically constructing a corresponding lifespan topology map. Furthermore, it incorporates a long short-term memory mechanism to extract corresponding temporal degradation features. The system also includes: The multi-source anomaly data is mapped along different dimensions to the actual working content of the driver chip at the physical level, thereby dynamically constructing a lifespan topology map that reflects the evolution of the driver chip's health status. This lifespan topology map uses nodes to represent degraded parts and edges to represent failure propagation paths. Furthermore, by combining the long short-term memory mechanism, the time-series degradation features with long-term dependence are deeply extracted from the time-series data stream of the lifespan topology map, thus revealing the degradation content that is hidden in the fluctuations and has a trend.

6. The lifespan management method for driver chips based on digital twins according to claim 1, characterized in that, The nonlinear degradation trajectory is formed by sorting along various temporal degradation characteristics, and the critical phase transition point that triggers abnormal conditions in the driver chip is located by combining the dynamic optimization mechanism of the driver chip. Multi-level iterations are performed on each critical phase transition point, and failure prediction is conducted during the iteration process to predict the combination of lifespan characteristics of the driver chip under the current operating conditions, further determining the remaining lifespan of the driver chip, including: The priority of each timing degradation feature is marked, and the timing degradation features are sorted according to the priority order to perform corresponding nonlinear fitting to form a corresponding nonlinear degradation trajectory. This nonlinear degradation trajectory depicts the dynamic path of the driver chip evolving from a healthy state to a failed state. Combined with the dynamic optimization mechanism of the driver chip, the critical phase transition point that triggers the abnormal situation in the driver chip is located in the nonlinear degradation trajectory. This critical phase transition point presents the moment when a sudden change or a sharp increase in the risk of failure can occur.

7. The lifespan management method for driver chips based on digital twins according to claim 6, characterized in that, The process of forming corresponding nonlinear degradation trajectories by sorting along various temporal degradation characteristics, and locating the critical phase transition points that trigger abnormal conditions in the driver chip using the dynamic optimization mechanism of the driver chip, performing multi-level iterations on each critical phase transition point, and performing failure deduction during the iteration process, thereby predicting the combination of lifespan characteristics of the driver chip under the current operating conditions, and further determining the remaining lifespan of the driver chip, also includes: Real-time monitoring of each critical phase transition point and multi-level iterative analysis of each critical phase transition point are performed. During the iteration process, failure physics mechanisms are introduced to perform failure inference and simulate the degradation acceleration effect under different stress conditions. This allows the prediction of the lifespan characteristic combination of the driver chip under the current operating conditions, and the remaining lifespan of the driver chip is determined based on the dynamic identification of this characteristic combination.

8. The lifespan management method for driver chips based on digital twins according to claim 1, characterized in that, The remaining lifespan is integrated with the current usage history of the driver chip to dynamically construct a lifespan management system for the driver chip. This system combines lifespan thresholds and corresponding safety margins to determine emergency measures for the driver chip's operation and simultaneously triggers a re-inspection of the driver chip's remaining lifespan, including: The current usage history of the driver chip is determined by traversing the database of the driver chip. The remaining lifespan data and the current usage history of the driver chip are input into the same data space and deeply integrated in this data space. During the integration process, the lifespan management system of the driver chip is built step by step by combining the previous lifespan management content of the driver chip. The lifespan management system of the driver chip presents the working cycle content of the driver chip.

9. The lifespan management method for a driver chip based on digital twins according to claim 8, characterized in that, The process of integrating the remaining lifespan with the current usage history of the driver chip to dynamically construct a lifespan management system for the driver chip, and determining emergency measures for the driver chip's operation based on lifespan thresholds and corresponding safety margins, while simultaneously triggering a re-inspection of the driver chip's remaining lifespan, also includes: The system obtains the preset lifespan threshold of the driver chip, compares the lifespan threshold with the lifespan information output by the lifespan management system from multiple dimensions, and dynamically constructs a corresponding lifespan management framework. Furthermore, it determines the graded early warning content for the driver chip based on the corresponding safety margin, and then determines the emergency measures for the driver chip's operation to ensure that the driver chip is in a safe and controllable state before critical failure. These emergency measures include frequency reduction, switching to backup channels, or triggering safety shutdown. Simultaneously, it triggers a re-inspection mechanism for the remaining lifespan of the driver chip, using the re-inspection data to reverse-correct the driver chip twin, forming a closed-loop management ecosystem, and ultimately achieving proactive early warning for the driver chip.

10. A lifespan management system for a driver chip based on digital twins, characterized in that, The lifespan management system for the driver chip based on digital twins is applied to the lifespan management method for the driver chip based on digital twins as described in any one of claims 1-9. The lifespan management system for the driver chip based on digital twins includes: The driver chip twin module is used to collect multiple parameters of the driver chip in different dimensions during the operation of the driver chip, perform spatiotemporal alignment of the multiple parameters, and determine the online data cluster of the driver chip by combining the status detection signal of the driver chip. The online data cluster is then input into the digital twin space, and the corresponding driver chip twin is determined by combining the preset digital twin mechanism. The topology module is used to dynamically output multiple deviation contents of the driver chip twin, determine the corresponding multi-source abnormal data by tracing each deviation content, and perform multi-directional mapping between the multi-source abnormal data and the actual working content of the driver chip at the physical level, thereby dynamically constructing the corresponding lifespan topology map, and extracting the corresponding temporal degradation features by combining the long short-term memory mechanism. The iterative module is used to form a corresponding nonlinear degradation trajectory by sorting along various temporal degradation features, and combined with the dynamic optimization mechanism of the driver chip, locate the critical phase transition point that triggers abnormal conditions in the driver chip. It performs multi-level iterations on each critical phase transition point and performs failure inference during the iteration process, thereby predicting the combination of lifespan characteristics of the driver chip under the current operating conditions, and further determining the remaining lifespan of the driver chip. The emergency module is used to integrate the remaining lifespan with the current usage history of the driver chip, thereby dynamically constructing a lifespan management system for the driver chip. It also determines emergency measures for the operation of the driver chip by combining the lifespan threshold and the corresponding safety margin, and simultaneously triggers a re-inspection of the remaining lifespan of the driver chip.

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