A data verification integrated circuit chip, a data verification method, device and server frame

Abstract

This application relates to a data verification integrated circuit chip, a data verification method, an apparatus, and a server chassis. It includes: a control unit, multiple parallel processing units, and a shared bus; the control unit is used to allocate multiple data tables to be verified, received through a data input interface, to different parallel processing units; each parallel processing unit is used to independently execute queries on its assigned data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus; the control unit is also used to collect all intermediate query results through the shared bus and send all intermediate query results to a target processing unit determined within the parallel processing units; the target processing unit is used to summarize and analyze all intermediate query results, generate verification results for multiple data tables, and output the verification results through a data output interface. This application can improve the efficiency of processing large-scale data.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design and data processing technology, and in particular to a data verification integrated circuit chip, a data verification method, an apparatus, and a server chassis. Background Technology

[0002] With the advent of the big data era, the demand for multi-table data linkage verification is increasing. It is often necessary to perform joint queries and comparisons on multiple data tables to ensure the accuracy of the data and retrieve the required data.

[0003] In related technologies, software-level implementation methods are often used to achieve multi-table linkage verification. These include database-based join query methods, which use SQL (Structured Query Language) statements to perform multi-table join queries, data processing based on distributed computing frameworks, and caching technologies based on in-memory databases (such as Redis).

[0004] However, the multi-table linkage verification method in related technologies has poor performance when processing large-scale data and is difficult to meet real-time requirements. Summary of the Invention

[0005] Therefore, it is necessary to provide a data verification integrated circuit chip, a data verification method, an apparatus, and a server chassis to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a data verification integrated circuit chip, which includes a control unit, multiple parallel processing units, and a shared bus:

[0007] The control unit is used to distribute multiple data tables to be verified received through the data input interface to different parallel processing units;

[0008] Each parallel processing unit is used to independently execute queries on the assigned data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus;

[0009] The control unit is also used to collect all intermediate query results via a shared bus and send all intermediate query results to the target processing unit determined in the parallel processing unit;

[0010] The target processing unit is used to summarize and analyze all intermediate query results, generate verification results for multiple data tables, and output the verification results through the data output interface.

[0011] In one embodiment, the control unit is configured to preprocess each data table when multiple data tables are received through a data input interface, and send the preprocessed data tables to the corresponding parallel processing unit.

[0012] In one embodiment, the control unit is configured to, when receiving multiple data tables through a data input interface, perform a global analysis on each data table, determine the cardinality of fields in each data table, determine a query strategy based on the cardinality, and send the data table and the corresponding query strategy to the corresponding parallel processing unit, wherein the preprocessed data table includes the data table and the corresponding query strategy.

[0013] In one embodiment, the control unit is configured to, when receiving multiple data tables through a data input interface, obtain a verification task through the data input interface, split the verification task into multiple subtasks, wherein each subtask has a dependency relationship; construct a subquery tree based on the subtasks and the dependency relationship state; and allocate the data tables to the corresponding parallel processing units based on the working state of each parallel processing unit and the subquery tree.

[0014] In one embodiment, the control unit is configured to determine the target processing unit based on the operating state of each parallel processing unit.

[0015] In one embodiment, a fully trained first neural network is deployed in the target processing unit;

[0016] The target processing unit is used to input the intermediate query results output by each parallel processing unit into the first neural network for data comparison and verification processing to obtain the data verification results.

[0017] In one embodiment, at least one parallel processing unit is equipped with a fully trained second neural network.

[0018] The parallel processing unit is used to perform feature extraction processing on the acquired data table to be verified based on the second neural network to obtain intermediate query results.

[0019] Secondly, this application also provides a data verification method, applied to a control unit in an integrated circuit chip for data verification, comprising:

[0020] Multiple data tables can be obtained through the data input interface;

[0021] The data table is distributed to multiple parallel processing units, which are instructed to independently execute queries based on the acquired data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus.

[0022] All intermediate query results are aggregated through a shared bus and sent to the target processing unit determined in the parallel processing unit to instruct the target processing unit to aggregate and analyze all intermediate query results and obtain the verification results of multiple data tables.

[0023] The verification results are output through the data output interface.

[0024] Thirdly, this application also provides a data verification device, including a data verification integrated circuit chip as described in any of the above claims and a memory coupled to the data verification integrated circuit chip;

[0025] The memory is used to store the verification results output by the integrated circuit chip for data verification.

[0026] Fourthly, this application also provides a server chassis, including a function board, on which a data verification integrated circuit chip as described above is disposed.

[0027] The aforementioned data verification integrated circuit chip, data verification method, apparatus, and server chassis include a control unit for distributing multiple data tables to be verified, received via a data input interface, to different parallel processing units. Each parallel processing unit independently executes queries on its assigned data table, generates intermediate query results, and sends these results to a shared bus. The control unit also collects all intermediate query results via the shared bus and sends them to a target processing unit determined within the parallel processing units. The target processing unit summarizes and analyzes all intermediate query results, generates verification results for multiple data tables, and outputs these results via a data output interface. By integrating multiple parallel processing units on a single chip, each unit independently executes query tasks, achieving parallel computing through hardware circuitry. This allows for simultaneous verification of multiple data tables, effectively improving data verification efficiency. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a data verification integrated circuit chip in one embodiment;

[0030] Figure 2 This is a flowchart illustrating a data verification method in one embodiment;

[0031] Figure 3 This is a structural block diagram of a data verification device in one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] The technical background of this application will be explained below.

[0034] With the advent of the big data era, the demand for multi-table data linkage verification is increasing. It is often necessary to perform joint queries and comparisons on multiple data tables to obtain query results and ensure the accuracy and consistency of the data.

[0035] In related technologies, multi-table linkage verification methods typically rely on software-level database queries and comparisons. This approach suffers from inefficiency and slow response times when handling large-scale data. Furthermore, software implementation is limited by computing resources and memory constraints, making it difficult to meet the real-time requirements of applications. Specifically, common multi-table linkage verification solutions include: database-based join queries and in-memory database (such as Redis) caching techniques. Database-based join queries use SQL statements to perform multi-table joins, offering the advantage of simplicity but poor performance when handling large-scale data. In-memory database (such as Redis) caching techniques improve query speed by loading data into memory, but are limited by memory capacity and struggle to handle extremely large datasets.

[0036] In summary, the above description illustrates the main problems existing in the relevant technologies: in multi-table joint verification, the performance is poor and the efficiency is low when processing large-scale data.

[0037] Based on this, this application provides a data verification integrated circuit chip, which includes a control unit, multiple parallel processing units, and a shared bus. The control unit is used to allocate multiple data tables to be verified, received through a data input interface, to different parallel processing units. Each parallel processing unit is used to independently execute queries on the allocated data tables, generate intermediate query results for the data tables, and send the intermediate query results to the shared bus. The parallel processing units are also used to collect all intermediate query results through the shared bus, summarize and analyze them, generate verification results for multiple data tables, and output the verification results through a data output interface. The embodiments of this application can improve the efficiency of multi-data-table linkage verification, as detailed in the following specific embodiments.

[0038] In one exemplary embodiment, such as Figure 1As shown, a data verification integrated circuit chip is provided, including a control unit 12, multiple parallel processing units 13 and a shared bus;

[0039] Control unit 12 is used to distribute multiple data tables to be checked received through data input interface 11 to different parallel processing units 13;

[0040] Each parallel processing unit 13 is used to independently execute queries on the assigned data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus;

[0041] Control unit 12 is also used to collect all intermediate query results via a shared bus and send all intermediate query results to the target processing unit determined in parallel processing unit 13;

[0042] The target processing unit is used to summarize and analyze all intermediate query results, generate verification results for multiple data tables, and output the verification results through data output interface 14.

[0043] The aforementioned data verification integrated circuit chip can be implemented using either an ASIC chip or an FPGA (Field-Programmable Gate Array) chip. Furthermore, the FPGA-based solution offers superior programmability, making it suitable for scenarios requiring frequent algorithm updates. However, compared to ASIC (Application Specific Integrated Circuit) solutions, FPGAs have higher power consumption and cost, making them more suitable for small-batch customization needs. The aforementioned integrated circuit chip utilizes a 28nm process.

[0044] The aforementioned integrated circuit chip preferably has 16 parallel processing units 13, each equipped with an independent cache memory (capacity of 128KB). In practical applications, multiple parallel processing units 13 can perform computing tasks simultaneously without interfering with each other.

[0045] In practical applications, the aforementioned shared bus is a set of metal wires to which all parallel processing units 13 are connected, enabling data transmission and reception via the bus protocol. The aforementioned data table refers to the dataset to be verified, with each data table including multiple rows of records and multiple columns of fields. Furthermore, the aforementioned data input interface 11 supports the PCIe 3.0 protocol, and the data output interface 14 supports the USB 3.0 protocol. Moreover, the aforementioned data input interface 11 can be replaced with an interface supporting the Thunderbolt protocol.

[0046] In this embodiment of the application, the data verification integrated circuit chip receives verification task instructions and multiple data tables to be verified from the outside through the data input interface 11. The verification task instructions include at least the unique identifier of the data table to be compared and analyzed, and the specific task (e.g., querying a certain type of data, or checking the consistency of data in multiple data tables, etc.).

[0047] After the control unit 12 parses the verification task instruction, it allocates the multiple data tables to be verified to different parallel processing units 13. The allocation method includes, but is not limited to, in one embodiment, determining the currently idle parallel processing unit 13 and allocating the data table to the idle processing unit; in another embodiment, different data tables can be allocated to the processing units according to their different hardware designs. For example, some processing units have built-in bitmap index acceleration circuits, which are suitable for high-radix number segment queries, while some processing units have built-in dictionary encoding compression circuits, which are suitable for low-radix number segment queries. Therefore, when allocating data tables, high-radix data tables can be allocated to processing units with bitmap index acceleration circuits, and low-radix data tables can be allocated to processing units with dictionary encoding acceleration circuits. It is understood that different parallel processing units 13 can be completely identical units or different units, that is, their specific circuit designs are different.

[0048] Using the above method, the control unit 12 splits multiple data tables into multiple data table groups and assigns different data table groups to different parallel processing units 13. A data table group includes one or more data tables.

[0049] After obtaining the data table, each parallel processing unit 13 independently reads and queries the contents of the data table according to the pre-obtained verification tasks (such as finding duplicate records, finding the number of a certain type of data, data volume statistics, etc.). Each parallel processing unit 13 outputs the corresponding intermediate query results, which include, but are not limited to, the query results of a certain type of data, whether there are duplicate records, null values ​​or other abnormal values ​​in the data table, and the statistical characteristics of the data table (such as the number of rows).

[0050] After obtaining the intermediate query results, the intermediate query results are sent to the shared bus, so that other parallel processing units 13 can obtain the corresponding intermediate query results by reading the data on the bus.

[0051] The control unit 12 determines the target processing unit for data aggregation and analysis among all parallel processing units 13. At this time, the target processing unit can be the unit used to independently query the data table in the previous step, or it can be the unit that did not independently query the data table before. For example, if two data tables are obtained, the two data tables are input into parallel processing unit a and parallel processing unit b respectively to independently execute the query task, thereby obtaining the intermediate query results of units a and b. Then, the intermediate query results can be aggregated and analyzed by parallel processing unit c to obtain the verification result. Alternatively, the intermediate query results can be aggregated and analyzed by parallel processing unit a or parallel processing unit b to obtain the verification result.

[0052] The specific method by which the control unit 12 selects the target processing unit may be to determine the target processing unit based on the current working state of each parallel processing unit 13 (such as processing data or being idle).

[0053] Understandably, the specific summary analysis depends on the instructions of the verification task. For example, if it is a data consistency verification, the abnormal records in the intermediate query results can be merged into a complete table as the above verification result; if it is a statistical verification of a certain type of item, the query results of that type of item in each intermediate query result can be summarized to obtain the complete verification result of that type of item.

[0054] Finally, the above verification results can be output through the data output interface 14. After receiving the verification results, the external host or the host computer can save them to a preset location or restrict them to a preset display unit.

[0055] It is important to emphasize that each parallel processing unit 13 is configured to process only one predetermined data table. That is, each parallel processing unit 13 performs data queries on only one fixed data table to obtain intermediate query results. In practical applications, this can be achieved by writing the unique identifier or address of the data table into the register of the corresponding parallel processing unit 13, thus ensuring that the parallel processing unit 13 consistently accesses only this one data table throughout the entire verification task, without accessing other data tables. The above describes a method for establishing a one-to-one correspondence between parallel processing units 13 and data tables. In practical applications, methods commonly used in the art can also be employed to ensure that each parallel processing unit 13 consistently accesses only one corresponding data table. Therefore, since each parallel processing unit 13 accesses only one fixed data table, and the data table and parallel processing unit 13 have a one-to-one correspondence, multiple units can initiate access requests without causing conflicts.

[0056] Through the embodiments of this application, multiple parallel processing units 13 are integrated on a single chip. Each unit independently executes the query task, achieving parallel computing through hardware circuitry (rather than software-level round-robin). Verification tasks for multiple data tables can be performed simultaneously, effectively improving data verification efficiency. Furthermore, the number of parallel processing units 13 in this application can be determined according to actual needs. For example, four processing units can be integrated in low-power scenarios, while 16 parallel processing units 13 can be integrated in high-performance scenarios, flexibly adapting to different verification tasks.

[0057] In an exemplary embodiment, the control unit 12 is configured to preprocess each data table when multiple data tables are received through the data input interface 11, and send the preprocessed data tables to the corresponding parallel processing unit 13.

[0058] In this embodiment, the control unit 12 processes the data table content according to a preset processing logic. In one embodiment, preprocessing includes data cleaning and standardization, that is, removing invalid, duplicate, or redundant records from the data table and unifying the field format. In another embodiment, preprocessing includes extracting the fields that are truly needed for subsequent verification tasks from the original data table, while ignoring or deleting other fields, thereby reducing the amount of data transmission and the amount of computation of the processing unit.

[0059] In an exemplary embodiment, the control unit 12 is configured to, upon receiving multiple data tables through the data input interface 11, perform a global analysis on each data table, determine the cardinality of fields in each data table, determine a query strategy based on the cardinality, and send the data table and the corresponding query strategy to the corresponding parallel processing unit 13. The preprocessed data table includes the data table and the corresponding query strategy.

[0060] The global analysis is used to scan the entire data table to unify the value distribution characteristics of each field, and can be used for sampling statistics, full statistics, etc., which are common in this field. The cardinality mentioned above refers to the number of different values ​​in each field. For example, the gender field only has two values, male and female, so the cardinality is 2. It can be understood that a high cardinality means that the field value is almost unique, while a low cardinality means that there are a large number of duplicate values. Accordingly, the cardinality situation mentioned above reflects the degree of cardinality of the field. In this embodiment, fields with cardinality values ​​greater than a preset high cardinality threshold can be identified as high cardinality fields, and fields with cardinality values ​​less than a preset low cardinality threshold can be identified as low cardinality fields.

[0061] This application provides a specific data table preprocessing method. First, the control unit 12 performs a global analysis of all data tables and calculates the cardinality of each data table to determine the cardinality of each data table.

[0062] The corresponding query strategy is determined for each data table based on the cardinality of the fields in different data tables. For example, bitmap index query can be used for high cardinality fields, and dictionary encoding compression query can be used for low cardinality fields. The above query strategy includes at least bitmap index query and dictionary encoding compression query.

[0063] Finally, the control unit 12 sends the data table and the corresponding query strategy to the corresponding parallel processing unit 13. After obtaining the data table and the query strategy, the parallel processing unit 13 selects the corresponding execution method. For example, if the strategy indicates field compression encoding, the processing unit first performs dictionary decoding on the data table and then performs a scan.

[0064] In this embodiment, the control unit 12 first preprocesses the data table, that is, it automatically determines the optimal query strategy based on the field data distribution (i.e., cardinality) of the data table, and sends the query strategy and the data table together to the corresponding parallel processing unit 13, thereby effectively improving the processing efficiency of each parallel processing unit 13.

[0065] In an exemplary embodiment, the control unit 12 is configured to, when receiving multiple data tables through the data input interface 11, obtain a verification task through the data input interface 11, split the verification task into multiple subtasks, wherein each subtask has a dependency relationship; construct a subquery tree based on the subtasks and the dependency relationship, and allocate the data tables to the corresponding parallel processing units 13 based on the working status of each parallel processing unit 13 and the subquery tree.

[0066] The verification task refers to the specific verification instructions obtained. For example: Example 1: Calculate the average salary for each department based on Table 1 and Table 2 (where Table 1 is the salary record table for Department 1, and Table 2 is the salary record table for Department 2). Example 2: Check whether the data in Tables 3, 4, and 5 are contradictory (where Tables 3, 4, and 5 are related data tables; for example, Table 3 could be an employee attendance record table, Table 4 could be an employee salary detail table, and Table 5 could be an employee information table). It is understood that Tables 1, 2, 3, 4, and 5 are only examples; besides salary tables and attendance record tables, they could also be tables storing other data. Subtasks are multiple smaller, independently executable calculation subtasks broken down by Control Unit 12 from the original verification task. For example, in the above task of calculating the average salary for each department based on Table 1 and Table 2, it can be broken down into two subtasks: calculating the average salary for Department 1 based on Table 1 and calculating the average salary for Department 2 based on Table 2. The aforementioned dependencies characterize the constraints on the execution order between subtasks, with dependency states including those with and without dependencies. The subquery tree is a tree-like structure, or a directed acyclic graph structure, built based on subtasks and their dependencies. The root node of the subquery tree represents the final verification result, leaf nodes represent scans of the original data table or other basic operations, and intermediate nodes represent calculations, links, and other operations. The working states of the parallel processing unit 13 include, but are not limited to, idle, running, and completed.

[0067] In this embodiment of the application, the control unit 12 receives multiple data tables and verification tasks through the data input interface 11, and then splits the verification tasks into multiple sub-tasks and determines the dependency status between each sub-task. For example, the JOIN operation can be decomposed into two stages: pre-aggregation on the Map side and precise matching on the Reduce side.

[0068] Then, a subquery tree is constructed based on the subtasks and their dependencies. Finally, based on the working status of the parallel processing unit 13 and the subquery tree, the data table is allocated to the corresponding parallel processing unit 13. The following is an allocation logic: First, the subtasks in the subquery tree are traversed to check whether the subtask can start execution (i.e., whether it depends on other preceding subtasks, and whether the preceding subtasks have been completed). If it can start execution, the control unit 12 reads the working status of each parallel processing unit 13. For the subtasks that can start execution, a suitable parallel processing unit 13 that is in an idle state is selected for allocation. In this data verification task, the parallel processing unit 13 is configured to access only a fixed data table.

[0069] In this embodiment, a separate control unit 12 parses the tasks, enabling rapid task splitting and dependency determination upon task reception, thus improving processing efficiency. Furthermore, task allocation is performed based on the overall working status of the processing units and the subquery tree, avoiding assigning tasks to busy units and preventing idle units from waiting, maximizing resource utilization. It also ensures that subtasks are only scheduled after all their preceding tasks have been completed, improving the efficiency and success rate of data verification.

[0070] In one exemplary embodiment, the control unit 12 is configured to determine the target processing unit based on the operating state of each parallel processing unit 13.

[0071] The target processing unit is a specific parallel processing unit 13 used to perform the final summarization and comparison tasks. In practical applications, the control unit 12 may also designate a unit with a neural network acceleration circuit as the target processing unit.

[0072] In one exemplary embodiment, a fully trained first neural network is deployed in the target processing unit;

[0073] The target processing unit is used to input the intermediate query results output by each parallel processing unit 13 into the first neural network for data comparison and verification processing to obtain the data verification results.

[0074] The first neural network is a pre-trained artificial neural network model, including but not limited to fully connected networks, convolutional neural networks, and recurrent neural networks, which are deployed on the target processing unit. Understandably, the first neural network can use neural networks commonly used in this field. To optimize the network, a cross-modal attention module can be embedded in the neural network to automatically learn the correlation weights between different data sources (such as text / images / time series), for example, by using the Transformer's Encoder-Decoder structure to achieve semantic alignment between structured and unstructured data.

[0075] In this embodiment, all intermediate query results are input into the first neural network described above for forward propagation calculation to obtain the corresponding data verification results.

[0076] In one exemplary embodiment, at least one parallel processing unit 13 is equipped with a fully trained second neural network.

[0077] The parallel processing unit 13 is used to perform feature extraction processing on the acquired data table to be checked based on the second neural network to obtain intermediate query results.

[0078] The second neural network is a pre-trained neural network model deployed in at least one parallel processing unit 13. The first neural network is different from the second neural network and is used to perform different types of tasks.

[0079] In this embodiment, the control unit 12 sends the data table to the corresponding parallel processing unit 13. The second neural network deployed in this unit performs feature extraction on the data table to obtain intermediate query results. These intermediate query results can be in the form of feature vectors or data corresponding to the subtasks retrieved based on the second neural network. It is understood that retraining the neural network is necessary when processing different subtasks, which is inefficient. Therefore, the second neural network can be deployed only in some of the parallel processing units 13, rather than in every parallel processing unit 13.

[0080] In this application embodiment, a preferred embodiment of a data verification integrated circuit chip is also provided, including a data input interface 11, a control unit 12, a data processing unit and a data output interface 14. The data processing unit includes multiple parallel processing modules, each module independently executes a query task of a data table, and exchanges intermediate query results through a shared bus, and finally outputs the verification result through the output interface.

[0081] In this embodiment, hardware acceleration is used to achieve multi-table linkage verification, which significantly improves processing efficiency and response speed, and meets the application scenarios with high real-time requirements without relying on software implementation.

[0082] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0083] Based on the same inventive concept, this application also provides a data verification method for implementing the aforementioned data verification integrated circuit chip. The solution provided by this method is similar to the implementation scheme described in the aforementioned circuit chip; therefore, the specific limitations in one or more data verification method embodiments provided below can be found in the limitations of the data verification integrated circuit chip described above, and will not be repeated here.

[0084] In one exemplary embodiment, such as Figure 2 As shown, a data verification method is provided, applied to the control unit in an integrated circuit chip for data verification, including:

[0085] S210, obtains multiple data tables through the data input interface;

[0086] S220: Distribute the data table to multiple parallel processing units, instructing the parallel processing units to independently execute queries based on the acquired data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus;

[0087] S230 aggregates all intermediate query results via the shared bus and sends all intermediate query results to the target processing unit determined in the parallel processing unit, so as to instruct the target processing unit to aggregate and analyze all intermediate query results and obtain the verification results of multiple data tables.

[0088] S240 outputs the verification results through the data output interface.

[0089] In one exemplary embodiment, a data verification device is also provided, such as... Figure 3 As shown, it includes the data verification integrated circuit chip 10 as described above and the memory 30 coupled to the chip;

[0090] The memory 30 is used to store the verification results output by the data verification integrated circuit chip 10.

[0091] Each module in the aforementioned data verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0092] In one exemplary embodiment, a server chassis is also provided, including a function board on which a data verification integrated circuit chip as described in any of the above claims is disposed.

[0093] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data verification integrated circuit chip, characterized in that, The data verification integrated circuit chip includes a control unit, multiple parallel processing units, and a shared bus; The control unit is used to distribute multiple data tables to be checked, received through the data input interface, to different parallel processing units; Each of the parallel processing units is used to independently execute queries on the assigned data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus; The control unit is also configured to collect all intermediate query results via the shared bus and send all intermediate query results to the target processing unit determined in the parallel processing unit; The target processing unit is used to summarize and analyze all intermediate query results, generate verification results for the multiple data tables, and output the verification results through the data output interface.

2. The data verification integrated circuit chip according to claim 1, characterized in that, The control unit is configured to preprocess each data table when multiple data tables are received through the data input interface, and then send the preprocessed data tables to the corresponding parallel processing unit.

3. The data verification integrated circuit chip according to claim 2, characterized in that, The control unit is configured to, when receiving multiple data tables through the data input interface, perform a global analysis on each data table, determine the cardinality of fields in each data table, determine a query strategy based on the cardinality, and send the data table and the corresponding query strategy to the corresponding parallel processing unit. The preprocessed data table includes the data table and the corresponding query strategy.

4. The data verification integrated circuit chip according to any one of claims 1 to 3, characterized in that, The control unit is configured to, when receiving multiple data tables through the data input interface, obtain a verification task through the data input interface, split the verification task into multiple subtasks, wherein each subtask has a dependency relationship; construct a subquery tree based on the subtasks and the dependency relationship, and allocate the data tables to the corresponding parallel processing units based on the working status of each parallel processing unit and the subquery tree.

5. The data verification integrated circuit chip according to any one of claims 1 to 3, characterized in that, The control unit is used to determine the target processing unit based on the working status of each parallel processing unit.

6. The data verification integrated circuit chip according to claim 5, characterized in that, The target processing unit is equipped with a fully trained first neural network. The target processing unit is used to input the intermediate query results output by each parallel processing unit into the first neural network for data comparison and verification processing to obtain the verification result.

7. The data verification integrated circuit chip according to any one of claims 1 to 3, characterized in that, At least one parallel processing unit is equipped with a fully trained second neural network. The parallel processing unit is used to perform feature extraction processing on the acquired data table to be verified based on the second neural network to obtain the intermediate query result.

8. A data verification method, characterized in that, The method, applied to a control unit in a data verification integrated circuit chip, includes: Multiple data tables can be obtained through the data input interface; The data table is distributed to multiple parallel processing units, which instruct the parallel processing units to independently execute queries based on the acquired data table, generate intermediate query results for the data table, and send the intermediate query results to the shared bus; All intermediate query results are aggregated through the shared bus and sent to the target processing unit determined in the parallel processing unit to instruct the target processing unit to aggregate and analyze all intermediate query results to obtain the verification results of the multiple data tables. The verification results are output through the data output interface.

9. A data verification device, characterized in that, Includes a data verification integrated circuit chip as described in any one of claims 1 to 7 and a memory coupled to the data verification integrated circuit chip; The memory is used to store the verification results output by the data verification integrated circuit chip.

10. A server chassis, characterized in that, It includes a function board, on which a data verification integrated circuit chip as described in any one of claims 1 to 7 is provided.

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