A method and system for identifying IGBT hotspots based on transient thermal resistance curves

Abstract

This application relates to a method and system for IGBT hotspot identification based on transient thermal resistance curves, belonging to the field of IGBT thermal monitoring technology. The method includes: loading the junction-shell transient thermal resistance curve from the datasheet to construct a fractional-order thermal network model containing equivalent thermal resistance, thermal capacity, and fractional order; obtaining model parameters through parameter identification; real-time acquisition of electrical quantities and temperature to calculate power loss; substituting the power loss into the fractional-order differential equation to solve for the junction-shell temperature difference, and combining this with the operating temperature to obtain a real-time estimated junction temperature; and identifying hotspots based on the estimated junction temperature to obtain hotspot status information. This method achieves a complete closed loop from offline modeling and parameter identification to real-time junction temperature monitoring and hotspot identification. This application solves the problems of low reliability of a single junction temperature criterion and the inability to distinguish the location of thermal aging in the chip layer, solder layer, and substrate layer in IGBT thermal monitoring.

Description

Technical Field

[0001] This application relates to the field of IGBT thermal monitoring technology, and in particular to an IGBT hotspot identification method and system based on transient thermal resistance curves. Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device that combines the high input impedance of a metal-oxide-semiconductor field-effect transistor (MOSFET) with the low on-state voltage drop of a bipolar transistor. It is widely used in power electronics fields such as motor drives, new energy power generation, and rail transportation. During operation, the junction temperature of the IGBT directly determines its reliability, lifespan, and output capability. Excessive temperature can lead to bond wire detachment, solder layer fatigue, and even device burnout. Therefore, real-time monitoring of the junction temperature and thermal anomaly diagnosis are necessary. Existing monitoring methods mainly rely on thermistors to measure the casing temperature and combine this with thermal impedance models to estimate the junction temperature, or offline experimental methods such as infrared imaging and fiber optic temperature measurement.

[0003] However, the existing technologies mentioned above have the following shortcomings: First, they rely on a single shell temperature or a single junction temperature estimate as a criterion for thermal status, lacking multi-dimensional monitoring of the thermal resistance evolution of the chip layer, solder layer, and substrate layer, resulting in low reliability of the comprehensive criterion for thermal anomalies and difficulty in distinguishing the root cause of aging; second, they only provide overall temperature values ​​and cannot accurately pinpoint which internal physical layer thermal aging occurs, leading to blind maintenance decisions and high repair costs. Therefore, there is an urgent need for an automated detection solution that can locate hotspots at different levels and has a high-reliability early warning capability. Summary of the Invention

[0004] This application provides an IGBT hotspot identification method and system based on transient thermal resistance curves, which solves the technical problems in the prior art such as low reliability of single junction temperature monitoring criteria, inability to distinguish the thermal aging location of chip layer, solder layer, and substrate layer, and the inability of offline parameters to adapt to long-term device aging leading to decreased monitoring accuracy.

[0005] This application discloses the following technical solution: In a first aspect, this application provides a method for identifying IGBT hotspots based on transient thermal resistance curves, the method comprising: The junction-to-case transient thermal impedance curve from the datasheet of the target insulated gate bipolar transistor; Based on the junction-shell transient thermal impedance curve, a fractional-order thermal network model of the target insulated gate bipolar transistor is constructed, wherein the fractional-order thermal network model includes equivalent thermal resistance parameters, equivalent thermal capacity parameters, and fractional order. Based on the fractional-order thermal network model and the junction-shell transient thermal impedance curve, parameter identification is performed to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order. Real-time acquisition of electrical quantities and operating temperature of the target insulated gate bipolar transistor, and calculation of real-time power loss; The real-time power loss is input into the fractional-order thermal network differential equation composed of the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order, and the real-time junction-shell temperature difference is obtained by solving the equation. The estimated value of the real-time junction temperature is then calculated based on the operating temperature. Based on the estimated real-time junction temperature, hotspot identification is performed to obtain hotspot status information.

[0006] Secondly, this application provides an IGBT hotspot identification system based on transient thermal resistance curves, the system comprising: The curve loading module is used to load the junction-case transient thermal impedance curve from the datasheet of the target insulated gate bipolar transistor. The model building module is used to construct a fractional-order thermal network model based on the junction-shell transient thermal impedance curve. The fractional-order thermal network model includes equivalent thermal resistance parameters, equivalent heat capacity parameters, and fractional order. The parameter identification module is used to perform parameter identification based on the fractional-order thermal network model and the junction-shell transient thermal impedance curve to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order. The real-time acquisition and calculation module is used to acquire the electrical quantities and operating temperature of the target insulated gate bipolar transistor in real time and calculate the real-time power loss. The junction temperature calculation module is used to input the real-time power loss into the fractional-order thermal network differential equation composed of the identified parameters, solve for the real-time junction-shell temperature difference, and calculate the estimated value of the real-time junction temperature based on the operating temperature. The hotspot identification module is used to perform hotspot identification based on the real-time junction temperature estimation value and obtain hotspot status information.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages: The technical solution of this application provides an IGBT hotspot identification method based on transient thermal resistance curves. First, by loading the junction-case transient thermal resistance curve from the target insulated gate bipolar transistor datasheet, a standard benchmark for obtaining the thermal characteristics of the device without any actual measurement equipment is achieved. This provides a traceable data source for subsequent modeling and parameter identification, and solves the technical problem of not being able to start thermal monitoring when there are no actual measurement conditions.

[0008] Furthermore, by constructing a fractional-order thermal network model based on the junction-shell transient thermal impedance curve, which includes equivalent thermal resistance, equivalent thermal capacity, and fractional order, and by preferably cascading sub-models built from the chip layer, solder layer, and substrate layer respectively, the ability to accurately describe thermal impedance characteristics over a wide time range with fewer parameters and to characterize the thermal contribution of each layer can be achieved. This solves the technical problem of redundant parameters and inability to distinguish the thermal aging location of each physical layer in traditional integer-order RC networks.

[0009] Furthermore, by flexibly selecting offline calibration mode, adaptive identification mode, or online interactive mode according to actual measurement conditions and operating conditions during the parameter identification step, full-scenario coverage is achieved from pure manual curve calibration to periodic actual measurement updates and then to online closed-loop correction. This enables the model parameters to be dynamically adjusted as the device ages and operating conditions change, solving the technical problem that a single offline parameter cannot adapt to long-term drift and time-varying power loss leading to distortion in junction temperature estimation.

[0010] Furthermore, by acquiring collector current, collector-emitter voltage, and switching frequency in real time and using the insulated gate bipolar transistor loss model to calculate the sum of conduction loss and switching loss, the dynamic and accurate acquisition of real-time heating power was achieved. This provides the thermal model with excitation input that varies with operating conditions, solving the technical problem of power input deviating from actual operating conditions due to reliance on static loss assumptions or typical values ​​from manuals.

[0011] Furthermore, by employing a combination of discrete scheme and explicit difference method to solve the fractional-order thermal network differential equation, and by accumulating the historical power loss values ​​of all past moments into the current temperature difference calculation with power-law weights, efficient recursive solution of the fractional-order model on a digital processor is achieved, and the long memory characteristics of heat diffusion are accurately characterized. This solves the technical problems of fractional-order differential equations being difficult to embed in real-time calculation and the distortion of transient junction temperature estimation caused by ignoring historical power contributions.

[0012] Finally, by performing hotspot identification based on real-time junction temperature estimation, the time evolution trajectory of the equivalent thermal resistance of the chip layer, solder layer, and substrate layer is monitored. Based on whether the thermal resistance of each layer increases monotonically for multiple consecutive cycles and the cumulative magnitude exceeds the corresponding threshold, a layered thermal aging warning is output. This achieves physical layer positioning and advanced diagnosis of hotspot locations, solving the technical problems that a single junction temperature value cannot determine the root cause of the fault and cannot achieve layered aging warning.

[0013] In summary, this application achieves accurate characterization of IGBT thermal state and hotspot physical layer location through multi-level fractional-order modeling, three-mode adaptive parameter identification, real-time power loss calculation, power-law weight accumulation solution, and layered thermal resistance evolution monitoring. This effectively improves the problems in the prior art, such as low reliability of single junction temperature criterion, inability to distinguish the aging location of chip layer, solder layer, and substrate layer, and the inability of offline parameters to adapt to long-term aging and time-varying operating conditions, which leads to a decrease in monitoring accuracy. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A flowchart illustrating an IGBT hotspot identification method based on transient thermal resistance curves provided in this application embodiment; Figure 2 This is a schematic diagram of the structure of an IGBT hotspot identification system based on transient thermal resistance curves, provided in an embodiment of this application.

[0016] The components represented by each number in the attached diagram are described as follows: Curve loading module 11, Model building module 12, Parameter identification module 13, Real-time acquisition and calculation module 14, Junction temperature solution module 15, Hotspot identification module 16. Detailed Implementation

[0017] This application provides an IGBT hotspot identification method and system based on transient thermal resistance curves, which solves the technical problems in the prior art such as low reliability of single junction temperature monitoring criteria, inability to distinguish the thermal aging location of chip layer, solder layer, and substrate layer, and the inability of offline parameters to adapt to long-term device aging leading to decreased monitoring accuracy.

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Example 1, as shown in the appendix Figure 1 As shown, this application provides a method for identifying IGBT hotspots based on transient thermal resistance curves. The method includes the following steps: S100: Junction-to-case transient thermal impedance curve from the datasheet of the target insulated gate bipolar transistor; S200: Based on the junction-shell transient thermal impedance curve, construct a fractional-order thermal network model of the target insulated gate bipolar transistor, wherein the fractional-order thermal network model includes equivalent thermal resistance parameters, equivalent thermal capacity parameters, and fractional order; In this embodiment of the application, in the scenario where the junction-to-case transient thermal impedance curve from the datasheet of the insulated gate bipolar transistor has been loaded, in order to construct the fractional-order thermal network model of the target insulated gate bipolar transistor, it is necessary to introduce a fractional-order calculus framework and establish sub-models for the chip layer, solder layer, and substrate layer respectively, and then cascade them. This solves the technical problems of traditional integer-order RC networks requiring multiple series units to fit the thermal impedance curve over a wide time range, resulting in parameter redundancy and unclear physical meaning, and the inability of a single overall model to distinguish the thermal resistance contribution of each physical layer, thus making it impossible to locate the thermal aging position.

[0020] In this embodiment of the application, step S200 of the method provided in this embodiment includes: Fractional-order sub-models are established for the chip layer, solder layer, and substrate layer of the target insulated-gate bipolar transistor. These fractional-order sub-models are then cascaded to obtain a multi-layer fractional-order thermal network model. Each fractional-order sub-model includes the layer's equivalent thermal resistance parameter, layer's equivalent thermal capacity parameter, and the layer's fractional order. A detailed explanation follows: In this embodiment, the chip layer refers to the layer where the inner wafer of the insulated gate bipolar transistor is located. It is the source of heat generation and has the smallest thermal time constant, typically in the range of microseconds to milliseconds.

[0021] Solder layer refers to the welding material that connects the chip layer and the substrate layer. It is prone to fatigue cracks due to thermal cycling, which leads to a gradual increase in thermal resistance.

[0022] The substrate layer refers to the ceramic copper-clad laminate layer, which is used for heat dissipation and electrical insulation. It has the largest thermal time constant, ranging from seconds to hundreds of seconds.

[0023] A fractional-order sub-model refers to a mathematical model describing the thermal behavior of a single layer, consisting of fractional-order differential equations: P(t) = Parameters include equivalent thermal resistance. The unit is K / W, equivalent heat capacity. The unit is J / K, and the fractional order is... Dimensionless and 0 < <1, The temperature difference between the junction and the shell is represented by , where i refers to a specific layer (e.g., i=1 refers to a chip layer). This equation reflects the thermal diffusion process using power-law memory characteristics, making it more accurate than integer-order models.

[0024] Cascading refers to connecting fractional-order sub-models of chip layer, solder layer, and substrate layer in series, with the same power loss flowing through each layer sequentially. In summary, the temperature difference of the casing is equal to the sum of the temperature differences of each layer.

[0025] In this step, in order to track the thermal resistance evolution of the chip layer, solder layer and substrate layer inside the insulated gate bipolar transistor and to locate the hot spot physical layer, it is necessary to establish an independent fractional-order sub-model for each physical layer. Each sub-model includes the equivalent thermal resistance, equivalent thermal capacity and fractional order of the layer. The three sub-models are cascaded to form a multi-layer fractional-order thermal network model, so that the same power loss flows through each layer in sequence and the sum of the case temperature difference is equal to the sum of the temperature differences of each layer. This can distinguish the thermal aging contribution of different layers and achieve the effect of independent early warning, which can solve the technical problem that a single-layer overall model cannot locate the physical location of the hot spot.

[0026] For example, taking the Infineon FF600R12ME4 insulated gate bipolar transistor as an example, the junction-to-case transient thermal impedance curve under typical conditions with a duty cycle D=0.5 was extracted from the datasheet, and discrete data at 30 logarithmically uniform time points were obtained: at t=0.01s =0.012 K / W, t=0.1s 0.045 K / W, at t=1s =0.12K / W, t=10s =0.23K / W. Based on this curve, a three-layer fractional-order thermal network model is constructed: the chip layer has a preset thermal resistance. =0.05K / W, heat capacity =0.02J / K, fractional order =0.70; Solder layer preset =0.03K / W =0.50J / K =0.85; substrate layer preset =0.15K / W =5.0J / K =0.95. Each layer satisfies the fractional differential equation P(t) = Summary—Shell Temperature Difference = + + .

[0027] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0028] In summary, this step constructs a multi-layer fractional-order thermal network model based on the junction-shell transient thermal impedance curve, incorporating equivalent thermal resistance, equivalent thermal capacity, and fractional order. This establishes a precise and hierarchical physical foundation for subsequent real-time junction temperature estimation and hotspot identification. Compared to existing technologies, the multi-layer fractional-order structure accurately describes thermal impedance characteristics over a wide time range with fewer parameters and enables independent characterization of the chip layer, solder layer, and substrate layer. This overcomes the shortcomings of traditional integer-order RC networks, which suffer from parameter redundancy and the inability to distinguish the thermal resistance contributions of each layer. It also solves the technical problem of being unable to locate the thermal aging position due to overly simplified models or missing physical layer information.

[0029] S300: Based on the fractional-order thermal network model and the junction-shell transient thermal impedance curve, perform parameter identification to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order. In this application embodiment, in the scenario where a fractional-order thermal network model has been constructed, in order to identify and obtain the equivalent thermal resistance, equivalent heat capacity, and fractional order from the transient thermal impedance curve, three modes—offline calibration, adaptive identification, or online interaction—are required, depending on whether actual measurement conditions are available and whether the operating conditions are time-varying. This addresses the technical problems of existing technologies that only perform single offline parameter calibration, which cannot adapt to the lack of actual measurement data, cannot track device aging drift, and cause large junction temperature estimation errors due to model mismatch under time-varying power conditions.

[0030] In this embodiment of the application, step S300 of the method provided in this embodiment includes: When only the datasheet of the target insulated-gate bipolar transistor is available and actual testing conditions are not available, execute the offline calibration mode: Extract the junction-shell transient thermal resistance curve from the datasheet; A combined error objective function for amplitude and phase is constructed, and a system constraint term is introduced into the combined error objective function. The system constraint term assigns different weights to the thermal impedance prediction error in the short time interval and the long time interval, respectively. A swarm intelligence optimization algorithm is used to search for the global optimal solution. During the search process, the positive definiteness of the equivalent thermal resistance parameter, the positive definiteness of the equivalent heat capacity parameter, and the physical validity of the fractional order are used as hard constraints. A detailed explanation follows: In this embodiment of the application, the offline calibration mode refers to the method of parameter identification based solely on the transient thermal impedance curve in the datasheet of the insulated gate bipolar transistor, without relying on any measured data.

[0031] The comprehensive error objective function is a criterion used to evaluate the goodness of fit of a model. It is composed of a weighted sum of magnitude error and phase error. The magnitude error is calculated as the square of the difference between the model's thermal impedance and the thermal impedance value from the manual curve. The phase error is calculated as the square of the difference between the derivatives of the two curves on the logarithmic time axis. The objective function is in the form of... Where N is the total number of time points on the curve in the datasheet. The unit for the k-th time point is seconds. and The curves in the model and the manual are respectively... The thermal resistance value at that location is expressed in K / W. () represents the amplitude weighting coefficient in a short time interval When <0.1s, take 10; long time interval. Take 1 when ≥0.1s. and The model and manual curves are respectively in logarithmic time. The derivative on the phase is used to characterize the phase properties. The phase weight coefficients also employ a segmented strategy of high weight for short time intervals and low weight for long time intervals. Specifically, a weight of 10 is assigned to the short time interval t < 0.1s, and a weight of 1 is assigned to the long time interval t ≥ 0.1s. The smaller the value of this function, the more accurate the model.

[0032] The system constraint term refers to multiplying the prediction error for different time intervals in the error function by different weights, with higher weights for shorter time intervals and lower weights for longer time intervals, in order to prioritize ensuring the accuracy of transient response.

[0033] Swarm intelligence optimization algorithms refer to algorithms that search for the global optimal solution by simulating the cooperation of biological groups, such as particle swarm optimization or genetic algorithms, to avoid getting trapped in local optima.

[0034] In this step, in order to obtain the initial model parameters in a scenario where only the datasheet curves are available and no actual measurement conditions are available, the junction-shell transient thermal impedance curve needs to be extracted from the datasheet. This provides the reference data for subsequent calibration and solves the technical problem of not being able to obtain thermal characteristic parameters when no actual measurement equipment is available.

[0035] Furthermore, in order to accurately evaluate the degree of agreement between the fractional-order model and the manual curve at different time scales, it is necessary to construct a comprehensive error objective function that includes amplitude and phase and introduce system constraint terms into it. Different weights are assigned to the thermal impedance prediction errors in short-time intervals and long-time intervals, so as to optimize the fitting accuracy for different thermal processes of different speeds. This can solve the technical problem that a single error index cannot take into account both transient response and steady-state accuracy.

[0036] Furthermore, in order to find the global optimal solution that minimizes the comprehensive error in the parameter space, a swarm intelligence optimization algorithm is needed to search for the global optimal solution. This can avoid getting trapped in local optima and solve the technical problem that gradient-based algorithms tend to converge to non-physical parameters.

[0037] Finally, to ensure that the identified parameters meet the basic requirements of thermodynamics and fractional calculus, the positive definiteness of equivalent thermal resistance, the positive definiteness of equivalent heat capacity, and the physical validity of fractional order should be used as hard constraints during the search process. Candidate parameters that do not meet the conditions should be rejected or corrected. This will result in physically interpretable and numerically stable model parameters, which can solve the technical problem of negative resistance or out-of-range order causing model distortion in the parameter identification results.

[0038] For example, taking the Infineon FF600R12ME4 insulated-gate bipolar transistor as an example, in offline calibration mode, the parameters of a three-layer fractional-order model are identified using a particle swarm optimization algorithm based solely on the datasheet curves. The particle swarm size is set to 30, and the iterations are 200. The error objective function includes amplitude error and phase error, with a weight of 10 for short time intervals t < 0.1s and a weight of 1 for long time intervals t ≥ 0.1s. The hard constraints are... >0、 >0、0< <1. The chip layer was finally identified. =0.048K / W =0.018J / K =0.72; Solder layer =0.028K / W =0.48J / K =0.86; substrate layer =0.16K / W =5.2J / K =0.94. This set of parameters ensures that the overall error between the model's output curve and the datasheet curve is less than 2%.

[0039] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0040] In this embodiment of the application, step S300 of the method provided in this embodiment of the application further includes: When transient thermal impedance measurement conditions are available, the adaptive identification mode is executed: The measured transient thermal impedance curve of the target insulated gate bipolar transistor was obtained by electrical measurement method; Based on the measured transient thermal impedance curve, an initial identification is performed to obtain the reference equivalent thermal resistance parameter, the reference equivalent heat capacity parameter, and the reference fractional order. In subsequent monitoring cycles, the deviations between each newly measured transient thermal impedance curve and the reference thermal impedance curve corresponding to the reference equivalent thermal resistance parameter, the reference equivalent thermal capacity parameter, and the reference fractional order are iteratively corrected using regularized least squares method to obtain updated equivalent thermal resistance parameters, updated equivalent thermal capacity parameters, and updated fractional orders. Simultaneously, the time evolution trajectory of the updated equivalent thermal resistance parameter is continuously recorded. A detailed explanation follows: In this embodiment of the application, the adaptive identification mode refers to establishing a benchmark model through the first measurement when the actual measurement conditions are available, and periodically re-measuring the transient thermal impedance curve in subsequent operation, using the regularized least squares method to iteratively correct the model parameters, so that the model can maintain long-term accuracy as the insulated gate bipolar transistor ages, avoiding the one-time defects of offline calibration.

[0041] The electrical measurement method refers to the experimental method of applying a step power to an insulated gate bipolar transistor and simultaneously acquiring the case temperature change curve, and then obtaining the measured transient thermal impedance curve after normalization.

[0042] The measured transient thermal impedance curve is a discrete-time thermal impedance numerical sequence that is directly measured by electrical measurement methods and reflects the true thermal diffusion characteristics of the current device.

[0043] The baseline parameter refers to the equivalent thermal resistance obtained from the initial identification. The unit is K / W, equivalent heat capacity The units are J / K and fractional order. This serves as the starting reference point for subsequent corrections.

[0044] Regularized least squares is a parameter-corrected algorithm that adds a regularization term to standard least squares. Its objective function is: [ ],in Parameters to be corrected , , The vector formed For the new measured curve, Calculate the curve for the model. As the baseline parameter vector, The regularization coefficient ranges from 0.01 to 0.1. This formula ensures that the update closely approximates the new curve while maintaining smoothness and stability.

[0045] The time evolution trajectory refers to the sequence formed by recording the equivalent thermal resistance values ​​obtained after each correction in chronological order, such as... =0.051K / W, 0.054K / W, and 0.058K / W are used to analyze the trend of thermal resistance variation in each layer.

[0046] In this step, in order to obtain the true transient thermal impedance data when the actual measurement conditions are available, the measured transient thermal impedance curve of the target insulated gate bipolar transistor needs to be obtained by electrical measurement method. This provides a benchmark that reflects the true thermal state of the current device and can solve the technical problem that relying solely on the datasheet curve cannot reflect individual differences and the initial state of aging.

[0047] Furthermore, in order to establish a traceable initial health state reference, it is necessary to perform initial identification based on the measured transient thermal impedance curve to obtain the reference equivalent thermal resistance parameter, the reference equivalent thermal capacity parameter, and the reference fractional order. The initial model parameters of the device can be obtained as the zero point for subsequent comparison, which can solve the technical problem of not being able to quantify parameter drift due to the lack of original reference.

[0048] Furthermore, in order to ensure that the model parameters are updated smoothly as the device ages in subsequent monitoring cycles, the deviation between the new measured transient thermal impedance curve and the reference thermal impedance curve corresponding to the reference parameters needs to be iteratively corrected using the regularized least squares method to obtain the updated equivalent thermal resistance, equivalent thermal capacity, and fractional order. This allows the model parameters to be gradually corrected over time and remain stable, which can solve the technical problem that one-time offline identification cannot adapt to long-term aging.

[0049] Finally, in order to quantitatively analyze the aging trend of each physical layer and provide a data basis for hotspot location, it is necessary to continuously record the time evolution trajectory of the updated equivalent thermal resistance parameter. This will yield a sequence of thermal resistance changes over time, which can solve the technical problem of not being able to determine the monotonic increase and cumulative magnitude of thermal resistance due to the lack of historical data.

[0050] For example, taking the Infineon FF600R12ME4 insulated-gate bipolar transistor as an example, in adaptive identification mode, a step power of 100W was applied to the same model of insulated-gate bipolar transistor under laboratory conditions, and the measured transient thermal impedance curve was obtained through electrical measurement methods. The initial identification yielded the following reference parameters: =0.051K / W =0.021J / K =0.71; =0.031K / W =0.52J / K =0.84; =0.14K / W =4.9J / K =0.96. After 1000 hours of operation, the curve was measured again, and a deviation was found when compared with the baseline curve. Regularized least squares iterative correction was used, with a regularization coefficient λ=0.05, resulting in the updated parameters: =0.054K / W =0.035K / W =0.15K / W, with other parameters varying by less than 1%. The time evolution trajectory of the equivalent thermal resistance of the three layers was also recorded.

[0051] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0052] In this embodiment of the application, step S300 of the method provided in this embodiment of the application further includes: When the target insulated gate bipolar transistor operates under time-varying power loss conditions, the online interactive mode is executed: Based on a pre-defined baseline fractional-order thermal network model, the theoretical shell temperature response under the current power loss is calculated. The actual shell temperature is collected in real time, and the continuous deviation between the theoretical shell temperature response and the actual shell temperature is calculated. When the sustained deviation exceeds a preset threshold, real-time junction temperature estimation based on the baseline fractional-order thermal network model is paused. Instead, the equivalent thermal resistance parameter, the equivalent heat capacity parameter, and the fractional-order order are updated online via reverse heat conduction calculation using measurement data from the built-in negative temperature coefficient thermistor. A detailed explanation follows: In this embodiment of the application, the time-varying power loss condition refers to the working state in which the power loss of the insulated gate bipolar transistor changes drastically over time, such as the rapid acceleration or deceleration of an electric vehicle or the sudden change in the load of an inverter.

[0053] Online interactive mode is a special case of adaptive identification mode, suitable for scenarios where parameters drift rapidly due to drastic changes in operating conditions. This mode continuously compares the theoretical case temperature with the actual case temperature during device operation. When the deviation exceeds the limit, it automatically triggers online parameter correction without stopping the device. After correction, junction temperature estimation is immediately resumed.

[0054] The theoretical shell temperature response refers to the shell temperature value calculated by substituting real-time power loss into the current benchmark fractional-order thermal network model, which serves as a reference value for comparison with actual measurements.

[0055] Persistent deviation refers to the difference between the theoretical shell temperature and the actual shell temperature exceeding a preset threshold for multiple consecutive sampling periods, used to determine whether the model is mismatched.

[0056] Negative temperature coefficient thermistors are temperature sensors built into insulated gate bipolar transistor modules. Their resistance decreases as the temperature increases, and they are used to measure the housing temperature in real time.

[0057] Reverse heat conduction calculation refers to the process of using measured shell temperature data to inversely deduce model parameters. By iteratively adjusting thermal resistance, heat capacity, and order, the theoretical shell temperature is brought close to the desired value, thereby updating the model online.

[0058] In this step, in order to deal with the operating conditions where power loss changes drastically over time, it is necessary to determine whether the target insulated gate bipolar transistor is operating under time-varying power loss conditions. This provides the prerequisite for triggering the online interactive mode and can solve the problem of delayed response of the conventional adaptive identification mode when operating conditions change drastically.

[0059] Furthermore, in order to detect the degree of model mismatch in real time without new measured curves, it is necessary to calculate the theoretical shell temperature response under the current power loss based on the preset benchmark fractional-order thermal network model, and compare it with the real-time collected actual shell temperature to obtain the continuous deviation. This can achieve the effect of uninterrupted monitoring of the model prediction accuracy and solve the technical problem of not being able to identify parameter drift online.

[0060] Furthermore, in order to prevent the propagation of erroneous junction temperature estimation when the deviation exceeds the limit, the real-time junction temperature estimation based on the benchmark model should be suspended when the continuous deviation exceeds the preset threshold. This provides a safety mechanism to freeze unreliable outputs and can solve the technical problem of distorted junction temperature data leading to misleading decision-making when the mismatch model is continued to be used.

[0061] Finally, in order to complete the model parameter correction without shutting down the system, the measurement data of the built-in negative temperature coefficient thermistor is used to update the equivalent thermal resistance parameter, equivalent heat capacity parameter and fractional order online through reverse heat conduction calculation. This achieves the effect of online closed-loop adaptive correction and can solve the technical problem of maintaining model accuracy under time-varying conditions.

[0062] For example, taking the Infineon FF600R12ME4 insulated-gate bipolar transistor (IGBT) as an example, in online interactive mode, the IGBT operates under time-varying power loss conditions of frequent acceleration and deceleration in electric vehicles. The baseline model uses the baseline parameters initially obtained through adaptive identification mode. The case temperature is acquired in real time, and the deviation between the theoretical and actual case temperature is calculated every 10ms. When the deviation exceeds 2°C for five consecutive sampling cycles, reverse heat conduction calculation is triggered. Using the measurement data from the built-in negative temperature coefficient thermistor, the parameters are updated online using the recursive least squares method, iterating every 0.1 seconds until the deviation drops below 0.5°C. After the update, the real-time junction temperature estimation is restored. This process can be completed automatically during a rapid acceleration condition without downtime.

[0063] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0064] In summary, this step provides a flexible solution for parameter acquisition and updating under different test conditions and operating scenarios through three parameter identification modes: offline calibration, adaptive identification, and online interaction. Compared with existing technologies, the offline calibration mode only requires datasheet curves to complete the initial modeling; the adaptive identification mode uses periodic measurements and regularized least squares iterations to make the model follow device aging; and the online interaction mode uses case temperature feedback to achieve closed-loop correction without shutdown. This overcomes the shortcomings of traditional offline calibration in adapting to time-varying power losses and long-term device drift, and solves the technical problem of the junction temperature estimation error accumulating over time due to model parameter mismatch.

[0065] S400: Real-time acquisition of electrical quantities and operating temperature of the target insulated gate bipolar transistor, and calculation of real-time power loss; In this embodiment of the application, in the scenario where the parameters of the fractional-order thermal network model of the insulated gate bipolar transistor have been identified and obtained, in order to calculate the power loss under the current operating condition in real time as the input excitation of the thermal model, it is necessary to collect the collector current, collector-emitter voltage and switching frequency in real time, and use a loss model that superimposes conduction loss and switching loss to perform the calculation, so as to solve the technical problem that relying solely on static manual curves or offline parameters cannot reflect real-time load changes, resulting in lagging and low accuracy in junction temperature estimation.

[0066] In this embodiment of the application, step S400 of the method provided in this embodiment includes: Based on real-time acquired collector current, collector-emitter voltage, and switching frequency, the sum of conduction loss and switching loss is calculated using an insulated-gate bipolar transistor (IGBT) loss model, and this sum is taken as the real-time power loss. A detailed explanation follows: Collector current refers to the current flowing between the collector and emitter of an insulated-gate bipolar transistor, measured in amperes (A), and is acquired in real time by a current sensor.

[0067] Collector-emitter voltage refers to the voltage drop across the collector and emitter terminals when an insulated-gate bipolar transistor is turned on, measured in volts (V), and is acquired in real time by a voltage detection circuit.

[0068] Switching frequency refers to the number of times an insulated gate bipolar transistor (IGBT) turns on and off per second, measured in Hz, and is directly obtained from the pulse width modulation signal inside the controller.

[0069] The insulated-gate bipolar transistor (IGBT) loss model is a mathematical formula for calculating real-time power loss, including conduction losses. With switching losses Two parts. = × + × 2 ,in The threshold voltage is in units of V. The unit of on-resistance is Ω. The unit of average current is A. The effective value of the current is measured in amperes (A). =( + )× ×k, where and The unit of energy consumption for a single power-on and power-off cycle is J. Where is the switching frequency in Hz, and k is a correction factor. Real-time power loss P = + , unit W.

[0070] Conduction loss refers to the energy loss caused by the current flowing through the saturation voltage drop when an insulated gate bipolar transistor is in the conduction state, and is measured in watts (W).

[0071] Switching loss refers to the energy loss caused by the overlap of voltage and current during each turn-on and turn-off process of an insulated gate bipolar transistor (IGBT). It is measured in watts (W) and is proportional to the switching frequency.

[0072] In this step, in order to obtain the raw electrical data required for real-time power loss calculation, it is necessary to collect the collector current, collector-emitter voltage and switching frequency of the target insulated gate bipolar transistor in real time. This will provide the basic input parameters for subsequent loss calculation and solve the technical problem that the lack of real-time electrical quantities will prevent the power loss from being dynamically updated.

[0073] Furthermore, in order to convert the original electrical quantities into the excitation values ​​required by the thermal model, the insulated gate bipolar transistor loss model is used to calculate the conduction loss and switching loss separately, which yields a standardized loss decomposition method. This can solve the technical problem that empirical estimation or fixed loss values ​​cannot reflect time-varying operating conditions.

[0074] Furthermore, in order to quantify the energy consumption during the conduction phase, conduction loss needs to be calculated. This is usually based on the formulas for threshold voltage, conduction resistance, average current, and effective current. This yields the dynamic value of conduction loss as the load changes, which can solve the technical problem of underestimating loss due to neglecting the nonlinearity of conduction voltage drop.

[0075] Finally, in order to quantify the energy consumption of the switching transient, the switching loss needs to be calculated. It is usually based on the product of the single turn-on energy consumption, the turn-off energy consumption and the switching frequency, and a correction factor is introduced. The conduction loss and the switching loss are summed as the real-time power loss, which can obtain a value that fully reflects the total heat generation power. This can solve the technical problem of inaccurate heat input caused by only considering conduction loss or switching loss.

[0076] For example, taking the Infineon FF600R12ME4 insulated-gate bipolar transistor as an example, this insulated-gate bipolar transistor operates in an inverter with a switching frequency f=5kHz. The collector current is collected in real time. =120A, collector-emitter voltage =1.8V, casing temperature =85℃. Conductive loss is calculated using the formula... = × + × Threshold voltage =0.9V, on-resistance =0.0075Ω, average current =60A, =85A, therefore... =0.9×60+0.0075×85 2 =54 + 54.2 = 108.2W. Switching losses are based on the datasheet's single-cycle power consumption. =15mJ, shutdown energy consumption =12mJ, correction factor k=1.1, therefore... =(0.015+0.012)×5000×1.1=148.5W. Real-time power loss P= + =256.7W.

[0077] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0078] In summary, this step provides a dynamic and accurate power input excitation for the fractional-order thermal network model by real-time acquisition of collector current, collector-emitter voltage, and switching frequency, and by calculating the sum of conduction and switching losses using an insulated-gate bipolar transistor (IGBT) loss model. Compared with existing technologies, this method of calculating losses in real time based on electrical quantities can reflect the impact of load abrupt changes and switching frequency variations on the heating power, overcoming the shortcomings of relying on static manual curves or constant loss assumptions that cannot track real operating conditions. It also solves the core problem of junction temperature estimation deviating from actual values ​​due to inaccurate power input.

[0079] S500: Input the real-time power loss into the fractional-order thermal network differential equation composed of the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional order, solve to obtain the real-time junction-shell temperature difference, and calculate the estimated value of the real-time junction temperature based on the operating temperature. In this embodiment of the application, in the scenario where the real-time power loss value has been obtained, in order to substitute the power loss into the fractional-order thermal network differential equation to obtain the real-time junction-shell temperature difference and thus obtain the junction temperature estimate, it is necessary to use the discrete scheme and explicit difference method to numerically solve the fractional-order differential equation, and to accumulate the historical power loss with power-law weights to reflect the long memory characteristics of heat diffusion, so as to solve the technical problems that the fractional-order differential equation is difficult to solve directly in the embedded controller and that the transient junction temperature estimation is distorted due to ignoring the historical power accumulation effect.

[0080] In this embodiment of the application, step S500 of the method provided in this embodiment includes: The fractional-order thermal network differential equation is solved using a combination of discrete schemes and explicit difference methods. Historical power loss values ​​from all past moments are accumulated with power-law weights and added to the current temperature response calculation. A detailed explanation follows: Discrete format refers to splitting a continuous fractional differential equation into a series of discrete time-point algebraic equations along the time axis with a fixed step size h, so that a digital processor can calculate the temperature difference value time by time.

[0081] The explicit difference method is a numerical solution strategy in which the temperature difference at the current moment is directly calculated from the known data of the previous moment and even earlier moments through formulas, without the need for a system of simultaneous equations, and the calculation speed is fast.

[0082] Power-law weighting refers to multiplying historical power loss values ​​by a power-law decay coefficient when accumulating them. Its mathematical expression is: = C( ,j), where j is the historical time number, α is the fractional order, C( ,j) are binomial coefficients. The absolute value of the weight decreases as j increases, and the more distant the history, the smaller its impact on the current temperature.

[0083] In this step, in order to transform the continuous fractional differential equation into algebraic operations that can be executed by a digital processor and accurately describe the long-memory characteristics of heat diffusion, it is necessary to use a combination of discrete scheme and explicit difference method to solve the fractional thermal network differential equation. The historical power loss values ​​of all past moments are accumulated into the temperature response calculation at the current moment with power-law weights. This yields an efficient recursive algorithm suitable for embedded real-time systems that reflects the effect of historical heat accumulation. This solves the technical problems that the continuous fractional equation cannot be directly calculated and that the transient junction temperature estimation is distorted due to ignoring historical power contributions.

[0084] In this embodiment of the application, step S500 of the method provided in this embodiment of the application further includes: The solution process of the fractional-order thermal network differential equation is deployed on a digital signal processor or field-programmable gate array, wherein the short-memory principle is used to truncate the discrete scheme, and the memory window length is adaptively adjusted according to the thermal time constant distribution of the target insulated gate bipolar transistor. A detailed explanation follows: A digital signal processor (DSP) is a microprocessor specifically designed for real-time digital signal processing. It features fast multiplication and addition operations and rapid interrupt response, making it suitable for running algorithms for solving fractional differential equations.

[0085] A Field Programmable Gate Array (FPGA) is a reconfigurable logic chip capable of performing a large number of simple computations in parallel, used to accelerate computationally intensive tasks such as power-law weight accumulation.

[0086] The short memory principle states that when discretizing fractional derivatives, only the data from the most recent L historical moments are retained for accumulation, while the contributions of earlier historical moments are approximately zero. This effectively truncates the infinite memory into a finite length, significantly reducing storage and computational costs.

[0087] Thermal time constant distribution refers to the numerical range of thermal time constants for the chip layer, solder layer, and substrate layer of an insulated gate bipolar transistor. The chip layer is in the millisecond range, while the substrate layer can reach tens of seconds, with a wide distribution range.

[0088] Adaptive adjustment of memory window length refers to dynamically setting the short memory window length L based on the current thermal time constant distribution. Short windows are used for rapidly changing layers to speed up the response, while long windows are used for slowly changing layers to avoid truncation errors. In this step, in order to solve the fractional-order thermal network differential equations in real time on a digital signal processor or field-programmable gate array with limited resources, the short memory principle is used to truncate the discrete format and adaptively adjust the memory window length according to the thermal time constant distribution of the target insulated gate bipolar transistor. This can significantly reduce the storage and computation burden while maintaining acceptable accuracy in engineering, and can solve the technical problems of memory overflow and computation timeout caused by infinitely long historical accumulation in embedded platforms.

[0089] For example, taking the Infineon FF600R12ME4 insulated-gate bipolar transistor as an example, the real-time power loss of this insulated-gate bipolar transistor, P=256.7W, is used as the input. The time step h=0.001s, the memory window length L=5000 steps, corresponding to 5s of historical data. Explicit difference and Grünwald-Letnikov discrete schemes are used to solve the fractional differential equations of the chip layer. The historical power is accumulated with power-law weights, and the weighting coefficients are... = C( ,j), where =0.72. Current chip layer temperature difference. =0.022K, solder layer temperature difference =0.015K, substrate temperature difference =0.35K, Summary—Shell Temperature Difference =0.022 + 0.015 + 0.35 = 0.387 K. Measured shell temperature. =85℃, estimated real-time junction temperature = + =85 + 0.387 = 85.387℃. Repeat this calculation every 1ms to form a continuous junction temperature monitoring stream.

[0090] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0091] In summary, this step achieves efficient recursive solution of the fractional-order thermal network differential equations by jointly solving the discrete scheme and the explicit difference method, and by accumulating historical power losses with power-law weights into the current temperature difference calculation. Compared with existing technologies, the explicit difference method avoids the iterative solution of the implicit scheme, and the power-law accumulation accurately characterizes the long-memory characteristics of heat diffusion. It overcomes the shortcomings of traditional integer-order models that ignore the historical power accumulation effect, resulting in large transient response deviations, and solves the technical problem that fractional-order differential equations are difficult to deploy in embedded real-time systems due to computational complexity.

[0092] S600: Based on the real-time junction temperature estimate, perform hotspot identification to obtain hotspot status information.

[0093] In this embodiment of the application, in the scenario where a real-time junction temperature estimate has been obtained, in order to identify the location and aging degree of hot spots inside the insulated gate bipolar transistor, it is necessary to monitor the time evolution trajectory of the equivalent thermal resistance parameters of the chip layer, solder layer and substrate layer, and output a layered warning based on whether the thermal resistance of each layer increases monotonically for multiple consecutive cycles and the cumulative magnitude exceeds the corresponding threshold, so as to solve the technical problems that a single junction temperature value cannot distinguish which physical layer the hot spot comes from and cannot achieve early warning of aging.

[0094] In this embodiment of the application, step S600 of the method provided in this embodiment includes: When the multi-layer fractional thermal network model is used, the time evolution trajectory of the layer equivalent thermal resistance parameter corresponding to each physical layer is monitored. If the equivalent thermal resistance parameter of the chip layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the first preset threshold, a chip layer thermal aging warning will be output. If the equivalent thermal resistance parameter of the solder layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the second preset threshold, a solder layer thermal aging warning will be output. If the equivalent thermal resistance parameter of the substrate layer monotonically increases over multiple consecutive monitoring cycles and the cumulative increase exceeds a third preset threshold, a substrate layer thermal aging warning will be issued. A detailed explanation follows: In this embodiment of the application, the time evolution trajectory refers to the sequence formed by recording the equivalent thermal resistance values ​​obtained after each identification or correction in chronological order, such as... =0.048K / W, 0.051K / W, and 0.054K / W are used to analyze the trend of thermal resistance change.

[0095] The monitoring cycle refers to the time interval between two consecutive records of the equivalent thermal resistance parameter, such as once every 100 hours of operation, usually in hours or operating hours.

[0096] Monotonic increase means that in multiple consecutive monitoring cycles, the thermal resistance value recorded in each subsequent record is greater than the value recorded in the previous record. A slight fluctuation of no more than 0.5% due to measurement noise is allowed and is considered to be flat.

[0097] The cumulative increase refers to the percentage increase of the current thermal resistance value relative to the initial baseline value. The calculation formula is (current value - initial value) / initial value × 100%, which is used to determine whether the warning threshold has been exceeded.

[0098] Thermal aging warning refers to the prompt information output when the equivalent thermal resistance of a physical layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the corresponding preset threshold, indicating that the layer may undergo thermal degradation.

[0099] In this step, in order to achieve physical layer tracking of hot spots, it is necessary to monitor the time evolution trajectory of the equivalent thermal resistance parameters of the chip layer, solder layer and substrate layer respectively. This will provide the sequence data of the thermal resistance of each layer changing over time, which can solve the technical problem of not being able to distinguish which layer the thermal aging originates from.

[0100] Furthermore, in order to provide a specific early warning for chip layer thermal aging, a chip layer thermal aging warning should be output when the equivalent thermal resistance of the chip layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the first preset threshold. This provides an early alarm for chip layer degradation and can solve the problem of chip-level faults being difficult to identify individually.

[0101] Finally, in order to provide specific early warning for the thermal aging of the solder layer and the substrate layer, an early warning for the thermal aging of the solder layer should be output when the equivalent thermal resistance of the solder layer meets the condition of monotonically increasing and the cumulative increase exceeds the second preset threshold, and an early warning for the thermal aging of the substrate layer should be output when the equivalent thermal resistance of the substrate layer meets the condition of monotonically increasing and the cumulative increase exceeds the third preset threshold. This allows for a layer-by-layer independent early warning mechanism, which can solve the problem of difficulty in diagnosing the cross-effect of aging of different physical layers.

[0102] For example, taking the Infineon FF600R12ME4 insulated-gate bipolar transistor as an example, the time evolution trajectory of the equivalent thermal resistance of each layer was continuously monitored. The monitoring cycle was once every 100 hours of operation, and five data points were recorded consecutively. The initial thermal resistance of the chip layer R1 was 0.048 K / W, the first time was 0.049 K / W, the second time was 0.051 K / W, the third time was 0.054 K / W, the fourth time was 0.058 K / W, and the fifth time was 0.063 K / W, showing a monotonically increasing trend for five consecutive times, with a cumulative increase of 31.3%. The initial thermal resistance of the solder layer R2 was 0.028 K / W, and the five measured values ​​were 0.028, 0.029, 0.028, 0.030, and 0.029, without showing a monotonically increasing trend. The initial R3 of the substrate layer was 0.16 K / W. Five measurements showed no change: 0.16, 0.16, 0.16, 0.16, 0.16. The chip layer aging threshold was set to 25%. The actual cumulative increase was 31.3%, exceeding the threshold, triggering a chip layer thermal aging warning. The solder layer and substrate layer did not exceed their thresholds, so no warning was issued.

[0103] It should be noted that the above values ​​are for illustrative purposes only and do not constitute a limitation on this application.

[0104] In summary, this step monitors the temporal evolution of the equivalent thermal resistance of the chip layer, solder layer, and substrate layer, and outputs a layered thermal aging warning based on whether the thermal resistance of each layer increases monotonically over multiple cycles and the cumulative amplitude exceeds the corresponding threshold. This achieves physical layer localization and proactive diagnosis of hotspot locations. Compared with existing technologies, layered monitoring can distinguish whether thermal aging originates from the chip, solder, or substrate. The cumulative amplitude and monotonic trend judgment avoid false alarms caused by instantaneous fluctuations, and overcomes the shortcomings of traditional junction temperature monitoring, which only provides a single temperature value and cannot determine the root cause of the fault. This solves the technical problem of blind maintenance decisions and high costs due to the inability to locate hotspots.

[0105] Example 2, as shown in the appendix Figure 2 As shown, based on the inventive concept of the IGBT hotspot identification method based on transient thermal resistance curves provided in Embodiment 1, this application also provides an IGBT hotspot identification system based on transient thermal resistance curves, specifically including: Curve loading module 11 is used to load the junction-case transient thermal impedance curve from the datasheet of the target insulated gate bipolar transistor; Model building module 12 is used to build a fractional-order thermal network model based on the junction-shell transient thermal impedance curve. The fractional-order thermal network model includes equivalent thermal resistance parameters, equivalent heat capacity parameters, and fractional order. The parameter identification module 13 is used to perform parameter identification based on the fractional-order thermal network model and the junction-shell transient thermal resistance curve to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order. The real-time acquisition and calculation module 14 is used to acquire the electrical quantities and operating temperature of the target insulated gate bipolar transistor in real time and calculate the real-time power loss. Junction temperature calculation module 15 is used to input the real-time power loss into the fractional-order thermal network differential equation composed of the identified parameters, solve for the real-time junction-shell temperature difference, and calculate the estimated value of the real-time junction temperature based on the operating temperature. Hotspot identification module 16 is used to perform hotspot identification based on the real-time junction temperature estimation value to obtain hotspot status information.

[0106] In one embodiment, the model building module 12 is further configured to: establish fractional-order sub-models for the chip layer, solder layer and substrate layer of the target insulated gate bipolar transistor, and cascade the fractional-order sub-models to obtain a multi-layer fractional-order thermal network model, wherein each fractional-order sub-model includes the layer equivalent thermal resistance parameter, layer equivalent thermal capacity parameter and layer fractional order of the corresponding layer.

[0107] In one embodiment, the parameter identification module 13 is further configured to: execute an offline calibration mode when only the datasheet of the target insulated gate bipolar transistor can be obtained and actual measurement conditions are not available. Extract the junction-shell transient thermal resistance curve from the datasheet; A combined error objective function for amplitude and phase is constructed, and a system constraint term is introduced into the combined error objective function. The system constraint term assigns different weights to the thermal impedance prediction error in the short time interval and the long time interval, respectively. A swarm intelligence optimization algorithm is used to search for the global optimal solution. During the search process, the positive definiteness of the equivalent thermal resistance parameter, the positive definiteness of the equivalent heat capacity parameter, and the physical validity of the fractional order are used as hard constraints.

[0108] Furthermore, the parameter identification module 13 is also used to: execute an adaptive identification mode when transient thermal impedance measurement conditions are available. The measured transient thermal impedance curve of the target insulated gate bipolar transistor was obtained by electrical measurement method; Based on the measured transient thermal impedance curve, an initial identification is performed to obtain the reference equivalent thermal resistance parameter, the reference equivalent heat capacity parameter, and the reference fractional order. In subsequent monitoring cycles, the deviations between each newly measured transient thermal impedance curve and the reference thermal impedance curve corresponding to the reference equivalent thermal resistance parameter, the reference equivalent thermal capacity parameter, and the reference fractional order are iteratively corrected using the regularized least squares method to obtain the updated equivalent thermal resistance parameter, the updated equivalent thermal capacity parameter, and the updated fractional order. At the same time, the time evolution trajectory of the updated equivalent thermal resistance parameter is continuously recorded.

[0109] Furthermore, the parameter identification module 13 is also used to: execute an online interactive mode when the target insulated gate bipolar transistor is operating under time-varying power loss conditions. Based on a pre-defined baseline fractional-order thermal network model, the theoretical shell temperature response under the current power loss is calculated. The actual shell temperature is collected in real time, and the continuous deviation between the theoretical shell temperature response and the actual shell temperature is calculated. When the continuous deviation exceeds the preset threshold, the real-time junction temperature estimation based on the benchmark fractional-order thermal network model is paused, and the equivalent thermal resistance parameter, the equivalent heat capacity parameter, and the fractional order are updated online through reverse heat conduction calculation using the measurement data of the built-in negative temperature coefficient thermistor.

[0110] In one embodiment, the real-time acquisition and calculation module 14 is further configured to: calculate the sum of conduction loss and switching loss using an insulated gate bipolar transistor loss model based on the real-time acquired collector current, collector-emitter voltage and switching frequency, as the real-time power loss.

[0111] In one embodiment, the junction temperature solution module 15 is further configured to: solve the fractional-order thermal network differential equation using a discrete scheme and an explicit difference method, wherein the historical power loss values ​​of all past moments are accumulated into the temperature response calculation at the current moment with power-law weights.

[0112] Furthermore, the junction temperature solving module 15 is also used to: deploy the solution process of the fractional-order thermal network differential equation on a digital signal processor or field-programmable gate array, wherein the short memory principle is used to truncate the discrete format and the memory window length is adaptively adjusted according to the thermal time constant distribution of the target insulated gate bipolar transistor.

[0113] In one embodiment, the hotspot identification module 16 is further configured to: When the multi-layer fractional thermal network model is used, the time evolution trajectory of the layer equivalent thermal resistance parameter corresponding to each physical layer is monitored. If the equivalent thermal resistance parameter of the chip layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the first preset threshold, a chip layer thermal aging warning will be output. If the equivalent thermal resistance parameter of the solder layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the second preset threshold, a solder layer thermal aging warning will be output. If the equivalent thermal resistance parameter of the substrate layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the third preset threshold, a thermal aging warning for the substrate layer will be output.

[0114] This application provides an IGBT hotspot identification system based on transient thermal resistance curves. This system enables intelligent thermal monitoring in scenarios such as daily operation and maintenance of power electronic equipment, aging condition assessment, and thermal anomaly early warning. The monitoring process involves loading transient thermal resistance curves, multi-level fractional-order modeling, three-mode adaptive parameter identification, and hierarchical thermal aging early warning. It can be integrated into equipment health management systems or condition monitoring platforms, effectively improving the accuracy and location capability of thermal anomaly identification, reducing the risk of unplanned downtime due to overheating, and ensuring the accuracy and model adaptability of junction temperature monitoring during long-term operation. For the specific workflow and optimization details of this system, please refer to Example 1.

[0115] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

Claims

1. An IGBT hot spot recognition method based on transient thermal resistance curve, characterized in that, include: The junction-to-case transient thermal impedance curve from the datasheet of the target insulated gate bipolar transistor; Based on the junction-shell transient thermal impedance curve, a fractional-order thermal network model of the target insulated gate bipolar transistor is constructed, wherein the fractional-order thermal network model includes equivalent thermal resistance parameters, equivalent thermal capacity parameters, and fractional order. Based on the fractional-order thermal network model and the junction-shell transient thermal impedance curve, parameter identification is performed to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order. Real-time acquisition of electrical quantities and operating temperature of the target insulated gate bipolar transistor, and calculation of real-time power loss; The real-time power loss is input into the fractional-order thermal network differential equation composed of the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order parameter. The real-time junction-shell temperature difference is obtained by solving the equation, and the estimated real-time junction temperature is calculated based on the operating temperature. Based on the estimated real-time junction temperature, hotspot identification is performed to obtain hotspot status information.

2. The method of claim 1, wherein, Constructing a fractional-order thermal network model of the target insulated-gate bipolar transistor includes: Fractional-order sub-models are established for the chip layer, solder layer and substrate layer of the target insulated gate bipolar transistor, and the fractional-order sub-models are cascaded to obtain a multi-layer fractional-order thermal network model, wherein each fractional-order sub-model includes the layer equivalent thermal resistance parameter, layer equivalent thermal capacity parameter and layer fractional order of the corresponding layer.

3. The method of claim 1, wherein, Perform parameter identification to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional order, including: When only the datasheet of the target insulated-gate bipolar transistor is available and actual testing conditions are not available, execute the offline calibration mode: Extract the junction-shell transient thermal impedance curve from the datasheet; A combined error objective function for amplitude and phase is constructed, and a system constraint term is introduced into the combined error objective function. The system constraint term assigns different weights to the thermal impedance prediction error in the short time interval and the long time interval, respectively. A swarm intelligence optimization algorithm is used to search for the global optimal solution. During the search process, the positive definiteness of the equivalent thermal resistance parameter, the positive definiteness of the equivalent heat capacity parameter, and the physical validity of the fractional order are used as hard constraints.

4. The method of claim 1, wherein, Perform parameter identification to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional order, including: When transient thermal impedance measurement conditions are available, the adaptive identification mode is executed: The measured transient thermal impedance curve of the target insulated gate bipolar transistor was obtained by electrical measurement method; Based on the measured transient thermal impedance curve, an initial identification is performed to obtain the reference equivalent thermal resistance parameter, the reference equivalent heat capacity parameter, and the reference fractional order. In subsequent monitoring cycles, the deviations between each newly measured transient thermal impedance curve and the reference thermal impedance curve corresponding to the reference equivalent thermal resistance parameter, the reference equivalent thermal capacity parameter, and the reference fractional order are iteratively corrected using the regularized least squares method to obtain the updated equivalent thermal resistance parameter, the updated equivalent thermal capacity parameter, and the updated fractional order. At the same time, the time evolution trajectory of the updated equivalent thermal resistance parameter is continuously recorded.

5. The method of claim 1, wherein, Perform parameter identification to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional order, and also include: When the target insulated gate bipolar transistor operates under time-varying power loss conditions, the online interactive mode is executed: Based on a pre-defined baseline fractional-order thermal network model, the theoretical shell temperature response under the current power loss is calculated. The actual shell temperature is collected in real time, and the continuous deviation between the theoretical shell temperature response and the actual shell temperature is calculated. When the continuous deviation exceeds the preset threshold, the real-time junction temperature estimation based on the benchmark fractional-order thermal network model is paused, and the equivalent thermal resistance parameter, the equivalent heat capacity parameter, and the fractional order are updated online through reverse heat conduction calculation using the measurement data of the built-in negative temperature coefficient thermistor.

6. The method of claim 1, wherein, The real-time junction-shell temperature difference is obtained by solving for: The fractional-order thermal network differential equation is solved by a combination of discrete scheme and explicit difference method, wherein the historical power loss values ​​of all past moments are accumulated into the temperature response calculation at the current moment with power-law weights.

7. The method of claim 2, wherein, Perform hotspot identification to obtain the hotspot status information, including: When the multi-layer fractional thermal network model is used, the time evolution trajectory of the layer equivalent thermal resistance parameter corresponding to each physical layer is monitored. If the equivalent thermal resistance parameter of the chip layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the first preset threshold, a chip layer thermal aging warning will be output. If the equivalent thermal resistance parameter of the solder layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the second preset threshold, a solder layer thermal aging warning will be output. If the equivalent thermal resistance parameter of the substrate layer increases monotonically over multiple consecutive monitoring cycles and the cumulative increase exceeds the third preset threshold, a thermal aging warning for the substrate layer will be output.

8. The method of claim 1, wherein, Also includes: The solution process of the fractional-order thermal network differential equation is deployed on a digital signal processor or field-programmable gate array, wherein the short memory principle is used to truncate the discrete scheme and the memory window length is adaptively adjusted according to the thermal time constant distribution of the target insulated gate bipolar transistor.

9. The method of claim 1, wherein, Calculate real-time power loss, including: Based on the real-time collected collector current, collector-emitter voltage, and switching frequency, the sum of conduction loss and switching loss is calculated using the insulated gate bipolar transistor loss model, and is taken as the real-time power loss.

10. An IGBT hot spot identification system based on transient thermal resistance curve, characterized in that, The system is used to perform the method according to any one of claims 1-9, the system comprising: Curve loading module, used to load the junction-case transient thermal impedance curve from the datasheet of the target insulated gate bipolar transistor; The model building module is used to construct a fractional-order thermal network model based on the junction-shell transient thermal impedance curve. The fractional-order thermal network model includes equivalent thermal resistance parameters, equivalent heat capacity parameters, and fractional order. The parameter identification module is used to perform parameter identification based on the fractional-order thermal network model and the junction-shell transient thermal impedance curve to obtain the identified equivalent thermal resistance parameter, the identified equivalent heat capacity parameter, and the identified fractional-order order. The real-time acquisition and calculation module is used to acquire the electrical quantities and operating temperature of the target insulated gate bipolar transistor in real time and calculate the real-time power loss. The junction temperature calculation module is used to input the real-time power loss into the fractional-order thermal network differential equation composed of the identified parameters, solve for the real-time junction-shell temperature difference, and calculate the estimated value of the real-time junction temperature based on the operating temperature. The hotspot identification module is used to perform hotspot identification based on the real-time junction temperature estimation value and obtain hotspot status information.

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