A Scalable Hardware Accelerator for Neural Networks Based on FPGA

Abstract

This invention provides a scalable hardware accelerator for neural networks based on FPGA, comprising a storage module, a computing module, and a control module. The storage module includes a preset parameter storage area and an intermediate feature map storage area. The preset parameter storage area stores convolutional weight parameters, bias parameters, and computation instruction sequences. The intermediate feature map storage area stores feature map data generated by each layer of the neural network, employing a multi-bank parallel feature map storage structure to achieve parallel access to intermediate feature map data through the collaborative work of multiple banks. The computing module includes a large-scale parallel computing unit array for convolutional neural network computation, achieving high-speed execution of convolution operations through the collaborative work of multiple parallel computing units. The control module performs timing control on convolutional kernel loading, bias loading, feature map reading, and computation instruction sequence execution. This invention improves computational efficiency while enhancing the system's flexibility and scalability.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence computing technology, and in particular to a scalable hardware accelerator for neural networks based on FPGA. Background Technology

[0002] With the rapid development of artificial intelligence technology, neural networks have become a crucial technological foundation in fields such as computer vision, speech recognition, and natural language processing. The introduction of convolutional neural networks (CNNs) effectively solved the problems existing in traditional neural networks when processing grid-structured data such as images. Convolutional layers achieve feature extraction through local receptivity and weight sharing mechanisms, significantly reducing the number of network parameters while maintaining expressive power. With the development of CNNs, various deep network structures have emerged, such as ResNet and DenseNet. These structures improve the expressive power of deep networks through cross-layer connections or feature concatenation. However, while improving model performance, these structures also further increase computational load and data transmission requirements, placing higher demands on computing platforms.

[0003] In the actual deployment of neural networks, the central processing unit (CPU) has limited parallel computing capabilities, making it difficult to meet the real-time requirements when processing large-scale neural networks. While graphics processing units (GPUs) possess strong parallel computing capabilities, their high power consumption and large size limit their application in edge devices or embedded systems. Application-specific integrated circuits (ASICs) offer high performance and energy efficiency, but their long development cycles, high costs, and difficulty in adapting to rapidly evolving neural network model structures limit their use. In contrast, field-programmable gate arrays (FPGAs) offer reconfigurability, high parallelism, low power consumption, and low latency, enabling customized designs based on specific neural network models, thus gradually becoming an important implementation platform for neural network hardware acceleration. However, some problems still exist in existing FPGA neural network accelerator designs. For example, the massive amount of intermediate feature map data makes it difficult for traditional BRAM-based storage structures to provide sufficient bandwidth; cross-layer connection operations in complex network structures require frequent data transfers, increasing system latency; furthermore, the constantly evolving neural network model structures place higher demands on the scalability and flexibility of the hardware architecture. Summary of the Invention

[0004] The present invention aims to design a flexible, scalable, and data-access-efficient neural network hardware accelerator to improve the execution efficiency of neural networks on FPGA platforms and adapt to neural network models of different sizes and structures.

[0005] This invention proposes a scalable hardware accelerator for neural networks based on FPGA, comprising a storage module, a computing module, and a control module. The storage module includes a preset parameter storage area and an intermediate feature map storage area. The preset parameter storage area stores convolution weight parameters, bias parameters, and computation instruction sequences. The intermediate feature map storage area stores feature map data generated by each layer of the neural network, employing a multi-bank parallel feature map storage structure to achieve parallel access to intermediate feature map data through the collaborative work of multiple banks. The computing module includes a large-scale parallel computing unit array for convolutional neural network computation, achieving high-speed execution of convolution operations through the collaborative work of multiple parallel computing units. The control module performs timing control on convolution kernel loading, bias loading, feature map reading, and computation instruction sequence execution.

[0006] Optionally, the storage module further includes an input / output data storage area, which is used to realize data interaction between the FPGA and the host computer.

[0007] Optionally, the multi-bank parallel feature map storage structure includes at least four banks, which form a unified feature map storage pool through a data cross-access network to support the parallel reading of multiple feature map data during convolution calculation.

[0008] Optionally, the multi-bank parallel feature map storage structure introduces a channel transformation and multi-bank synchronous reading mechanism to directly read data from different banks in parallel during cross-layer connection or feature splicing, and completes channel rearrangement at the hardware layer.

[0009] Optionally, the computing module implements continuous processing of feature map data in a pipeline manner.

[0010] Optionally, the calculation module includes a sliding window generation unit and a multiply-accumulate calculation unit; The sliding window generation unit constructs a convolutional window using a row cache structure; The multiply-add calculation unit implements convolution operations through multiple parallel multipliers and adders.

[0011] Optionally, the convolution calculation is divided into a multi-stage pipeline structure so that the computing array outputs a new convolution result in each clock cycle.

[0012] This invention also provides an FPGA-based method for accelerating neural network computation. This method is used in the aforementioned FPGA-based scalable hardware accelerator for neural networks, and includes the following steps: After the FPGA system is powered on, the neural network weight parameters, bias parameters, and control instructions are automatically loaded into the preset parameter storage area of ​​the storage module. The control module reads and parses the control commands; Load the corresponding parameters based on the parsing results and start the calculation module to perform convolution calculation; Write the calculation results into the intermediate feature map storage area; Repeat the instructions until all neural network computation tasks are completed, and output the computation results.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the aforementioned FPGA-based neural network accelerated computing method.

[0014] The present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, characterized in that the computer program, when executed by a processor, implements the FPGA-based neural network accelerated computing method as described in claim 8.

[0015] The FPGA-based scalable hardware accelerator for neural networks and the FPGA-based accelerated computing method for neural networks provided by this invention achieve high parallel computing, efficient data access, and flexible instruction control in the neural network computing process through the collaborative design of computing architecture, data storage structure, and control scheduling mechanism. This effectively improves the computing performance and resource utilization efficiency of neural network models on the FPGA platform, and enhances the system's adaptability and scalability among neural network models of different scales. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is an overall structural diagram of the FPGA-based scalable hardware accelerator for neural networks provided by this invention.

[0018] Figure 2 This is a schematic diagram of the structure of an embodiment of the intermediate feature map storage area in the storage module of the FPGA-based neural network scalable hardware accelerator provided by the present invention.

[0019] Figure 3 yes Figure 2 The diagram shows the design of a Bank within the intermediate feature map storage area mentioned earlier.

[0020] Figure 4This is a schematic diagram of an embodiment of the computing module in the FPGA-based neural network scalable hardware accelerator provided by the present invention.

[0021] Figure 5 This is a schematic diagram of an embodiment of constructing a spatial sliding window in the computing module of the FPGA-based neural network scalable hardware accelerator provided by the present invention.

[0022] Figure 6 This is a schematic diagram of an embodiment of the control module in the FPGA-based scalable hardware accelerator for neural networks provided by the present invention, used to implement the operation scheduling of the entire accelerator system.

[0023] Figure 7 This is a flowchart of the FPGA-based scalable hardware accelerator for neural networks provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] This invention proposes a scalable hardware accelerator for neural networks based on FPGA, such as... Figure 1 The diagram includes a storage module 1, a computation module 2, and a control module 3. The storage module 1 includes a preset parameter storage area 11 and an intermediate feature map storage area 12. The preset parameter storage area 11 is used to store convolution weight parameters, bias parameters, and computation instruction sequences. The intermediate feature map storage area 12 is used to store feature map data generated by each layer of the neural network. It adopts a multi-bank parallel feature map storage structure, which enables parallel access to intermediate feature map data through the collaborative work of multiple banks. The computation module includes a large-scale parallel computing unit array for convolutional neural network computation, which enables high-speed execution of convolution operations through the collaborative work of multiple parallel computing units. The control module performs timing control on convolution kernel loading, bias loading, feature map reading, and computation instruction sequence execution.

[0026] This invention employs a multi-bank parallel feature map storage structure to support synchronous read operations, thereby meeting the data access requirements of complex network structures such as convolutional computation and cross-layer connections. Each storage bank can complete read and write operations simultaneously within the same clock cycle, significantly improving the bandwidth of feature map data access and effectively alleviating the bandwidth bottleneck caused by frequent data access during convolutional neural network computation.

[0027] The aforementioned FPGA-based scalable hardware accelerator for neural networks adopts a modular architecture. Each functional module is connected through standardized interfaces, thereby improving the system's scalability and reconfigurability. The accelerator's internal data path uses a lightweight data protocol for transmission. This protocol mainly includes quantized feature map data, spatial coordinate information, and valid data signals, thus ensuring data integrity while reducing data parsing overhead and improving data transmission efficiency. The storage module, computing module, and control module work collaboratively through an on-chip data path to jointly complete the neural network inference computation task. Specifically, the storage module stores various types of data required during neural network operation, including convolution kernel weight parameters, bias parameters, control commands, input data, and intermediate feature map data generated during computation. The computing module implements hardware-accelerated computation of neural network operators, including convolution operations, channel accumulation, and related data processing operations in convolutional and recurrent neural networks. The control module performs unified scheduling of the entire accelerator through an instruction-driven approach, responsible for parsing control commands and coordinating data transmission and computation processes between modules, thereby achieving the orderly execution of neural network computation tasks.

[0028] As one specific implementation, the preset parameter storage area is implemented based on the FPGA's on-chip Block RAM resources and instantiated using Xilinx Parameterized Macros (XPM) primitives. This parameterized design approach allows for flexible configuration of the memory depth and data bit width within the hardware description language, thereby improving the reusability of the hardware design. During system deployment, the neural network model first undergoes training and quantization in the host computer environment. Subsequently, software tools convert the quantized weight parameters and bias parameters into an initialization file. When the FPGA system powers on, the initialization file is automatically loaded into the corresponding Block RAM storage area, thus completing the pre-configuration of the neural network model parameters. This method avoids frequent loading of model parameters during operation, thereby reducing communication latency and improving system startup efficiency.

[0029] By defining parameterized instruction fields, the system achieves unified scheduling of operations such as convolution calculation, data reading, and data writing back, enabling it to flexibly adapt to neural network models of different sizes and structures, while expanding system functionality without changing the underlying hardware structure.

[0030] As a specific implementation method, to enhance the scalability of the system, this invention designs a parameterized instruction set structure. This instruction set adopts a fixed-length binary encoding format, containing multiple fields such as computation operation type, feature map size, convolution kernel parameters, and data read / write control. The bit width of each field and its position in the instruction word are parameterized through macro definitions, allowing for flexible adjustment of the instruction structure without changing the underlying control logic, thereby supporting the computational needs of neural network models of different scales.

[0031] As one specific implementation, the intermediate feature map storage area is constructed using the FPGA's internal Ultra RAM resources and employs a multi-bank parallel storage architecture. For example... Figure 2 As shown, this module is designed with a four-bank storage structure, each bank having an independent read / write interface. These banks form a unified feature map storage pool through a data cross-network, supporting the parallel reading of multiple feature map data during convolution computation. This structure supports single-bank writes and multi-bank parallel reads, enabling convolution computation and cross-layer connection computation to complete data access within the same clock cycle, thereby effectively improving storage bandwidth utilization. Furthermore, as... Figure 3 As shown, each Bank is constructed using multiple cascaded URAM primitives to meet the storage requirements of high-channel feature map data. Simultaneously, address generation logic is implemented in the storage module to automatically calculate the physical storage address based on the spatial coordinates of the input feature map, thus establishing a mapping relationship between the spatial coordinates of the feature map and the physical address. Furthermore, a channel exchange mechanism is designed in the data reading path. When performing cross-layer feature concatenation operations, the order of data output from different Banks can be rearranged by configuring control signals, enabling the correct combination of feature maps from different network layers along the channel dimension. This avoids additional data handling operations and improves system efficiency.

[0032] The multi-bank parallel feature map storage structure introduces a channel transformation and multi-bank synchronous reading mechanism to directly read data from different banks in parallel during cross-layer connection or feature splicing, and completes channel rearrangement at the hardware layer.

[0033] The storage module is used to store and manage various types of data during the operation of the neural network. In addition to the aforementioned preset parameter storage area and intermediate feature map storage area, it also includes an input / output data storage area. This input / output data storage area is used to realize data interaction between the FPGA and the host computer. Different storage areas meet the bandwidth requirements of different data access modes during neural network computation and reduce storage access conflicts. The input / output data storage area includes functions such as writing input feature map data and outputting inference results. As a specific implementation, such as... Figure 1As shown, the storage structure in this region is also implemented based on the FPGA's internal Block RAM resources and establishes a data communication channel with the host computer through a high-speed PCIe interface. In this embodiment, the system uses the Xilinx XDMA IP core as a PCIe communication bridge, converting the PCIe interface into an AXI bus interface, enabling the host computer to perform high-speed read and write operations on the FPGA's internal memory via Direct Memory Access (DMA). During operation, the host computer first writes the input feature map data into the FPGA's internal storage area through the PCIe interface. The accelerator reads the data from this area and performs neural network calculations. After the calculations are completed, the results are written to the output storage area, and then the host computer reads the calculation results through the PCIe interface. This method reduces the CPU's involvement in the data transfer process, thereby significantly improving the system's data throughput.

[0034] The computing module is the core component of an FPGA-based scalable hardware accelerator for neural networks. It is primarily used to perform convolution operations and related neural network operator computations. Figure 4 As shown, the computation module adopts a parallel computing unit array structure, achieving high-speed execution of convolution operations through the collaborative work of multiple parallel processing elements (PEs). Continuous processing of feature map data is achieved through a pipelined approach. Input feature map data is transmitted between modules in row-major order, and synchronization control is achieved by combining data validity signals and spatial coordinate signals, thereby ensuring correct alignment of data in the pipeline.

[0035] To accommodate the computational needs of different convolutional structures, this module innovatively designs and utilizes a configurable data channel processing module. By performing channel duplication or channel selection on the input feature map data, it achieves unified support for both ordinary convolution and grouped convolution computation modes. Different data processing methods are designed for different types of convolutional operations.

[0036] When performing a 1×1 convolution operation, since the convolution only involves a linear combination of channel dimensions, there is no need to construct a spatial sliding window. The input feature data can be directly multiplied and accumulated with the convolution kernel weights, thereby reducing the data caching structure and lowering the complexity of the control logic.

[0037] When performing a 3×3 convolution operation, a corresponding spatial sliding window needs to be constructed. The computation module includes a sliding window generation unit and a multiply-accumulate unit; the sliding window generation unit constructs the convolution window through a row cache structure; the multiply-accumulate unit implements the convolution operation through multiple parallel multipliers and adders.

[0038] As one specific implementation, a row buffer structure based on shift registers is used to generate the sliding window, such as... Figure 5As shown, by caching the first two rows of feature map data, the input data forms a continuous 3×3 window matrix in the pipeline, thus meeting the requirements of convolution calculation. After obtaining the 3×3 convolution window, the calculation module performs multiplication operations on the window data and the convolution kernel parameters and accumulates them.

[0039] For the 3×3 convolution kernel structure commonly used in convolution operations, this implementation innovatively designs a convolution windowing buffer structure. This structure generates the sliding window data required for convolution calculation through a combination of row buffers and shift registers, enabling the corresponding convolution window to be formed in real time during the streaming of the input data stream. After obtaining the convolution window data, a multi-stage pipelined multiply-accumulate structure performs parallel multiply-accumulate operations on the window data and the convolution kernel parameters to complete the convolution calculation process. This pipelined structure shortens the critical path and improves circuit timing performance through staged accumulation, while ensuring that the computation module can maintain high throughput operation.

[0040] As a specific implementation method, in order to reduce hardware resource consumption, the computing module supports multiple quantization calculation methods, including fixed-point quantization mode and binary quantization mode.

[0041] In fixed-point quantization mode, convolution weights are represented with a fixed bit width, and multiplication-accumulation operations are implemented through the FPGA's internal DSP computing unit, thus ensuring high computational accuracy. In binary quantization mode, convolution weights only take the values ​​+1 or -1. In this mode, multiplication can be converted into a simple sign-inverting operation. Binary quantization replaces traditional multiplication with logical operations, significantly reducing hardware resource consumption, i.e., significantly reducing DSP resource usage and improving hardware resource utilization. By supporting multiple quantization modes, the accelerator can be flexibly configured according to the needs of different neural network models. While ensuring neural network computational accuracy, it reduces hardware resource consumption and improves FPGA resource utilization, enabling the accelerator to achieve a good balance between computational performance and power consumption.

[0042] To improve timing performance, the computation process is divided into a multi-stage pipeline structure. First, multiple parallel multiplication units perform multiplication operations between the window data and the convolution kernel parameters. Then, the multiplication results are grouped and summed to obtain the convolution calculation output. This pipeline structure enables the computation array to output a new convolution result every clock cycle, thereby significantly improving computational throughput.

[0043] The control module is used to manage the operation and scheduling of the entire accelerator system. As one specific implementation, such as... Figure 6As shown, the control module adopts a finite state machine-based control structure as the main control module, which performs timing control on operations such as convolution kernel loading, bias loading, feature map reading, and computation execution, thereby realizing an instruction-driven pipelined computation process. The entire control process includes multiple stages such as instruction reading, instruction decoding, parameter loading, and computation execution. Each stage is switched sequentially through a state machine to ensure the coordinated work between functional modules.

[0044] The following describes two specific scenarios.

[0045] As a specific implementation, cross-layer connections are required to achieve deep network feature fusion in convolutional neural networks. This invention implements cross-layer connections through a multi-bank parallel read structure in the storage module. When performing residual connection operations, the control module simultaneously reads feature map data from corresponding positions in two storage banks and performs element-wise addition operations through the addition unit of the computation module. When performing feature concatenation operations, by configuring the read address and channel order, feature map data from different storage banks are concatenated along the channel dimension, thus serving as input for subsequent convolutional layers.

[0046] As another specific implementation, to reduce the spatial size of feature maps and expand the receptive field in convolutional neural networks, this invention designs a storage module that supports two methods in the feature map writing path: convolutional downsampling with a stride of 2 and pooling downsampling. The convolutional downsampling with a stride of 2 is implemented through an address control mechanism in the feature map writing stage, performing data writing only when specific spatial coordinate conditions are met, thereby compressing the feature map size. For pooling downsampling, a 2×2 sliding window similar to convolution is constructed, and the maximum or average value is calculated to obtain the output result, thus achieving max pooling or average pooling functions. Through this implementation, the amount of data written can be reduced through address compression when performing downsampling-related operations, achieving automatic compression of the feature map spatial size, thereby reducing storage bandwidth usage and improving data storage efficiency.

[0047] Through the above technical solution, this invention constructs a neural network hardware accelerator that is flexible, efficient, suitable for visual tasks, and has good scalability. This accelerator, through a hierarchical storage structure, a highly parallel computing array, and an instruction-driven control mechanism, achieves efficient deployment of complex neural network models on an FPGA platform, while reducing hardware resource consumption and improving the overall system operating efficiency.

[0048] This invention also provides an FPGA-based method for accelerating neural network computation. This method is used in the aforementioned FPGA-based scalable hardware accelerator for neural networks, and includes the following steps: After the S1.FPGA system is powered on, it automatically loads the neural network weight parameters, bias parameters, and control instructions into the preset parameter storage area of ​​the storage module. S2. The control module reads and parses the control command; S3. Load the corresponding parameters based on the parsing results and start the calculation module to perform convolution calculation; S4. Write the calculation results into the intermediate feature map storage area; S5. Repeat the instructions until all neural network computation tasks are completed, and output the computation results.

[0049] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the aforementioned FPGA-based neural network accelerated computing method.

[0050] The present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, characterized in that the computer program, when executed by a processor, implements the FPGA-based neural network accelerated computing method as described in claim 8.

[0051] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0052] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A scalable hardware accelerator for neural networks based on FPGA, characterized in that, The system includes a storage module, a computation module, and a control module. The storage module includes a preset parameter storage area and an intermediate feature map storage area. The preset parameter storage area stores convolution weight parameters, bias parameters, and computation instruction sequences. The intermediate feature map storage area stores feature map data generated by each layer of the neural network. It adopts a multi-bank parallel feature map storage structure, enabling parallel access to intermediate feature map data through the collaborative work of multiple banks. The computation module includes a large-scale parallel computing unit array for convolutional neural network computation, enabling high-speed execution of convolution operations through the collaborative work of multiple parallel computing units. The control module performs timing control on convolution kernel loading, bias loading, feature map reading, and computation instruction sequence execution.

2. The scalable hardware accelerator for neural networks according to claim 1, further characterized in that, The storage module further includes an input / output data storage area, which is used to realize data interaction between the FPGA and the host computer.

3. The scalable hardware accelerator for neural networks according to claim 1, further characterized in that, The multi-bank parallel feature map storage structure includes at least four banks, which form a unified feature map storage pool through a data cross-access network to support the parallel reading of multiple feature map data during convolution calculation.

4. The scalable hardware accelerator for neural networks according to claim 1, characterized in that, The multi-bank parallel feature map storage structure introduces a channel transformation and multi-bank synchronous reading mechanism to directly read data from different banks in parallel during cross-layer connection or feature splicing, and completes channel rearrangement at the hardware layer.

5. The scalable hardware accelerator for neural networks according to claim 1, characterized in that, The computing module uses a pipelined approach to continuously process feature map data.

6. The scalable hardware accelerator for neural networks according to claim 1, characterized in that, The calculation module includes a sliding window generation unit and a multiply-accumulate calculation unit; The sliding window generation unit constructs a convolutional window using a row cache structure; The multiply-add calculation unit implements convolution operations through multiple parallel multipliers and adders.

7. The scalable hardware accelerator for neural networks according to claim 6, characterized in that, The convolution calculation is divided into a multi-stage pipeline structure so that the computing array outputs a new convolution result in each clock cycle.

8. A neural network acceleration computing method based on FPGA, characterized in that, This method is used in the FPGA-based scalable hardware accelerator for neural networks as described in any one of claims 1-7, and the method includes the following steps: After the FPGA system is powered on, the neural network weight parameters, bias parameters, and control instructions are automatically loaded into the preset parameter storage area of ​​the storage module. The control module reads and parses the control commands; Load the corresponding parameters based on the parsing results and start the calculation module to perform convolution calculation; Write the calculation results into the intermediate feature map storage area; Repeat the instructions until all neural network computation tasks are completed, and output the computation results.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the FPGA-based neural network accelerated computing method as described in claim 8.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the FPGA-based neural network accelerated computing method as described in claim 8.

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