Semiconductor gain chip based on asymmetric multiple quantum wells

Abstract

This disclosure provides a semiconductor gain chip based on asymmetric multiple quantum wells, comprising: a lower electrode layer (201), a substrate layer (202), a buffer layer (203), a lower waveguide layer (207), a buried active region (208), an upper waveguide layer (209), a capping layer (205), and an upper electrode layer (206) stacked sequentially; the lower waveguide layer (207), the buried active region (208), and the upper waveguide layer (209) together constitute a longitudinal optical waveguide; the buried active region (207) 208) is an asymmetric multi-quantum-well structure containing at least two quantum wells that are different in thickness and / or material composition, so that the gain spectral peaks of each quantum well are staggered; the longitudinal optical waveguide includes a tapered straight waveguide segment (301) and a curved waveguide segment (302) connected in sequence; the tapered straight waveguide segment (301) has a width that gradually changes along its length direction, and the optical axis extension direction of the curved waveguide segment (302) has a non-zero angle with respect to the optical axis direction of the tapered straight waveguide segment (301).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor gain chip based on asymmetric multiple quantum wells. Background Technology

[0002] With the development of optical communication and optical sensing technologies, the demand for broadband light sources and amplifiers is becoming increasingly urgent. For example, tunable external cavity lasers require wide gain bandwidth to achieve wide-range tuning; broadband semiconductor optical amplifiers are expected to replace erbium-doped fiber amplifiers to cover a wider wavelength range; supercontinuum light sources require broadband seed sources; and ASE broadband light sources play an important role in gyroscopes, fiber optic sensing, and other fields. Therefore, realizing ultra-wide gain spectrum on a single chip has significant application value.

[0003] However, the gain spectrum of traditional semiconductor gain chips is typically narrow, limited by the material's gain peak width, generally only covering tens of nanometers. Even with multi-quantum-well designs, the gain peaks are still concentrated near specific wavelengths, making it difficult to provide uniform high gain across the entire wavelength range and failing to meet wide tuning requirements. Furthermore, broadening the gain spectrum often results in a decrease in saturated output power. The gain bandwidth and output power of semiconductor gain devices are often mutually restrictive; wide-spectrum designs tend to lead to a reduction in peak gain, causing the device to saturate earlier and limiting its application in high-power scenarios. In addition, end-face reflections introduce dense cavity-mode interference, disrupting the smoothness and stability of the wide-spectrum output. Traditional anti-reflective coatings struggle to reduce reflectivity to ideal levels, while physical methods such as bevel cutting increase process complexity. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor gain chip based on asymmetric multiple quantum wells.

[0005] One aspect of this disclosure provides a semiconductor gain chip based on asymmetric multiple quantum wells, comprising: a lower electrode layer, a substrate layer, a buffer layer, a lower waveguide layer, a buried active region, an upper waveguide layer, a capping layer, and an upper electrode layer stacked sequentially; the lower waveguide layer, the buried active region, and the upper waveguide layer together constitute a longitudinal optical waveguide; the buried active region is an asymmetric multiple quantum well structure, containing at least two quantum wells that are different in thickness and / or material composition, such that the gain spectral peaks of each quantum well are staggered; the longitudinal optical waveguide includes a tapered straight waveguide segment and a curved waveguide segment connected sequentially; the tapered straight waveguide segment has a width that gradually changes along its length direction, and the optical axis extension direction of the curved waveguide segment has a non-zero angle relative to the optical axis direction of the tapered straight waveguide segment.

[0006] According to an embodiment of this disclosure, the asymmetric multi-quantum-well structure includes at least one strained quantum well.

[0007] According to an embodiment of this disclosure, the longitudinal optical waveguide has confinement layers on both sides to achieve lateral confinement of charge carriers and optical field.

[0008] According to an embodiment of this disclosure, the semiconductor gain chip has a first end face and a second end face disposed opposite to each other; the first end face is located at the end of the tapered straight waveguide segment and is coated with a reflective film, and the second end face is located at the end of the curved waveguide segment and is coated with an anti-reflective film.

[0009] According to embodiments of this disclosure, the non-zero included angle is 6° to 12°.

[0010] According to embodiments of this disclosure, the tapered straight waveguide segment is configured in any of the following ways: the narrow end of the tapered straight waveguide segment is connected to the first end face, and the width of the narrow end is not greater than 3 micrometers; the wide end of the tapered straight waveguide segment is connected to the first end face, and the width of the wide end is not less than 4 micrometers.

[0011] According to an embodiment of this disclosure, the length of the tapered straight waveguide segment is not less than 300 micrometers.

[0012] According to embodiments of this disclosure, the total number of quantum wells in the asymmetric multi-quantum-well structure is less than 6.

[0013] According to an embodiment of this disclosure, an InP transparent window area is formed on the second end face.

[0014] According to embodiments of this disclosure, the substrate layer is an InP substrate, the lower waveguide layer and the upper waveguide layer are InP materials, and the quantum well and barrier layer materials for the buried active region are InGaAsP-based or InAlGaAs-based materials.

[0015] Compared with the prior art, this disclosure has the following beneficial effects:

[0016] (1) By integrating multiple asymmetric quantum wells with mutually staggered gain peaks in the same active region, the gain spectral width limitation of a single quantum well structure is broken, and the spectrum is significantly broadened, which is particularly suitable as a gain medium for tunable external cavity lasers.

[0017] (2) The unique tapered-bending composite waveguide structure effectively expands the optical mode field at the output end while ensuring high gain, reduces power density, not only delays gain saturation, but also reduces the risk of end-face optical damage and improves coupling efficiency with external optical fiber, thereby significantly improving the practical output power of the chip.

[0018] (3) The differences in thickness, composition and strain of each well in the asymmetric multi-quantum well result in different energy levels and gain responses under an external electric field. When the operating current changes, the gain peaks of each quantum well drift asynchronously, and the overall gain spectrum is composed of multiple components with different responses, thereby effectively suppressing the spectral distortion caused by factors such as the quantum confinement Stark effect and improving the spectral stability of the device over a wide current range. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor gain chip based on asymmetric multiple quantum wells according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A cross-sectional view of a semiconductor gain chip based on asymmetric multiple quantum wells according to an embodiment of the present disclosure is shown schematically.

[0022] Figure 3 A side view of a semiconductor gain chip based on an asymmetric multiple quantum well according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0023] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0027] like Figure 1 and Figure 2 As shown, this disclosure provides a semiconductor gain chip based on asymmetric multiple quantum wells, including a lower electrode layer 201, a substrate layer 202, a buffer layer 203, a lower waveguide layer 207, a buried active region 208, an upper waveguide layer 209, a capping layer 205 and an upper electrode layer 206 stacked sequentially.

[0028] The lower electrode layer 201 is disposed at the bottom of the substrate layer 202 to provide a backside ohmic contact. A buffer layer 203 is grown on the substrate layer 202 to provide a high-quality, flat epitaxial growth interface and to prevent substrate defects from extending upwards. The lower waveguide layer 207 constitutes the lower confinement layer of the optical waveguide. The lower waveguide layer 207, the buried active region 208, and the upper waveguide layer 209 together form a longitudinal optical waveguide. The upper waveguide layer 209 is grown on the active region 208 and, together with the lower waveguide layer 207, forms a longitudinal optical waveguide, confining the optical field to the vicinity of the active region 208. A capping layer 205 is grown on the upper waveguide layer 209 to reduce the contact resistance with the upper electrode layer 206. The upper electrode layer 206 is disposed on the surface of the capping layer 205 to provide a front-side current injection electrode.

[0029] In this embodiment of the disclosure, the semiconductor gain chip employs a buried structure, and the longitudinal optical waveguide further includes a confinement layer 204 formed on both sides thereon. The confinement layer 204 consists of a p-type buried layer and an n-type buried layer grown sequentially, used to limit current leakage to both sides of the waveguide.

[0030] In this embodiment, the buried active region 208 is an asymmetric multi-quantum-well structure, comprising at least two quantum wells with different thicknesses and / or material compositions, causing the gain spectral peaks of each quantum well to be staggered. This design avoids synchronous drift of peaks by making the response of the gain peaks of different quantum wells to current changes different, thereby making the shape, width, and center wavelength of the overall composite gain spectrum less sensitive to changes in external driving conditions (such as current), significantly improving the stability of the chip's output spectrum. This asymmetric design of the active region can overcome the inherent spectral width limitations of the gain medium, covering a wider wavelength range.

[0031] In some embodiments, the asymmetric multi-quantum-well structure includes at least one strained quantum well. By introducing at least one strained quantum well into the asymmetric multi-quantum-well, the polarization characteristics of the gain can be actively tuned. Specifically, strain engineering can design the band structure of the quantum well to achieve a more balanced optical gain response to TE and TM modes, thereby significantly reducing the dependence of the chip's output spectrum on the polarization state of the input light and improving its operational stability and reliability under polarization state changing environments. Simultaneously, strain design also helps to further enhance the optical gain of the material.

[0032] In this embodiment, the asymmetric multi-quantum-well structure has fewer than 6 quantum wells, with each quantum well typically having a thickness ranging from 6 to 12 nm, and the barrier layer typically having a thickness ranging from 10 to 20 nm. The typical range of quantum well strain is ±0.5% to 1.2%.

[0033] like Figure 3 As shown, the longitudinal optical waveguide includes a tapered straight waveguide section 301 and a curved waveguide section 302 connected in sequence. The tapered straight waveguide section 301 has a width that gradually changes along its length, and the optical axis of the curved waveguide section 302 has a non-zero angle relative to the optical axis of the tapered straight waveguide section 301. This non-zero angle is preferably 6° to 12°. The tapered straight waveguide section 301 is located on one side of the chip and is used to maintain and gradually broaden the optical mode; the curved waveguide section 302 is located on the other side of the chip and is inclined relative to the end face to change the light propagation direction and reduce end face feedback. The tapered waveguide section design allows the fundamental mode field to gradually expand, and the curved waveguide section design significantly reduces the effective reflectivity of the chip's output end, thereby improving the actual saturated output power of the gain chip.

[0034] The semiconductor gain chip has a first end face and a second end face that are arranged opposite to each other; the first end face is located at the end of the tapered straight waveguide section 301 and is coated with a reflective film, and the second end face is located at the end of the curved waveguide section 302 and is coated with an anti-reflective film.

[0035] Optionally, the narrow end of the tapered straight waveguide section 301 is connected to the first end face, and the width of the narrow end is no greater than 3 micrometers; or, the wide end of the tapered straight waveguide section 301 is connected to the first end face, and the width of the wide end is no less than 4 micrometers. It should be understood that both types of tapered straight waveguide sections 301 can expand the mode field, but the latter structure is preferred unless the process only allows the former structure.

[0036] The tapered waveguide segment should be long enough to ensure gradual mode broadening. Preferably, the length of the tapered straight waveguide segment 301 is not less than 300 micrometers. (In practice, it can be appropriately lengthened according to the device length layout, such as 500–1000 μm).

[0037] In some embodiments, an InP transparent window region is formed on the second end face. This window region not only further reduces cavity surface reflection into the active region, but also significantly reduces the risk of heat generation and optical catastrophic damage caused by non-radiative absorption at the end face, effectively improving the chip's maximum safe output power and long-term operational reliability.

[0038] In this embodiment of the disclosure, the substrate layer 202 is an InP substrate, the lower waveguide layer 207 and the upper waveguide layer 209 are InP materials, and the quantum well and barrier layer materials of the buried active region 208 are InGaAsP-based or InAlGaAs-based materials.

[0039] The following is the fabrication process of a semiconductor gain chip based on asymmetric multiple quantum wells provided in the embodiments of this disclosure.

[0040] On a single-crystal substrate, through precision thin film growth techniques such as MOCVD (metal-organic chemical vapor deposition) or MBE (molecular beam epitaxy), layers from the buffer layer to the lower waveguide layer, the active region (asymmetric multiple quantum wells), the upper waveguide layer, and the capping layer are grown in one step and sequentially.

[0041] After epitaxial growth, a layer of silicon dioxide (SiO2) is deposited on the wafer surface as a hard mask using plasma-enhanced chemical vapor deposition (PECVD). Next, the tapered straight waveguide segment and the curved waveguide segment are patterned on the SiO2 mask using photolithography. Specifically, the corresponding shapes are formed on the photoresist according to the designed tapered contour and curved curve, and the patterns are transferred and etched into the SiO2 layer to obtain the waveguide mask. The width of the tapered waveguide in the pattern gradually changes to achieve variations in the optical mode field; the curved waveguide segment is at a certain angle (preferably 6~12°) relative to the chip edge.

[0042] Using a SiO2 mask as a shield, the epitaxial layer outside the mask is selectively etched to form the mesa structure required for the waveguide.

[0043] The waveguide mesa is buried using a secondary epitaxial growth process. This embodiment preferably employs a PN current blocking layer scheme: while maintaining the SiO2 mask covering the top of the waveguide mesa, a second epitaxial growth is performed on the entire wafer. First, p-type InP confinement layers are epitaxially grown on both sides of the waveguide mesa, then n-type InP confinement layers are grown until the buried layer is flush with the top surface of the waveguide mesa.

[0044] After the above burial is completed, the residual SiO2 mask layer on the top of the waveguide mesa is removed by chemical wet etching. Then, a third epitaxial growth is performed to grow a highly doped p⁺-type contact layer (InGaAs in this embodiment) on the entire wafer surface.

[0045] Next, P-plane metal ohmic contact electrodes are fabricated on the contact layer exposed in the gain region using processes such as magnetron sputtering.

[0046] The wafer is flipped over and the substrate is thinned to approximately 100 μm thickness, and an N-side metal ohmic contact electrode is deposited on the back side of the substrate.

[0047] After cleaning, the wafer can be diced and cleaved to obtain individual device bars. According to chip design requirements, the device bars are cleaved into several individual dies (each die containing the complete structure of the aforementioned tapered and curved waveguides). Optical thin films are deposited on the clean die end faces using high-vacuum evaporation or sputtering methods: a reflective film is deposited on the end face containing the tapered straight waveguide, and multiple anti-reflective films are deposited on the end face containing the curved waveguide.

[0048] In this embodiment, the active region of the gain chip employs an asymmetric multi-quantum-well structure with fewer than six quantum wells. Gain and polarization stability of the gain spectrum are improved through strain engineering. The peak values ​​of the gain spectra of each quantum well are staggered, resulting in non-synchronous peak shifts in the output spectrum under different bias currents, thus reducing the overall spectrum's sensitivity to changes in driving conditions. Furthermore, the tapered waveguide design gradually expands the fundamental mode field, and the curved waveguide design significantly reduces the effective reflectivity at the device's AR end. The tapered-curved waveguide buried structure significantly improves the device's output performance. These measures collectively ensure that the chip achieves a wide gain bandwidth while maintaining high saturated output power and good spectral stability.

[0049] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor gain chip based on asymmetric multiple quantum wells, characterized in that, include: The following layers are stacked in sequence: lower electrode layer (201), substrate layer (202), buffer layer (203), lower waveguide layer (207), buried active region (208), upper waveguide layer (209), capping layer (205) and upper electrode layer (206). The lower waveguide layer (207), the buried active region (208), and the upper waveguide layer (209) together constitute a longitudinal optical waveguide; The buried active region (208) is an asymmetric multi-quantum-well structure, containing at least two quantum wells that are different in thickness and / or material composition, such that the gain spectral peaks of each quantum well are staggered. The longitudinal optical waveguide includes a tapered straight waveguide segment (301) and a curved waveguide segment (302) connected in sequence; the tapered straight waveguide segment (301) has a width that gradually changes along its length direction, and the optical axis extension direction of the curved waveguide segment (302) has a non-zero angle relative to the optical axis direction of the tapered straight waveguide segment (301).

2. The semiconductor gain chip according to claim 1, characterized in that, The asymmetric multi-quantum-well structure includes at least one strained quantum well.

3. The semiconductor gain chip according to claim 1, characterized in that, The longitudinal optical waveguide has confinement layers (204) on both sides to achieve lateral confinement of carriers and optical field.

4. The semiconductor gain chip according to claim 1, characterized in that, The semiconductor gain chip has a first end face and a second end face that are arranged opposite to each other; the first end face is located at the end of the tapered straight waveguide section (301) and is coated with a reflective film, and the second end face is located at the end of the curved waveguide section (302) and is coated with an anti-reflective film.

5. The semiconductor gain chip according to claim 4, characterized in that, The non-zero included angle is 6° to 12°.

6. The semiconductor gain chip according to claim 4, characterized in that, The tapered straight waveguide section (301) can be configured in any of the following ways: The narrow end of the tapered straight waveguide section (301) is connected to the first end face, and the width of the narrow end is no greater than 3 micrometers; The wide end of the tapered straight waveguide section (301) is connected to the first end face, and the width of the wide end is not less than 4 micrometers.

7. The semiconductor gain chip according to claim 1, characterized in that, The length of the tapered straight waveguide section (301) is not less than 300 micrometers.

8. The gain chip according to claim 1, characterized in that, The total number of quantum wells in the asymmetric multi-quantum-well structure is less than 6.

9. The semiconductor gain chip according to claim 4, characterized in that, An InP transparent window area is formed on the second end face.

10. The semiconductor gain chip according to claim 1, characterized in that, The substrate layer (202) is an InP substrate, the lower waveguide layer (207) and the upper waveguide layer (209) are InP materials, and the quantum well and barrier layer materials of the buried active region (208) are InGaAsP or InAlGaAs materials.

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