An ultra-low power over-temperature protection circuit

Abstract

This invention discloses an ultra-low power over-temperature protection circuit, belonging to the field of integrated circuits, including a temperature detection circuit and a voltage comparison circuit; the temperature detection circuit generates a positive temperature coefficient current I that increases with increasing temperature. PTAT Voltage V that does not change with temperature BG and bias current I bias To the voltage comparator circuit; the voltage comparator circuit converts the positive temperature coefficient current I through a resistor. PTAT The voltage is converted to a voltage proportional to the temperature coefficient and a comparison circuit with hysteresis is generated to prevent noise interference. The hysteresis function is implemented internally by two PMOS transistors to prevent the output from oscillating due to noise or temperature fluctuations. This invention can control the current of the entire circuit to within 100nA by adjusting the number of PMOS transistor chains, NMOS transistor chains, and diodes in the temperature detection circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an ultra-low power over-temperature protection circuit. Background Technology

[0002] Currently, the current of over-temperature protection circuits is in the μA range and above. Because over-temperature protection circuits are generally normally open, this value is too high in extremely low-power applications. Therefore, there is an urgent need for an extremely low-power over-temperature protection circuit. Summary of the Invention

[0003] The purpose of this invention is to provide an ultra-low power over-temperature protection circuit to solve the problems in the background art.

[0004] To solve the above-mentioned technical problems, the present invention provides an ultra-low power over-temperature protection circuit, comprising: an ultra-low power temperature detection circuit and a voltage comparison circuit; The temperature detection circuit generates a positive temperature coefficient current I that increases with increasing temperature. PTAT Voltage V that does not change with temperature BG and bias current I bias To voltage comparator circuit; The voltage comparator circuit uses a resistor to convert the positive temperature coefficient current I... PTAT It is converted into a voltage that is proportional to the temperature coefficient and generates a comparison with hysteresis to prevent noise interference.

[0005] In one feasible implementation, the temperature detection circuit includes NMOS transistors MN1~MN3, PMOS transistors MP1~MP3, resistors R1~R3, several diodes, and six PMOS transistor chains and two NMOS transistor chains. The six PMOS transistor chains include the first PMOS transistor chain, the second PMOS transistor chain, the third PMOS transistor chain, the fourth PMOS transistor chain, the fifth PMOS transistor chain, and the sixth PMOS transistor chain, each consisting of several PMOS transistors connected in series with their source and drain connected together, and the gates of each PMOS transistor are interconnected; the two NMOS transistor chains include the first NMOS transistor chain and the second NMOS transistor chain, each consisting of several NMOS transistors connected in series with their source and drain connected together, and the gates of each NMOS transistor are interconnected. The startup circuit consists of PMOS transistors MP1~MP3, NMOS transistors MN1~MN3, resistor R1, and the first PMOS transistor chain. The source of PMOS transistor MP1 is connected to VDD, the gate is connected to the enable signal ENB, and the drain is connected to the first end of resistor R1. The second end of resistor R1 is connected to the drain and gate of NMOS transistor MN1, the gate of NMOS transistor MN2, and the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is connected to the enable signal ENB, and its source is grounded. The drain of NMOS transistor MN2 is connected to VDD, and its source is grounded. The source of PMOS transistor MP2 is connected to VDD, the gate is connected to the enable signal EN, and its drain is connected to the drain of NMOS transistor MN2. The source and drain of the first PMOS transistor in the first PMOS transistor chain are both connected to VDD. The gates of all PMOS transistors in the first PMOS transistor chain are interconnected and connected to the source of PMOS transistor MP3. The drain of PMOS transistor MP3 is grounded, and its gate is connected to the drain of NMOS transistor MN2. The core circuit of BG consists of a second PMOS transistor chain, a third PMOS transistor chain, a fourth PMOS transistor chain, two NMOS transistor chains, resistors R2 and R3, and several diodes. The source and drain terminals of the first PMOS transistors in the second, third, and fourth PMOS transistor chains are all connected to VDD. The gate terminals of all PMOS transistors in the second PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The gate terminals of all PMOS transistors in the third PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The gate terminals of all PMOS transistors in the fourth PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The drain terminal of the last PMOS transistor in the second PMOS transistor chain is connected to the drain terminal of the first NMOS transistor chain in the first NMOS transistor chain. The third PMOS transistor chain... The drain of the PMOS transistor at the end of the S-chain is connected to the drain of the NMOS transistor at the beginning of the second NMOS chain. The gates of all NMOS transistors in the first NMOS chain are interconnected and then connected to the drain of the NMOS transistor at the beginning of the first NMOS chain. The gates of all NMOS transistors in the second NMOS chain are interconnected and then connected to the drain of the NMOS transistor at the beginning of the first NMOS chain. The source of the NMOS transistor at the end of the first NMOS chain is grounded through diode D1. The source of the NMOS transistor at the end of the second NMOS chain is grounded sequentially through resistor R2 and k diodes. The drain of the PMOS transistor at the end of the fourth PMOS chain is grounded sequentially through resistor R3 and diode D3, and the drain of the PMOS transistor at the end of the fourth PMOS chain outputs a voltage V that does not change with temperature. BG ; The fifth and sixth PMOS transistor chains constitute the PTAT current generation circuit. The gate terminals of each PMOS transistor in the fifth PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The source terminal of the first PMOS transistor in the fifth PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor outputs a positive temperature coefficient current I. PTATIn the sixth PMOS transistor chain, the gate terminals of each PMOS transistor are interconnected and then connected to the source terminal of PMOS transistor MP3. The source terminal of the first PMOS transistor in the sixth PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor outputs a bias current I. bias .

[0006] In one feasible implementation, the number of PMOS transistors in the first PMOS transistor chain, the second PMOS transistor chain, and the third PMOS transistor chain are each n; The fourth PMOS transistor chain contains n·a1 PMOS transistors, the fifth PMOS transistor chain contains n·a2 PMOS transistors, and the sixth PMOS transistor chain contains n·a3 PMOS transistors. The number of NMOS transistors in the first NMOS transistor chain and the second NMOS transistor chain are m respectively; Where a1, a2, and a3 are all integers, representing the current multiples of the BG core circuit being replicated; the positive temperature coefficient current I is adjusted by changing resistors R1 and k. PTAT To achieve the nA level, by setting different values ​​for n, m, and k, the current of the entire circuit can be controlled within 100nA.

[0007] In one feasible implementation, the voltage comparison circuit includes PMOS transistors MP4~MP10, NMOS transistors MN4~MN10, and resistor R4; A positive temperature coefficient current I is connected to the first terminal of resistor R4. PTAT The second terminal is grounded; the source terminals of PMOS transistors MP4~MP10 are all connected to VDD; the drain terminal of PMOS transistor MP4 is simultaneously connected to the first terminal of resistor R4, the drain and gate terminals of NMOS transistor MN4, and the gate terminal of NMOS transistor MN5; the gate terminal of PMOS transistor MP4 is simultaneously connected to the drain and gate terminals of PMOS transistor MP5, the drain terminal of NMOS transistor MN5, and the drain terminal of PMOS transistor MP7; the gate terminal of PMOS transistor MP6 is connected to the gate terminal of PMOS transistor MP5; the drain terminal of PMOS transistor MP6 is simultaneously connected to the drain terminal of PMOS transistor MP8 and the drain terminal of NMOS transistor MN6; the gate terminal of PMOS transistor MP7 is simultaneously connected to the gate terminal of PMOS transistor MP8, the drain terminal of NMOS transistor MN6, and the gate terminal of PMOS transistor MP9; the drain terminal of PMOS transistor MP9 is simultaneously connected to the gate terminals of PMOS transistor MP10 and NMOS transistor MN9; the drain terminals of PMOS transistor MP10 and NMOS transistor MN9 are connected and output Vout; the source terminal of NMOS transistor MN9 is grounded; The source terminals of NMOS transistors MN5 and MN6 are connected to the drain terminal of NMOS transistor MN7. The gate terminal of NMOS transistor MN6 is connected to a voltage V that does not change with temperature. BGThe gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN10, and its source is grounded; the drain and gate of NMOS transistor MN10 are connected to the bias current I. bias The source terminal is grounded; the gate terminal of NMOS transistor MN4 is connected to the gate terminal of NMOS transistor MN8, and the source terminals of both NMOS transistor MN4 and NMOS transistor MN8 are grounded.

[0008] In one feasible implementation, the voltage comparator circuit internally implements a hysteresis function through PMOS transistors MP6 and MP7 to prevent the output from oscillating back and forth due to noise or temperature fluctuations.

[0009] In one feasible implementation, the positive temperature coefficient current I PTAT Converted to V by a resistor PTAT One end of the voltage comparison circuit is connected to the voltage; the other end of the voltage comparison circuit is connected to a voltage V that does not change with temperature. BG .

[0010] This invention provides an ultra-low power over-temperature protection circuit, comprising a temperature detection circuit and a voltage comparison circuit; the temperature detection circuit generates a positive temperature coefficient current I that increases with increasing temperature. PTAT Voltage V that does not change with temperature BG and bias current I bias To the voltage comparator circuit; the voltage comparator circuit converts the positive temperature coefficient current I through a resistor. PTAT It converts the voltage to a voltage proportional to the temperature coefficient and generates a comparison with hysteresis to prevent noise interference. This invention can control the current of the entire circuit to within 100nA by adjusting the number of PMOS transistors, NMOS transistors, and diodes in the temperature detection circuit. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the ultra-low power over-temperature protection circuit provided by the present invention.

[0013] Figure 2 This is a schematic diagram of the temperature detection circuit structure provided by the present invention.

[0014] Figure 3 This is a schematic diagram of the voltage comparison circuit structure provided by the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] The serial numbers assigned to components in this application, such as "first" and "second," are merely for distinguishing the described objects and have no sequential or technical meaning. The terms "connection" and "linkage," unless otherwise specified, are not limited to physical or mechanical connections and can include electrical communication connections, whether direct or indirect. In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "middle," "between," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0017] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0018] This invention provides an ultra-low power over-temperature protection circuit, the principle architecture of which is as follows: Figure 1 As shown, it consists of two parts: an extremely low-power temperature detection circuit and a voltage comparison circuit. The temperature detection circuit generates a positive temperature coefficient current I that increases with increasing temperature. PTAT Voltage V that does not change with temperature BG and bias current I bias To the voltage comparator circuit; the voltage comparator circuit converts the positive temperature coefficient current I through a resistor. PTAT It is converted into a voltage that is directly proportional to the temperature coefficient, and a comparison with hysteresis function is generated to prevent noise interference.

[0019] Temperature detection circuit such as Figure 2 As shown, the system includes NMOS transistors MN1~MN3, PMOS transistors MP1~MP3, resistors R1~R3, several diodes, and six PMOS transistor chains (first PMOS transistor chain, second PMOS transistor chain, third PMOS transistor chain, fourth PMOS transistor chain, fifth PMOS transistor chain, and sixth PMOS transistor chain) and two NMOS transistor chains (first NMOS transistor chain and second NMOS transistor chain). Each PMOS transistor chain consists of several PMOS transistors connected in series with their source and drain connected together, and the gates of each PMOS transistor are interconnected. Similarly, each NMOS transistor chain consists of several NMOS transistors connected in series with their source and drain connected together, and the gates of each NMOS transistor are interconnected.

[0020] The startup circuit consists of PMOS transistors MP1-MP3, NMOS transistors MN1-MN3, resistor R1, and the first PMOS transistor chain. The source of PMOS transistor MP1 is connected to VDD, its gate is connected to the enable signal ENB, and its drain is connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the drain and gate of NMOS transistor MN1, the gate of NMOS transistor MN2, and the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is connected to the enable signal ENB, and its source is grounded. The drain of NMOS transistor MN2 is connected to VDD, and its source is grounded. The source of PMOS transistor MP2 is connected to VDD, its gate is connected to the enable signal EN, and its drain is connected to the drain of NMOS transistor MN2. In the first PMOS transistor chain, the source of the first PMOS transistor and the drain of the last PMOS transistor are both connected to VDD. The gates of all PMOS transistors in the first PMOS transistor chain are interconnected and connected to the source of PMOS transistor MP3. The drain of PMOS transistor MP3 is grounded, and its gate is connected to the drain of NMOS transistor MN2.

[0021] The core circuit of BG consists of a second PMOS transistor chain, a third PMOS transistor chain, a fourth PMOS transistor chain, two NMOS transistor chains, resistors R2 and R3, and several diodes. The source and drain terminals of the first PMOS transistors in the second, third, and fourth PMOS transistor chains are all connected to VDD. The gate terminals of each PMOS transistor in the second PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The gate terminals of each PMOS transistor in the third PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The gate terminals of each PMOS transistor in the fourth PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The drain of the last PMOS transistor in the second PMOS chain is connected to the drain of the first NMOS transistor in the first NMOS chain. The drain of the last PMOS transistor in the third PMOS chain is connected to the drain of the first NMOS transistor in the second NMOS chain. The gates of all NMOS transistors in the first NMOS chain are interconnected and then connected to the drain of the first NMOS transistor in the first NMOS chain. The gates of all NMOS transistors in the second NMOS chain are interconnected and then connected to the drain of the first NMOS transistor in the first NMOS chain. The source of the last NMOS transistor in the first NMOS chain is grounded through diode D1. The source of the last NMOS transistor in the second NMOS chain is grounded sequentially through resistor R2 and k diodes. The drain of the last PMOS transistor in the fourth PMOS chain is grounded sequentially through resistor R3 and diode D3. The drain of the last PMOS transistor in the fourth PMOS chain outputs a voltage V that does not change with temperature. BG .

[0022] The fifth and sixth PMOS transistor chains constitute the PTAT current generation circuit. The gate terminals of each PMOS transistor in the fifth PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The source terminal of the first PMOS transistor in the fifth PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor outputs a positive temperature coefficient current I. PTAT In the sixth PMOS transistor chain, the gate terminals of all PMOS transistors are interconnected and then connected to the source terminal of PMOS transistor MP3. The source terminal of the first PMOS transistor in the sixth PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor outputs a bias current I. bias .

[0023] The first, second, and third PMOS transistor chains each contain n PMOS transistors; the fourth PMOS transistor chain contains n·a1 PMOS transistors; the fifth PMOS transistor chain contains n·a2 PMOS transistors; and the sixth PMOS transistor chain contains n·a3 PMOS transistors. The first and second NMOS transistor chains each contain m NMOS transistors. Here, a1, a2, and a3 are integers representing the current multiples of the BG core circuit. By setting different values ​​for n, m, and k, the current of the entire circuit can be controlled to be within 100nA.

[0024] Voltage comparator circuit, such as Figure 3 As shown, the circuit includes PMOS transistors MP4~MP10, NMOS transistors MN4~MN10, and resistor R4. A positive temperature coefficient current I is connected to the first terminal of resistor R4. PTAT The second terminal is grounded; the source terminals of PMOS transistors MP4~MP10 are all connected to VDD; the drain terminal of PMOS transistor MP4 is simultaneously connected to the first terminal of resistor R4, the drain and gate terminals of NMOS transistor MN4, and the gate terminal of NMOS transistor MN5; the gate terminal of PMOS transistor MP4 is simultaneously connected to the drain and gate terminals of PMOS transistor MP5, the drain terminal of NMOS transistor MN5, and the drain terminal of PMOS transistor MP7; the gate terminal of PMOS transistor MP6 is connected to the gate terminal of PMOS transistor MP5; the drain terminal of PMOS transistor MP6 is simultaneously connected to the drain terminal of PMOS transistor MP8 and the drain terminal of NMOS transistor MN6; the gate terminal of PMOS transistor MP7 is simultaneously connected to the gate terminal of PMOS transistor MP8, the drain terminal of NMOS transistor MN6, and the gate terminal of PMOS transistor MP9; the drain terminal of PMOS transistor MP9 is simultaneously connected to the gate terminals of PMOS transistor MP10 and NMOS transistor MN9; the drain terminals of PMOS transistor MP10 and NMOS transistor MN9 are connected together and output Vout; the source terminal of NMOS transistor MN9 is grounded. The source terminals of NMOS transistors MN5 and MN6 are connected to the drain terminal of NMOS transistor MN7. The gate terminal of NMOS transistor MN6 is connected to a voltage V that does not change with temperature. BG The gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN10, and its source is grounded. The drain and gate of NMOS transistor MN10 are connected to a bias current I. bias The source terminals are grounded. The gate terminal of NMOS transistor MN4 is connected to the gate terminal of NMOS transistor MN8, and the source terminals of both NMOS transistor MN4 and NMOS transistor MN8 are grounded.

[0025] Positive temperature coefficient current I PTAT Converted to V by a resistor PTAT One end (P terminal) of the voltage comparator circuit is connected, and the other end (N terminal) of the voltage comparator circuit is connected to a voltage V that does not change with temperature. BGThe voltage comparator circuit internally implements hysteresis via MP6 and MP7 to prevent the output from oscillating due to noise or temperature fluctuations. The positive temperature coefficient current I is controlled by adjusting resistors R1 and k. PTAT It can achieve the nA level, and the entire voltage comparator circuit can be controlled within 100nA.

[0026] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0027] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A low-power over-temperature protection circuit, characterized in that, include: Extremely low power temperature detection circuit and voltage comparison circuit; The temperature detection circuit generates a positive temperature coefficient current I that increases with increasing temperature. PTAT Voltage V that does not change with temperature BG and bias current I bias To voltage comparator circuit; The voltage comparator circuit uses a resistor to convert the positive temperature coefficient current I... PTAT It is converted into a voltage that is proportional to the temperature coefficient and generates a comparison with hysteresis to prevent noise interference.

2. The ultra-low power over-temperature protection circuit as described in claim 1, characterized in that, The temperature detection circuit includes NMOS transistors MN1~MN3, PMOS transistors MP1~MP3, resistors R1~R3, several diodes, and six PMOS transistor chains and two NMOS transistor chains; The six PMOS transistor chains include the first PMOS transistor chain, the second PMOS transistor chain, the third PMOS transistor chain, the fourth PMOS transistor chain, the fifth PMOS transistor chain, and the sixth PMOS transistor chain, each consisting of several PMOS transistors connected in series with their source and drain connected together, and the gates of each PMOS transistor are interconnected; the two NMOS transistor chains include the first NMOS transistor chain and the second NMOS transistor chain, each consisting of several NMOS transistors connected in series with their source and drain connected together, and the gates of each NMOS transistor are interconnected. The startup circuit consists of PMOS transistors MP1~MP3, NMOS transistors MN1~MN3, resistor R1, and the first PMOS transistor chain. The source of PMOS transistor MP1 is connected to VDD, the gate is connected to the enable signal ENB, and the drain is connected to the first end of resistor R1. The second end of resistor R1 is connected to the drain and gate of NMOS transistor MN1, the gate of NMOS transistor MN2, and the drain of NMOS transistor MN3. The gate of NMOS transistor MN3 is connected to the enable signal ENB, and its source is grounded. The drain of NMOS transistor MN2 is connected to VDD, and its source is grounded. The source of PMOS transistor MP2 is connected to VDD, the gate is connected to the enable signal EN, and its drain is connected to the drain of NMOS transistor MN2. The source and drain of the first PMOS transistor in the first PMOS transistor chain are both connected to VDD. The gates of all PMOS transistors in the first PMOS transistor chain are interconnected and connected to the source of PMOS transistor MP3. The drain of PMOS transistor MP3 is grounded, and its gate is connected to the drain of NMOS transistor MN2. The core circuit of BG consists of a second PMOS transistor chain, a third PMOS transistor chain, a fourth PMOS transistor chain, two NMOS transistor chains, resistors R2 and R3, and several diodes. The source and drain terminals of the first PMOS transistors in the second, third, and fourth PMOS transistor chains are all connected to VDD. The gate terminals of all PMOS transistors in the second PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The gate terminals of all PMOS transistors in the third PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The gate terminals of all PMOS transistors in the fourth PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The drain terminal of the last PMOS transistor in the second PMOS transistor chain is connected to the drain terminal of the first NMOS transistor chain in the first NMOS transistor chain. The third PMOS transistor chain... The drain of the PMOS transistor at the end of the S-chain is connected to the drain of the NMOS transistor at the beginning of the second NMOS chain. The gates of all NMOS transistors in the first NMOS chain are interconnected and then connected to the drain of the NMOS transistor at the beginning of the first NMOS chain. The gates of all NMOS transistors in the second NMOS chain are interconnected and then connected to the drain of the NMOS transistor at the beginning of the first NMOS chain. The source of the NMOS transistor at the end of the first NMOS chain is grounded through diode D1. The source of the NMOS transistor at the end of the second NMOS chain is grounded sequentially through resistor R2 and k diodes. The drain of the PMOS transistor at the end of the fourth PMOS chain is grounded sequentially through resistor R3 and diode D3, and the drain of the PMOS transistor at the end of the fourth PMOS chain outputs a voltage V that does not change with temperature. BG ; The fifth and sixth PMOS transistor chains constitute the PTAT current generation circuit. The gate terminals of each PMOS transistor in the fifth PMOS transistor chain are interconnected and then connected to the source terminal of PMOS transistor MP3. The source terminal of the first PMOS transistor in the fifth PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor outputs a positive temperature coefficient current I. PTAT In the sixth PMOS transistor chain, the gate terminals of each PMOS transistor are interconnected and then connected to the source terminal of PMOS transistor MP3. The source terminal of the first PMOS transistor in the sixth PMOS transistor chain is connected to VDD, and the drain terminal of the last PMOS transistor outputs a bias current I. bias .

3. The ultra-low power over-temperature protection circuit as described in claim 2, characterized in that, The first PMOS transistor chain, the second PMOS transistor chain, and the third PMOS transistor chain each contain n PMOS transistors; The fourth PMOS transistor chain contains n·a1 PMOS transistors, the fifth PMOS transistor chain contains n·a2 PMOS transistors, and the sixth PMOS transistor chain contains n·a3 PMOS transistors. The number of NMOS transistors in the first NMOS transistor chain and the second NMOS transistor chain are m respectively; Where a1, a2, and a3 are all integers, representing the current multiples of the BG core circuit being replicated; the positive temperature coefficient current I is adjusted by changing resistors R1 and k. PTAT To achieve the nA level, by setting different values ​​for n, m, and k, the current of the entire circuit can be controlled within 100nA.

4. The ultra-low power over-temperature protection circuit as described in claim 1, characterized in that, The voltage comparison circuit includes PMOS transistors MP4~MP10, NMOS transistors MN4~MN10, and resistor R4; A positive temperature coefficient current I is connected to the first terminal of resistor R4. PTAT The second terminal is grounded; the source terminals of PMOS transistors MP4~MP10 are all connected to VDD; the drain terminal of PMOS transistor MP4 is simultaneously connected to the first terminal of resistor R4, the drain and gate terminals of NMOS transistor MN4, and the gate terminal of NMOS transistor MN5; the gate terminal of PMOS transistor MP4 is simultaneously connected to the drain and gate terminals of PMOS transistor MP5, the drain terminal of NMOS transistor MN5, and the drain terminal of PMOS transistor MP7; the gate terminal of PMOS transistor MP6 is connected to the gate terminal of PMOS transistor MP5; the drain terminal of PMOS transistor MP6 is simultaneously connected to the drain terminal of PMOS transistor MP8 and the drain terminal of NMOS transistor MN6; the gate terminal of PMOS transistor MP7 is simultaneously connected to the gate terminal of PMOS transistor MP8, the drain terminal of NMOS transistor MN6, and the gate terminal of PMOS transistor MP9; the drain terminal of PMOS transistor MP9 is simultaneously connected to the gate terminals of PMOS transistor MP10 and NMOS transistor MN9; the drain terminals of PMOS transistor MP10 and NMOS transistor MN9 are connected and output Vout; the source terminal of NMOS transistor MN9 is grounded; The source terminals of NMOS transistors MN5 and MN6 are connected to the drain terminal of NMOS transistor MN7. The gate terminal of NMOS transistor MN6 is connected to a voltage V that does not change with temperature. BG The gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN10, and its source is grounded; the drain and gate of NMOS transistor MN10 are connected to the bias current I. bias The source terminal is grounded; the gate terminal of NMOS transistor MN4 is connected to the gate terminal of NMOS transistor MN8, and the source terminals of both NMOS transistor MN4 and NMOS transistor MN8 are grounded.

5. The ultra-low power over-temperature protection circuit as described in claim 4, characterized in that, The voltage comparator circuit internally implements a hysteresis function through PMOS transistors MP6 and MP7 to prevent the output from oscillating due to noise or temperature fluctuations.

6. The ultra-low power over-temperature protection circuit as described in claim 1, characterized in that, The positive temperature coefficient current I PTAT Converted to V by a resistor PTAT One end of the voltage comparison circuit is connected to the voltage; the other end of the voltage comparison circuit is connected to a voltage V that does not change with temperature. BG .

Images