A battery charging equalization control system of a battery swap cabinet based on a dynamic topology network

Abstract

This application relates to the field of battery charging control technology and discloses a battery charging equalization control system for battery swapping cabinets based on a dynamic topology network. The system includes a main control unit, a power distribution bus, multiple power units, a routing matrix, and bay terminals. The main control unit acquires the operating status data of the batteries to be charged in the bay terminals through the control communication bus and generates a Boolean adjacency matrix. Based on this, it controls the operation of the electrical switching nodes of the routing matrix, dynamically connecting designated power units in parallel to the target bay terminal. Simultaneously, the main control unit calculates the target phase offset and transmits high-frequency reference pulses to the power units through a hardware synchronization bus physically isolated from the control communication bus, performing phase shift interleaving control on multiple power units connected in parallel to the same bay terminal. This invention improves the overall utilization rate of the battery swapping cabinet equipment by dynamically allocating power units and cancels the superposition of current ripple from multiple parallel modules through phase shift interleaving control, thereby improving the charging power quality.

Description

Technical Field

[0001] This invention relates to the field of battery charging control technology, specifically to a battery charging equalization control system for battery swapping cabinets based on dynamic topology networks. Background Technology

[0002] With the increasing popularity of electric vehicles and two-wheeled electric vehicles, battery swapping stations have become widely used as an efficient energy replenishment infrastructure. These stations typically contain multiple independent battery compartments and corresponding charging power modules for centralized charging of recycled depleted batteries.

[0003] In existing battery swapping cabinet charging systems, power modules and battery compartments typically use a fixed one-to-one or one-to-many physical connection. This static hardware topology prevents the system from flexibly allocating power based on the actual charge status and charging needs of the batteries in each compartment. When batteries in some compartments are in the constant voltage, low current stage at the end of charging, or even when they are fully charged, their associated power modules will be under low load or idle. Meanwhile, other compartments with newly added depleted batteries are limited by the power limit of a single module and cannot obtain a higher charging current. This results in low power utilization of the entire battery swapping cabinet and prolongs the overall battery turnaround time.

[0004] To improve equipment utilization, some charging systems have begun to use relay matrices to achieve dynamic parallel allocation of power modules. However, due to the extremely low internal resistance of power batteries, during the dynamic parallel connection of multiple modules, there is often a significant absolute difference between the output capacitor voltage of the power module that has just completed state reconfiguration and the terminal voltage of the target battery. If a physical switch or semiconductor device is directly driven to close under this voltage difference condition, a huge capacitive surge current will be instantly generated, causing arcing or welding adhesion of the relay mechanical contacts, or thermal breakdown damage to the solid-state switching elements.

[0005] Furthermore, when multiple power modules are connected in parallel to the same battery compartment for high-current charging, the operating frequencies of the switching transistors within each module are difficult to synchronize perfectly, resulting in severe current ripple superposition on the output bus after parallel connection. High-frequency current ripple not only increases polarization heating within the battery, affecting the cell's cycle life, but also causes severe electromagnetic interference to the communication bus and control circuits within the battery swapping cabinet, reducing the overall power supply quality and operational stability of the system. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a battery charging equalization control system for battery swapping cabinets based on dynamic topology networks. This system solves the technical defects of existing battery swapping cabinet battery charging systems, such as low equipment utilization due to the fixed power distribution mode, capacitive inrush current that can easily cause switch contacts to stick or break down during dynamic parallel switching of execution modules, and current ripple superposition that affects power quality when multiple modules are connected in parallel.

[0007] The first aspect of this invention provides a battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network. The system includes a main control unit, a power distribution bus, multiple power units, a routing matrix, and multiple bay terminals. The power distribution bus, power units, routing matrix, and bay terminals are sequentially electrically connected, and each bay terminal houses a battery to be charged. The main control unit communicates with the power units, routing matrix, and bay terminals via a control communication bus, and is also hardwired with the power units via a physically isolated hardware synchronization bus. The main control unit generates a Boolean adjacency matrix based on the operating status data obtained via the control communication bus, and controls the routing matrix to dynamically connect the power units in parallel to the corresponding bay terminals. It also sends high-frequency reference pulses to the power units via the hardware synchronization bus to perform phase-shift interleaving control on multiple power units connected in parallel to the same bay terminal.

[0008] Furthermore, the aforementioned routing matrix consists of an array of interconnected electrical switch nodes, establishing a fully connected mapping path between the power unit output side and the warehouse terminal input side. The main control unit acquires the operating status data of the battery to be charged, which includes the limiting current value and the warehouse exit priority weight value. Based on this, the main control unit generates a globally weighted demand vector. Using the upper limit value of the grid feed-in power and the physical node exclusivity mechanism as constraint boundary conditions, the main control unit performs planning and solving with the objective function corresponding to maximizing the globally weighted demand vector as the direction, generating the Boolean adjacency matrix for the current control cycle.

[0009] Furthermore, the power unit is internally configured with a pulse width modulation generator. The main control unit extracts the algebraic sum of the elements column-by-column of the Boolean adjacency matrix to obtain the total number of parallel branches of the power units allocated to each warehouse terminal. Based on the total number of parallel branches, the system's fundamental phase shift angle is calculated, and local sequence numbers are assigned among the multiple power units connected in parallel to the same warehouse terminal, thereby solving for the target phase offset. The underlying hardware of the power unit aligns with the high-frequency reference pulse transmitted by the hardware synchronization bus, and, in conjunction with the target phase offset, resets the pulse width modulation generator, so that multiple power units combine and output a composite waveform with interleaved phase shifts at the bus port.

[0010] Furthermore, the main control unit is configured with a zero-dropout matching verification mechanism when controlling the routing matrix. The main control unit issues an open-circuit voltage following command to the power unit to be connected to the grid, so that it dynamically follows the measured polarization voltage of the battery terminal of the target compartment terminal. When the absolute difference between the actual voltage at the output port of the power unit and the measured polarization voltage at the battery terminal is continuously within the preset safe voltage drop tolerance threshold, the main control unit establishes zero-dropout engagement permission in its internal state machine. The main control unit is configured with low-level logic gate circuits. After establishing zero-dropout engagement permission, it integrates the node logic instructions of the Boolean adjacency matrix, the rated drive level threshold, the global hardware enable flag, and the logic flag representing zero-dropout engagement permission, and completes pin level mapping through the low-level logic gate circuits to output the control level that directly drives the closing of the electrical switch node corresponding to the routing matrix.

[0011] The second aspect of this invention provides a battery charging equalization control method for battery swapping cabinets based on a dynamic topology network, applied to the system provided in the first aspect above. The method includes the following steps: a main control unit acquires the operating status data of the batteries to be charged in the battery bay terminal through a control communication bus, and performs a planning solution to generate a Boolean adjacency matrix; the main control unit controls the routing matrix to dynamically connect multiple power units in parallel to the corresponding battery bay terminal according to the Boolean adjacency matrix; the main control unit calculates the target phase offset and transmits a high-frequency reference pulse to the power units through a hardware synchronization bus, performing phase shift interleaving control on the multiple power units connected in parallel to the same battery bay terminal.

[0012] Furthermore, before the above method drives the electrical switching nodes to perform actions, it also includes the following steps: performing an XOR differential extraction operation on the Boolean adjacency matrix of the current control cycle and the historical matrix of the previous cycle to establish the set of power units whose states need to change; issuing a zero-unloading command to the set of power units, and after the control loop current decays to the zero threshold, driving the routing matrix to perform a bridging action under no-current load conditions. Furthermore, before performing the bridging action, a pre-voltage following matching step is also included: issuing an no-load voltage following command to the power unit to be connected to the grid, so that its output voltage reference value dynamically anchors to the measured polarization voltage at the battery terminal of the target storage unit; only when the absolute difference between the output voltage reference value and the measured polarization voltage at the battery terminal is less than or equal to a preset differential voltage tolerance threshold, and the filtering and anti-jitter time is continuously met, is the corresponding node of the driving routing matrix allowed to close. In the specific steps of calculating the target phase offset, the algebraic sum of the elements of the Boolean adjacency matrix is ​​extracted column by column to obtain the total number of parallel branches, and the system's basic phase shift angle is calculated; local sequence numbers are assigned among multiple power units connected in parallel to the same warehouse terminal, and the target phase offset of each power unit is calculated based on the product of the system's basic phase shift angle and the local sequence number.

[0013] This invention provides a battery charging equalization control system for battery swapping cabinets based on a dynamic topology network. It has the following beneficial effects: 1. This invention generates a Boolean adjacency matrix by obtaining parameters such as battery operating status and priority weights, and drives the entire connection path to perform bridging actions based on the matrix. This technical feature changes the traditional hardware physical connection mode of fixed binding between power modules and charging compartments in battery swapping cabinets, enabling the system to dynamically allocate multiple power units in parallel to the corresponding compartments according to the actual charging needs of the batteries inside each compartment, thereby improving the overall utilization rate of power modules and the charging turnover efficiency of the battery swapping cabinet.

[0014] 2. This invention introduces a zero-current unloading and pre-emptive zero-difference voltage matching verification mechanism when performing dynamic network reconfiguration. Before the routing matrix node closes, the system identifies the node to be modified through XOR differential operation and waits for the current to return to zero. Simultaneously, it forces the output voltage of the power unit to be connected to the grid to dynamically follow the battery terminal voltage of the target location, allowing the closing action only when the absolute voltage difference decays to within the tolerance threshold. This mechanism eliminates capacitive surge currents caused by voltage difference at the hardware level, effectively preventing arcing of switch contacts or semiconductor breakdown, and extending the service life of the electrical switch node array. Attached Figure Description

[0015] Figure 1 This is an architecture diagram of the battery charging equalization control system for a battery swapping cabinet according to an embodiment of the present invention. Figure 2 This is a flowchart of a battery charging equalization control method for a battery swapping cabinet according to an embodiment of the present invention; Figure 3 This is a topology and control timing diagram of the multimodal power routing matrix according to an embodiment of the present invention; Figure 4 This is a comparison waveform diagram of the transient response of the output grid-connected current during the reconstruction of the multimodal routing matrix provided in this embodiment of the invention. Figure 5 A waveform comparison of voltage drop on the central DC bus on the grid side when a high-power load is connected in a step manner, as provided in an embodiment of the present invention. Figure 6 The waveform diagram shows the comparison of the microscopic high-frequency ripple of the total output current under the condition of parallel charging of multiple power units provided in the embodiments of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] See attached document Figure 1 , Figure 1 This is an architecture diagram of a battery charging balancing control system for a battery swapping cabinet according to an embodiment of the present invention. The present invention provides a battery charging balancing control system for a battery swapping cabinet, comprising: a power distribution bus, a power unit, a routing matrix, bay terminals, and a main control unit.

[0018] The power distribution bus is electrically connected to the input sides of multiple power units. The output sides of the multiple power units are connected to the input side nodes of the routing matrix. The output side nodes of the routing matrix are connected to multiple bay terminals. The bay terminals are used to house batteries and establish electrical connections.

[0019] The number of power units is set to The number of warehouse terminals is set to [number]. The routing matrix is ​​composed of switching devices and is generated using a cross-connected physical structure. An array of electrical switching nodes in a scale dimension. Each power unit is equipped with an independent pulse width modulation generator. The pulse width modulation generator is used to adjust the output current and pulse phase according to the received control commands.

[0020] The main control unit establishes data communication links with all power units, the routing matrix, and the measurement boards in each compartment terminal via a control communication bus. The main control unit is internally equipped with a hardware high-frequency timer. The hardware high-frequency timer pin of the main control unit is hardwired to the time stamp input pins of the microcontrollers in all power units via a hardware synchronization bus.

[0021] The control communication bus transmits system operating status data and control frames. The hardware synchronization bus independently transmits high-frequency reference pulses. The control communication bus and the hardware synchronization bus are physically isolated from each other in terms of channel and data transmission logic.

[0022] See attached document Figure 2 , Figure 2 This is a flowchart of a battery charging equalization control method for a battery swapping cabinet according to an embodiment of the present invention. The present invention provides a battery charging equalization control method for a battery swapping cabinet, comprising the following steps: S10, In the current control cycle, the main control unit obtains the operating status parameters of the storage battery in the warehouse terminal through the control communication bus, calculates the battery's limit current value and the warehouse exit priority weight value, and generates a global weighted demand vector for all warehouse terminals. S20, the main control unit reads the current power grid feed-in limit value, uses the power grid feed-in limit value and the physical node exclusion mechanism as the solution constraint boundary conditions, and performs planning solution in the direction of maximizing the objective function corresponding to the global weighted demand vector to obtain the Boolean adjacency matrix; S30, the main control unit extracts the algebraic sum of the elements of the Boolean adjacency matrix column by column to obtain the total number of parallel branches of the power units allocated to each warehouse terminal, calculates the system basic phase shift angle based on the total number of parallel branches, allocates local sequence numbers in the power unit group connected to the same warehouse terminal, and calculates the target phase offset of each power unit. S40, the main control unit performs an XOR differential extraction operation on the Boolean adjacency matrix of the current cycle and the historical matrix of the previous cycle to determine the set of power units whose physical state needs to be changed, and sends a zero-unloading instruction for the working reference value to the set of power units within the reconstruction range. After the control loop current decays to the zero threshold, the driving routing matrix performs a cross-track change action under no-current load conditions. S50, the main control unit sends the calculated target phase offset to the corresponding power unit through the control communication bus. The power unit's underlying hardware aligns with the reference signal of the hardware synchronization bus to reset the pulse width modulation generator. Multiple power units connected to the same warehouse terminal merge and output a composite waveform with specific phase shift interleaving features at the bus port. S60: The battery status parameters change dynamically with the electrical power supply. The updated parameters are sent back to the main control unit. The main control unit increments the time stamp to enter the next control cycle. Based on the updated feedback characteristic parameters, the start operation sequence is triggered again and executed cyclically until the charging operation is stopped.

[0023] This invention provides a battery charging equalization control method for a battery swapping cabinet, which specifically includes the following execution steps in the main control unit: S100, at the beginning of the control cycle, the main control unit acquires the operating status parameters of each battery in the storage terminal through the control communication bus. Considering the communication delay and frame congestion characteristics of the distributed bus network, in this embodiment, the main control unit is equipped with a ring data buffer at the front end. It uses a global timestamp attached to the message to perform timestamp alignment and first-order hysteresis filtering on the collected multi-source parameters to eliminate discrete noise interference caused by asynchronous sampling. The operating status parameters specifically include the battery state of charge, battery health status, and real-time cell temperature. The main control unit calculates the current charge acceptance rate boundary current value corresponding to each battery based on the operating status parameters. The charge acceptance rate boundary current value represents the absolute value of the maximum real-time charging current that the battery can withstand without triggering the lithium-ion deposition side reaction.

[0024] As a preferred underlying algorithm implementation, due to the highly nonlinear electrochemical polarization characteristics of batteries, a pre-trained multi-layer feedforward neural network model is deployed within the main control unit to replace the traditional static empirical lookup table method. The network architecture of this neural network model includes an input layer, a single hidden layer, and a corresponding single-node output layer. The input layer is set to four dimensions, with the corresponding input data vector being the time-aligned battery state of charge, battery health state, real-time cell temperature, and the polarization voltage fed back from the underlying layer. The hidden layer activation function uses a nonlinear rectified linear unit to avoid the gradient vanishing problem. The single-node output of the output layer is the boundary current value of the charge acceptance rate for the battery in the current control cycle.

[0025] Furthermore, considering the potential for communication bus silence, long-term sensor message loss, or severely excessive cell acquisition temperature under extreme electrical conditions, which could lead to missing or distorted input tensor data and cause model output divergence, this embodiment forcibly incorporates a fallback protection strategy based on a hard-coded state machine into the algorithm execution layer. Specifically, when the main control unit's circular data buffer fails to collect a complete four-dimensional valid input vector within the set timeout threshold, or when the input parameters exceed the physically reasonable range threshold, the algorithm scheduler will automatically suspend the forward inference pipeline of the multi-layer feedforward neural network model and instead use the conservative safety blind charging threshold preset in the system memory (e.g., a default trickle charging rate of 0.1C) as the forced charging acceptance rate boundary current value. Through this degradation protection strategy, the system establishes a smooth software-level fallback barrier before triggering the underlying pure hardware tri-state isolation protection (as described in S1500), ensuring that the target battery can still maintain the most basic safe charging state and never cross the irreversible lithium plating safety red line when it encounters local acquisition failure or abnormal AI model computing power.

[0026] Before being deployed to the main control unit, the neural network model needs to undergo complete supervised offline training on the host computer platform. The training sample set comes from the real cell charge and discharge history time series data recorded on a hybrid power pulse capability characteristic test bench in a laboratory environment. The data labels are extracted from the measured inflection point values ​​of the limiting current in various temperature zones and life stages that approximate the critical point of lithium plating potential. The training process uses mean square error as the loss function of the model and uses an adaptive moment estimation gradient descent optimizer to update the connection weights and bias term parameters of the neuron nodes in each network layer until the global mean square error evaluation standard of the test set decays and stabilizes within a specific tolerance threshold, thereby ensuring a high degree of fit between the predicted boundary and the real physical safety boundary.

[0027] The main control unit obtains the expected vehicle retrieval time and target state of charge for each node from the user terminal management system of the battery swapping station, and calculates the priority weight value for each battery node. The priority weight value is negatively correlated with the remaining expected retrieval time and positively correlated with the safe power gap between the target state of charge and the current state of charge. The main control unit multiplies the priority weight value of each battery node by the charging acceptance rate boundary current value to construct a globally weighted demand vector for all terminals at the current moment. The calculation principle of the priority weight corresponds to the following equation: ; In the formula, generation Table 1 Each battery node in the control cycle The weight value of the exit priority; Represents the target state of charge; Represents the current state of charge; This represents the expected remaining time for vehicle retrieval. To mitigate the risk of microprocessor division-by-zero overflow caused by the time window approaching the control cycle step size when the user is about to retrieve the vehicle, a safety time lower bound minimum constant is introduced into the denominator of the formula through a maximization function. . The value of is limited by the absolute duration of a single control cycle. This represents the system normalization adjustment coefficient, which typically ranges from 0.8 to 1.2, depending on the incentive weighting of local peak-valley electricity pricing periods.

[0028] S200 addresses the multi-path power allocation problem with strong coupling properties, where blindly traversing combinations can lead to computational power collapse. The main control unit configures the upper limit of grid feed power collected by sensors at the macro-level feed input pin, the boundary current values ​​of charging acceptance rates for each battery node, and the physical exclusivity of the switching nodes as rigid constraint boundary conditions. The main control unit optimizes by maximizing the sum of loads corresponding to the global weighted demand vector, performing integer nonlinear programming within its internal digital signal processing hardware core. The objective function logic maximizes the integral of the charging current utility allocated according to the weights of the entire system. The physical exclusivity specifically means that a single power unit is only allowed to be physically connected to a single warehouse terminal at any given time; the system prohibits single power units from cascading across multiple warehouse terminals and causing short-circuit output. The upper limit of grid feed power specifically means that the product of the total output currents from all active power units to the back end must not exceed the rated derating curve of the main incoming circuit breaker. After iterative optimization, the main control unit outputs a scale... The result of the Boolean adjacency matrix operation. The matrix elements within the Boolean adjacency matrix are presented as Boolean binary values, representing the network topology connectivity planning guidelines for the next control cycle. A true element value indicates that the power unit at the corresponding address number needs to establish physical electrical connectivity with the warehouse terminal at the corresponding address number; conversely, a false value indicates disconnection. The nonlinear programming solution structure corresponds to the following equation: ; In the formula, This represents the total number of warehouse terminals configured in the system. Represents the total number of power units; Represents the Boolean adjacency matrix of the first... Line number The elements of the column are numerical values, and their values ​​are limited to pure numbers, zero or one; Representing the The rated output current of each power unit is based on the factory-calibrated reference value. Representing the The priority weight value for each battery leaving the warehouse. For specific integer nonlinear programming internal optimization convergence algorithms, those skilled in the art can use the branch and bound method or heuristic swarm intelligence optimization program to complete the underlying engineering code. The simple algorithm optimization divergence and convergence steps are well-known technologies in this field and will not be elaborated here.

[0029] In S300, the main control unit extracts the algebraic sum of all corresponding elements in the generated Boolean adjacency matrix according to the column distribution direction. The algebraic sum of the corresponding elements in each column equivalently represents the total number of power unit branches connected in parallel to the corresponding compartment terminal port in the next control cycle. The main control unit calculates the multi-module basic phase shift span angle value of the current battery compartment group in real time based on the total number of branches. The specific parameter conversion process is that the main control unit divides the angle value of the complete electrical cycle by the total number of parallel branches to obtain the equally divided phase interval step size. The main control unit assigns a local digital sequence number within the set of associated power units connected to the same compartment terminal as confirmed by the Boolean adjacency matrix. The main control unit combines the local digital sequence number with the basic phase shift span angle value for multiplication and accumulation calculation to solve for the target phase offset value that needs to be established in the underlying pulse width modulation hardware generator for each specific power unit within the set. This target phase offset value is converted into the count value of the hardware timer compare register to trigger the bias parameter and is pre-stored in the main control cache instruction area. The solution characteristics of the micro phase shift step size correspond to the following relationship equation: ; ; In the formula, Representatives gathered at the The basic phase shift span angle value of each warehouse terminal. The corresponding denominator term represents the Boolean adjacency matrix. The total number of physical parallel branches obtained by column summation. Considering the extreme no-load condition where a certain warehouse terminal is not allocated any power unit in this cycle, a lower bound clamping constraint for the number 1 is implanted in the denominator to intercept illegal division-by-zero interruption faults in the calculation pipeline. Representing the The target phase offset value of each power unit; This represents the local digital sequence number assigned to the power unit within the corresponding physical parallel group, and its value naturally increases from zero.

[0030] In the S400 control process, during the physical port phase of the formal control command issuance, the main control unit performs an XOR differential logic gate operation on the corresponding element positions of the Boolean adjacency matrix of the current control cycle and the historical Boolean adjacency matrix of the previous control cycle in its internal logic calculation area. The output matrix of the XOR differential extraction operation precisely defines the set of power unit addresses that need to undergo connection path transitions. The main control unit identifies the extracted variable power units as the unit group to be reconfigured. The main control unit sends pulse blocking commands and output current reference value forced zero commands to the unit group to be reconfigured. The main control unit is configured with a polling and listening mechanism to collect the actual output current sampling values ​​returned by the internal current transformers of these power units. After determining that the physical transmission current of the internal control loop has decayed to within the preset absolute safety zero dead zone determination threshold, the main control unit triggers the physical relay action gate pin.

[0031] In this embodiment, the absolute safety zero dead zone determination threshold range is typically defined as follows: The threshold range is between 0.5A and +0.5A. The selection of this threshold range is primarily based on compensation mapping of the static zero drift and white noise fluctuation range of the underlying Hall current sensor, thus balancing the sensitivity of the state machine's judgment with the physical safety of preventing high-voltage arcing. Based on this closed-loop pre-intervention strategy, the main control unit independently drives the routing matrix network node level to execute the contact engagement and release actions of the connecting path. Utilizing XOR lookup tables and current clearing waiting state pre-intervention processing methods at the pure digital logic level, the main control unit transforms the high-voltage arcing welding action accompanying the physical disconnection under load into a safe dry cutting action without load. The state difference extraction mechanism corresponds to the following equation: ; In the formula, This represents the result of the state difference matrix of the reconstructed unit group; The Boolean adjacency matrix representing the current control cycle; This represents the historical Boolean adjacency matrix of the previous period; The symbol for the XOR logical physical operation representing the corresponding element points of the matrix. When When the internal specific coordinate parameters are expressed as first-order Boolean truth values, the hardware power unit corresponding to the mapped coordinates is included in the reconfiguration execution sequence and enters the current cutoff control attenuation stage.

[0032] This invention provides a battery charging equalization control method for battery swapping cabinets, specifically addressing multi-node communication and time base control at the system's underlying level, and includes the following execution steps: In the S500, the main control unit physically isolates the data transmission link and clock synchronization link within the system through a dual-mode decoupled network interface. In this embodiment, the control communication bus adopts a controller area network (MAN) bus physical architecture. The hardware synchronization bus uses an independently laid high-speed differential signal harness configuration. Based on the complete separation of these two physical entities, the system removes long-cycle state machine message data interaction and waveform synchronization instructions that are highly sensitive to nanosecond-level jitter at the hardware level. This decoupled architecture aims to avoid the distortion of the interleaved phase shift angle of the final output waveform caused by random transmission delay jitter due to message priority arbitration mechanisms, bit stuffing mechanisms, and network congestion at the protocol level.

[0033] In the S600, at the data link communication execution layer, the control communication bus is responsible for carrying the closed-loop upload of parameter data in a slowly changing state. The main control unit packages the target phase offset value, action enable flag, and Boolean adjacency matrix fragments obtained from the previous steps into a standard data structure control long frame. The main control unit sends out such low-frequency state frame messages using an asynchronous broadcast mechanism. After receiving the control message corresponding to its hardware address, each underlying power unit does not immediately trigger the underlying power execution state toggle. Each power unit decomposes the extracted target phase offset and moves it to the corresponding digital signal baseband shadow buffer register of the internal microprocessor for latching and waiting. For this read-write separated register operation, the local microprocessor can ensure that the update of control parameters will not disrupt the continuous physical waveform currently in the conduction duty cycle before the old switching cycle has ended.

[0034] In the S700, at the time base alignment operation level, the hardware high-frequency timer configured inside the main control unit broadcasts an absolute reference clock pulse to any node within the entire system's jurisdiction via a hardware synchronization bus. It's important to note that this hardware synchronization bus level channel does not carry any protocol-encoded messages. During the control cycle, the main control unit continuously outputs a high-frequency square wave sequence with a specific frequency and an extremely steep rising edge as a time anchor point to the bus. Considering the natural differences in physical wiring distances among the hundreds or thousands of power unit nodes widely distributed within the battery swapping cabinet, the system's underlying layer introduces passive compensation calculation constraints for node time base propagation delay. The actual time distribution model of signal edges arriving at each node corresponds to the following equation: ; In the formula, Representing the The physical pins at the ports of each peripheral power unit actually capture the absolute time elapsed for the rising edge transition; The initial origin time represents the rising edge transition event occurring at the bottom layer of the main control unit; Represents the output from the main control terminal to the first... Each power unit receives the total wire laying length from the endpoint; The standard propagation speed constant representing electromagnetic wave signals within a twisted pair with a specific insulating medium; its value is typically defined in practical twisted pair engineering standards as 0.6 to 0.75 times the speed of light in a vacuum. The fixed delay time caused by the resistor-capacitor buffer network configured at the front end of the power unit signal receiver to filter out spike noise.

[0035] However, in extremely demanding high-frequency applications, the response drift of the optocoupler isolator and the temperature drift of the resistor-capacitor network can cause the actual delay to deviate significantly from the theoretical static constant. As a preferred dynamic compensation method, this embodiment incorporates a lightweight delay prediction feedforward neural network model within the microprocessor of the power unit. This delay prediction feedforward neural network model adopts a classic multilayer perceptron structure, internally consisting of a two-dimensional environmental parameter input layer, a single-layer nonlinear hidden layer containing eight fully connected neurons, and a single-node linear output layer. The input data dimension of the input layer specifically includes the absolute temperature of the current operating environment collected by a local thermal sensor, and the cumulative operating time of the device accumulated by memory, thereby representing the thermal drift amplitude and the degree of hardware aging and fatigue degradation, respectively. The hidden layer is configured with a continuous nonlinear sigmoid activation function, and the final output layer directly outputs the normalized and restored dynamic delay adjustment microsecond correction value. .

[0036] Considering the stringent timing constraints imposed by nanosecond-level high-frequency synchronous interrupts, conventional digital signal processors cannot complete the floating-point matrix multiplication, addition, and activation operations of a multilayer perceptron within a single extremely short interrupt slice. Therefore, this delay-predictive feedforward neural network model is deployed in a low-priority asynchronous background task scheduling chain within the microprocessor core, or its forward inference is performed by a separately configured hardware neural processing unit (NPU). The model continuously solves in the background at a low, slowly varying environmental refresh rate (e.g., on the order of hundreds of milliseconds), and outputs the final dynamic delay correction value. The value is latched into a globally shared, wait-free shadow buffer register. When a pin captures a high-frequency edge triggering an interrupt, the underlying code within the critical section only needs to consume one to two extremely concise machine cycles to directly read the shadow buffer value for alignment compensation. This "asynchronous decoupling architecture" perfectly avoids the risks of blocking and overflowing crashes caused by complex AI inference on high-frequency timers, ensuring that independent controller modules under different physical states are always safely and accurately aligned on the same microscopic clock cross-section.

[0037] In the S800, during the receiver's low-level triggering and duty cycle generation process, each power unit is allocated an external interrupt trigger pin with extremely high interrupt preemption priority on the logic hardware. This pin is continuously suspended and monitors the differential level status of the hardware synchronization bus in real time. When a preset physical level rising edge event is captured, the microprocessor core forcibly interrupts low-priority temperature measurement or communication tasks running in the background and switches to the interrupt service routine in the critical protection segment. Within the few machine cycle execution slices of this subroutine, the low-level program extracts the preset target phase offset value from the previous shadow buffer register and maps it to the reload threshold of the micro-pulse width comparison output timer based on the core operating clock frequency. To achieve target control, all independent power units connected in parallel and operating in the same compartment forcibly clear the dominant timer count value to zero based on this same external level edge. The corresponding register conversion calculation structure that determines the high-frequency bridge arm conduction time corresponds to the following relationship equation: ; In the formula, Representing the The target integer count value to be written to the timer comparator register inside each power unit, which determines the flip position of the pulse rising edge. The integer function is used to ensure that the scaling result calculated through the continuous floating-point field meets the safe write standard of the discrete unsigned integer register, preventing the kernel bus from triggering an unaligned data access bus error. This represents the target phase offset setting value assigned to this work number unit; The high-frequency clock generator constant representing the peripheral bus of the internal microprocessor core has a typical value range of 100MHz to 200MHz. The set switch response frequency constant represents the selected main circuit topology of the system. It is generally constrained to be greater than or equal to 20kHz to avoid inverter audio frequency disturbances and hardware division by zero anomalies. This represents the theoretical upper limit of the overflow period of the master timer at the controlled switching frequency; mod represents the modulo remainder operation characteristic. Considering that the instruction sudden change may exceed the 360-degree control span of a single waveform when a network switch occurs, the modulo operation provides a periodic clamping defense constraint against digital overflow.

[0038] Based on this dual-dimensional network architecture control strategy combining an independent asynchronous data loading bus and a nanosecond-level hard-edge high-speed synchronous capture bus, multiple power module clusters that were previously operating in different frequency bands or randomly idle can, upon receiving the main electromagnetic relay action reconfiguration command, abandon the lengthy and complex multi-point network timing arbitration or protocol handshake waiting verification cycle. The overall system can transiently merge to achieve the optimal micro-output harmonic interleaving cancellation effect in the first high-frequency switching action cycle after the local hardware timer restarts. Regarding the context stack protection method in this hardware interrupt handling process, those skilled in the art can complete pointer calls according to conventional reduced instruction set or complex instruction set kernel architecture specifications. The underlying stack saving mechanism is a well-known digital protection technology in this field and will not be elaborated here.

[0039] See attached document Figure 3 , Figure 3 This is a multimodal power routing matrix topology and control timing diagram according to an embodiment of the present invention. The present invention provides a battery charging equalization control method for battery swapping cabinets, which specifically includes the following execution steps in constructing the physical trunk matrix for system-level power free flow allocation and the action response mechanism: In the S900, during the energy flow path physical layer allocation phase, the system constructs a multi-modal power routing matrix as the underlying on / off actuator. This matrix employs a parallel arrangement of high-current physical electromagnetic relay arrays or wide-bandgap solid-state semiconductor switches, with multiple sets of switch nodes interleaved to form a fully interconnected cross-mesh topology corresponding to the number of connection poles of the multi-module power supply ports and multi-compartment busbars of the corresponding system.

[0040] Considering that the terminal unit houses a power battery with extremely low internal resistance (an active high-voltage source), and that the output bus support capacitor of a power unit that has just completed network reconfiguration or joined a group may have a significant voltage difference with the target battery terminal, directly driving the switch to close based on the matrix calculation results would generate a highly destructive capacitive surge current, which could easily cause the mechanical contacts to instantly arc and weld together or trigger avalanche breakdown of wide-bandgap semiconductors. Therefore, this embodiment forcibly introduces a pre-voltage follower and zero-difference voltage matching verification mechanism before the physical matrix performs the bridging and closing action.

[0041] Specifically, after obtaining the Boolean adjacency matrix operation result generated by the uplink logic domain, the main control unit first issues an open-circuit voltage following command to the power unit to be connected to the grid, adjusting the output voltage reference value of the closed loop inside the power unit so that it dynamically anchors to and follows the measured polarization voltage of the battery terminal reported by the target storage terminal. The main control unit continuously calculates the absolute difference between the actual voltage at the output port of the power unit and the target battery voltage. Only when the absolute voltage difference decays and stabilizes within the preset safe voltage difference tolerance threshold (usually calibrated as an absolute tolerance band of 2V to 5V) will the system establish "zero voltage difference pull-in" permission in the internal state machine.

[0042] Based on the engineering requirement of high-frequency real-time response, after obtaining the engagement permission, the main control unit directly completes the level mapping of peripheral pins through dedicated low-level logic gate circuits, thereby avoiding the instruction cycle delay caused by the unpacking of conventional bus routing protocols. This hardware direct-drive operation mode accurately converts the calculated discretized Boolean values ​​into gate drive or coil excitation signals for specific array nodes, thus establishing the on and off states of the entity. After introducing differential pressure safety verification, the matrix mapping control relationship of the channel on state corresponds to the following equation: ; In the formula, Representative applied to the first The power unit branch and the first The direct drive voltage command amplitude of the switching devices at the cross-node of each warehouse terminal; The binary extraction result of the corresponding logical coordinate system in the Boolean adjacency matrix of the current control cycle calculated by the preceding algorithm module; The rated drive level threshold constant represents the necessary level for the underlying switch controller to reach full saturation conduction. In this embodiment, depending on the selected industrial-grade relay or silicon carbide module, this constant is typically calibrated as a 12V or 24V DC reference. Representative regarding the first The enable flag of the global slave hardware pin of each associated power unit, with a value limited to pure digital 1 or zero, is used to achieve the highest priority hardware-level tri-state isolation cutoff in the event of a low-level hard fault.

[0043] Specifically, the newly added product term This represents the Boolean flag indicating zero differential pressure matching permission. It is valid only if... After h (i.e., the measured absolute pressure difference at the port is less than or equal to the safe pressure difference tolerance threshold) continuously meets the set filtering and anti-jitter time, The logic 0 was just flipped to logic 1. Based on this mechanism, the system completely eliminates the destructive arcing and sudden impact caused by hard closing with differential pressure at the hardware level.

[0044] In the S1000 high-power DC loop, if the mechanical or solid contacts are forcibly disconnected under load current conditions, the energy storage inductor in the loop will generate a high-voltage arc, potentially causing severe ablation and adhesion failure of the contact metal. Therefore, the logical switching actions of the matrix network nodes are strictly controlled by the local closed-loop state feedback results of the hardware zero-current sensing network. When issuing network topology reconstruction commands, the main control unit pre-sends a pulse blocking command to suppress the duty cycle output of each power unit, causing the main loop to enter the natural follow current energy decay stage. However, the internal space of the battery swapping cabinet is filled with strong electromagnetic radiation interference from high-frequency pulse width modulation. If the single transient current sampling value crossing the zero baseline is used as the cutoff permission judgment, it is very easy to trigger dangerous false disconnection actions when noise occurs at a trough. As a preferred protection control method, this system constructs a steady-state zero-point establishment logic that combines the absolute value tolerance noise floor threshold and the time-domain slope change rate as dual-feature weighted evaluation logic. The corresponding zero-point cutoff permission energy judgment function relationship satisfies: ; In the formula, This represents a discrete safety cut-off Boolean permission signal for the output of a specific power unit link. The master control register is only allowed to release the gate voltage to the drive gate when this flag parameter is inverted to the true value 1. This represents the current measured residual current value of the link captured by the underlying high-bandwidth analog-to-digital converter with timestamp alignment. The absolute noise tolerance threshold representing the static zero current is determined mainly by referring to the static temperature drift and white noise standard deviation of the full-scale range of the matching Hall sensor, and is usually defined in the range of 0.1A to 0.3A, in order to shield the measurement substrate noise interference; the latter half of the judgment difference term represents the differential descent slope of the current discharge time series. The equivalent discrete sampling period span represents the core setting of the analog-to-digital conversion; the limiting constant in the denominator. This is a constant of instruction cycle width that characterizes the operating frequency of the underlying chip. Its purpose is to address the kernel's illegal calculation failure caused by the collapse of the sampling time scale due to external crystal oscillator jitter, which leads to the denominator returning to zero. This represents the safe threshold for a stable slope of the current change, typically ranging from 0.01 A / μs to 0.05 A / μs. Through comprehensive evaluation using multi-source data, the command center establishes the final execution point for arc-free reconfiguration only when the physical current value is extremely small and its attenuation waveform approaches absolute horizontal stillness.

[0045] S1100, when the system performs dynamic reconstruction of the multimodal power routing matrix based on the global optimal strategy output by the pre-algorithm, the main control unit needs to control specific power units to disconnect from the currently associated battery compartment busbar and connect to the new target battery compartment busbar.

[0046] Considering the significant hysteresis effects of physical switching devices during turn-off operations—such as the armature mechanical release time and arc extinguishing time of high-capacity electromagnetic relays, or the tail current of minority carrier recombination during turn-off in silicon carbide (SiC) / insulated gate bipolar transistors (IGBTs)—if the reconfiguration commands issued by the upper-level software do not physically isolate the turn-off and turn-on timings, it is highly likely that the newly added conduction path will overlap with the old path that has not yet been completely physically disconnected within a microsecond-level time window (i.e., "turn-on before turn-off"). This will establish a direct path with extremely low impedance between two power battery compartments with voltage differences, instantly triggering a catastrophic high-voltage cascade short circuit and hardware meltdown.

[0047] To address this, this embodiment forcibly injects an extremely strict dead-zone timing interlock mechanism to prevent short circuits in the underlying state machine transition slice of the control kernel. Specifically, after receiving the topology reconfiguration command, the main control unit first identifies all nodes whose states in the current control cycle's Boolean adjacency matrix have been flipped from "1" to "0" and immediately issues a low-level hardware truncation signal to initiate the no-load interruption disconnection process. Subsequently, the system forcibly starts a dead-zone masking window based on a hardware high-frequency timer. Before the window expires, all new node drive signals intended to be closed are forcibly blocked by the underlying logic gates.

[0048] Dead zone shielding window time threshold The final drive state update equation, which includes dead-time interlocking logic, is calibrated as follows: ; ; In the formula, This represents the maximum mechanical release hysteresis time of the selected mechanical relay throughout its entire life cycle and under extreme high and low temperature conditions. The ultimate self-extinguishing time represents the residual arcing time between contacts under inductive load; This represents the maximum turn-off tail time of a solid-state semiconductor switching device. The redundancy security margin reserved for the system is typically set to a value of [value missing]. to It varies, depending on the physical properties of the underlying execution hardware.

[0049] In the driving update equation, This represents the Boolean adjacency matrix representing the new round of goals that the upper-layer routing algorithm expects to achieve. The absolute physical timestamp representing the system issuing a truncation command to the node to be disconnected; The dead-zone step permission function is defined if and only if the input argument is... When the physical time has completely crossed the safety dead zone, the function outputs a logic 1; otherwise, it forces a logic 0 output. Relying on this "break-before-connect" high-frequency timer hard interlocking mechanism, the system completely eliminates the fatal hidden danger of overlapping short circuits between different battery clusters from the underlying time-series physical layer under extremely frequent dynamic reconstruction and frequency switching conditions, ensuring the absolute topology security of the routing matrix.

[0050] In S1200 systems operating in overlapping grid-connected sections with frequent cross-bay switching of busbar branches, the system architecture must unconditionally suppress various power supply-side direct-to-ground short-circuit crossover accidents caused by electrical time misalignment. To establish robust multi-layered protection, during the transition from the previous steady-state network topology to the next spatial reconstructed network topology, the main control unit utilizes the dead-time generator register of the on-chip microprocessor to forcibly implant a global electrical intervention dead zone between the upper and lower transistor drive state machines. This dead-time intervention mechanism ensures that before the original conducting actuator contacts completely disconnect their release contact surfaces, any intended activation voltage for connecting a new topology branch is physically suspended and forcibly pulled down. The safety definition logic for the dead-time bandwidth of the reconstructed interval conforms to the following time series inequality equation: ; In the formula, The absolute execution start timestamp is specified for the power devices in the next set of reconfigurable topology loops that need to be paralleled to be allowed to be raised to the drive high-level threshold. This represents the control trigger origin moment when the low-level cancellation command is received in the release branch of the previous steady-state topology. The representative indicates, based on the specific switch component material manual, the ultimate physical release hysteresis time constant caused by the superposition of the demagnetization reduction of the internal electromagnetic coil and the mechanical damping inertia of the reset spring; This represents a specific reserved temperature correction time margin constant, used to compensate for the slow response caused by continuous material aging or cold environment contraction. Utilizing this safety insulation boundary, which is wider than the response dead zone specifications of conventional components (statistically verified to have its empirical parameters typically set within a safety window of 15 to 45 milliseconds), the main control unit completely blocks the risk of unplanned coupling backflow between different energy nodes at the hardware physical level, laying a solid foundation for the matrix reconfiguration function.

[0051] This invention provides a battery charging equalization control method for battery swapping cabinets. In this embodiment, the execution mechanism for microcarrier generation and inner-loop power feedback adjustment in the underlying charging submodule specifically includes the following execution steps: In S1300, to map the theoretical duty cycle of the control domain to physical switching behavior, the local digital signal processor, upon receiving the target phase offset value and current reference command from the main control domain, immediately initiates the internal pulse width modulation micro-waveform reconstruction routine. Each power unit uses the aforementioned captured high-frequency hardware synchronization interrupt as the anchor point for zeroing or re-comparison of the internal counter, loading the allocated phase shift compensation value as the initial state into the high-resolution triangular wave generator in the core. Based on this benchmark, the control loop dynamically adjusts the comparison threshold according to the specific duty cycle requirements calculated by the inner loop, thereby driving the hardware comparison module to output alternating gate trigger level signals. Due to the inherent, non-eliminable charging and discharging junction capacitance time constant of wide-bandgap semiconductor devices, if the theoretical duty cycle directly output by the closed-loop algorithm is too narrow, it will induce internal dead-time logic chaos, resulting in metastable narrow pulses that cause shoot-through breakdown in the same bridge arm. Due to this physical limitation, before mapping floating-point control values ​​to carry-in values ​​in the hardware comparator registers, the processor forcibly performs non-linear saturation clamping operations based on hardware dead-zone boundaries, and must defend against extreme values ​​in the denominator. The underlying conversion relationship between duty cycle instructions and digital pulse width count values ​​has the following form: ; In the formula, Representative at the The discrete integer machine count value that is finally legally written into the specified timer reload compare register within a high-frequency calculation control cycle; This represents the continuously adjustable control voltage demand value calculated by the voltage and current dual closed-loop control feedback network. A digital scaling constant representing the amplitude of the triangular wave carrier wave, which is configured internally by the microprocessor. The non-zero minimum safety constant is set to provide a lower bound for division operations during program initialization or abnormal register clearing, thereby shielding the division-by-zero interrupt error of the kernel arithmetic logic unit. This represents the upper limit of the timer duty cycle that determines the fundamental frequency of the physical switch; This represents the constant offset of the count value calculated based on the bridge arm interlock dead time recommended in the complementary switch silicon wafer manufacturer's datasheet. By symmetrically introducing boundary barrier constraints to both sides of the duty cycle, the sub-power module can intercept singular out-of-bounds or flip-out extreme value instructions thrown due to algorithm transient divergence at the source of the underlying driver.

[0052] In S1400, after the multimodal routing matrix performs a dynamic topology reorganization under system commands, the parasitic distributed inductance of the physical wires connected in parallel to a specific common node and the equivalent ohmic polarization resistance of the battery cell group connected to the terminal will both experience transient step jumps. If the underlying power unit continues to operate the fixed linear proportional-integral (PI) static feedback gain for voltage regulation control, such nonlinear impedance abrupt changes will induce continuous high-frequency oscillations or large-area bias instability in the micro-loop during the initial stage of operation. To achieve impedance jump feedforward adaptation, this embodiment embeds a lightweight dynamic feedforward gain adjustment neural network model in the local flash memory area of ​​the sub-power unit. This gain adjustment neural network model is dedicated to analyzing the gradient evolution of the error over time, and inferring and superimposing the nonlinear correction factor of the feedback reference gain parameter in real time.

[0053] Regarding the core data flow and internal architecture of this diagnostic model, the gain-adjusting neural network model primarily employs a lightweight multilayer perceptron (MLP) front-end spatial topology. Its hierarchical structure consists of: a 3D input layer performing data standardization preprocessing; a hidden processing layer deploying dual-column eight-node neurons and relying on the ReLU function for unidirectional half-region activation; and a single-path feature convergence layer containing smooth nonlinear output. To avoid feature aliasing interference caused by noise in different frequency bands, all input data in the model's input layer is forced to trigger the corresponding analog-to-digital conversion interrupt at the valley point of the main timer count to ensure timely sampling and that multi-source physical quantities are under strict timing alignment. The specific sequence of elements collected for the input tensor includes: the measured value of the control voltage deviation in the current steady-state cycle purified by a hardware low-pass resistor-capacitor filter network; the backward differential rate of change of this deviation calculated within the cycles of two adjacent action edges; and the total number of active modules currently integrated into the parallel topology group, obtained through high-speed bus addressing and monitoring.

[0054] The hidden layer projects the aforementioned physical features with nonlinear jumps onto a high-dimensional diagnostic plane based on the synaptic weight matrix, and calculates the correction factor coefficients for the controller's proportional gain through the output layer neurons. To eliminate the huge computational conflict between the complex nonlinear floating-point network calculation and the microsecond-level high-frequency switching control cycle, this embodiment establishes an "asynchronous multi-rate decoupling control mechanism" in the local control kernel. Specifically, the gain adjustment neural network model runs in the microprocessor's secondary task stack, asynchronously reading feature quantities at millisecond-level intervals and continuously refreshing the output proportional and integral correction factors, safely overwriting them into the dual-port high-speed memory pool. At the same time, the voltage and current high-frequency inner loop regulator running in the highest priority hardware interrupt does not participate in the AI ​​calculation at all, but directly calls the latest correction factor already fixed in the memory pool, performing an extremely fast single-instruction multiply-accumulate operation.

[0055] To ensure the reconstructed closed-loop physical circuit possesses absolute Lyapunov boundary stability, the final output correction gain is uniformly bounded within a safety factor range of 0.5 to 1.8 using a Sigmoid variant function to intercept feedback overflow from the algorithm itself. The static network weights of the model are obtained through offline training and calibration on a hardware-in-the-loop (HIL) high-frequency test platform of the same specifications matched to the control motherboard. The platform batch-extracts transient voltage and current characteristic traces under extreme impedance jump conditions as the original sample source, and the optimal critical damping adjustment coefficient calculated based on the Bode plot frequency domain phase margin constraint is designated as the offline data label. The training loop uses mean squared error (MSE) as the dominant loss function and employs a stochastic gradient descent algorithm with a first-order momentum acceleration strategy to backtrack and correct the weights of internal hierarchical nodes until the transient tracking error index for the test set is reduced to the specified per-unit control tolerance band, at which point the output deployment is solidified.

[0056] With the support of real-time AI memory parameter delivery under the above decoupled architecture, the adjustment law of the power drive architecture during topology replacement is visualized as the following differential drive control equation: ; In the formula, This represents the original reference offset that the microprocessor intends to output after completing the internal closed-loop adjustment calculation process in the current high-frequency beat cycle. and These represent the baseline proportional quantization coefficient and the baseline integral quantization gain constant, respectively, which were calibrated offline for the open-loop Bode plot characteristics of a single module under rated dead zone conditions before the equipment was put into operation. and This represents a dynamic gain adjustment correction factor calculated by the asynchronous background neural network forward and pre-stored in high-speed memory. This represents the period difference between the system-level target setpoint and the measured digital signal obtained by the analog-to-digital converter after conversion and sampling. This corresponds to the discrete time step constant triggered by a single control interrupt. Based on this reconfiguration gain adjustment mechanism, each sub-power module can mitigate transient voltage overshoot at the common bus port by relying on its characteristic dynamic convergence damping deviation during the microsecond-level initial period of switching.

[0057] In the S1500 system, during the global safety scheduling and abnormal circuit breaker protection phases, the main control unit dynamically assesses and disconnects abnormal power modules by polling the fault diagnosis messages of each node. However, in complex electromagnetic interference environments or under high-concurrency data throughput conditions on multi-node buses, the microprocessor's software execution flow faces potential risks of stack overflow, deadlock, or communication bus silence. Once the upper-level control kernel crashes, the original protection logic based on software code and AI algorithms will be completely paralyzed, easily leading to disordered energy collisions between power units and the disordered bus grid.

[0058] Therefore, in this embodiment, a nanosecond-level bypass hardware interlocking and three-state isolation mechanism that does not rely on any microprocessor software computing power is independently and parallelly deployed in the underlying physical link of the multimodal power routing matrix as an inviolable security bottom line for the system.

[0059] Specifically, each power unit's underlying driver board integrates a nanosecond-level analog comparator network and an independent hardware watchdog circuit via hardwired connections. The analog comparators are directly connected across the high-precision shunt and bus capacitors of critical power buses, using purely analog circuitry to monitor in real-time for short-circuit overcurrents or avalanche overvoltages exceeding physical limits. Simultaneously, the independent hardware watchdog continuously captures periodic heartbeat pulses from the main control unit via a dedicated edge monitoring pin. These underlying hardware monitoring signals are directly fed into a fail-safe array (such as a CPLD or high-frequency logic gate chip) composed of purely combinational logic gates, which calculates and outputs enable flags for the global hardware pins of that module in real-time. .

[0060] The enable flag remains high only if all physical security boundaries are not triggered and the communication heartbeat remains active. Its pure hardware combinational logic Boolean equation mapping is as follows: ; In the formula, Representing the j The extreme overcurrent hardware fault latch level signal of each power module is captured by a nanosecond-level analog comparator; This represents the corresponding extreme overvoltage hardware fault latch level signal; This flag represents the valid heartbeat level monitored by the hardware watchdog. If the microprocessor crashes or communication is interrupted, causing the heartbeat to time out, this flag will automatically drop to logic zero without software control. This represents the highest priority disaster interlock disconnect signal triggered by a global manual mechanical emergency stop or a physical collision sensor.

[0061] Because this mechanism completely bypasses the software code execution instruction cycle and bus communication latency, once any of the above fatal exceptions occurs, the hardware enable flag will be activated. It will be pulled down to zero within tens of nanoseconds. Linked to the underlying drive equation in the aforementioned S900 step, regardless of what drive command is issued by the main control unit or AI algorithm at this time, the underlying logic gate will forcibly block all gate drive and coil excitation signals, causing the drive pin to instantly drop to a high-impedance state (tri-state isolation). In the event of extreme hardware or software failure, this mechanism can instantly cut off all physical connections of the multi-mode power routing matrix, completely avoiding the risk of thermal runaway caused by system malfunction from the hardware root.

[0062] This invention provides a battery charging equalization control method for battery swapping cabinets, which, at the level of the basic energy intake system connecting the external power grid and the internal reconfiguration topology, specifically includes the following execution steps: The S1600, addressing the physical energy acquisition link for the cabinet's basic energy, features a high-power active front-end rectifier at the front end of the power distribution bus system. This rectifier connects to the mains power grid via a three-phase AC interface and is responsible for converting the alternating power from the grid side into constant high-voltage DC power on the central DC bus, providing a steady-state energy pool for all subsequent intelligent charging sub-units. The main control system continuously monitors the instantaneous values ​​of the three-phase AC voltage and line current using a Hall sensor array deployed on the grid side. To remove the distorted reactive and harmonic components from the grid voltage, the microprocessor's built-in software algorithm projects the electrical parameters in the three-phase stationary coordinate system onto a coordinate system that rotates synchronously with the grid's fundamental frequency using a Parker transformation. In an orthogonal two-phase vector coordinate system. Based on the acquired... The active component of the shaft and The system establishes a decoupled control benchmark for grid-side energy intake based on the shaft reactive component. Regarding the grid-side phase-locked loop (PLL) phase tracking extraction method and the underlying switch sequence allocation mechanism of the space vector pulse width modulation (SVPWM) generator that this system relies on for operation, those skilled in the art can configure the software library according to conventional digital power control specifications. The underlying derived logic is well-known in the field and will not be elaborated upon here.

[0063] During normal system operation, the S1700 distribution bus, constrained by the capacity limit of the transformer at the site, must strictly enforce dynamic threshold blocking on the output power of its internally deployed busbars. The main control module periodically aggregates charging power demands submitted by each terminal unit via a high-speed industrial bus. To prevent multiple units from simultaneously reaching full load, causing the external network input circuit breaker to trip, the digital controller internally employs a calculation framework based on physical extreme value limiting for the given active current of the dd axis. This limiting calculation not only considers the upper limit of logical allocation but also forcibly counteracts abnormal zero-value measurements caused by external network faults. The corresponding instruction generation equation satisfies: .

[0064] In the formula, Representative at the The global total active power limit command value that the grid-side rectifier is allowed to extract within each control cycle; This represents the total number of physically inserted and legally verified batteries currently available for charging. Representing the The specific power replenishment requirements parameters uploaded by each battery node; This represents the rated physical allocation limit constant of the transformer at this site, which is issued by the cloud platform. This represents a safety derating factor that is negatively correlated with ambient temperature or the temperature of the internal heat sink of the device. As a safety setting criterion in this embodiment, when the temperature reported by the miniature temperature probe inside the chamber exceeds 75°C, this derating factor will decrease non-linearly at a slope of 0.05 per degree Celsius until it approaches zero to prevent thermal runaway of the power devices.

[0065] Based on the characteristics of the S1800's internal topology routing matrix during large-scale cross-compartment switching operations, it can be seen that such high-frequency switching behaviors are equivalent to an extremely severe impedance drop and energy surge from the bus side. Relying solely on the traditional bus voltage outer loop for hysteresis tracking will result in unacceptable transient voltage sags, which may even trigger the underlying undervoltage protection lockout in severe cases. As a preferred feedforward approach, the system microcontroller incorporates a load feedforward compensation model based on a one-dimensional convolutional neural network (1D-CNN) to extract transient load characteristics and generate advanced energy injection commands.

[0066] This load feedforward compensation model employs a deep learning architecture tailored to time series identification. Its structure includes an input layer performing sliding window truncation, a feature extraction layer with two parallel one-dimensional convolutional kernels (each kernel being a typically 3×1 size), a global average pooling layer for noise smoothing, and an output layer performing final numerical regression via a fully connected network. To ensure strict time-domain alignment between the periodic fluctuation data from the three-phase AC grid and the megahertz-level RF communication data within the cabinet, all data fed into the input layer is synchronously resampled within the zero-crossing interruption captured by the grid-side AC voltage phase-locked loop. The aligned input feature tensor contains three dimensions: the first-order differential slope of the cabinet's power demand, the current drop depth of the DC bus ripple voltage, and the temperature rise coefficient of the bus support capacitor smoothed by mean filtering.

[0067] Before deployment and commissioning, the model's internal synaptic weights needed to be calibrated and trained offline on a high-fidelity physical-in-the-loop (HIL) AC / DC pairing test bench. The test platform simulated tens of thousands of extreme boundary conditions, including extreme cold, high temperature, and various nonlinear large-load step access scenarios. The model training employed the Huber loss function, which, when the error is small, represents a squared error to ensure steady-state accuracy, and transforms into an absolute error to resist gradient explosion interference from outliers when encountering severe grid surges that cause excessive instantaneous prediction deviations. An RMSprop optimization algorithm incorporating momentum terms was used to inversely update the convolutional kernel parameters until the network output could accurately compensate for the gap in the early stages of load switching abrupt changes, ensuring that the physical bus drop deviation under the closed-loop system was suppressed within 2% of the engineering rated standard before the weights were solidified. Using this type of prediction model, the output layer ultimately outputs one-dimensional continuous floating-point parameters. This refers to the predicted feedforward compensation power limit.

[0068] After completing the traditional steady-state voltage feedback closed-loop calculation and the feedforward calculation of the aforementioned transient artificial intelligence prediction model, the S1900 microprocessor algebraically adds these two independent and time-orthogonal control currents, transforming them into a physical tracking target ultimately applied to the inner loop of the base current. To ensure the safety of the microcontroller's logic unit, it is necessary to avoid numerical overflow collapse that may be caused by transient drops on the external grid side. The final formula for the derived active current reference quantity is as follows: ; In the formula, Representing the Control timing is sent to the space vector modulator inside the grid-side rectifier. Final reference value for shaft command current; Represents the anti-steady-state error integral current component generated in real time by the system's outer PI loop with the target steady-state DC bus voltage rating; 1.51.5 is the fixed physical conversion factor under the synchronous rotating coordinate system equal power transformation; This represents the real-time feedback from the front-end power grid extracted via the Parker transform. Amplitude of the active voltage component along the shaft; The non-zero isolation baseline constant is defined. Its physical meaning is that when the external power grid experiences a lightning strike or phase-to-phase short circuit, the depth transient drops to near zero volts, providing a mathematical lower bound for the underlying divider, thereby physically intercepting the system from throwing out an infinitely large crash illegal instruction operator. A bidirectional saturation limiting cutoff term is set for the combination of hardware and software; The red line constant represents the physical extreme value of thermal breakdown current, which is defined by the combined parameters of the hardware heat sink and the IGBT power semiconductor. Through multi-source feature extraction and dual-channel parallel energy intake scheduling, the power distribution bus can establish a solid isolation zone by relying on deterministic safety barriers and flexible AI pre-judgment under the dual pressure of continuous frequency conversion demand from micro sub-units and random drops in the external power grid, which greatly enhances the robustness of the whole system to complex power grid characteristics.

[0069] This invention provides a battery charging equalization control method for battery swapping cabinets. In this embodiment, the execution mechanism for maintaining the acquisition of underlying basic physical parameters and multi-dimensional state evaluation specifically includes the following execution steps: To achieve efficient coupling between the multimodal energy network and the physical load, the S2000's main control domain is equipped with independent front-end sensor acquisition sub-nodes in each isolated compartment, based on the specific physical compartment structure of the battery swapping cabinet. Each compartment terminal includes quick-connect mechanical terminals for the main circuit used to support large-span high-voltage DC transmission, and a high-sensitivity thermistor matrix that fits tightly into the heat-pressed joints of the connecting cables. Based on the digital communication layer design, the compartment base is equipped with independent differential communication bus transceivers to wake up and periodically read the safety messages broadcast by the target power battery's built-in battery management system (BMS). Regarding the underlying baud rate adaptive handshake logic and general data frame structure parsing mechanism of the Controller Area Network (CAN) bus communication protocol within the battery swapping cabinet compartments, those skilled in the art can call and configure software library routines according to conventional new energy charging interconnection protocol specifications. Its network layer data unpacking and verification mechanism is a well-known technology in the field and will not be elaborated upon here.

[0070] In the S2100, when the multi-source composite sensor network is in continuous monitoring mode, high-frequency common-mode interference spikes induced by high-power matrix reassembly will couple to the sampling front end via parasitic capacitance. If strict time-domain alignment is not performed on the multi-dimensional data, small drops in the main circuit voltage and fluctuations in local temperature measurement will result in phase misalignment, leading to complete distortion of subsequent impedance calculations. To suppress the above interference mechanism, this embodiment constructs a global timestamp latch synchronization strategy based on the general-purpose hardware timer of the main control unit. High-precision analog-to-digital converters mounted on the same digital acquisition bus trigger forced sampling at the same microsecond-level cross-section when the underlying high-frequency isolation handshake pulse flips, and push the synchronization state quantity captured by the hardware interrupt into an alignment buffer queue with a first-in-first-out rule. After completing the synchronization alignment loading, the microprocessor calculates the dynamic contact impedance of the directly connected mechanical terminals in the compartment in real time based on the power supply voltage difference and the real-time current closed-loop value of the circuit. To avoid the illegal interruption exception of the core arithmetic logic unit caused by the extremely weak freewheeling current due to the topology's natural turn-off, the conversion process of contact impedance is designed to follow the following discrete calculation formula with a clamping baseline: ; In the formula, Representative at the The equivalent on-resistance value of the target connector component calculated by the system microprocessor within each measurement frame period; This represents the measured relative high potential reference value allocated to the beginning of the power distribution feeder in this warehouse. This represents the measured low potential at the battery receiving interface captured by the isolated sensor network after crossing the physical connection terminal; the core purpose of subtracting these two voltage parameters is to eliminate the additional interference of the inherent ohmic voltage drop of the long busbar line on the local endpoint impedance derivation. It represents the absolute amount of physical current that is synchronously latched and flowing through the current charging branch at the current calculation moment; This represents a small tolerance reference parameter for zero-point correction, which is fixed in the underlying digital logic. Considering the background zero-point temperature drift characteristics and modular quantization error of the signal conditioning operational amplifier at the sensor backend, this constant is typically preset between 0.5 amps and 1.5 amps. The physical purpose of introducing this lower bound is to forcibly block the irrational infinite impedance output caused by weak leakage current background noise fluctuations during no-load sleep conditions, providing a stable mathematical support for division calculations throughout the entire link.

[0071] Based on the mechanical material decay characteristics, after long-term, complex plug-in / plug-out cycles, the copper-based connectors in large commercial battery swapping cabinets inevitably suffer from mechanical fatigue scratch amplification and oxidation corrosion caused by high-voltage arc interruption. Traditional monitoring logic typically relies on a single absolute high-temperature threshold for passive fuse failure determination, which has significant lag. As a preferred proactive intervention method, this embodiment deploys a temporal convolutional predictive neural network model (TCN model) in the memory blocks of each module's microcontroller to detect the physical decay envelope characteristics of the terminal. This model uses multi-dimensional historical time series to deduce the hidden local connector thermal runaway critical risk.

[0072] At the digital topology level, the TCN prediction model is divided into multi-layer cascaded processing modules. Its front end includes an input layer that performs data channel fusion, while the middle and rear cascades contain two sets of core hidden extraction layers with dilated causal convolution operations. This architecture can effectively expand the receptive field for slowly decaying physical quantities without increasing network depth. The core layers have parallel skip-type residual network connection branches to combat long gradient vanishing, and the final layer uses a multilayer perceptron (MLP) with finite-amplitude activation mapping to perform linear regression operations on future temperature rise risk indicators.

[0073] In the forward inference pipeline of this system, the network extracts a 3D input state tensor within a sliding time window at fixed step sizes. The specific dimensions of this input tensor are... The two-dimensional feature matrix, where The historical frame count of the sequence is represented (in this embodiment, it is generally set to 128 consecutive calculation cycles based on system memory capacity). The physical representations of these three specific input channels are as follows: the first channel takes in the recent discrete contact impedance value after Z-score standard normalization. The second channel inputs a dimensionless wear ratio coefficient obtained by dividing the cumulative number of triggers of the in-cabin mechanical limit switches by the rated number of plug-in / plug-out cycles of the connector. The third channel inputs the background relative temperature rise gradient value measured by the cabin probe after Kalman filtering to remove white noise. After causal convolution operation, the network output layer outputs a scalar rating result in the range of 0 to 1. Its business meaning corresponds to the probability index that the insulation structure of the contact will soften due to heat within the next 100 working cycles.

[0074] Before on-site deployment, the R&D team completed labeled supervised training of the network weights on an offline high-order pneumatic insertion and removal fatigue verification bench. The system continuously recorded hundreds of thousands of data spectra throughout its entire lifecycle, from brand new manufacturing to impedance abrupt changes and even degradation, to construct the sample source. The actual input labels were determined based on the actual peak temperature range of the contact micro-element surface captured by a synchronously connected high-resolution infrared thermal imager under current pulse conditions. The training loop specified an error calculation method combining the Huber function as the loss criterion, ensuring the quadratic convergence rate of the normal deviation segment while using absolute value constraints to smooth out the large penalty gradients generated during sudden local micro-discharge periods. Parameter backpropagation used the Adam optimizer, initially configured to 10. -3 The adaptive learning rate is used to iterate through multiple batches until the mean square error (MSE) of the end-of-life risk assessment probability in the test set drops below the preset control tolerance of 0.05. Then, the network is solidified to generate a prediction model matrix that matches the hardware specifications.

[0075] In the S2300, to accurately map the predictions of the intelligent model into physical control actions, the state sensor network, after completing the underlying parameter alignment and degradation probability assessment, immediately pushes the packaged state features to the uplink allocation center. The master control decision unit then utilizes the received degradation probabilities of each independent charging sub-node. A current limit penalty with dynamic damping tendency is imposed on specific nodes. The model-based prediction derating compensation constraint formula is specifically set as follows: ; In the formula, The main control unit will send data to the next reconfiguration and allocation cycle. The maximum restricted instruction current base amount for authorized circulation at the potential deterioration node; Refers to the rated maximum peak current carrying capacity constant of the contact terminal as defined in the original manufacturer's structural specification; The derating penalty proportional gain coefficient is obtained through measured closed-loop thermodynamic calibration, thereby establishing a linear reduction mapping from degradation risk to physical flow suppression intensity; This is the lower bound of the trickle current amplitude required to maintain the battery pack's own baseline communication and heartbeat maintenance. Relying on this dimensionality-reduced feedback correlation where the command output threshold is directly intervened by the edge prediction probability, the system master controller can selectively reduce the charging burden allocated to high-risk ports before executing multi-channel high-current grid-connected fast charging, thus constructing an automatic electrical safety margin guarantee mechanism at the hardware level to resist the thermal breakdown of components at the end of the period.

[0076] To more clearly illustrate the operating mechanism of the system and method of this invention in a real-world scenario, this embodiment takes a typical food delivery battery swapping station (rated total input power of 15kW, power units M=6, storage terminals N=8, single battery rated voltage 60V, capacity 30Ah) as an example to detail the system's execution process: During a peak period on a certain day At this moment, the batteries in compartments 1 to 4 are fully charged (SOC > 95%) and in trickle charging mode; compartments 5 to 8 are empty. A rider inserts a nearly depleted battery (SOC = 15%, temperature 35℃) into compartment 5 and scans a code requesting rapid charging within 40 minutes. The main control unit retrieves the battery message through the S100's ring data buffer. After evaluating its current polarization voltage and temperature using a neural network model (MLP), it outputs the safe charge acceptance rate boundary current for the battery. Meanwhile, due to its extremely short expected pick-up time, the algorithm assigns it the highest priority weight in the entire system for leaving the vehicle.

[0077] 1. Initial State and Input Acquisition: 2. Matrix Solving and Physical Reconstruction: The main control unit executes the S200 nonlinear programming solution. Since the rated current of a single module is 20A, the system Boolean adjacency matrix allocates power unit 1, power unit 2, and power unit 3 (a total of 3 physical branches) to serve bay 5 in parallel. Entering the S900 execution phase, the three power units first enter the no-load voltage following mode, anchoring their respective output port voltages to the actual battery terminal voltage (approximately 52.5V) fed back from bay 5. When the absolute value of the voltage difference stabilizes within 2V, the three physical relays of the multi-mode power routing matrix engage after the dead time, achieving perfect arc-free "zero-voltage difference grid connection".

[0078] 3. Phase shift interleaving and dynamic parameter compensation: Based on steps S300 and S800, the main control unit calculates the number of parallel branches to be 3, and the basic phase shift step size to be 360° / 3 = 120°. Through the nanosecond-level interrupt of the hardware high-frequency synchronous bus, the microprocessors of power units 1, 2, and 3 set their respective PWM carrier reference phase shifts to 0°, 120°, and 240°, thereby achieving perfect cancellation of the output current ripple on the busbar.

[0079] At this instant of parallel connection, the load impedance drops sharply (from no-load to the low-internal-resistance battery terminal with extremely high capacitance characteristics). According to step S1400, the asynchronous AI feedforward gain adjustment model in each cell instantly identifies the impedance change rate and temporarily reduces the proportional gain of the PI controller to 0.6 times, effectively suppressing the overshoot current that surges into compartment 5 at startup. Subsequently, it smoothly recovers to the steady-state gain within 50 milliseconds, ensuring that the system can safely fast charge with a full-load synthetic current of 45A.

[0080] To verify the superiority of the multi-dimensional fusion control strategy proposed in this invention, a 15kW hardware-in-the-loop (HIL) physical test platform was used based on the aforementioned embodiments. The comparison was made with a "traditional fixed PID constant current battery swapping system" that did not employ the AI ​​dynamic compensation and high-frequency synchronization strategy of this invention. The core experimental data are compared below: Experiment 1: Comparison of busbar voltage / current transient stability during multimodal routing matrix reconstruction: Traditional solution: When three power units are instantaneously connected in parallel to a battery compartment with a SOC of 15%, severe oscillations occur because traditional PI parameters cannot adapt to the step drop in physical impedance. Actual measurements show a bus voltage sag of up to 8.5V, an overshoot peak of 18A (40% exceeding the limit) in the charging current, and a recovery time as long as 120ms. Such repeated impacts easily damage relay contacts and puncture the battery SEI film.

[0081] The present invention (introducing S1400 neural network dynamic gain adjustment) achieves the following: Under the same reconstruction operation, the AI ​​model proactively issues a damping compensation factor to correct the PI parameters. The measured voltage sag is clamped within 1.2V, current overshoot is completely suppressed (overshoot amplitude < 2A), and the entire transient recovery time is shortened to an extremely short 15ms. This demonstrates that the system possesses absolute electrical smoothness under frequent matrix reconstruction conditions.

[0082] Experiment 2: The voltage stabilization effect of grid load feedforward compensation on DC bus: During the front-end S1800 stage, when the above-mentioned high-power grid connection action is initiated inside the battery swapping cabinet, it is equivalent to instantly drawing a large current from the power distribution bus.

[0083] Traditional solution: Relying solely on closed-loop feedback of the outer voltage, this causes a voltage drop of up to 35°C on the central DC bus (set to 400V) during sudden load increases. The drop of nearly 8.7% is approaching the red line of the bottom under-pressure protection.

[0084] The present invention utilizes a 1D-CNN load feedforward compensation model to convert the energy surge characteristics within the cabinet into active power feedforward commands for the grid-side rectifier several milliseconds in advance. Tests show that the DC bus drop under sudden full load is only [a certain percentage]. (Approximately 1.1%), significantly improving the rigidity and immunity of the power distribution bus.

[0085] Experiment 3: The effect of bottom-layer phase-shifted staggered wave generation on the suppression of charging ripple: Traditional solution: Since the three modules rely solely on CAN bus communication for startup, there is a latency of hundreds of microseconds, causing random overlap of the emitted waveforms. The measured peak-to-peak value of the high-frequency ripple of the charging current at the combined input slot 5 reached as high as 6.2A, which not only caused severe audible howling from the inductor but also increased battery heat generation.

[0086] The present invention utilizes the hardware decoupling and nanosecond-level hardware coaxial timescale capture of the S500, precisely locking the three units at 0°, 120°, and 240°. The measured peak-to-peak value of the equivalent current ripple after the current collection is drastically reduced to 0.8A (a decrease of over 87%), which not only significantly reduces the hysteresis loss of the magnetic components but also provides an extremely smooth, high-quality DC source for the accurate prediction of the lithium plating boundary at the bottom layer.

Claims

1. A battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network, characterized in that, include: Main control unit, power distribution bus, multiple power units, routing matrix and multiple warehouse terminals; The power distribution bus, the power unit, the routing matrix, and the warehouse terminal are sequentially electrically connected, and the warehouse terminal contains a battery to be charged. The main control unit communicates with the power unit, the routing matrix, and the warehouse terminal via a control communication bus, and is hardwired to the power unit via a physically isolated hardware synchronization bus. The main control unit is configured to generate a Boolean adjacency matrix based on the operating status data obtained through the control communication bus, and control the routing matrix to dynamically connect the power units to the corresponding warehouse terminals. A high-frequency reference pulse is sent to the power unit via the hardware synchronization bus to perform phase shift interleaving control on multiple power units connected in parallel to the same warehouse terminal.

2. The battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network according to claim 1, characterized in that, The routing matrix consists of an array of interconnected electrical switch nodes, used to establish a fully connected mapping path between the output sides of the multiple power units and the input sides of the multiple warehouse terminals.

3. The battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network according to claim 1, characterized in that, The specific configuration for the main control unit to generate the Boolean adjacency matrix is ​​as follows: The operating status data of the battery to be charged is obtained through the control communication bus. The operating status data includes the limit current value and the outbound priority weight value, and a global weighted demand vector is generated accordingly. Using the upper limit of the grid feed-in power and the physical node exclusivity mechanism as constraint boundary conditions, the planning solution is executed with the objective function corresponding to the global weighted demand vector as the direction, and the Boolean adjacency matrix is ​​generated.

4. The battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network according to claim 3, characterized in that, The power unit is internally configured with a pulse width modulation generator, and the main control unit performs phase shift interleaving control as follows: The algebraic sum of the elements in the Boolean adjacency matrix is ​​extracted column by column to obtain the total number of parallel branches of the power units allocated to each of the warehouse terminals; The system's basic phase shift angle is calculated based on the total number of parallel branches, and local sequence numbers are assigned among multiple power units connected in parallel to the same warehouse terminal to calculate the target phase offset. The underlying hardware of the power unit aligns with the high-frequency reference pulse, and the pulse width modulation generator is reset in conjunction with the target phase offset to output a composite waveform with phase shifts interleaved.

5. The battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network according to claim 1, characterized in that, When controlling the routing matrix, the main control unit is configured to execute a zero-difference matching verification mechanism: Send an open-circuit voltage following command to the power unit to be connected to the grid, so that it dynamically follows the measured polarization voltage of the battery terminal of the target warehouse terminal; Calculate the absolute difference between the actual voltage at the output port of the power unit and the measured polarization voltage at the battery terminal. When the absolute difference remains within the preset safe differential voltage tolerance threshold, establish zero differential voltage pull-in permission in the internal state machine.

6. A battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network according to claim 5, characterized in that, The main control unit is internally configured with low-level logic gate circuits; After establishing the zero-dropout pull-in permission, the main control unit integrates the node logic instructions of the Boolean adjacency matrix, the rated drive level threshold, the global hardware enable flag, and the logic flag representing the zero-dropout pull-in permission, and completes the pin level mapping through the underlying logic gate circuit to drive the electrical switch node corresponding to the routing matrix to close.

7. A battery charging equalization control method for a battery swapping cabinet based on a dynamic topology network, applied to a battery charging equalization control system for a battery swapping cabinet based on a dynamic topology network as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S10, the main control unit obtains the operating status data of the batteries to be charged in the warehouse terminal through the control communication bus, and performs planning and solving to generate a Boolean adjacency matrix; S20, according to the Boolean adjacency matrix, control the operation of the routing matrix to dynamically connect multiple power units in parallel to the corresponding warehouse terminal; S30, the main control unit calculates the target phase offset and transmits a high-frequency reference pulse to the power unit through a hardware synchronization bus to perform phase shift interleaving control on multiple power units connected in parallel to the same warehouse terminal.

8. A battery charging equalization control method for a battery swapping cabinet based on a dynamic topology network according to claim 7, characterized in that, Before the control routing matrix is ​​activated in step S20, the following steps are also included: Perform an XOR difference extraction operation between the Boolean adjacency matrix of the current control cycle and the historical matrix of the previous cycle to determine the set of power units whose states need to be changed. A zero-load command is issued to the power unit set. After the control loop current decays to the zero threshold, the routing matrix is ​​driven to perform a bridging action under no-current load conditions.

9. A battery charging equalization control method for a battery swapping cabinet based on a dynamic topology network according to claim 8, characterized in that, Before the control routing matrix operates in step S20, a voltage following matching step is also included: Send an open-circuit voltage follow command to the power unit to be connected to the grid, so that its output voltage reference value is dynamically anchored to the measured polarization voltage of the battery terminal of the target warehouse terminal; Only when the absolute difference between the output voltage reference value and the measured polarization voltage at the battery terminal is less than or equal to the preset differential voltage tolerance threshold, and the filtering anti-jitter time is continuously satisfied, is it permissible to drive the corresponding node of the routing matrix to close.

10. A battery charging equalization control method for a battery swapping cabinet based on a dynamic topology network according to claim 7, characterized in that, The specific steps in step S30 for calculating the target phase offset are as follows: Extract the algebraic sum of the elements column by column from the Boolean adjacency matrix to obtain the total number of parallel branches of the power units allocated to each of the warehouse terminals and calculate the system's basic phase shift angle; Local serial numbers are assigned among the multiple power units connected in parallel to the same warehouse terminal, and the target phase offset of each power unit is calculated based on the product of the system's basic phase shift angle and the local serial number.

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