A phase-shifted PWM modulation control method based on duty cycle scaling of upper and lower bridge arms

Abstract

The application provides a phase-shift PWM modulation control method based on duty cycle scaling, which realizes real-time dynamic adjustment of output duty cycle by introducing a duty cycle scaling mechanism, can be used for active equalization control of branch currents in a multiple interleaved topology, makes the current and thermal stress distribution of each branch device more consistent, and thus significantly improves the overall operation stability and long-term reliability of the system. The application supports a large range of phase shift and is suitable for various high-power multiple interleaved topology structures. The application does not require an external synchronization signal and can generate double-bridge-arm driving signals only by relying on a single PWM input, which significantly reduces the system implementation complexity, simplifies the control interface and saves control resources.

Description

Technical Field

[0001] This invention relates to the field of PWM modulation method technology. Specifically, it relates to a phase-shifting PWM modulation control method for upper and lower bridge arms based on duty cycle scaling, which is suitable for improving the current sharing characteristics of interleaved systems. Background Technology

[0002] In high-power applications such as photovoltaic grid-connected inverters, high-power DC / DC converters, and motor drives, interleaved structures are often used to improve output current capability and reduce ripple. As power levels increase, traditional two-level PWM struggles to balance efficiency, harmonics, and switching losses, while three-level topologies such as I-type and T-type are widely used due to their low device stress, low losses, and excellent harmonic performance.

[0003] In interleaved three-level systems, each phase typically operates at a fixed phase shift angle to increase the equivalent switching frequency and reduce bus ripple. However, during operation, factors such as phase drift, duty cycle deviation, device dispersion, and temperature variations can cause uneven current distribution in each branch, leading to local device overheating and decreased reliability. Traditional methods relying on synchronous clocks can only guarantee phase consistency and cannot compensate for duty cycle deviations caused by load disturbances or device aging, making it difficult to meet high dynamic current sharing requirements.

[0004] Therefore, there is an urgent need for a duty cycle scaling mechanism that can automatically adjust the high-level time according to the real-time current state while maintaining the phase shift relationship, and combined with reasonable dead-time control, to achieve a more stable current sharing effect. Leveraging the high-speed parallel computing, precise timing characteristics, and abundant I / O resources of FPGA, a duty cycle scaling-based phase-shifting PWM modulation control method for the upper and lower bridge arms is proposed. This method effectively improves the current sharing characteristics by scaling and shifting the duty cycle of the upper and lower bridge arms, thereby enhancing system efficiency and reliability. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention discloses a phase-shifting PWM modulation control method for upper and lower bridge arms based on duty cycle scaling.

[0006] The present invention solves its technical problem by adopting the following technical solution: A phase-shifting PWM modulation control method for upper and lower bridge arms based on duty cycle scaling, characterized by the following steps: The input-side PWM signal is denoted as input signal A, the output-side upper bridge arm PWM signal is denoted as output signal B, and the output-side lower bridge arm PWM signal is denoted as output signal C. The periodic boundary of the input signal A is defined as the trigger time of the first action. Based on the continuously triggered first actions, a first periodic sequence is constructed, denoted as... ; The periodic boundaries of both output signal B and output signal C are jointly defined as the trigger time of the second action. Based on the continuously triggered second action, a sequentially increasing second periodic sequence is constructed for output signal B and output signal C, denoted as... sequence; Wherein, the triggering time of the second action has a predetermined timing offset relative to the triggering time of the first action, causing the... The starting point of the sequence's period is relative to the time axis. The starting point of the sequence's period is shifted, thus causing the input signal A's period to... The period interval and the first period interval of output signal B and output signal C The periodic intervals are interleaved in the time domain; The trigger time for the first action is set to the high level of the input signal A and the counting of the beat counter. Reaching the preset threshold The input terminal may be the moment a valid rising edge is detected; after the first action is triggered, Counting with the phase-shifting beat counter All were reset to zero and the counting started again; Set the trigger time of the second action as Reaching the preset threshold two At the moment when the second action is triggered, first determine Is it 0? If the value is not 0, then the output signal B is set to high level, and the high level of the output signal B is used to start the count of the beat counter. Reset to zero and start counting again. If the value is 0, then the output signal B is set to low level; The triggering time for action three is set to the periodic sequence N when action three is triggered. When action three is triggered, the high-level beat count threshold two is calculated. ; The triggering time for action four is set to the periodic sequence M when action two is triggered; when satisfy If the input signal A is in a high-level state in the periodic sequence N+1, then action four will maintain the high level of the output signal B unchanged; otherwise, the output signal B will be set to a low level. After completing action four, After a delay at each beat point, perform action five: set the output signal C to a high level; This represents the number of frames corresponding to a single-sided dead zone. After action five is completed, then... After counting each beat point, perform action six: set the output signal C to low level; The threshold for the number of high-level beats that should be output within the periodic sequence M is 1.

[0007] Further improvements include the preset threshold. and preset threshold two It depends on the required functions and specific conditions.

[0008] Further improvements include the high-level beat count threshold two. The calculation method is as follows:

[0009] In the formula For the shift amount, This represents the scaling factor after shifting. , G S This represents the actual scaling factor, ranging from 0 to... G S <2.

[0010] Further improvements include a high-level beat count threshold. The calculation method is as follows: .

[0011] Further improvements include limiting the triggering timing of Action 3 to the same periodic sequence N as Action 1, with the latest triggering point not exceeding the last beat before the end of periodic sequence N. Action 3 is triggered immediately when a falling edge of input signal A is detected within periodic sequence N; if no falling edge is detected within the entire periodic sequence N, Action 3 is automatically triggered on the last beat before the end of periodic sequence N. In addition, if Action 1 detects that input signal A is low at beat 0 of periodic sequence N, Action 3 is forcibly triggered on the next beat after Action 1 is executed to ensure that the output side can enter the duty cycle calculation process in a timely manner.

[0012] A further improvement is that the triggering timing of the fourth action is limited to the same periodic sequence M as the second action. The latest triggering point must not be later than the penultimate beat before the end of periodic sequence M, and the earliest triggering point is the first beat after the execution of the second action; if the calculated value in periodic sequence N is... satisfy Furthermore, if the input signal A is determined to be at a high level in the periodic sequence N+1, then action four maintains the output signal B at a high level. When T is calculated in the periodic sequence N... hh_th satisfy When the output is high, the beat counter is activated. Count to target threshold T hh_th When the time is triggered, action four is set to low level for output signal B.

[0013] Further improvements require that actions five and six satisfy the following four rules: Rule 1: When input signal A has a duty cycle in both periodic sequence N and periodic sequence N+1, then in periodic sequence M, when When, execute actions five and six; when At that time, actions five and six are not executed; Rule 2: When the periodic sequence N has a duty cycle but the periodic sequence N+1 does not, only action 5 is executed, and action 6 is not executed; when At that time, action five is executed in the periodic sequence M; when At that time, action five, which was executed in periodic sequence M, is postponed to the next action in periodic sequence M+1. Execution by shooting; The calculation formula is:

[0014] Rule 3: When there is no duty cycle in periodic sequence N but there is a duty cycle in periodic sequence N+1, execute action 6 in periodic sequence M, but do not execute action 5; action 6 is executed in the periodic sequence M. Execution by shooting; Rule 4: When the input signal A in both periodic sequence N and periodic sequence N+1 has no duty cycle, actions 5 and 6 will not be executed in periodic sequence M.

[0015] Further improvements are made to ensure that actions five and six are executed precisely according to the set phase shift period. Constraints are placed on the number of phase shifts to ensure that the trigger points of actions five and six are within a valid modulation window. The constraints are as follows:

[0016] Action three in periodic sequence N must precede action four in periodic sequence M. The following constraints must be satisfied: .

[0017] Further improvements include pre-calculating G on the DSP side. Specifically, the DSP amplifies the calculated scaling factor according to its corresponding decimal value and outputs it in fixed-point format. When the DSP acquires the interleaved branch inductor current I... L1 with I L2 Then, the updated G is obtained through the PI control algorithm and sent to the FPGA through the SPI interface. Upon receiving the updated G, the FPGA updates the output signal B and the output signal C in real time, thereby realizing closed-loop modulation control.

[0018] Compared with the prior art, the present invention has the following main advantages: 1. This invention supports a wide range of phase shifts and is applicable to various high-power multi-interleaved topologies.

[0019] 2. This invention does not require an external synchronization signal and can generate a dual-bridge arm drive signal by relying only on a single PWM input, which significantly reduces the complexity of system implementation, simplifies the control interface, and saves control resources.

[0020] 3. This invention achieves real-time dynamic adjustment of the output duty cycle by introducing a duty cycle scaling mechanism, which can be used for active equalization control of the current of each branch in a multi-interleaved topology, making the current and thermal stress distribution of each branch device more consistent, thereby significantly improving the overall operational stability and long-term reliability of the system. Attached Figure Description

[0021] Figure 1 Signal connection diagram.

[0022] Figure 2 Example 1: FPGA input and output PWM waveform diagrams.

[0023] Figure 3 Example 2: FPGA input and output PWM waveform diagrams.

[0024] Figure 4 Example 3: FPGA input and output PWM waveform diagrams. Detailed Implementation

[0025] The method provided by the present invention will be further described below with reference to specific embodiments. This is only for illustrating the technical concept and features of the present invention, and does not constitute any limitation on the present invention.

[0026] In this invention, the DSP is responsible for generating and outputting PWM signals to the FPGA. The PWM uses a rising edge counting mode, and the switching frequency is set to 10 kHz. The counter sets the PWM signal high when the count value is 0, and pulls the PWM signal low when the count value reaches a set comparison value. The FPGA's system clock frequency is 30 MHz, corresponding to a counting range of 0 to 2999 for a single PWM cycle.

[0027] In this embodiment, the duty cycle scaling factor G of the output PWM is pre-calculated by the DSP. Specifically, the DSP amplifies the calculated scaling factor by a factor of 32768 and outputs it in fixed-point format, so the quantization bit width of this factor is 15 bits. When the DSP acquires the interleaved branch inductor current I... L1 with I L2Then, the updated scaling factor G is obtained through a PI control algorithm and sent to the FPGA via the SPI interface. Upon receiving the new scaling factor, the FPGA updates the output PWM in real time, thus achieving closed-loop modulation control. The signal interaction and connection relationships of the system are shown in Figure 1.

[0028] Example 1: Considering the number of beats in a cycle T prd = 2999, Phase Shift Number T ps_th = 999, Dead Zone Number of Beats T dz_th = 39. For example... Figure 2 As shown, within period N, the first action is triggered when the rising edge of the input signal A is detected, and the high-level input beat counter T is activated. D Phase Shift Counter Reset to zero and restart the count.

[0029] when When the count reaches the set threshold of 999 from 0, the second action is executed in the next clock cycle. This is because the high-level clock counter T inputs the PWM at this time... D Since the input signal is no longer zero, the second action sets the output signal B to a high level. Furthermore, the input signal A remains high when the second action occurs, therefore T must be satisfied. ps_th <T D In this embodiment, the high-level duration T of input signal A is... D The final count is 1499, from which we obtain T. ps_th <T D In T ps_th <T D Under the given conditions, the scaling factor G must satisfy the following constraints:

[0030] In this embodiment, the scaling factor G is set to 34100. After the input signal A goes low within period N and triggers action three, the number of high-level beats T of the output signal B within period M is obtained. hh_th for:

[0031] From this, we can further deduce the number of beats T that the output signal C should maintain at a high level within the period M. lh_th for:

[0032] Therefore, when the high-level beat counter When the value increases to 1559, action four is triggered. Action four switches the output signal B from high level to low level.

[0033] Since the input signal A has an effective duty cycle in both period N and period N+1, and according to the aforementioned calculation results, the conditions for output signal C are met within period M, actions five and six will be triggered sequentially according to rule one, thereby generating the corresponding drive signal for output signal C.

[0034] Example 2: Considering the number of beats in a cycle T prd = 2999, Phase Shift Rate (Preset Threshold 2) = 1499, Dead Zone Rumble Count = 39. As shown in Figure 3, based on the state transition of the input signal A, the following two typical cases can be distinguished: For scenario one, the first action is triggered when a rising edge of input signal A is detected within period N-1. At this time, the high-level input beat counter T is activated. D Phase-shifting beat counter T ps Reset to zero and restart the count.

[0035] when When the count reaches 1499, the second action is triggered in the next beat. This is because the high-level pulse counter T inputs the PWM signal at this time. D Since the input signal is no longer zero, the second action will set the output signal B to a high level. And because the input signal A is still high when the second action occurs, therefore... <T D When input signal A switches from high level to low level and triggers action three, the final duration T of the high level of input signal A in period N-1 is obtained. D = 2850, scaling factor G is 34500, satisfying the constraints. This can be based on T. D Using the scaling factor G, we obtain the number of high-level target beats T of the output signal B during period M-1. hh_th Since the value is 2999, the output signal B remains high throughout the output period M-1. Therefore, action four is triggered at the last beat before the end of period M-1, i.e., the 2999th beat of period M-1. Simultaneously, since input signal A is high during period N, action four maintains the high level of output signal B. Because T... hh_th =2999, so the number of high-level beats of the output signal C within the output period M-1 is 0. On the other hand, since the input signal A in both period N-1 and period N has an effective duty cycle and satisfies the triggering condition of rule one, actions five and six are not executed within period M-1.

[0036] When the rising edge of input signal A is detected, the first action of period N is triggered, and T is simultaneously...D With T ps The count is reset and restarted. When Tps reaches 1499, the second action is triggered on the next beat. This is because the beat counter T is at a high level at this time. D Since the input signal is already greater than zero, the second action sets the output signal B to a high level. The input signal A remains high throughout period N; therefore, the third action is not triggered midway, but rather automatically triggered at the last beat before the end of period N. Based on the aforementioned calculations, we can obtain... , Therefore, action four will be triggered at the last beat before the end of output cycle M. Furthermore, since the input signal A is still at a high level during the first action determination in cycle N+1, the output signal B will remain at a high level after action four is triggered. On the other hand, input signal A has an effective duty cycle in both cycle N and cycle N+1, satisfying the constraint condition of rule one; therefore, actions five and six do not need to be executed in cycle M.

[0037] When the rising edge of input signal A is detected, the first action of period N+1 is triggered, and T is simultaneously... D and The count is reset and restarted. When Tps reaches 1499, the second action is triggered on the next beat, because the high-level pulse counter T is input to the PWM at this time. D Since the input signal is no longer zero, the second action will set the output signal B to a high level. When a falling edge of the input signal A is detected within period N+1, action three will be triggered immediately, resulting in the number of level beats T. D The value is 2900. Since the scaling factor is 33500 in period N+1, based on the number of high-level pulses T at the input... D T is calculated using the scaling factor G. hh_th With T lh_th The values ​​are 2964 and 0 respectively. Therefore, according to action four, it is triggered at the 2964th beat of period M-1, and the output signal B is set to low. As shown in the diagram, period N+1 has a duty cycle while period N+2 does not. Based on rule 2, combined with... Action 5, which was executed in period M+1, is then carried over to the 5th beat of period M+2.

[0038] For scenario two, the processes of generating output signals B and C based on input signal A in periods N-1 and N are basically the same as the steps described above, so they will not be repeated here.

[0039] In cycle N+1, when Tps counts to 1499, the second action is triggered in the next cycle; since the input is high-level, the cycle counter T is activated at this time. DSince the value is already greater than zero, the second action sets the output signal B to a high level. Subsequently, when a falling edge is detected in signal A, the action is immediately triggered, and based on this, T is taken. D =2830, G=34000, T can be calculated. hh_th With T lh_th The values ​​are 2936 and 0 respectively. Therefore, when the output signal B is high, the beat counter... When the count reaches the target threshold of 2936 from 0, the next step triggers action four, setting the output signal B to a low level.

[0040] In period N+2, the first action detects that the input signal A is at a low level, so according to rule two, combined with... Given the condition, action five is executed in period M+1, but action six is ​​not executed.

[0041] Example 3: Considering the number of beats in a cycle T prd = 2999, Phase Shift Number T ps_th = 999, Dead Zone Number of Beats T dz_th = 39. As shown in Figure 4, since the input signal A remains at a low level during periods N-1 and N, the output signal B also remains at a low level during these two periods. Meanwhile, since the input signal A has switched from a high level to a low level before period N-1, according to the processing logic of case 2 in Embodiment 2, the output signal C remains at a high level during periods M-1 and M.

[0042] Depend on Figure 4 It can be seen that period N has no duty cycle while period N+1 has a duty cycle, and the input signal A switches from the normally low mode to the normal mode. According to rule three, in the output period M, action six should be executed instead of action five, and action six is ​​executed at the Tth time in period M. prd - T dz_th The shooting will proceed at the designated location.

[0043] In summary, this invention, based on a single-channel PWM input, achieves the reconstruction of the dual-bridge arm drive signal output by scaling and phase-shifting the input PWM signal, and enables real-time dynamic adjustment of the output duty cycle. This method can be applied to multiple parallel interleaved topologies to achieve active current sharing control of each power branch current, reducing the hardware resource requirements of the control system and significantly improving the system's operational stability and long-term reliability.

[0044] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. Other modifications can be easily made by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A phase-shifting PWM modulation control method for upper and lower bridge arms based on duty cycle scaling, characterized in that, Includes the following steps: The input-side PWM signal is denoted as input signal A, the output-side upper bridge arm PWM signal is denoted as output signal B, and the output-side lower bridge arm PWM signal is denoted as output signal C. The periodic boundary of the input signal A is defined as the trigger time of the first action. Based on the continuously triggered first actions, a first periodic sequence is constructed, denoted as... ; The periodic boundaries of both output signal B and output signal C are jointly defined as the trigger time of the second action. Based on the continuously triggered second action, a sequentially increasing second periodic sequence is constructed for output signal B and output signal C, denoted as... sequence; Wherein, the triggering time of the second action has a predetermined timing offset relative to the triggering time of the first action, causing the... The starting point of the sequence's period is relative to the time axis. The starting point of the sequence's period is shifted, thus causing the input signal A's period to... The period interval and the first period interval of output signal B and output signal C The periodic intervals are interleaved in the time domain; The trigger time for the first action is set to the high level of the input signal A and the counting of the beat counter. Reaching the preset threshold The input terminal may be the moment a valid rising edge is detected; after the first action is triggered, Counting with the phase-shifting beat counter All were reset to zero and the counting started again; Set the trigger time of the second action as Reaching the preset threshold two At the moment when the second action is triggered, first determine Is it 0? If the value is not 0, then the output signal B is set to high level, and the high level of the output signal B is used to start the count of the beat counter. Reset to zero and start counting again. If the value is 0, then the output signal B is set to low level; The triggering time for action three is set to the periodic sequence N when action three is triggered. When action three is triggered, the high-level beat count threshold two is calculated. ; The triggering time for action four is set to the periodic sequence M when action two is triggered; when satisfy If the input signal A is in a high-level state in the periodic sequence N+1, then action four will maintain the high level of the output signal B unchanged; otherwise, the output signal B will be set to a low level. After completing action four, After a delay at each beat point, perform action five: set the output signal C to a high level; This represents the number of frames corresponding to a single-sided dead zone. After action five is completed, then... After counting each beat point, perform action six: set the output signal C to low level; The threshold for the number of high-level beats that should be output within the periodic sequence M is 1.

2. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, The preset threshold and preset threshold two It depends on the required functions and specific conditions.

3. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, The high-level beat count threshold two The calculation method is as follows: ; In the formula For the shift amount, This represents the scaling factor after shifting. , G S This represents the actual scaling factor, ranging from 0 to... G S <2.

4. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, High-level beat count threshold 1 The calculation method is as follows: 。 5. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, The triggering timing of Action 3 is limited to the same periodic sequence N as Action 1, and the latest triggering point is no more than the last beat before the end of periodic sequence N. When a falling edge of input signal A is detected in periodic sequence N, Action 3 is triggered immediately. If no falling edge is detected in the entire periodic sequence N, Action 3 is automatically triggered on the last beat before the end of periodic sequence N. In addition, if the input signal A is detected to be low level in the 0th beat of periodic sequence N in Action 1, Action 3 is forcibly triggered in the next beat after the execution of Action 1 to ensure that the output side can enter the duty cycle calculation process in time.

6. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, The triggering timing of the fourth action is limited to the same periodic sequence M as the second action. The latest triggering point must not be later than the last beat before the end of periodic sequence M, and the earliest triggering point is the first beat after the second action is executed. If the calculated value in periodic sequence N is... satisfy Furthermore, if it is determined in the periodic sequence N+1 that the input signal A is in a high-level state, then action four maintains the output signal B at a high level. When T is calculated in the periodic sequence N... hh_th satisfy When the output is high, the beat counter is activated. Count to target threshold T hh_th When the time is triggered, action four is set to low level for output signal B.

7. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, Actions five and six must satisfy the following four rules: Rule 1: When the input signal A in both periodic sequences N and N+1 has a duty cycle, then in periodic sequence M, when... When, execute actions five and six; when At that time, actions five and six are not executed; Rule 2: When the periodic sequence N has a duty cycle but the periodic sequence N+1 does not, only action 5 is executed, and action 6 is not executed; when At that time, action five is executed in the periodic sequence M; when At that time, action five, which was executed in periodic sequence M, is postponed to the next action in periodic sequence M+1. Execution by shooting; The calculation formula is: ; Rule 3: When there is no duty cycle in periodic sequence N but there is a duty cycle in periodic sequence N+1, execute action 6 in periodic sequence M, but do not execute action 5; action 6 is executed in the periodic sequence M. Execution by shooting; Rule 4: When the input signal A in both periodic sequence N and periodic sequence N+1 has no duty cycle, actions 5 and 6 will not be executed in periodic sequence M.

8. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 1, characterized in that, To ensure that actions five and six are executed precisely according to the set phase shift period, the number of phase shift steps is constrained to ensure that the trigger points of actions five and six are within the valid modulation window. The constraint conditions are as follows: ; Action three in periodic sequence N must precede action four in periodic sequence M. G The following constraints must be satisfied: 。 9. The upper and lower bridge arm phase-shifting PWM modulation control method based on duty cycle scaling as described in claim 8, characterized in that, G is pre-calculated by the DSP. Specifically, the DSP amplifies the calculated scaling factor according to its corresponding decimal value and outputs it in fixed-point format. When the DSP acquires the interleaved branch inductor current I... L1 with I L2 Then, the updated G is obtained through the PI control algorithm and sent to the FPGA through the SPI interface. Upon receiving the updated G, the FPGA updates the output signal B and the output signal C in real time, thereby realizing closed-loop modulation control.

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