Soft start circuit

Abstract

The application discloses a soft start circuit, comprising: a first capacitor, the first and second ends of which are connected to ground and a power supply voltage through a first current path respectively, and the second end outputs a first voltage; a second capacitor, the first end of which is connected to ground, and the second end of which is connected to ground through a first switch and to the power supply voltage through a second switch and a second current path respectively, and the second end outputs a start voltage; the first voltage outputs a second voltage through an inverter, and the control ends of the first and second switches are connected to the second voltage; when power is on, the first current path charges the first capacitor to make the first voltage rise, before the inverter generates a flip, the second voltage makes the first switch conduct and the second switch cut off, the conduction of the first switch makes the second capacitor discharge completely and makes the start voltage decrease; after the first voltage rises to make the inverter generate a flip, the second voltage makes the first switch cut off and the second switch conduct, and the start voltage gradually rises. The application can make the start voltage discharge completely and then rise during the power-on process.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a soft-start circuit. Background Technology

[0002] A low dropout regulator (LDO) is an integrated circuit regulator that, compared to traditional linear regulators, typically features extremely low intrinsic noise and a high power supply rejection ratio (PSRR). Due to its ease of use, small size, good performance, and high reliability, LDOs hold a significant share of the power management market.

[0003] like Figure 1 The diagram shown is a loop structure diagram of an existing LDO circuit; the LDO circuit 101 includes: an error amplifier 103, a power switch 102, and a feedback circuit 104. Figure 1 The intermediate error amplifier 103 is also denoted by EA.

[0004] The output terminal of the error amplifier 103 is connected to the control terminal of the power switch 102, thereby controlling the current of the power switch 102. The power switch 102 is a power PMOS transistor. The control terminal of the power switch 102 is the gate of the power PMOS transistor.

[0005] The drain output LDO voltage VOUT of the power switch 102.

[0006] The feedback circuit 104 is connected between the LDO voltage and ground GND25 and outputs a feedback voltage VFB. Figure 1 In this context, the LDO voltage used to connect with the feedback voltage VFB is also separately labeled VOUTFB. Figure 1 In the circuit, the feedback circuit 104 is composed of resistors R1 and R2 connected in series.

[0007] The reference voltage VREF is connected to the negative input terminal of the error amplifier 103. Figure 1 The feedback voltage VFB is connected to the positive input terminal of the error amplifier 103. Figure 1 The + end in the middle.

[0008] Figure 1 The existing LDO circuit 101 shown does not establish a loop during power-up, causing the power switch 102 to charge the load capacitor, resulting in peak current and output overshoot. If the peak current exceeds the maximum load current or even higher, the LDO has a significant risk of failure.

[0009] The working principle of the existing LDO circuit 101 is as follows: The output voltage, i.e., the LDO voltage VOUT, is divided by feedback resistors R1 and R2 to generate the feedback voltage VFB, which is compared with the reference voltage VREF by error amplifier 103. This error amplifier 103 provides the necessary gate voltage to the power switch 102. However, during power-on, the error amplifier 103 is in an unbalanced state. Generally, a protection circuit is needed, typically a soft-start circuit, to limit the peak current and overshoot during power-on.

[0010] like Figure 2 The diagram shows the soft-start circuit of an existing LDO circuit. The current mirror formed by PMOS transistors PM0 and PM1, the drain and gate of PMOS transistor PM0, and the gate of PMOS transistor PM1 are all connected to the bias current IBIAS. The working principle of the existing LDO circuit's soft-start circuit is as follows: During power-up, the bias current IBIAS is mirrored into PMOS transistor PM1, forming a charging current to charge capacitor C0 and establish a startup voltage VSTART on the upper plate of capacitor C0. The build-up speed of VSTART is changed by adjusting the size of capacitor C0 and the magnitude of the charging current.

[0011] When applied in an LDO circuit, the startup voltage VSTART is connected to the error amplifier 103. For example... Figure 3 The diagram shown is a circuit diagram of the error amplifier of an existing LDO circuit. The error amplifier 103 includes a first input transistor PM6 and a second input transistor PM7. The first input is the gate of the first input transistor PM6 and is represented by VINN. The second input is the gate of the second input transistor PM7 and is represented by VINP.

[0012] The soft-start circuit also includes a soft-start transistor PM5 connected in parallel with the first input transistor PM6 of the error amplifier 103. The gate of the soft-start transistor PM5 is connected to the start-up voltage VSTART.

[0013] The first input transistor PM6, the second input transistor PM7, and the soft-start transistor PM5 are all PMOS transistors.

[0014] Depend on Figure 3 As shown, the error amplifier 103 also includes NMOS transistors NM0, NM1, NM2 and NM3, and PMOS transistors PM2, PM3 and PM4.

[0015] In this configuration, the gate of PMOS transistor PM2 is connected to the bias voltage VBIAS, forming current paths to PMOS transistors PM5, PM6, and PM7. Currents from PMOS transistors PM5 and PM6 flow to NMOS transistor NM0, and currents from PMOS transistor PM7 flow to NMOS transistor NM2. The values ​​of NMOS transistors NM0 and NM2 are related to the startup voltage VSTART and the input voltages VINN and VINP. The current in NMOS transistor NM1 is a mirror current of NMOS transistor NM0, which, after being mirrored by PMOS transistors PM3 and PM4, serves as the pull-up current for the output voltage VGP. The current in NMOS transistor NM3 is a mirror current of NMOS transistor NM2 and serves as the pull-down current for the output voltage VGP. The value of the output voltage VGP is determined by comparing the pull-up and pull-down currents.

[0016] Combination Figure 1 As shown, the reference voltage is connected to the gate of PMOS transistor PM6, i.e., the input terminal INN. VREF is an external signal. Therefore, during power-up, the current at the negative terminal of the differential input of error amplifier 103, i.e., the current of NMOS transistor NM0, mainly flows through PMOS transistor PM5 controlled by VSRART. This ensures that when the power supply is powered on, error amplifier 103 will not pull down the output voltage VGP due to the reference voltage VREF being established first. Also, the presence of PMOS transistor PM5 keeps the output voltage VGP at a high value. Conversely, in the existing circuit, after the reference voltage VREF pulls down the output voltage VGP, the power switch transistor 102 will generate a large current and a large overshoot due to the excessive gate-source voltage (VGS). When VSTART exceeds VFB, i.e., the voltage connected to the gate of PMOS transistor PM7, the positive input of the op-amp will switch to VREF control, which has no effect on the original loop. That is, at this time, VSTART has no effect on the loop.

[0017] However, in practical applications, power supplies may encounter various usage scenarios. In the existing soft-start structure, VSTART does not discharge completely when the power supply is powered off, which affects the function of the soft-start circuit when the power supply is powered on again. This results in large glitches in the output and may lead to risks such as false triggering of the subsequent reset circuit in system applications. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide a soft-start circuit that can reduce the starting voltage by discharging before it rises during the power-on process, and prevent the excessive starting voltage caused by the incomplete discharge of the charging and discharging capacitor of the starting voltage during the power-off process, which has an adverse effect on the power-on. It is particularly suitable for use in LDO circuits to prevent the LDO circuit from generating peak current and output voltage overshoot during the second power-on process.

[0019] To solve the above-mentioned technical problems, the soft-start circuit provided by the present invention includes: A first capacitor, wherein a first terminal of the first capacitor is grounded and a first current path is connected between the second terminal and the power supply voltage.

[0020] The second capacitor has a first terminal grounded; a first switch is connected between the second terminal of the second capacitor and ground; a second current path is connected between the second terminal of the second capacitor and the power supply voltage; and a second switch is connected in series in the second current path.

[0021] The second terminal of the first capacitor outputs a first voltage, and the second terminal of the second capacitor outputs a start-up voltage.

[0022] The first voltage is connected to the input terminal of the inverter, and the output terminal of the inverter outputs the second voltage. The control terminals of the first switch and the second switch are both connected to the second voltage.

[0023] When the power supply voltage is applied, the first current path provides a first current and charges the first capacitor to gradually increase the first voltage from ground potential. Before the first voltage rises to the point that the inverter flips, the second voltage turns the first switch on and the second switch off. The first switch turning on discharges the second capacitor and reduces the startup voltage. After the first voltage rises to the point that the inverter flips, the second voltage turns the first switch off and the second switch on. After the second switch turns on, the second current path provides a second current to charge the second capacitor and thus gradually increase the startup voltage.

[0024] A further improvement is that both the first current path and the second current path are mirror images of the third current path.

[0025] A further improvement is that the third current path includes a first PMOS transistor.

[0026] The first current path includes a second PMOS transistor.

[0027] The second current path includes a third PMOS transistor.

[0028] The source of the first PMOS transistor, the source of the second PMOS transistor, and the source of the third PMOS transistor are all connected to the power supply voltage.

[0029] The gate and drain of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor are connected together and connected to the bias current.

[0030] A further improvement is that the first switch is composed of a first NMOS transistor; the source of the first NMOS transistor is grounded, the drain is connected to the second terminal of the second capacitor, and the gate serves as the control terminal and is connected to the second voltage.

[0031] A further improvement is that the second switch is composed of a fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the second terminal of the second capacitor and the source is connected to the drain of the third PMOS transistor, and the gate of the fourth PMOS transistor serves as a control terminal and is connected to the second voltage.

[0032] A further improvement is that, before the first voltage rises to the point that the inverter flips, the amount of the startup voltage drop is determined by the size of the first capacitor, the flip voltage of the inverter, and the on-state current of the first NMOS transistor.

[0033] A further improvement is that the magnitude of the inverter's flip voltage is adjusted by regulating the threshold voltage of the logic transistors in the inverter.

[0034] A further improvement is that the soft-start circuit is applied to an LDO circuit, which includes an error amplifier, a power switch, and a feedback circuit.

[0035] The output of the error amplifier is connected to the control terminal of the power switch, thereby controlling the current of the power switch.

[0036] The drain of the power switch outputs an LDO voltage.

[0037] The feedback circuit is connected between the LDO voltage and ground and outputs a feedback voltage.

[0038] The reference voltage is connected to the first input terminal of the error amplifier, and the feedback voltage is connected to the second input terminal of the error amplifier.

[0039] The first input terminal is the gate of the first input transistor, and the second input terminal is the gate of the second input transistor.

[0040] The soft-start circuit also includes a soft-start transistor connected in parallel with the first input transistor of the error amplifier.

[0041] The gate of the soft-start transistor is connected to the startup voltage.

[0042] A further improvement is that the first input transistor, the second input transistor, and the soft-start transistor are all PMOS transistors.

[0043] A further improvement is that the power switch is a power PMOS transistor.

[0044] A further improvement is that the first input terminal is a negative input terminal, and the second input terminal is a positive input terminal.

[0045] This invention charges the first capacitor through a first current path, causing the first voltage at the second terminal of the first capacitor to gradually rise. Before reaching the inverter's flip-flop voltage, the second voltage output by the inverter rises with the power supply voltage. This second voltage causes the first switch to turn on and the second switch to turn off. The first switch turning on discharges the second capacitor, which outputs the startup voltage, thus lowering the startup voltage. When the first voltage rises further to the point where the inverter flips, the second voltage becomes the same as ground potential, causing the second switch to turn on and the first switch to turn off. The second switch turning on charges the second capacitor through the second current path, causing the startup voltage to gradually rise. Therefore, this invention eliminates the adverse effects of incomplete discharge of the second capacitor during the previous power-down process during the secondary power-on. Specifically, when the second capacitor is not completely discharged, the startup voltage rises from a voltage greater than 0V, making the startup voltage too high during power-on and adversely affecting the circuits requiring protection. This invention is applicable to LDO circuits, preventing peak current and output voltage overshoot during the secondary power-on process and preventing circuit failure or load damage. Attached Figure Description

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a loop structure diagram of an existing LDO circuit; Figure 2 This is a circuit diagram of the soft-start circuit for an existing LDO circuit; Figure 3 This is the circuit diagram of the error amplifier in an existing LDO circuit; Figure 4 This is a circuit diagram of the soft-start circuit according to an embodiment of the present invention. Detailed Implementation

[0047] like Figure 4 The diagram shown is a circuit diagram of a soft-start circuit according to an embodiment of the present invention; the soft-start circuit according to an embodiment of the present invention includes: The first capacitor C101 has a first terminal grounded and a first current path 201 connected between its second terminal and the power supply voltage VDD25.

[0048] The second capacitor C102 has its first terminal grounded; a first switch 206 is connected between the second terminal of the second capacitor C102 and ground; a second current path 202 is connected between the second terminal of the second capacitor C102 and the power supply voltage VDD25; and a second switch 205 is connected in series on the second current path 202.

[0049] The second terminal of the first capacitor C101 outputs a first voltage V1, and the second terminal of the second capacitor C102 outputs a start-up voltage VSTART.

[0050] The first voltage V1 is connected to the input terminal of the inverter 204, and the output terminal of the inverter 204 outputs the second voltage V2. The control terminals of the first switch 206 and the second switch 205 are both connected to the second voltage V2.

[0051] When the power supply voltage VDD25 is applied, the first current I2 path 201 provides a first current I2 and charges the first capacitor C101, causing the first voltage V1 to gradually rise from ground potential. Before the first voltage V1 rises to the point where the inverter 204 flips, the second voltage V2 turns on the first switch 206 and turns off the second switch 205. The first switch 206 turning on discharges the second capacitor C102 completely and reduces the startup voltage VSTART. After the first voltage V1 rises to the point where the inverter 204 flips, the second voltage V2 turns off the first switch 206 and turns on the second switch 205. After the second switch 205 turns on, the second current I1 path 202 provides a second current I1 to charge the second capacitor C102, thereby causing the startup voltage VSTART to gradually rise.

[0052] In this embodiment of the invention, the first current I2 path 201 and the second current I1 path 202 are both mirror paths of the third current path 203. The third current path 203 is connected to the bias current IBIAS.

[0053] Preferably, the third current path 203 includes a first PMOS transistor PM101.

[0054] The first current I2 path 201 includes a second PMOS transistor PM102.

[0055] The second current path I1 202 includes a third PMOS transistor PM103.

[0056] The source of the first PMOS transistor PM101, the source of the second PMOS transistor PM102, and the source of the third PMOS transistor PM103 are all connected to the power supply voltage VDD25.

[0057] The gate and drain of the first PMOS transistor PM101, the gate of the second PMOS transistor PM102, and the gate of the third PMOS transistor PM103 are connected together and connected to the bias current IBIAS.

[0058] Preferably, the first switch 206 is composed of a first NMOS transistor NM101; the source of the first NMOS transistor NM101 is grounded, the drain is connected to the second terminal of the second capacitor C102, and the gate is used as a control terminal and connected to the second voltage V2.

[0059] The second switch 205 is composed of a fourth PMOS transistor PM104; the drain of the fourth PMOS transistor PM104 is connected to the second terminal of the second capacitor C102 and the source is connected to the drain of the third PMOS transistor PM103, and the gate of the fourth PMOS transistor PM104 serves as the control terminal and is connected to the second voltage V2.

[0060] In this embodiment of the invention, before the first voltage V1 rises to the point that the inverter 204 flips, the amount of decrease in the startup voltage VSTART is determined by the size of the first capacitor C101, the flip voltage of the inverter 204, and the on-state current of the first NMOS transistor NM101. Therefore, the amount of decrease in the startup voltage VSTART can be adjusted by the size of the first capacitor C101, the flip voltage of the inverter 204, and the on-state current of the first NMOS transistor NM101.

[0061] The magnitude of the flip voltage of the inverter 204 is adjusted by adjusting the threshold voltage of the logic transistor in the inverter 204.

[0062] In this embodiment of the invention, the soft-start circuit is applied to an LDO circuit, and the structure of the LDO circuit can also be found in [reference needed]. Figure 1 As shown, the LDO circuit 101 includes: an error amplifier 103, a power switch 102, and a feedback circuit 104.

[0063] The output terminal of the error amplifier 103 is connected to the control terminal of the power switch 102, thereby controlling the current of the power switch 102.

[0064] The drain output LDO voltage VOUT of the power switch 102.

[0065] The feedback circuit 104 is connected between the LDO voltage and ground and outputs a feedback voltage VFB. Figure 1 In the figure, the LDO voltage used to connect with the feedback voltage 104 is also separately labeled with VOUTFB. Figure 1In the circuit, the feedback circuit 104 is composed of resistors R1 and R2 connected in series.

[0066] The reference voltage VREF is connected to the first input terminal of the error amplifier 103, and the feedback voltage VFB is connected to the second input terminal of the error amplifier 103. In this embodiment of the invention, the first input terminal is the negative input terminal. Figure 1 The - end in the middle, the second input end is the positive input end, that is... Figure 1 The + end in the middle.

[0067] Please refer to the circuit diagram of the error amplifier 103 at the same time. Figure 3 As shown, the first input terminal is the gate of the first input terminal transistor PM6, and the second input terminal is the gate of the second input terminal transistor PM7. Figure 3 In this context, the first input terminal is represented by VINN, and the second input terminal is represented by VINP.

[0068] The soft-start circuit also includes a soft-start transistor PM5 connected in parallel with the first input transistor PM6 of the error amplifier 103.

[0069] The gate of the soft-start transistor PM5 is connected to the startup voltage VSTART.

[0070] Preferably, the first input transistor PM6, the second input transistor PM7, and the soft-start transistor PM5 are all PMOS transistors.

[0071] The power switch 102 is a power PMOS transistor.

[0072] In this embodiment of the invention, the first capacitor C101 is charged through the first current path 201 (I2). This causes the first voltage V1 at the second terminal of the first capacitor C101 to gradually rise. Before reaching the switching voltage of the inverter 204, the second voltage V2 output by the inverter 204 rises with the power supply voltage VDD25. This second voltage V2 causes the first switch 206 to turn on and the second switch 205 to turn off. The turn-on of the first switch 206 discharges the second capacitor C102, which outputs the start-up voltage VSTART, thus lowering VSTART. When the first voltage V1 rises further to the point where the inverter 204 flips, the second voltage V2 becomes the same as the ground potential, thus causing the second switch 205 to turn on and the first switch 206 to turn off. When 05 is turned on, the second current I1 path 202 charges the second capacitor C102, causing the starting voltage VSTART to gradually rise. Therefore, this embodiment of the invention can eliminate the adverse effects caused by the incomplete discharge of the second capacitor C102 during the previous power-down process during the secondary power-on. Mainly, when the second capacitor C102 is not completely discharged, the starting voltage VSTART will rise from a voltage greater than 0V, making the starting voltage VSTART too high during the power-on process and causing adverse effects on the circuit that needs protection during the power-on process. This embodiment of the invention is applicable to the LDO circuit 101 to prevent the LDO circuit 101 from generating peak current and output voltage overshoot during the secondary power-on process and to prevent circuit failure or load damage.

[0073] The soft-start circuit of this invention implements a discharge structure for the soft-start signal, i.e., the start-up voltage VSTART, which can effectively solve the problem of secondary power-on glitches and improve the stability of the power supply system.

[0074] To reduce output glitches during LDO secondary power-up and prevent false triggering of the subsequent reset circuit, Figure 4 The soft-start circuit shown in the embodiment of the present invention can... Figure 2 Based on the existing soft-start circuit shown, two PMOS transistors (PM102 and PM104), one NMOS transistor (NM101), one capacitor (first capacitor C101), and one inverter (INV, inverter 204) are added to form a current mirror circuit and a charging / discharging circuit. Among them, PMOS transistors PM101 and PM104... Figure 2 The PMOS transistors PM0 and PM1 correspond to each other, and the second capacitor C102 and Figure 2 Corresponding to capacitor C0 in the first capacitor, the second capacitor C102 is the capacitor used for charging and discharging at the start-up voltage VSTART.

[0075] The working principle of the soft-start circuit in this embodiment of the invention is as follows: VSTART discharge phase: When the power supply, i.e., the power supply voltage VDD25, is powered on, V1 is initially at a low voltage, V2 follows VDD25, PM104 is cut off, VGS of NM101 increases, NM101 gradually turns on, and VSTART discharges to ground through NM101. For a simpler description, the power supply voltage is directly represented by VDD25, the startup voltage by VSTART, the first voltage by V1, the second voltage by V2, and the first NMOS transistor by NM101.

[0076] VSTART charging phase: As the power supply increases, the PM102 current I2 is established, charging C101. When V1 reaches the inverter switching voltage, V2 goes low, NM101 is cut off, the VSTART path to ground is closed, and the discharge stops. Simultaneously, PM103 turns on, and the PM103 current I1 charges C102, initiating the VSTART signal. Similarly, for simplicity, the second PMOS transistor PM102 is directly referred to as PM102, the third PMOS transistor PM103 as PM103, the first capacitor C101 as C101, the inverter 204 as inverter, and the second capacitor C102 as C102.

[0077] The voltage on the upper plate of capacitor C102 gradually increases until it reaches a steady state near the power supply voltage. At this point, the power consumption of the startup circuit and its discharge circuit is minimal. Through technical effect comparison, when the power supply is powered on again, the VSTART signal voltage drops rapidly under the action of the discharge circuit, so that there is no significant voltage difference at the differential input terminal of the operational amplifier, i.e., error amplifier 103, effectively reducing the problem of power-on overshoot.

[0078] In this embodiment of the invention, the discharge of the VSTART signal is determined by capacitor C101, the switching voltage of the logic circuit inverter, and NM101. By adjusting the magnitude of C101, the threshold voltage (Vth) of the logic transistor in the inverter, and the discharge rate of NM101, the overshoot amplitude of the LDO secondary power-on output can be adjusted.

[0079] The embodiments of the present invention have been verified by Virtuoso simulation. Compared with the prior art, the simulation results show that the secondary power-on of the embodiments of the present invention effectively reduces the initial value of the soft-start voltage and reduces the output overshoot by 74%.

[0080] In addition, the power consumption of the structure in the embodiment of the present invention was simulated. The simulation results show that the soft-start circuit of the present invention only generates power consumption during the power-on process due to the charging of capacitor C101. After stabilization, the power consumption of PM102 and PM103 is only in the pA level. The structure added in the embodiment of the present invention does not increase the power consumption of the circuit.

[0081] Simulation verification shows that the soft-start circuit of this invention is applicable to different processes, solving the problem of excessive start-up overshoot caused by multiple power supply step-up and step-down operations in existing structures, which leads to false triggering of the system reset circuit. This greatly expands the application of LDOs and effectively enhances their competitiveness and process adaptability.

[0082] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A soft-start circuit, characterized in that, include: A first capacitor, wherein a first terminal of the first capacitor is grounded and a first current path is connected between the second terminal and the power supply voltage; The second capacitor has a first terminal grounded; a first switch is connected between the second terminal of the second capacitor and ground; a second current path is connected between the second terminal of the second capacitor and the power supply voltage; and a second switch is connected in series in the second current path. The second terminal of the first capacitor outputs a first voltage, and the second terminal of the second capacitor outputs a start-up voltage; The first voltage is connected to the input terminal of the inverter, and the output terminal of the inverter outputs the second voltage. The control terminals of the first switch and the second switch are both connected to the second voltage. When the power supply voltage is applied, the first current path provides a first current and charges the first capacitor to gradually increase the first voltage from ground potential. Before the first voltage rises to the point that the inverter flips, the second voltage turns the first switch on and the second switch off. The first switch turning on discharges the second capacitor and reduces the startup voltage. After the first voltage rises to the point that the inverter flips, the second voltage turns the first switch off and the second switch on. After the second switch turns on, the second current path provides a second current to charge the second capacitor and thus gradually increase the startup voltage.

2. The soft-start circuit as described in claim 1, characterized in that: Both the first current path and the second current path are mirror images of the third current path.

3. The soft-start circuit as described in claim 3, characterized in that: The third current path includes a first PMOS transistor; The first current path includes a second PMOS transistor; The second current path includes a third PMOS transistor; The source of the first PMOS transistor, the source of the second PMOS transistor, and the source of the third PMOS transistor are all connected to the power supply voltage; The gate and drain of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor are connected together and connected to the bias current.

4. The soft-start circuit as described in claim 3, characterized in that: The first switch is composed of a first NMOS transistor; the source of the first NMOS transistor is grounded, the drain is connected to the second terminal of the second capacitor, and the gate serves as the control terminal and is connected to the second voltage.

5. The soft-start circuit as described in claim 4, characterized in that: The second switch is composed of a fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the second terminal of the second capacitor and the source is connected to the drain of the third PMOS transistor, and the gate of the fourth PMOS transistor serves as the control terminal and is connected to the second voltage.

6. The soft-start circuit as described in claim 5, characterized in that: Before the first voltage rises to the point that the inverter flips, the amount of the start-up voltage drop is determined by the size of the first capacitor, the flip voltage of the inverter, and the on-state current of the first NMOS transistor.

7. The soft-start circuit as described in claim 6, characterized in that: The magnitude of the flip voltage of the inverter is adjusted by regulating the threshold voltage of the logic transistors in the inverter.

8. The soft-start circuit as described in claim 1, characterized in that: The soft-start circuit is applied to an LDO circuit, which includes an error amplifier, a power switch, and a feedback circuit. The output of the error amplifier is connected to the control terminal of the power switch and thus controls the current of the power switch. The drain of the power switch outputs an LDO voltage; The feedback circuit is connected between the LDO voltage and ground and outputs a feedback voltage. The reference voltage is connected to the first input terminal of the error amplifier, and the feedback voltage is connected to the second input terminal of the error amplifier; The first input terminal is the gate of the first input transistor, and the second input terminal is the gate of the second input transistor; The soft-start circuit also includes a soft-start transistor connected in parallel with the first input transistor of the error amplifier; The gate of the soft-start transistor is connected to the startup voltage.

9. The soft-start circuit as described in claim 8, characterized in that: The first input transistor, the second input transistor, and the soft-start transistor are all PMOS transistors.

10. The soft-start circuit as described in claim 9, characterized in that: The power switch is a power PMOS transistor.

11. The soft-start circuit as described in claim 10, characterized in that: The first input terminal is a negative input terminal, and the second input terminal is a positive input terminal.

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