Interleaved pfc circuit current sharing control apparatus and method
By employing a current sharing compensation module and a clamping module in the interleaved PFC circuit to clamp the current sharing signal when the current is zero, the current sharing problem during startup is solved, improving the system's startup consistency and robustness under complex operating conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MORNSUN GUANGZHOU SCI & TECH
- Filing Date
- 2026-03-20
- Publication Date
- 2026-07-10
AI Technical Summary
In traditional interleaved PFC circuits, the current sharing compensation signal drops during startup due to capacitor charge release, causing the master and slave phase inductors to fail to share current, which affects system reliability and dynamic current sharing performance.
A current sharing compensation module and a clamping module are used to clamp the current sharing compensation signal to a set voltage threshold when the main phase current or the slave phase current is zero, generate the main phase and slave phase drive signals, and adjust the slave phase drive pulse width according to the current sharing compensation signal and the set reference signal.
This ensures that the master-slave phase current sharing loop starts working directly from the set voltage threshold during startup, solving the problem of inability to share current during startup, improving system startup consistency and robustness, and avoiding reliance on the ideal capacitor model.
Smart Images
Figure CN122371663A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a converter circuit, and more particularly to a current sharing control device and control method for an interleaved PFC circuit. Background Technology
[0002] Traditional single-phase bridged CRM mode PFC is often used in applications below 300W. To further increase power, single-phase bridged CCM mode PFC is selected for 300W~1000W. If it is necessary to further increase the power level, such as 1500W and above, an interleaved CCM mode control strategy is often used to achieve PFC function.
[0003] like Figure 1 As shown, CN119254039A proposes a method in which the sampling signals of the main phase inductor current and the sampling signals of the slave phase inductor current are connected to the non-inverting input and the inverting input of the transconductance operational amplifier, respectively. The output of the transconductance operational amplifier is connected to a filter network to generate a current sharing signal. The turn-on time of the slave phase switch is adjusted by the current sharing signal and the set threshold voltage to achieve current sharing control. Figure 2 The diagram shows a problem with this solution during startup. When the control device detects a fault signal, or when the interleaved PFC enters burst mode or enters single-phase operation, the transconductance operational amplifier collects zero current signals from both the master and slave phases, resulting in no output current from the transconductance operational amplifier. Furthermore, since the filter network capacitor is not an ideal capacitor, the charge stored on it will be released, causing the voltage of the current sharing compensation signal to drop. If the interleaved PFC circuit clears the fault or exits the burst state at this time, the current sharing between the master and slave phase inductors will not be able to share current, posing a risk to system reliability. Summary of the Invention
[0004] In view of the shortcomings of the prior art, the present invention provides a current sharing control device and control method for interleaved PFC circuits that can effectively solve the problem of inability to share current.
[0005] The specific technical solution proposed by this invention is as follows:
[0006] In a first aspect, the present invention provides an interleaved PFC circuit current sharing control device, including... The current sharing compensation module is used to generate a current sharing compensation signal based on the main phase current signal and the slave phase current signal of the interleaved PFC circuit. The current sharing compensation signal clamping module is used to clamp the voltage value of the current sharing compensation signal to a first set voltage threshold when either the main phase current signal or the slave phase current signal is zero, until both the main phase current signal and the slave phase current signal are not zero, and then release the clamping of the current sharing compensation signal. The pulse width modulation module is used to generate a master phase drive signal and a slave phase drive signal, and adjust the slave phase drive pulse width of the slave phase drive signal according to the comparison result between the current sharing compensation signal and the set reference signal.
[0007] Optionally, adjusting the slave phase drive pulse width of the slave phase drive signal based on the comparison result between the current sharing compensation signal and the set reference signal specifically includes: A pulse width reduction unit is used to determine that the current sharing compensation signal is less than the set reference signal, and to reduce the slave phase drive pulse width. The pulse width amplification unit is used to determine that the current sharing compensation signal is greater than the set reference signal and increase the slave phase drive pulse width.
[0008] Optionally, the first set voltage threshold is the same as the voltage of the set reference signal.
[0009] Optionally, the current sharing compensation module includes a transconductance operational amplifier and a filter network. The current sharing compensation module generates a current sharing compensation signal on the filter network based on the current sampling signals of the first power loop and the second power loop of the interleaved PFC circuit through the transconductance operational amplifier.
[0010] Optionally, the pulse width modulation module includes a main phase pulse width modulation module and a slave phase pulse width modulation module; The main phase pulse width modulation module generates the main phase drive signal of the interleaved PFC main phase switch, and the slave phase pulse width modulation module generates the slave phase drive signal of the interleaved PFC slave phase switch. At the same time, the slave phase pulse width modulation module adjusts the slave phase drive pulse width according to the comparison result of the current sharing compensation signal and the set reference signal.
[0011] Optionally, when the output power, output current, or output voltage feedback signal is detected to be lower than the second set threshold, the slave phase drive signal of the slave phase switch is turned off, the current sharing compensation module is turned off, and the current sharing compensation signal clamping module is turned on to clamp the current sharing compensation signal voltage value to the first set voltage threshold. When the output power, output current, or output voltage feedback signal is detected to be greater than the third set threshold, the slave phase drive signal of the slave phase switch is turned on, the current sharing compensation module is turned on, and the current sharing compensation signal clamping module is turned off.
[0012] Optionally, the difference between the second set threshold and the third set threshold can have multiple configurable levels.
[0013] Secondly, the present invention provides a current sharing control method for interleaved PFC circuits, comprising: A current sharing compensation signal is generated based on the main phase current signal and the slave phase current signal of the interleaved PFC circuit. When either the main phase current signal or the slave phase current signal is zero, the voltage value of the current sharing compensation signal is clamped to a first set voltage threshold until both the main phase current signal and the slave phase current signal are not zero, and then the clamping of the current sharing compensation signal is released. A master phase drive signal and a slave phase drive signal are generated, and the slave phase drive pulse width of the slave phase drive signal is adjusted according to the comparison result between the current sharing compensation signal and the set reference signal.
[0014] Optionally, adjusting the slave phase drive pulse width of the slave phase drive signal based on the comparison result between the current sharing compensation signal and the set reference signal specifically includes: If the current sharing compensation signal is determined to be less than the set reference signal, the slave phase drive pulse width is reduced. If the current sharing compensation signal is determined to be greater than the set reference signal, the slave phase drive pulse width is increased.
[0015] Optional, also includes: When the output power, output current, or output voltage feedback signal is detected to be lower than the second set threshold, the slave phase drive signal of the slave phase switch is turned off, the current sharing compensation is turned off, and the current sharing compensation signal voltage value is clamped to the first set voltage threshold. When the output power, output current, or output voltage feedback signal is detected to be greater than the third set threshold, the slave phase drive signal of the slave phase switch is turned on, the current sharing compensation is turned on, and the clamping of the current sharing compensation signal is released.
[0016] The beneficial effects of this invention are as follows: This invention clamps the current sharing compensation signal to a first set voltage threshold when the main phase current signal or the slave phase current signal is zero, thereby avoiding the current sharing compensation signal dropping during this period. Subsequently, the current sharing loop of the main and slave phases can start working directly from the first set voltage threshold during startup, solving the problem of failure to share current during startup. Attached Figure Description
[0017] Figure 1 This is a control block diagram of an interleaved PFC scheme in the prior art; Figure 2 A waveform diagram of an existing interleaved PFC control scheme; Figure 3 This is a flowchart illustrating an embodiment of the current sharing control method for interleaved PFC circuits according to the present invention. Figure 4 This is a flowchart illustrating an embodiment of the current sharing control method for interleaved PFC circuits according to the present invention. Figure 5 This is a flowchart illustrating an embodiment of the current sharing control method for interleaved PFC circuits according to the present invention. Figure 6 This is a waveform diagram of an interleaved PFC circuit current sharing control device according to the present invention; Figure 7 This is a block diagram illustrating the principle of an interleaved PFC circuit current sharing control device according to the present invention. Detailed Implementation
[0018] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods.
[0019] Furthermore, it should be understood that this disclosure can have various variations in different embodiments, all of which do not depart from the scope of this disclosure, and the descriptions and drawings herein are intended to illustrate these variations and not to limit this disclosure.
[0020] Furthermore, the serial numbers assigned to components in this document, such as "first" and "second," are merely for distinguishing the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).
[0021] To facilitate understanding of the meaning and effects of this application by those skilled in the art, prior art will be used as an example for explanation. Figure 1 A principle block diagram of a flow sharing control scheme proposed in the prior art. Figure 1 Module 101 is a current sampling module that can sample the current signals flowing through the main phase power circuit and the slave phase power circuit. These signals can be inductor current waveforms, or the currents flowing through the main phase power circuit S1 and the slave phase power circuit S2, etc. After the current sampling module collects the main phase power circuit current signal and the slave phase power circuit current signal, it processes them through the leading-edge blanking module. The difference between the slave phase power circuit current signal and the main phase power circuit current signal is then calculated, and the error signal is sent to the transconductance module 102. The transconductance module 102 outputs an error current based on the error signal. This error current is then connected to a first-order or second-order filter network, as shown in 104, to obtain the current sharing compensation signal V2.
[0022] The first modulation signal is a sawtooth wave signal, OSC is the first clock signal, the first modulation signal and the first clock signal have the same frequency, the first modulation signal is added to the first bias voltage 505 and input to the positive terminal of the comparator, and the first reference signal is... Figure 1The input average current sampling signal output by module 11 generates a rising edge signal when the sum of the first modulation signal and the first bias voltage is greater than the first reference signal. This signal is input to the S terminal of the trigger to make the main phase power circuit drive signal go high. When the rising edge of the first clock signal is input to the R terminal of the trigger, the main phase power circuit drive signal goes low.
[0023] Furthermore, the first modulation signal is phase-shifted to obtain the second modulation signal. Generally, the phase shift is 180° when the two phases are interleaved. The second modulation signal is added to the first bias voltage and the current sharing compensation signal V2 and input to the positive terminal of the comparator. The first reference voltage and the second bias voltage V106 are added to the inverting terminal of the comparator. When the sum of the second modulation signal, the first bias voltage, and the current sharing compensation signal V2 is greater than the sum of the first reference signal and the second bias voltage, the comparator generates a rising edge signal. This signal is input to the S terminal of the trigger to make the drive signal of the phase power circuit go high. At the same time, the first clock signal is phase-shifted to obtain the second clock signal. The phase shift angle is the same as when the rising edge of the second clock signal is input to the R terminal of the trigger, the drive signal of the phase power circuit goes low.
[0024] The principle of its current sharing regulation is shown in Figure 107. When the current of the main phase power circuit is large, the current sharing compensation signal V2 will be greater than the second bias voltage. Since the first reference signal is the power frequency cycle, it can be regarded as approximately constant during the switching cycle. Therefore, when the current sharing compensation signal V2 is greater than the second bias voltage, the driving signal of the phase power circuit will increase, thereby realizing the current sharing transmission of the two phase circuits, and vice versa.
[0025] Figure 2 for Figure 1The waveform diagram shows that 201 is the main phase current signal, 202 is the slave phase current signal, and 203 is the current sharing compensation signal. As can be seen from the diagram, when the current sharing control device detects a fault signal, or when the interleaved PFC enters burst mode or enters single-phase operation at time T0, both the main phase current signal 201 and the slave phase current signal 202 are zero, resulting in no output current from the transconductance operational amplifier. At this time, the filter network capacitor providing voltage bias for the current sharing loop enters a slow charge release phase. Since the filter network capacitor is not an ideal capacitor, the charge stored on it will be released, causing the voltage of the current sharing compensation signal to gradually drop over time. If, at time T1S, the interleaved PFC circuit clears the fault or exits the burst state and restarts, the control loops for the main and slave phases will adjust the current sharing based on an incorrect compensation voltage that is lower than the actual requirement. This can lead to inconsistent current gain between the master and slave modules at startup, which in turn causes the master phase current signal 201 and slave phase current signal 202 to fail to share current. In severe cases, it may cause overcurrent in one phase or system oscillation, affecting the startup reliability and dynamic current sharing performance of the multiphase parallel power supply system, and posing a risk of system damage.
[0026] To address the voltage drop problem caused by non-ideal characteristics, this invention proposes an active clamping mechanism. By forcibly clamping the voltage value of the current sharing compensation signal to a preset first voltage threshold when either the main phase current signal or the slave phase current signal is zero, this solution can fundamentally eliminate voltage drift caused by capacitor charge leakage. This invention also provides a current sharing control device for an interleaved PFC circuit, including... The current sharing compensation module is used to generate a current sharing compensation signal based on the main phase current signal and the slave phase current signal of the interleaved PFC circuit. The current sharing compensation signal clamping module is used to clamp the voltage value of the current sharing compensation signal to a first set voltage threshold when either the main phase current signal or the slave phase current signal is zero, until both the main phase current signal and the slave phase current signal are not zero, and then release the clamping of the current sharing compensation signal. The pulse width modulation module is used to generate a master phase drive signal and a slave phase drive signal, and adjust the slave phase drive pulse width of the slave phase drive signal according to the comparison result between the current sharing compensation signal and the set reference signal.
[0027] It should be noted that if either the main phase current signal or the slave phase current signal is zero, it can be that both the main phase drive signal and the slave phase drive signal are zero, or it can be that either the main phase current signal or the slave phase current signal is zero. When the current sharing compensation signal clamping module is activated, the voltage value of the current sharing compensation signal is clamped to the first set voltage threshold. When neither the main phase current signal nor the slave phase current signal is zero, the current sharing compensation signal clamping module is deactivated.
[0028] Specifically, when a fault signal is detected or the interleaved PFC circuit enters the burst operating mode, since the transconductance operational amplifier collects both the main phase current signal and the slave phase current signal as 0, a fault in the interleaved PFC circuit can be detected. Alternatively, when the interleaved PFC circuit is detected to have entered the burst state, the current sharing compensation signal clamping module is activated to clamp the current sharing compensation signal voltage value to the first set voltage threshold. When the fault in the interleaved PFC circuit is resolved or the burst state is exited, the current sharing compensation signal clamping module is deactivated.
[0029] In this embodiment, it is ensured that during standby or intermittent periods when the main phase current signal or the slave phase current signal is zero, the current sharing compensation reference is always maintained at a defined voltage level that matches the startup requirements. Thus, when the system receives a startup command again, the current sharing loop of the main and slave phases does not need to wait for the capacitor to recharge to the correct value, but directly starts working from this clamping voltage. This ensures that the main and slave inductors can achieve precise current sharing at startup, completely solving the persistent problem of "inability to share current during startup" in traditional solutions. Secondly, this solution, through clamping, not only improves the startup consistency of the system but also enhances the robustness of multi-phase parallel power supplies under complex operating conditions, making current sharing control no longer dependent on an ideal zero-leakage capacitor model, and more closely aligned with engineering realities.
[0030] The pulse width amplification unit, which adjusts the slave phase drive pulse width of the slave phase drive signal based on the comparison result between the current sharing compensation signal and the set reference signal, specifically includes: A pulse width reduction unit is used to determine that the current sharing compensation signal is less than the set reference signal, and to reduce the slave phase drive pulse width. The pulse width amplification unit is used to determine that the current sharing compensation signal is greater than the set reference signal and increase the slave phase drive pulse width.
[0031] In one embodiment, the first set voltage threshold is the same as the voltage of the set reference signal.
[0032] In one embodiment, the current sharing compensation module includes a transconductance operational amplifier and a filter network. The current sharing compensation module generates a current sharing compensation signal on the filter network based on the current sampling signals of the first power loop and the second power loop of the interleaved PFC circuit through the transconductance operational amplifier.
[0033] In one embodiment, the pulse width modulation module includes a main phase pulse width modulation module and a slave phase pulse width modulation module; The main phase pulse width modulation module generates the main phase drive signal of the interleaved PFC main phase switch, and the slave phase pulse width modulation module generates the slave phase drive signal of the interleaved PFC slave phase switch. At the same time, the slave phase pulse width modulation module adjusts the slave phase drive pulse width according to the comparison result of the current sharing compensation signal and the set reference signal.
[0034] In one embodiment, when the output power, output current, or output voltage feedback signal is detected to be lower than the second set threshold, the slave phase drive signal of the slave phase switch is turned off, the current sharing compensation module is turned off, and the current sharing compensation signal clamping module is turned on to clamp the current sharing compensation signal voltage value to the first set voltage threshold. When the output power, output current, or output voltage feedback signal is detected to be greater than the third set threshold, the slave phase drive signal of the slave phase switch is turned on, the current sharing compensation module is turned on, and the current sharing compensation signal clamping module is turned off.
[0035] In one embodiment, the difference between the second set threshold and the third set threshold has multiple configurable levels.
[0036] refer to Figure 3 This invention also provides a current sharing control method for interleaved PFC circuits, comprising: A current sharing compensation signal is generated based on the main phase current signal and the slave phase current signal of the interleaved PFC circuit. When either the main phase current signal or the slave phase current signal is zero, the voltage value of the current sharing compensation signal is clamped to a first set voltage threshold until both the main phase current signal and the slave phase current signal are not zero, and then the clamping of the current sharing compensation signal is released. A master phase drive signal and a slave phase drive signal are generated, and the slave phase drive pulse width of the slave phase drive signal is adjusted according to the comparison result between the current sharing compensation signal and the set reference signal.
[0037] In one embodiment, adjusting the slave phase drive pulse width of the slave phase drive signal based on the comparison result between the current sharing compensation signal and the set reference signal specifically includes: If the current sharing compensation signal is determined to be less than the set reference signal, the slave phase drive pulse width is reduced. If the current sharing compensation signal is determined to be greater than the set reference signal, the slave phase drive pulse width is increased.
[0038] In one embodiment, it further includes: When the output power, output current, or output voltage feedback signal is detected to be lower than the second set threshold, the slave phase drive signal of the slave phase switch is turned off, the current sharing compensation is turned off, and the current sharing compensation signal voltage value is clamped to the first set voltage threshold. When the output power, output current, or output voltage feedback signal is detected to be greater than the third set threshold, the slave phase drive signal of the slave phase switch is turned on, the current sharing compensation is turned on, and the clamping of the current sharing compensation signal is released.
[0039] Figure 3 The present invention proposes a control strategy that can solve the problems of the above-mentioned solutions, the steps of which are as follows: Step 301: Detect the main phase current signal of the main phase switch transistor and the slave phase current signal of the slave phase switch transistor; Step 302: Check whether both the main phase current signal and the slave phase current signal are present; Step 303: If both the main phase current signal and the slave phase current signal exist, turn off the current sharing compensation signal clamping module; Step 304: The current sharing compensation signal voltage is not clamped; Step 305: If the control signal of any one phase switch of the main phase current signal and the slave phase current signal disappears or both disappear, then the current sharing compensation signal clamping module is activated. Step 306: The current sharing compensation signal voltage is clamped to the first set voltage threshold. Figure 4 Another control strategy proposed in this invention that can solve the problems of the above-mentioned solutions comprises the following steps: Step 401: Check if the interleaved PFC circuit has entered a burst or malfunctioned; Step 402: If yes, then enable the current sharing compensation signal clamping module; Step 403: If not, turn off the current sharing compensation signal clamping module; Step 404: The current sharing compensation signal voltage is not clamped; Step 405: The current sharing compensation signal voltage is clamped to the first set voltage threshold. Figure 5 Another control strategy proposed in this invention that can solve the problems of the above-mentioned solutions comprises the following steps: Step 501: Detect the output power, output current, or output voltage feedback signal; Step 502: Detect whether the signal drops below the second preset threshold; Step 503: If not, turn on the control signal of the phase switch transistor and turn off the current sharing compensation signal clamping module at the same time; Step 504: If so, turn off the control signal of the phase switch transistor and turn on the current sharing compensation signal clamping module at the same time; Step 505: The current sharing compensation signal voltage is clamped to the first set voltage threshold. Step 506: The current sharing compensation signal voltage is not clamped; Step 507: When it is detected whether the output power, output current or output voltage feedback signal rises to less than the third set threshold, if so, the slave phase switch control signal is turned on and the current sharing compensation signal clamping module is turned off. If not, the slave phase switch control signal is turned off and the current sharing compensation signal clamping module is turned on. The current sharing compensation signal voltage is clamped to the first set voltage threshold. Figure 6 For the key waveforms used in this invention, at time T0, when the current sharing control device detects the presence of a fault signal, or when the interleaved PFC enters burst mode or enters single-phase operation, the current sharing compensation signal clamping module operates, and the current sharing compensation signal is clamped. At time T1, when the current sharing control device detects the disappearance of the fault signal, or when the interleaved PFC exits burst mode or exits single-phase operation, the interleaved PFC master-slave phase currents can operate normally for current sharing. Figure 6 In the figure, 602 is the current sharing compensation signal and 601 is the master-slave phase inductor current signal. It can be analyzed from the figure that by adopting the solution of the present invention, the current sharing compensation current model is clamped in the above operating conditions, and the problem of uneven current sharing of interleaved PFC can be effectively avoided when exiting the above operating conditions, thereby improving the system stability.
[0040] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or nature of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. A current sharing control device for interleaved PFC circuits, characterized in that: The interleaved PFC circuit current sharing control device includes: The current sharing compensation module is used to generate a current sharing compensation signal based on the main phase current signal and the slave phase current signal of the interleaved PFC circuit. The current sharing compensation signal clamping module is used to clamp the voltage value of the current sharing compensation signal to a first set voltage threshold when either the main phase current signal or the slave phase current signal is zero, until both the main phase current signal and the slave phase current signal are not zero, and then release the clamping of the current sharing compensation signal. The pulse width modulation module is used to generate a master phase drive signal and a slave phase drive signal, and adjust the slave phase drive pulse width of the slave phase drive signal according to the comparison result between the current sharing compensation signal and the set reference signal.
2. The current sharing control device for an interleaved PFC circuit according to claim 1, characterized in that: The adjustment of the slave phase drive pulse width of the slave phase drive signal based on the comparison result between the current sharing compensation signal and the set reference signal specifically includes: A pulse width reduction unit is used to determine that the current sharing compensation signal is less than the set reference signal, and to reduce the slave phase drive pulse width. The pulse width amplification unit is used to determine that the current sharing compensation signal is greater than the set reference signal and increase the slave phase drive pulse width.
3. The current sharing control device for an interleaved PFC circuit according to claim 1, characterized in that: The first set voltage threshold is the same as the voltage of the set reference signal.
4. The current sharing control device for an interleaved PFC circuit according to claim 1, characterized in that: The current sharing compensation module includes a transconductance operational amplifier and a filter network. The current sharing compensation module generates a current sharing compensation signal on the filter network based on the current sampling signals of the first power loop and the second power loop of the interleaved PFC circuit through the transconductance operational amplifier.
5. The current sharing control device for an interleaved PFC circuit according to claim 1, characterized in that: The pulse width modulation module includes a main phase pulse width modulation module and a slave phase pulse width modulation module; The main phase pulse width modulation module generates the main phase drive signal of the interleaved PFC main phase switch, and the slave phase pulse width modulation module generates the slave phase drive signal of the interleaved PFC slave phase switch. At the same time, the slave phase pulse width modulation module adjusts the slave phase drive pulse width according to the comparison result of the current sharing compensation signal and the set reference signal.
6. The current sharing control device for an interleaved PFC circuit according to claim 1, characterized in that: When the output power, output current, or output voltage feedback signal is detected to be lower than the second set threshold, the slave phase drive signal of the slave phase switch is turned off, the current sharing compensation module is turned off, and the current sharing compensation signal clamping module is turned on to clamp the current sharing compensation signal voltage value to the first set voltage threshold. When the output power, output current, or output voltage feedback signal is detected to be greater than the third set threshold, the slave phase drive signal of the slave phase switch is turned on, the current sharing compensation module is turned on, and the current sharing compensation signal clamping module is turned off.
7. The current sharing control device for an interleaved PFC circuit according to claim 6, characterized in that: The difference between the second set threshold and the third set threshold has multiple configurable levels.
8. A current sharing control method for an interleaved PFC circuit, characterized in that: The current sharing control method for the interleaved PFC circuit includes: A current sharing compensation signal is generated based on the main phase current signal and the slave phase current signal of the interleaved PFC circuit. When either the main phase current signal or the slave phase current signal is zero, the voltage value of the current sharing compensation signal is clamped to a first set voltage threshold until both the main phase current signal and the slave phase current signal are not zero, and then the clamping of the current sharing compensation signal is released. A master phase drive signal and a slave phase drive signal are generated, and the slave phase drive pulse width of the slave phase drive signal is adjusted according to the comparison result between the current sharing compensation signal and the set reference signal.
9. The current sharing control method for an interleaved PFC circuit according to claim 8, characterized in that: The adjustment of the slave phase drive pulse width of the slave phase drive signal based on the comparison result between the current sharing compensation signal and the set reference signal specifically includes: If the current sharing compensation signal is determined to be less than the set reference signal, the slave phase drive pulse width is reduced. If the current sharing compensation signal is determined to be greater than the set reference signal, the slave phase drive pulse width is increased.
10. A current sharing control method for an interleaved PFC circuit according to claim 8, characterized in that: Also includes: When the output power, output current, or output voltage feedback signal is detected to be lower than the second set threshold, the slave phase drive signal of the slave phase switch is turned off, the current sharing compensation is turned off, and the current sharing compensation signal voltage value is clamped to the first set voltage threshold. When the output power, output current, or output voltage feedback signal is detected to be greater than the third set threshold, the slave phase drive signal of the slave phase switch is turned on, the current sharing compensation is turned on, and the clamping of the current sharing compensation signal is released.