Current comparison circuit and five-tube three-level DCDC converter

Abstract

This invention discloses a current comparison circuit and a five-transistor three-level DC-DC converter. The comparison circuit includes: a first input module for converting a first comparison current; a second input module for converting a second comparison current; a current matching comparison module for differentially comparing the first and second comparison currents and outputting a current difference signal; and a logic output module connected to the current matching comparison module for outputting a logic signal characterizing the voltage magnitude relationship between the first and second comparison terminals based on the current difference signal. This invention converts the target voltage difference into two comparison currents through the first and second input modules, performs differential comparison through the current matching comparison module, and finally outputs a logic level signal characterizing the voltage magnitude relationship through the logic output module, achieving rapid and accurate detection of the current direction of the switching transistors (especially weak reverse currents).

Description

Technical Field

[0001] This invention relates to the field of current detection technology, and in particular to a current comparison circuit and a five-transistor three-level DC-DC converter. Background Technology

[0002] A three-level DC-DC converter is a switching power supply circuit that can divide high voltage into three levels for step-down / step-up voltage conversion.

[0003] Most existing three-level DC-DC converters use series sampling resistors or traditional shunt detection methods to monitor the current of the switching transistor.

[0004] However, traditional sampling methods introduce additional conduction losses and are prone to insufficient sampling accuracy due to node potential deviations. Furthermore, they cannot meet the application requirements of bidirectional current detection (especially weak reverse current), fast response, and low loss in three-level topologies. Summary of the Invention

[0005] This invention provides a current comparison circuit and a five-transistor three-level DC-DC converter to solve the problems of decreased sampling accuracy and current ratio distortion caused by voltage drop in the sampling path in traditional current detection schemes. At the same time, it is adapted to the current detection requirements of multiple switches and multiple operating conditions in three-level DC-DC converters.

[0006] In a first aspect, embodiments of the present invention provide a current comparison circuit, comprising: The first input module is connected to the voltage comparison terminal and the first comparison terminal respectively, and is used to convert the voltage difference between the two into a first comparison current. The second input module is connected to the voltage comparison terminal and the second comparison terminal respectively, and is used to convert the voltage difference between the two into a second comparison current. A current matching comparison module is connected to the first input module and the second input module respectively, and is used to perform differential comparison between the first comparison current and the second comparison current, and output a current difference signal. A logic output module, connected to the current matching comparison module, is used to output a logic level signal based on the current difference signal; The logic level signal is used to characterize the voltage relationship between the first comparison terminal and the second comparison terminal.

[0007] Optionally, the voltage at the voltage comparison terminal is 2×VDD, and the voltage range of the first comparison terminal and the second comparison terminal is 0~2×VDD; The current matching comparison module includes a comparison node; The current comparison circuit includes a first mirror branch and a second mirror branch. The first mirror branch is connected to the comparator node and is used to convert the first comparator current into a pull-up current injected into the comparator node; The second mirror branch is connected to the comparator node and is used to convert the second comparator current into a pull-down current drawn from the comparator node; The pull-up current and the pull-down current are differentially superimposed at the comparison node to generate a voltage difference signal corresponding to the voltage difference between the two input voltages. The logic output module is further configured to determine and output a logic level signal representing the magnitude relationship between the first comparison current and the second comparison current based on the voltage difference signal.

[0008] Optionally, the first mirror branch includes a first switch group and a second switch group connected in series. The first switch group is connected to the first input module and is used to replicate the first comparison current; The first switch group is connected to the second switch group and is used to convert the copied first comparison current into the pull-up current; In the first mirror branch, the channel types of adjacent switch groups are different.

[0009] Optional, The first switch group includes a first N-type switch and a third N-type switch, and the second switch group includes a third P-type switch and a fourth P-type switch; The control electrode of the first N-type switch is shorted to the second electrode of the third N-type switch and then connected to the first input module. The first electrode of the first N-type switch is grounded to the ground potential node. The first terminal of the third N-type switch is grounded, and the second terminal is connected to the control terminal of the third P-type switch. The first terminal of the third P-type switch is connected to the power supply terminal, and the control terminal of the third P-type switch is shorted to the second terminal of the third P-type switch and then connected to the control terminal of the fourth P-type switch. The first terminal of the fourth P-type switch is connected to the power supply terminal, and the second terminal of the fourth P-type switch is connected to the comparison node.

[0010] Optionally, the second mirror branch includes a third switch group; The third switch group is connected to the second input module and is used to convert the second comparison current into the pull-down current; The third switch group has a different channel type than the second switch group.

[0011] Optional, The third switch group includes a second N-type switch and a fourth N-type switch; The control electrode of the second N-type switch is shorted to the second electrode of the second N-type switch and then connected to the second input module. The first electrode of the second N-type switch is grounded to the potential node. The control electrode of the fourth N-type switch is connected to the control electrode of the second N-type switch, the first electrode of the fourth N-type switch is grounded to the potential node, and the second electrode of the fourth N-type switch is connected to the comparison node.

[0012] Optionally, the current comparison circuit further includes a fifth P-type switch and a sixth P-type switch; The control terminal of the fifth P-type switch is connected to the power supply terminal, the first terminal of the fifth P-type switch is connected to the first input module, and the second terminal of the fifth P-type switch is connected to the first mirror branch. The control electrode of the sixth P-type switch is connected to the control electrode of the fifth P-type switch, the first electrode of the sixth P-type switch is connected to the second input module, and the second electrode of the sixth P-type switch is connected to the second mirror branch.

[0013] Optionally, the current comparison circuit further includes a constant current source, the first input module includes a first P-type switch, and the second input module includes a second P-type switch. The first terminal of the first P-type switch is connected to the voltage comparison terminal via a constant current source, the control terminal of the first P-type switch is connected to the first comparison terminal, and the second terminal of the first P-type switch is connected to the first mirror branch. The first terminal of the second P-type switch is connected to the voltage comparison terminal via a constant current source, the control terminal of the second P-type switch is connected to the second comparison terminal, and the second terminal of the second P-type switch is connected to the second mirror branch.

[0014] Optionally, the first input module further includes a first capacitor; the second input module further includes a second capacitor; One end of the first capacitor is connected to the control electrode of the first P-type switching transistor, and the other end is connected to the second electrode of the first P-type switching transistor. One end of the second capacitor is connected to the control electrode of the second P-type switch, and the other end is connected to the second electrode of the second P-type switch.

[0015] Optionally, a high-voltage isolation module may also be included; The high-voltage isolation module includes a sixth type N switch and a fifth type N switch; The first terminal of the sixth N-type switch is connected to the second input module, the second terminal of the sixth N-type switch is grounded to a potential node, and the control terminal of the sixth N-type switch is connected to the first switch control signal terminal. The first terminal of the fifth N-type switch is connected to the first terminal of the sixth N-type switch, the second terminal of the fifth N-type switch is connected to the second comparison terminal, and the control terminal of the fifth N-type switch is connected to the second switch control signal terminal. The signals output from the first switch control signal terminal and the second switch control signal terminal are complementary signals.

[0016] Secondly, embodiments of the present invention also provide a five-transistor three-level DC-DC converter, including a main power supply, a bias power supply, a flying capacitor, a first N-type switch, a second N-type switch, a third N-type switch, a fourth N-type switch, a fifth N-type switch, a first inductor, and a current comparison circuit as described in any of the first aspects; the current comparison circuit is used to detect the reverse current of the second N-type switch or the third N-type switch to achieve zero-crossing detection; the first terminal of the fourth N-type switch is connected to the main power supply, and the second terminal of the fourth N-type switch is connected to the third N-type switch. The first end of the transistor is connected to form the first node, and the second end of the third N-type switching transistor is connected to the second node; the first end of the second N-type switching transistor is connected to the second node, and the second end of the second N-type switching transistor is connected to the first end of the first N-type switching transistor to form the third node, and the second end of the first N-type switching transistor is grounded to the potential node; one end of the flying capacitor is connected to the first node, and the other end of the flying capacitor is connected to the third node; the fifth N-type switching transistor is connected between the bias power supply and the third node to balance the voltage of the flying capacitor; one end of the first inductor is connected to the second node, and the other end of the first inductor is connected to the load.

[0017] This invention provides a current comparison circuit and a five-transistor three-level DC-DC converter. The current comparison circuit includes: a first input module connected to a voltage comparison terminal and a first comparison terminal, used to convert the voltage difference between them into a first comparison current; a second input module connected to the voltage comparison terminal and the second comparison terminal, used to convert the voltage difference between them into a second comparison current; a current matching comparison module connected to the first input module and the second input module, used to perform differential comparison on the first comparison current and the second comparison current, and output a current difference signal; and a logic output module connected to the current matching comparison module, used to output a logic level signal based on the current difference signal; wherein the logic level signal is used to characterize the voltage magnitude relationship between the first comparison terminal and the second comparison terminal. This invention converts the target voltage difference into two comparison currents through the first and second input modules, performs differential comparison through the current matching comparison module, and finally outputs a logic level signal characterizing the voltage magnitude relationship through the logic output module, achieving rapid and accurate detection of the current direction of the switching transistor (especially weak reverse current). Compared to traditional solutions using resistor sampling or operational amplifier amplification, this circuit eliminates the need for series sampling resistors, avoiding sampling losses and the impact of high-voltage common-mode noise on detection accuracy. It features fast detection speed, low power consumption, strong anti-interference capability, and ease of integration. When applied to a five-transistor three-level DC-DC converter, this circuit can accurately detect the zero-crossing moment of the inductor current, promptly turning off the corresponding switch and effectively preventing energy waste caused by reverse inductor current, significantly improving the converter's efficiency under light load conditions. In a preferred embodiment, the current matching comparison module uses a first mirror branch and a second mirror branch to convert the two comparison currents into pull-up and pull-down currents respectively, and differentially superimposes them at the comparison node to generate a voltage difference signal corresponding to the input voltage difference. This differential comparison structure replaces the traditional voltage comparator with current domain subtraction, eliminating the influence of common-mode voltage changes on the comparison result and improving detection accuracy. In another preferred embodiment, the first mirror branch uses a cascaded structure of switch groups with different channel types, realizing current direction conversion and output impedance improvement, achieving high-voltage domain isolation, and ensuring the accuracy and stability of current replication over a wide voltage range. In another preferred embodiment, by connecting a capacitor between the gate and drain of MP1 and MP2, when a rapid transition occurs between the voltage comparison terminal and the first and second comparison terminals, the transient charge is discharged to the outside through the capacitor, avoiding the flow of sudden current into the internal mirror branch, effectively suppressing false triggering caused by voltage transition, and ensuring that the current comparison circuit outputs an accurate detection signal only when the inductor current truly crosses zero, further improving the reliability and anti-interference capability of the system. Attached Figure Description

[0018] Figure 1This is a partial structural schematic diagram of a five-transistor three-level DC-DC converter provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the inductor current waveform of a five-transistor three-level DC-DC converter provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a current comparison circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit principle of a current comparison circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit principle of another current comparison circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit principle of another current comparison circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a partial structural schematic diagram of a five-transistor three-level DC-DC converter provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the inductor current waveform of a five-transistor three-level DC-DC converter provided in an embodiment of the present invention. This embodiment is applicable to various power management systems, such as power supply modules for small energy storage devices and portable electronic devices. Figure 1As shown, this embodiment of the invention provides a five-transistor three-level DC-DC converter, including a main power supply VDD, a bias power supply Vdd, a flying capacitor CF, a first N-type switch S1, a second N-type switch S2, a third N-type switch S3, a fourth N-type switch S4, a fifth N-type switch S5, a first inductor L1, and a current comparison circuit; the first terminal of the fourth N-type switch S4 is connected to the main power supply VDD, and the second terminal of the fourth N-type switch S4 is connected to the first terminal of the third N-type switch S3 to form a first node VCT, the third N-type switch S5... The second terminal of transistor S3 is connected to the second node VSW; the first terminal of the second N-type transistor S2 is connected to the second node VSW, and the second terminal of the second N-type transistor S2 is connected to the first terminal of the first N-type transistor S1 to form the third node VCB. The second terminal of the first N-type transistor S1 is grounded to node B; one end of the flying capacitor CF is connected to the first node VCT, and the other end of the flying capacitor CF is connected to the third node VCB; the fifth N-type transistor S5 is connected between the bias power supply Vdd and the third node VCB to balance the voltage of the flying capacitor CF. The current comparison circuit is used to detect the reverse current of the second N-type transistor S2 or the third N-type transistor S3 to achieve zero-crossing detection.

[0022] Specifically, the DC-DC converter provided in this embodiment of the invention has four operating states according to different voltage values ​​at the VSW terminal. In the first state, the fourth N-type switch S4, the third N-type switch S3, and the first N-type switch S1 are turned on, while the remaining power transistors are turned off. The main power supply VDD charges the flying capacitor CF and the first inductor L1 through the fourth N-type switch S4, and the voltage at the second node VSW is equal to the voltage of the main power supply VDD (assuming the voltage provided by the main power supply VDD is VDD). In the second state, the fifth N-type switch S5 and the third N-type switch S3 are turned on, while the remaining power transistors are turned off. The voltage at the second node VSW becomes 2VDD, and the flying capacitor CF charges the first inductor L1 through the third N-type switch S3. In the third state, the fourth N-type switch S4, the second N-type switch S2, and the first N-type switch S1 are turned on, while the remaining power transistors are turned off. The voltage at the second node VSW becomes VSS (assuming VSS is the ground potential at node B), the flying capacitor CF is charged, and the first inductor L1 either freewheels or discharges through the second N-type switch S2. In the fourth state, the fourth N-type switch S4 and the first N-type switch S1 are turned on, the remaining power transistors are turned off, the state of the second node VSW is unknown, and the flying capacitor CF is charged. In this embodiment, the current direction when the first inductor L1 is charging is defined as the positive current direction, and the current direction when the first inductor L1 is discharging is defined as the negative current direction. The current direction when the inductor is charging is defined as the positive current direction, and the current direction when the inductor is discharging is defined as the negative current direction. From the above descriptions of the various operating states, it can be seen that when the load current is small, the average current flowing through the inductor is also small, and the inductor current has a sawtooth waveform, such as... Figure 2As shown, the peak value is The average value is the load current. ,when When the inductor current is less than 0, such as Figure 2 The portion below the dashed line (0) indicates that the inductor current is reversed. Reverse inductor current wastes energy and reduces system efficiency.

[0023] Therefore, to solve this problem, embodiments of the present invention provide a current comparison circuit. Figure 3 This is a schematic diagram of a current comparison circuit provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the circuit principle of a current comparison circuit provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the circuit principle of another current comparison circuit provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the circuit principle of another current comparison circuit provided in an embodiment of the present invention. (Reference) Figure 3 The current comparison circuit provided in this embodiment of the invention is used to detect the current flowing through the switch transistor under test 1 (i.e., the second N-type switch transistor S2 or the third N-type switch transistor S3 mentioned above). The circuit specifically includes: a first input module 100, which is connected to the voltage comparison terminal VS and the first comparison terminal V1 respectively, and is used to convert the voltage difference between the two into a first comparison current; a second input module 200, which is connected to the voltage comparison terminal VS and the second comparison terminal V2 respectively, and is used to convert the voltage difference between the two into a second comparison current; a current matching comparison module 300, which is connected to the first input module 100 and the second input module 200 respectively, and is used to perform differential comparison on the first comparison current and the second comparison current, and output a current difference signal; and a logic output module 400, which is connected to the current matching comparison module 300, and is used to output a logic level signal according to the current difference signal.

[0024] The logic level signal is used to characterize the voltage relationship between the first comparison terminal and the second comparison terminal.

[0025] Specifically, the first input module 100 detects the voltage difference between the voltage comparison terminal VS and the first comparison terminal V1, and converts this voltage difference into a first comparison current, the magnitude of which is proportional to (VS-V1). The second input module 200 detects the voltage difference between the voltage comparison terminal VS and the second comparison terminal V2, and converts this voltage difference into a second comparison current, the magnitude of which is proportional to (VS-V2). By appropriately selecting the connection points of V1 and V2 (e.g., connecting them to the first and second terminals of the switch transistor 1 under test, respectively), (VS-V1) and (VS-V2) can reflect the actual voltage difference across the switch transistor. The current matching comparison module 300 receives the first comparison current and the second comparison current, performs a differential comparison, and outputs a current difference signal. The sign and magnitude of this signal directly reflect the difference between (VS-V1) and (VS-V2), that is, the voltage polarity across the switch transistor under test. When the current of the switch transistor under test is in the positive direction, the voltage across it exhibits one polarity; when the current of the switch transistor under test is in the negative direction (reverse current), the voltage polarity across it is reversed. The logic output module 400 converts the current difference signal into a logic level signal. By detecting whether this logic level is high or low, it can be determined whether there is reverse current in the switch under test. When reverse current is detected, this signal can be used to trigger the control circuit to turn off the corresponding switch in time, preventing the inductor current from reversing, thereby reducing energy loss and improving the efficiency of the DC-DC converter under light load conditions.

[0026] This invention provides a current comparison circuit that converts the voltage difference between the terminals of the switch under test (SUT) and a common reference point into two proportional comparison currents via a first input module and a second input module. These two currents are then differentially compared by a current matching comparison module. Finally, a logic output module converts the current difference signal into a logic level signal representing the current direction of the SUT. This current comparison circuit solves the problems of high losses, slow response, and difficulty in accurately detecting weak reverse currents caused by resistor sampling or operational amplifier amplification in traditional current detection schemes, as well as susceptibility to common-mode noise interference at high-voltage, high-speed switching nodes. It achieves fast, accurate, and low-loss detection of reverse current in the switch, thereby preventing reverse inductor current by timely switching off the switch, reducing energy loss, and improving system efficiency.

[0027] In an optional embodiment, the voltage at the voltage comparison terminal is 2×VDD, and the voltage range between the first comparison terminal and the second comparison terminal is 0~2×VDD. The current matching comparison module 300 includes a comparison node A; the current comparison module 300 includes a first mirror branch 310 and a second mirror branch 320; the first mirror branch 310 is connected to the comparison node A and is configured to convert a first comparison current into a pull-up current injected into the comparison node A; the second mirror branch 320 is connected to the comparison node A and is configured to convert a second comparison current into a pull-down current extracted from the comparison node A; the pull-up current and the pull-down current are differentially superimposed at the comparison node A to generate a voltage difference signal corresponding to the difference between the two input voltages; the logic output module 400 is further configured to determine and output a logic level signal characterizing the magnitude relationship between the first comparison current and the second comparison current according to the voltage difference signal.

[0028] Specifically, in the current comparison circuit 300, the voltage of the voltage comparison terminal VS is set to 2×VDD, and the voltage ranges of the first comparison terminal V1 and the second comparison terminal V2 are both 0 to 2×VDD. This voltage range setting is matched with the operating voltage of the five-transistor three-level DCDC converter (for example, VS corresponds to the 2VDD node, and V1 and V2 correspond to nodes such as VCF and VSW respectively). The first mirror branch 310 receives the first comparison current and replicates and converts it into a pull-up current injected into the comparison node A (the current flows into node A) through a current mirror structure; the second mirror branch 320 receives the second comparison current and replicates and converts it into a pull-down current extracted from the comparison node A (the current flows out of node A) through a current mirror structure. At the comparison node A, the pull-up current and the pull-down current are differentially superimposed to generate a voltage difference signal corresponding to the difference between the two input voltages (V1 - V2). When V1 > V2, the first comparison current is less than the second comparison current, the pull-down current is greater than the pull-up current, and the voltage of the comparison node A is pulled down; when V1 < V2, the first comparison current is greater than the second comparison current, the pull-up current is greater than the pull-down current, and the voltage of the comparison node A is pulled up. The logic output module 400 determines and outputs a logic level signal characterizing the magnitude relationship between the first comparison current and the second comparison current according to the voltage difference signal of the comparison node A. This signal directly reflects the voltage polarity at both ends of the待测开关管 (the second N-type switch tube S2 or the third N-type switch tube S3), and further characterizes its current direction, realizing the zero-crossing detection function.

[0029] In an optional embodiment, the first mirror branch 310 includes a first switch group 311 and a second switch group 312 connected in series in sequence; the first switch group 311 is connected to the first input module 100 and is configured to replicate the first comparison current; the first switch group 311 is connected to the second switch group 312 and is configured to convert the replicated first comparison current into a pull-up current; wherein, the channel types of adjacent switch groups in the first mirror branch 310 are different.

[0030] It should be noted that there is an unclear expression "待测开关管" in the original text, which may need to be further clarified according to the specific context. Here it is directly translated as "待测开关管".The first switch group 311 and the second switch group 312 can be understood as a current mirror circuit composed of several switching transistors of the same type (such as PMOS transistors).

[0031] Specifically, the first mirror branch 310 adopts a cascaded current mirror structure, consisting of a first switch group 311 and a second switch group 312 connected in series. The first switch group 311 (e.g., an NMOS current mirror) is connected to the first input module 100, receives the first comparison current, and generates an intermediate current proportional to the first comparison current through proportional replication via the current mirror. This intermediate current then flows into the second switch group 312 (e.g., a PMOS current mirror). Since the first switch group 311 and the second switch group 312 have different channel types (e.g., NMOS → PMOS), the second switch group 312 reverses the current direction of this intermediate current and further replicates it, ultimately outputting a pull-up current injected into the comparison node A. By superimposing two stages of current mirrors, the accuracy of current replication and output impedance are improved, the high-voltage environment is isolated, the ability to resist power supply voltage fluctuations and noise is enhanced, and stable operation is ensured within a wide voltage range (0~2×VDD).

[0032] In an optional embodiment, the first switch group 311 includes a first N-type switch MN1 and a third N-type switch MN3, and the second switch group 312 includes a third P-type switch MP3 and a fourth P-type switch MP4; the control electrode of the first N-type switch MN1 is shorted to the second electrode of the first N-type switch MN1 and then connected to the first input module 100, and the first electrode of the first N-type switch MN1 is grounded to the potential node B; the control electrode of the third N-type switch MN3 is connected to the control electrode of the first N-type switch MN1; the first electrode of the third N-type switch MN3 is grounded to the potential node B, and the second electrode is connected to the control electrode of the third P-type switch MP3; the first electrode of the third P-type switch MP3 is connected to the power supply terminal, and the control electrode of the third P-type switch MP3 is shorted to the second electrode of the third P-type switch MP3 and then connected to the control electrode of the fourth P-type switch MP4; the first electrode of the fourth P-type switch MP4 is connected to the power supply terminal, and the second electrode of the fourth P-type switch MP4 is connected to the comparison node A.

[0033] Among them, the grounding potential node B is not directly grounded, but can be understood as having an approximate zero potential.

[0034] Specifically, in the first mirror branch 310, the first switch group 311 consists of an NMOS current mirror formed by a first N-type switch MN1 and a third N-type switch MN3. The control electrode (gate) of the first N-type switch MN1 is shorted to its second electrode (drain) and connected to the first input module 100 to receive the first comparison current; the control electrode of the third N-type switch MN3 is connected to the control electrode of the first N-type switch MN1. The first electrode (source) of the first N-type switch MN1 and the first electrode (source) of the third N-type switch MN3 are connected through a ground potential node B. The second electrode (drain) of the third N-type switch MN3 is connected to the control electrode (gate) of the third P-type switch MP3. The first comparison current is replicated through the MN1-MN3 current mirror, generating a mirror current proportional to the first comparison current at the drain of the third N-type switch MN3. The second switch group 312 consists of a PMOS current mirror formed by a third P-type switch MP3 and a fourth P-type switch MP4. The control gate and drain of the third P-type switch MP3 are shorted and then connected to the control gate of the fourth P-type switch MP4. The first source of the third P-type switch MP3 is connected to the first source of the fourth P-type switch MP4, and an external voltage VDD is applied. The second drain is connected to the comparator node A. The mirrored current output from the first switch group 311 flows into the drain of the third P-type switch MP3, is replicated and its current direction is reversed through the current mirror of the third P-type switch MP3-fourth P-type switch MP4, and finally outputs as a pull-up current injected into the comparator node A at the drain of the fourth P-type switch MP4.

[0035] In an optional embodiment, the second mirror branch includes a third switch group 321; the third switch group 321 is connected to the second input module 200 and is used to convert the second comparison current into a pull-down current; The third switch group 321 has a different channel type than the second switch group 312.

[0036] Specifically, the third switch group 321 (such as an NMOS current mirror) is connected to the second input module 200 and receives the second comparison current. Through the current mirror replication, the third switch group 321 converts the second comparison current into a pull-down current drawn from the comparison node A. Since the channel type of the third switch group 321 is different from that of the second switch group 312 (PMOS current mirror) in the first mirror branch, the pull-up current output from the first mirror branch (current flowing into comparison node A) and the pull-down current output from the second mirror branch (current flowing out of comparison node A) are differentially superimposed at comparison node A. This ensures that the pull-up current and the pull-down current can be accurately subtracted at comparison node A to generate a voltage difference signal reflecting the voltage difference between the two inputs (V1-V2), providing a basis for the correct judgment of the subsequent logic output module.

[0037] In an optional embodiment, the third switch group 321 includes a second N-type switch MN2 and a fourth N-type switch MN4; The control electrode of the second N-type switch MN2 is shorted to the second electrode of the second N-type switch MN2 and then connected to the second input module 200. The first electrode of the second N-type switch MN2 is grounded to the potential node B. The control electrode of the fourth N-type switch MN4 is connected to the control electrode of the second N-type switch MN2. The first electrode of the fourth N-type switch MN4 is grounded to the potential node B, and the second electrode of the fourth N-type switch MN4 is connected to the comparison node 301.

[0038] Specifically, the third switch group 321 in the second mirror branch 320 consists of an NMOS current mirror formed by a second N-type switch MN2 and a fourth N-type switch MN4. The control electrode (gate) and the second electrode (drain) of the second N-type switch MN2 are shorted and connected to the second input module 200, forming a diode connection, to receive the second comparison current output from the second input module 200; the first electrode (source) of the second N-type switch MN2 is connected to ground potential node B. The control electrode (gate) of the fourth N-type switch MN4 is connected to the control electrode of the second N-type switch MN2, forming the common gate node of the current mirror; the first electrode (source) of the fourth N-type switch MN4 is connected to ground potential node B, and the second electrode (drain) of the fourth N-type switch MN4 is connected to comparator node A. When the second comparison current flows into MN2, it is proportionally replicated through the MN2-MN4 current mirror, resulting in a mirror current proportional to the second comparison current output at the drain of MN4. This current flows from comparator node A to MN4, forming a pull-down current drawn from comparator node A. The pull-down current and the pull-up current injected into the comparator node A by the first mirror branch 310 are differentially superimposed at the comparator node A to generate a voltage difference signal reflecting the difference between the two input voltages.

[0039] In an optional embodiment, the current comparison module 300 further includes a fifth P-type switch MP5 and a sixth P-type switch MP6; The control terminal of the fifth P-type switching transistor MP5 is connected to the power supply terminal, the first terminal of the fifth P-type switching transistor MP5 is connected to the first input module 100, and the second terminal of the fifth P-type switching transistor MP5 is connected to the first mirror branch 310. The control electrode of the sixth P-type switch MP6 is connected to the control electrode of the fifth P-type switch MP5. The first electrode of the sixth P-type switch MP6 is connected to the second input module 200, and the second electrode of the sixth P-type switch MP6 is connected to the second mirror branch 320.

[0040] Specifically, the gate of the sixth P-type switch MP6 is connected to the gate of the fifth P-type switch MP5 (i.e., common gate) and to the power supply terminal (such as the bias voltage VDD). The first terminal (source) of the fifth P-type switch MP5 is connected to the first input module 100, and the second terminal (drain) is connected to the first mirror branch 310. The first terminal (source) of the sixth P-type switch MP6 is connected to the second input module 200, and the second terminal (drain) is connected to the second mirror branch 320. The sixth P-type switch MP6 and the fifth P-type switch MP5 form a pair of current mirrors, providing equal bias currents to the first input module 100 and the second input module 200. This ensures that the two input modules operate at the same static operating point, effectively eliminating offset errors introduced by process deviations or temperature changes. It also improves the accuracy and stability of the current comparison circuit for detecting weak voltage differences, thereby ensuring the symmetry and matching of the two voltage-to-current conversions.

[0041] In an optional embodiment, the comparator circuit further includes a constant current source 700, the first input module 100 includes a first P-type switch MP1, and the second input module 200 includes a second P-type switch MP2; The first terminal of the first P-type switching transistor MP1 is connected to the voltage comparison terminal 101 through the constant current source 700, the control terminal of the first P-type switching transistor MP1 is connected to the first comparison terminal V1, and the second terminal of the first P-type switching transistor MP1 is connected to the first mirror branch 310 through the constant current source 700. The first terminal of the second P-type switch MP2 is connected to the voltage comparison terminal V1, the control terminal of the second P-type switch MP2 is connected to the second comparison terminal V2, and the second terminal of the second P-type switch MP2 is connected to the second mirror branch 320.

[0042] Specifically, the first input module 100 includes a first P-type switch MP1, and the second input module 200 includes a second P-type switch MP2. Both MP1 and MP2 are PMOS transistors, with their first terminal (source) connected to the voltage comparison terminal VS (e.g., a 2×VDD node). The control terminal (gate) of MP1 is connected to the first comparison terminal V1, and the second terminal (drain) of MP1 is connected to the first mirror branch 310; the control terminal (gate) of MP2 is connected to the second comparison terminal V2, and the second terminal (drain) of MP2 is connected to the second mirror branch 320. When the switch under test is turned on, there is a forward voltage drop between its first and second terminals, causing V1 and V2 to have different potentials. The source voltage of MP1 is VS, and the gate voltage is V1, with a gate-source voltage VGS1 = VS - V1; the source voltage of MP2 is VS, and the gate voltage is V2, with a gate-source voltage VGS2 = VS - V2. According to the saturation current formula of a PMOS transistor, the drain current of MP1 (i.e., the first comparison current) is proportional to the square of (VS-V1), and the drain current of MP2 (i.e., the second comparison current) is proportional to the square of (VS-V2). Therefore, the magnitudes of the first and second comparison currents directly reflect the voltage difference between V1 and V2 relative to VS, and thus reflect the voltage polarity across the transistor under test.

[0043] Continue to refer to Figure 3 In one specific embodiment, the current comparison circuit is used to detect the reverse current of S3. MP1 and MP2 are input differential pairs, connected to the first node VCT and VSW terminals respectively. Since the maximum voltage of VSW and VCT is 2VDD, the power supply providing the bias current is also 2VDD. The magnitude of the currents of MP1 and MP2 reflects the voltage levels of VCT and VSW. The current of MP1 is finally output to MP4 through two sets of current mirrors, MN1 and MN3, and MP3 and MP4. The current of MP2 is output to MN4 through the current mirrors MN2 and MN4. MP4 and MN4 are output through current comparison. When there is a reverse current in S3, it means that the voltage of VSW is higher than the voltage of VCT. Therefore, the current of MP1 is greater than the current of MP2, that is, the current of MP4 is greater than the current of MN4. Voltage node A is pulled high, and after processing by the logic output module 400, a high level is output, indicating that a reverse current has appeared on S3.

[0044] refer to Figure 4 In an optional embodiment, the first input module 100 further includes a first capacitor 111; the second input module 200 further includes a second capacitor 211. One end of the first capacitor 111 is connected to the control electrode of the first P-type switching transistor MP1, and the other end is connected to the second electrode of the first P-type switching transistor MP1. One end of the second capacitor 211 is connected to the control electrode of the second P-type switching transistor MP2, and the other end is connected to the second electrode of the second P-type switching transistor MP2.

[0045] Specifically, during the operation of the DC-DC converter, the voltages at the voltage comparison terminals VS and V1 rapidly change between different operating states. For example, when VSW changes from 2VDD to VDD, the change is extremely fast (approximately 1ns to 2ns). During this transient process, the source and drain of MP1 and MP2 both need to switch from higher to lower voltages. Without capacitors C1 / C2, the gate voltage change of MP1 / MP2 will discharge into the circuit through its channel, generating a sudden drain current. This current flows directly into the first mirror branch 310 and the second mirror branch 320, potentially causing uncontrollable transient current changes in MN1 / MN2. If the current in MN1 is greater than the current in MN2, it will trigger an increase in the voltage of the comparison node A, causing the logic output module 400 to output a high level. However, at this time, the actual inductor current is still in the positive direction (not yet crossing zero), resulting in a false trigger. By adding a first capacitor 111 and a second capacitor 211, during rapid voltage changes, the charge between the gate and drain of MP1 / MP2 is preferentially discharged to the outside through the low-impedance path formed by the capacitors, rather than flowing into the internal mirror branch. This design effectively suppresses the sudden current flowing into the first mirror branch 310 and the second mirror branch 320 during transient voltage changes, avoiding false triggering of MN1 / MN2 due to transient current mismatch. This ensures that the current comparison circuit outputs an accurate zero-crossing detection signal only when the inductor current truly crosses zero, improving the system's reliability and anti-interference capability.

[0046] In a specific embodiment, considering the detection speed, MN1~MN4, MP3, MP4, and subsequent circuits all use low-voltage devices, and the voltage of one VGS is generally less than 1V. When the gate voltage of MP1 and MP2 is VDD, the voltage difference between their drain and source is approximately VDD + VSGP - VGSN, where VSGP is the VSG voltage of MP1 / MP2, and VGSN is the VGS voltage of MN1 / MN2. (VDD + VSGP - VGSN) may be higher than VDD, posing an overvoltage risk to MP1 / MP2. Therefore, protection transistors MP5 / MP6 are needed to reduce the source-drain voltage difference of MP1 / MP2 and avoid overvoltage. When the voltage of the first comparison terminal V1 (e.g., VSW) and the first comparison terminal V2 (e.g., VCT) is 2VDD, the detection circuit does not work, and the current of MP1 and MP2 is 0. When VSW and VCT voltages transition to VDD, MP1 and MP2 begin to draw current. However, because the transition from 2VDD to VDD is very rapid, typically occurring within 1ns to 2ns, both the source and drain of MP1 / MP2 need to switch from a higher voltage to a lower voltage, resulting in discharge into the circuit. Specifically, this discharge occurs into MN1 / MN2, causing a sudden increase in current in MN1 and MN2. Since this current change is not constant, the magnitude of the sudden current in MN1 and MN2 is uncertain. If the current in MN1 is greater than the current in MN2, then the current in MP4 is greater than the current in MN4, causing the voltage at comparator node A to go high, resulting in a high-level output. At this time, VSW has only just transitioned from 2VDD to VDD, and the current is still positive. Therefore, the high level of zc_out at this moment is actually a false trigger. To avoid this problem, a capacitor C1 / C2 is added between the gate and drain terminals of MP1 / MP2. When the VSW / VCT voltage switches from 2VDD to VDD, it does not discharge into the circuit, but discharges to the outside through the capacitor to reduce false triggering caused by sudden current changes on MN1 / MN2.

[0047] refer to Figure 5 In an optional embodiment, it further includes a high-voltage isolation module 600; the high-voltage isolation module 600 includes a sixth N-type switch MN6 and a fifth N-type switch MN5; The first terminal of the sixth N-type switch MN6 is connected to the second input module 200, the second terminal of the sixth N-type switch MN6 is grounded to the potential node B, and the control terminal of the sixth N-type switch MN6 is connected to the first switch control signal terminal S1_ON_B. The first terminal of the fifth N-type switch MN5 is connected to the first terminal of the sixth N-type switch MN6, the second terminal of the fifth N-type switch MN5 is connected to the second comparison terminal V2, and the control terminal of the fifth N-type switch MN5 is connected to the second switch control signal terminal S1_ON. The signals output from the first switch control signal terminal S1_ON_B and the second switch control signal terminal S1_ON are complementary signals.

[0048] Specifically, it is used to detect the zero-crossing current of S2. As can be seen from the operating state of the DC-DC converter in the above embodiment, S2 is only turned on in GND state. When the current is positive, the drain voltage of S2 is less than the source voltage, and both are less than 0. When the current is negative, the drain voltage of S2 is greater than the source voltage, and both are greater than 0. Therefore, the drain voltage of S2 and the 0 voltage are selected as the input voltage of the zero-crossing detection circuit. The drain voltage is the voltage of the second node VSW. The working principle of this zero-crossing detection circuit is basically the same as that of the S3 zero-crossing detection circuit in the above embodiment, determining whether a reverse current has occurred by comparing the magnitudes of the currents of MP1 and MP2. Since the voltage of the second node VSW is different in different states, when it rises to 2VDD, the device faces the risk of overvoltage; therefore, 2VDD cannot be connected to the circuit. A pair of high-voltage transistors (the fifth N-type switch MN5 and the sixth N-type switch MN6) are introduced, where MN5 is connected between the gates of VSW and MP2, and MN6 is connected between VSW and GND. When VSW is in the 2VDD state, S1 is off. In both GND and VDD states, S1 is on. Therefore, the switching signal of S1 can be used as the switching signal for MN5 / MN6. When VSW is 2VDD, S1_ON is low and S1_ON_B is high, MN5 is off, MN6 is on, VSW is isolated from the detection circuit, and VSW1 is pulled to 0. When VSW is in the GND or VDD state, S1_ON is high and S1_ON_B is low, MN5 is on, VSW1 = VSW, and the high voltage will no longer be seen at the MP2 input.

[0049] It should be noted that VSW1 can be approximately understood as VSW after removing the 2VDD high voltage state.

[0050] refer to Figure 1This invention also provides a five-transistor three-level DC-DC converter, including a main power supply VDD, a bias power supply Vdd, a flying capacitor CF, a first N-type switch S1, a second N-type switch S2, a third N-type switch S3, a fourth N-type switch S4, a fifth N-type switch S5, a first inductor L1, and a current comparison circuit; the first terminal of the fourth N-type switch S4 is connected to the main power supply VDD, and the second terminal of the fourth N-type switch S4 is connected to the first terminal of the third N-type switch S3 to form a first node VCT, and the third N-type switch... The second terminal of transistor S3 is connected to the second node VSW; the first terminal of the second N-type switch S2 is connected to the second node VSW, and the second terminal of the second N-type switch S2 is connected to the first terminal of the first N-type switch S1 to form the third node VCB. The second terminal of the first N-type switch S1 is grounded to node B; one end of the flying capacitor CF is connected to the first node VCT, and the other end of the flying capacitor CF is connected to the third node VCB; the fifth N-type switch S5 is connected between the bias power supply Vdd and the third node VCB to balance the voltage of the flying capacitor CF. The current comparison circuit is used to detect the reverse current of the second N-type switch S2 or the third N-type switch S3 to achieve zero-crossing detection.

[0051] Specifically, the five-transistor three-level DC-DC converter provided in this embodiment of the invention comprises a main power supply VDD, a flying capacitor CF, five N-type switches (S1-S5), and a first inductor L1. The fourth N-type switch S4, the third N-type switch S3, the second N-type switch S2, and the first N-type switch S1 are connected in series to form a current path from the main power supply VDD to ground. The fifth N-type switch S5 is connected between the bias power supply Vdd and the third node VCB to balance the voltage across the flying capacitor CF. The flying capacitor CF is connected between the first node VCT and the third node VCB, and the three-level output is achieved through the timing coordination of the switches. During converter operation, the second N-type switch S2 and the third N-type switch S3 carry the charging and discharging current of the inductor L1. In the S3 zero-crossing detection circuit, the first comparison terminal V1 is connected to the voltage signal VCT, whose voltage range covers 0V, VDD to 2VDD, serving as the gate input voltage of the differential pair transistor MP1. The second comparison terminal V2 is connected to the voltage signal VSW, whose voltage range covers 0V, VDD to 2VDD, serving as the gate input voltage of the differential pair transistor MP2. The circuit uses a cross-difference comparison method between VCT and VSW, without an independent external reference point, directly using the voltage difference between the two signals as the criterion. When the VSW voltage is higher than the VCT voltage, it is determined that a reverse current has occurred in the S3 branch. In the S2 zero-crossing detection circuit… The first comparison terminal V1 is connected to a fixed reference voltage GND, i.e., 0V, which serves as the gate input voltage for the differential pair transistor MP1. The second comparison terminal V2 is connected to a voltage signal VSW1 that has undergone high-voltage isolation. The voltage range of this signal is limited to between 0V and VDD, corresponding to the 0V and VDD states of the original VSW voltage. When the original VSW voltage is 2VDD, the signal is completely isolated and serves as the gate input voltage for the differential pair transistor MP2. The circuit uses a direct comparison method between VSW1 and 0V to determine whether the current in the S2 branch crosses zero and its direction by comparing the voltage levels of VSW1 and GND.

[0052] It should be understood that the specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A current comparison circuit, characterized in that, include: The first input module is connected to the voltage comparison terminal and the first comparison terminal respectively, and is used to convert the voltage difference between the two into a first comparison current. The second input module is connected to the voltage comparison terminal and the second comparison terminal respectively, and is used to convert the voltage difference between the two into a second comparison current. A current matching comparison module is connected to the first input module and the second input module respectively, and is used to perform differential comparison between the first comparison current and the second comparison current, and output a current difference signal. A logic output module, connected to the current matching comparison module, is used to output a logic level signal based on the current difference signal; The logic level signal is used to characterize the voltage relationship between the first comparison terminal and the second comparison terminal.

2. The current comparison circuit according to claim 1, characterized in that, The voltage at the voltage comparison terminal is 2×VDD, and the voltage range of the first comparison terminal and the second comparison terminal is 0~2×VDD; The current matching comparison module includes a comparison node; The current comparison circuit includes a first mirror branch and a second mirror branch. The first mirror branch is connected to the comparator node and is used to convert the first comparator current into a pull-up current injected into the comparator node; The second mirror branch is connected to the comparator node and is used to convert the second comparator current into a pull-down current drawn from the comparator node; The pull-up current and the pull-down current are differentially superimposed at the comparison node to generate a voltage difference signal corresponding to the voltage difference between the two input voltages. The logic output module is further configured to determine and output a logic level signal representing the magnitude relationship between the first comparison current and the second comparison current based on the voltage difference signal.

3. The current comparison circuit according to claim 2, characterized in that, The first mirror branch includes a first switch group and a second switch group connected in series. The first switch group is connected to the first input module and is used to replicate the first comparison current; The first switch group is connected to the second switch group and is used to convert the copied first comparison current into the pull-up current; In the first mirror branch, the channel types of adjacent switch groups are different.

4. The current comparison circuit according to claim 3, characterized in that, The first switch group includes a first N-type switch and a third N-type switch, and the second switch group includes a third P-type switch and a fourth P-type switch; The control electrode of the first N-type switch is shorted to the second electrode of the first N-type switch and then connected to the first input module. The first electrode of the first N-type switch is grounded to the ground potential node. The control electrode of the third N-type switch is connected to the control electrode of the first N-type switch; The first terminal of the third N-type switch is grounded, and the second terminal is connected to the control terminal of the third P-type switch. The first terminal of the third P-type switch is connected to the power supply terminal, and the control terminal of the third P-type switch is shorted to the second terminal of the third P-type switch and then connected to the control terminal of the fourth P-type switch. The first terminal of the fourth P-type switch is connected to the power supply terminal, and the second terminal of the fourth P-type switch is connected to the comparison node.

5. The current comparison circuit according to claim 3, characterized in that, The second mirror branch includes a third switch group; The third switch group is connected to the second input module and is used to convert the second comparison current into the pull-down current; The third switch group has a different channel type than the second switch group.

6. The current comparison circuit according to claim 5, characterized in that, The third switch group includes a second N-type switch and a fourth N-type switch; The control electrode of the second N-type switch is shorted to the second electrode of the second N-type switch and then connected to the second input module. The first electrode of the second N-type switch is grounded to the potential node. The control electrode of the fourth N-type switch is connected to the control electrode of the second N-type switch, the first electrode of the fourth N-type switch is grounded to the potential node, and the second electrode of the fourth N-type switch is connected to the comparison node.

7. The current comparison circuit according to claim 2, characterized in that, The current comparison circuit also includes a fifth P-type switch and a sixth P-type switch; The control terminal of the fifth P-type switch is connected to the power supply terminal, the first terminal of the fifth P-type switch is connected to the first input module, and the second terminal of the fifth P-type switch is connected to the first mirror branch. The control electrode of the sixth P-type switch is connected to the control electrode of the fifth P-type switch, the first electrode of the sixth P-type switch is connected to the second input module, and the second electrode of the sixth P-type switch is connected to the second mirror branch.

8. The current comparison circuit according to claim 2, characterized in that, The current comparison circuit further includes a constant current source; the first input module includes a first P-type switching transistor; the second input module includes a second P-type switching transistor. The first terminal of the first P-type switch is connected to the voltage comparison terminal through the constant current source, the control terminal of the first P-type switch is connected to the first comparison terminal, and the second terminal of the first P-type switch is connected to the first mirror branch. The first terminal of the second P-type switch is connected to the voltage comparison terminal through the constant current source, the control terminal of the second P-type switch is connected to the second comparison terminal, and the second terminal of the second P-type switch is connected to the second mirror branch.

9. The current comparison circuit according to claim 8, characterized in that, The first input module further includes a first capacitor; the second input module further includes a second capacitor; One end of the first capacitor is connected to the control electrode of the first P-type switching transistor, and the other end is connected to the second electrode of the first P-type switching transistor. One end of the second capacitor is connected to the control electrode of the second P-type switch, and the other end is connected to the second electrode of the second P-type switch.

10. The current comparison circuit according to claim 1, characterized in that, It also includes a high-voltage isolation module; The high-voltage isolation module includes a sixth type N switch and a fifth type N switch; The first terminal of the sixth N-type switch is connected to the second input module, the second terminal of the sixth N-type switch is grounded to a potential node, and the control terminal of the sixth N-type switch is connected to the first switch control signal terminal. The first terminal of the fifth N-type switch is connected to the first terminal of the sixth N-type switch, the second terminal of the fifth N-type switch is connected to the second comparison terminal, and the control terminal of the fifth N-type switch is connected to the second switch control signal terminal. The signals output from the first switch control signal terminal and the second switch control signal terminal are complementary signals.

11. A five-transistor three-level DC-DC converter, characterized in that, It includes a main power supply, a bias power supply, a flying capacitor, a first N-type switch, a second N-type switch, a third N-type switch, a fourth N-type switch, a fifth N-type switch, a first inductor, and a current comparison circuit as described in any one of claims 1 to 10; The current comparison circuit is used to detect the reverse current of the second N-type switch or the third N-type switch to achieve zero-crossing detection. The first end of the fourth N-type switch is connected to the main power supply, the second end of the fourth N-type switch is connected to the first end of the third N-type switch to form a first node, and the second end of the third N-type switch is connected to the second node. The first end of the second N-type switch is connected to the second node, the second end of the second N-type switch is connected to the first end of the first N-type switch to form a third node, and the second end of the first N-type switch is grounded to the potential node. One end of the flying capacitor is connected to the first node, and the other end of the flying capacitor is connected to the third node; The fifth N-type switch is connected between the bias power supply and the third node to balance the voltage of the flying capacitor; One end of the first inductor is connected to the second node, and the other end of the first inductor is connected to the load.

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