Delta-sigma modulation and parallel implementation method for high-speed permanent magnet synchronous motor

Abstract

The application discloses a high-speed permanent magnet synchronous motor Delta-Sigma modulation and parallel implementation method, and belongs to the field of power electronics. The method applies the Delta-Sigma modulation technology to high-speed permanent magnet synchronous motor control and is realized through a field programmable gate array. The system adopts a cooperative architecture of a controller and the FPGA: the controller is responsible for double closed-loop control and non-inductive algorithm, and outputs d-q axis voltage; in order to adapt to FPGA fixed-point operation, the voltage is first converted to a 60° g-h coordinate system to strip off irrational number operation. The FPGA utilizes a parallel pipeline structure to synchronously judge reference voltage vector sector n and deviation vector area m. Finally, a switch vector output is selected according to the setting rules of n and m. The method optimizes voltage spectrum, suppresses current high-frequency harmonics and significantly improves the real-time performance and engineering realizability of the modulation link without increasing the burden of the controller.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor. Background Technology

[0002] In recent years, significant improvements in the performance of permanent magnet materials, breakthroughs in power electronics technology, and the maturity of advanced control theories have driven comprehensive progress in permanent magnet synchronous motor (PMSM) technology. The core design of PMSMs establishes the excitation magnetic field through permanent magnets, eliminating the need for traditional electrically excited systems and their associated excitation windings and brush-slip ring structures. This design not only simplifies the motor topology and improves system reliability but also brings significant advantages such as high power density, excellent operating efficiency, and outstanding dynamic speed regulation performance. Therefore, PMSMs have become a core component of high-efficiency, high-performance drive systems in aerospace, high-end manufacturing, and new energy vehicles. To further expand performance boundaries, high-speed PMSMs have emerged, representing a significant evolution of this technology towards ultimate performance. By eliminating mechanical transmission links and adopting a direct-drive mode, high-speed PMSMs significantly shorten the energy conversion path, improve system efficiency and dynamic response, and significantly enhance operational reliability. Due to its superior performance in power density and response speed, high-speed permanent magnet synchronous motors have demonstrated irreplaceable advantages in cutting-edge equipment such as flywheel energy storage, high-speed compressors, and precision spindle drives, becoming the focus of research in the field of high-performance motor drives.

[0003] With the emergence of higher fundamental frequencies, lower carrier ratios, and more complex interference problems in the high-speed domain, achieving stable and high-precision control of high-speed motors across the entire speed range becomes increasingly difficult. The extremely high electrical operating frequency significantly enhances the cross-coupling effect in the motor's mathematical model, severely limiting the adjustment capability of traditional linear controllers under these conditions, potentially leading to dynamic performance degradation or even instability. Secondly, when using a traditional two-level inverter as the drive topology, high-frequency harmonic components in the stator current are very significant. The resulting high-frequency harmonic magnetic field not only exacerbates eddy current and hysteresis losses in the rotor core, leading to increased rotor temperature and reduced system efficiency, but also threatens the safety of the rotor structure. Simultaneously, harmonic components can induce significant torque pulsation and mechanical vibration, increasing electromagnetic noise levels and thus affecting the control accuracy of high-speed permanent magnet synchronous motors under sensorless control strategies. Furthermore, strong electromagnetic interference accelerates the aging process of the drive unit. During transient operation or short-circuit faults, the low inductance characteristics can also cause a sharp increase in instantaneous current, posing a severe challenge to the reliability of the sensorless control system for high-speed permanent magnet synchronous motors. However, many current solutions to the above problems involve improving modulation strategies to optimize harmonic distribution and reduce the impact of current harmonics on motor performance, but this will add unnecessary computational burden to the controller.

[0004] Based on this, the present invention designs a high-speed permanent magnet synchronous motor Delta-Sigma modulation and parallel implementation method to solve the above problems. Summary of the Invention

[0005] This invention addresses the above-mentioned problems by proposing a Delta-Sigma modulation and parallel implementation method for high-speed permanent magnet synchronous motors, belonging to the field of power electronics. In this invention, Delta-Sigma modulation technology is applied to the control system of a high-speed permanent magnet synchronous motor, and the modulation method is implemented using a field-programmable gate array (FPGA). Through the overall architecture of the controller and the parallel implementation method, the optimization of the voltage spectrum and the suppression of high-frequency harmonics in the three-phase current are achieved without compromising the original computational resources.

[0006] To achieve the above objective, the method includes the following steps:

[0007] A method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor includes the following steps:

[0008] S1. A control strategy for a high-speed permanent magnet synchronous motor drive system is implemented using a control architecture based on a controller and a field-programmable gate array (FPGA). The controller is responsible for implementing the dual-closed-loop control strategy and the sensorless algorithm, while the FPGA is responsible for implementing Delta-Sigma modulation. The controller outputs the reference voltage from the current loop controller. Transformed by coordinate transformation Then switch to , Send to FPGA;

[0009] S2. In the FPGA, the input... Simultaneously, the reference voltage vector sector n is determined and the deviation vector region m is selected;

[0010] The determination of the reference voltage vector sector n is based on the gh coordinate system. , and The symbols are used;

[0011] The selection process for the deviation vector region m is as follows: at time k, input... and The voltage vector corresponding to the output at the previous moment and Feedback calculation is performed to obtain and Then, by integration, we can obtain... and ;based on , and The sign discrimination of the three sector boundaries determines the deviation vector region m;

[0012] S3 determines the final output switching vector based on the reference voltage vector sector n and the deviation vector region m, according to the set rules.

[0013] Furthermore, in step S1, the gh coordinate system is established as follows: Axis as axis, Rotating the axis counterclockwise by 60° yields The axis, at this time let the coordinates of the reference voltage vector be... The transformation from the α-β coordinate system to the gh coordinate system is as follows: .

[0014] Furthermore, in step S2, the method for determining the reference vector sector n in the gh coordinate system is as follows:

[0015] The sector boundary on the gh plane is determined by three discriminants. , and Unique portrayal:

[0016] (1) When and hour, ;

[0017] (2) When and At that time, according to Distinguishing symbols : At that time, ;otherwise ;

[0018] (3) When and At that time, according to Distinguishing symbols :like At that time, ;otherwise ;

[0019] (4) Select sector in other cases 1. To ensure that the judgments are complete and mutually exclusive.

[0020] Furthermore, the method for dividing the deviation vector region in step S2 is as follows:

[0021] The voltage space vector diagram corresponding to a three-phase two-level inverter is re-divided into 7 deviation vector regions:

[0022] Area A: Angle range -30° to 30°;

[0023] Area B: Angle range 30°~90°;

[0024] Region C: Angle range 90°~150°;

[0025] Region D: Angle range 150°~210°;

[0026] Region E: Angle range 210°~270°;

[0027] Region F: Angle range 270°~330°;

[0028] Region G: satisfies The area, in which This is the DC bus voltage.

[0029] Furthermore, the method for selecting the deviation vector region in step S2 is as follows:

[0030] In the gh coordinate system, by constructing , and The three sector boundaries are used for sign determination, among which... , and Corresponding to , and The boundary line; for any deviation vector, its region is determined by comparing the combination of signs of (u, v, w):

[0031] (1) If Then the region where the deviation vector is located ;

[0032] (2) Divide the vector space into two parts by the sign of w: If If the deviation vector is located in the upper half of AC, then it is located in the lower half of DF.

[0033] (3) When At that time, if ,but ;like and but ;otherwise, ;

[0034] (4) At that time, if ,but ;like and but ;otherwise, .

[0035] Furthermore, in step S2, the basic logic for implementing Delta-Sigma modulation based on FPGA is as follows:

[0036] The controller sends data to the FPGA. , The input data range is a Q12.4 format fixed-point number from -2048 to +2047.9375, where the most significant bit is the sign bit. The reference vector sector determination module and the deviation vector region selection module are driven by the same clock signal clk. When the FPGA receives data transmitted from the controller... , At that time, the two modules start in parallel, obtaining the reference vector sector n and the deviation vector region m.

[0037] Furthermore, when both the reference vector sector judgment module and the deviation vector region selection module have completed their judgments, the switch vector selection module is activated, and the corresponding switch vector is output. , , .

[0038] Furthermore, in step S3, the final switching vector output by the quantizer is determined by the reference voltage vector sector n and the region m where the deviation voltage is located, according to the following rules:

[0039] (1) If the reference voltage vector sector n and the deviation vector region m have an overlapping region, then the voltage vector in the overlapping region is selected as the output;

[0040] (2) If the reference voltage vector sector n and the deviation vector region m have no overlapping region, but the adjacent sectors of the deviation vector region m and the reference voltage vector sector n have overlapping regions, then the non-zero voltage vector corresponding to the common edge of the reference voltage vector sector n and the adjacent sector is selected as the output.

[0041] (3) If the reference voltage vector sector n and its two adjacent sectors do not overlap with the deviation vector region m, then the zero vector output is selected; where, when the reference voltage vector sector n is odd, then the vector output is selected. When the reference voltage vector sector n is even, select the vector. .

[0042] Compared with the prior art, the beneficial effects of this invention are as follows:

[0043] 1. Superior Modulation Strategy: By replacing the traditional SVPWM with Delta-Sigma modulation, the quantization noise (harmonic) spectrum is essentially pushed to a higher frequency, making the inverter output voltage spectrum smoother. This significantly suppresses the low-frequency and mid-frequency harmonic content in the motor current, reducing harmonic losses and torque ripple.

[0044] 2. Innovative System Architecture: The system innovatively adopts a collaborative architecture between the controller and the FPGA, offloading the complex Delta-Sigma modulation logic to the FPGA for implementation. This eliminates the need for harmonic suppression functionality to occupy the controller's core computing resources, ensuring the real-time performance of the dual-loop control and sensorless algorithm, and achieving decoupling of performance improvement and computational load.

[0045] 3. Achieving Efficiency and Reliability: In the FPGA implementation, by employing a 60°gh coordinate system, this invention further improves the optimization of the voltage spectrum by increasing the sampling frequency. This avoids the problems involved in the traditional α-β coordinate system. The irrational number operations simplify the fixed-point implementation logic and improve the timing margin and system stability of the data path. Simultaneously, by utilizing the hardware parallelism and pipeline technology of FPGA, the reference sector determination and deviation region selection are processed in parallel, greatly reducing the computational latency and timing jitter in the modulation stage.

[0046] 4. Strong engineering applicability: While ensuring control flexibility, the method significantly improves the real-time performance and engineering feasibility of the entire modulation algorithm, and is especially suitable for high-speed permanent magnet synchronous motor drive scenarios with extremely high requirements for switching frequency and real-time performance. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0048] Figure 1 A general block diagram illustrating the implementation of this invention;

[0049] Figure 2 A schematic diagram illustrating the Delta-Sigma modulation application principle applicable to this invention;

[0050] Figure 3 Two-level space vector diagram applicable to this invention;

[0051] Figure 4 A deviation vector region division diagram for application of the present invention;

[0052] Figure 5 A schematic diagram illustrating the selection of the deviation vector region in the α-β coordinate system to which this invention is applicable;

[0053] Figure 6 A region partitioning diagram for the Delta-Sigma quantizer to which this invention is applicable;

[0054] Figure 7 A schematic diagram of region division in the gh coordinate system to which this invention is applicable;

[0055] Figure 8 The three-phase current waveforms are shown for a speed of 1500 r / min with a sudden load of 1 N·m applied in 0.5 s, which is applicable to the present invention.

[0056] Figure 9 The waveform of the rotational speed at 1500 r / min with a sudden application of 1 N·m load in 0.5 s is used to illustrate the application of this invention.

[0057] Figure 10 The FFT analysis results of phase A current at a rotational speed of 1500 r / min, to which this invention applies;

[0058] Figure 11 The three-phase current waveform diagram is shown for a speed of 6000 r / min and a sudden load of 1 N·m applied in 0.5 s, which is applicable to the present invention.

[0059] Figure 12 The waveform of the rotational speed at 6000 r / min with a sudden application of 1 N·m load in 0.5 s is used to illustrate the application of this invention.

[0060] Figure 13The FFT analysis results of phase A current at a speed of 6000 r / min applicable to this invention are shown in the figure.

[0061] Figure 14 The three-phase current waveform diagram is shown for a speed of 18000 r / min and a sudden load of 1 N·m applied at 0.8 s, which is applicable to the present invention.

[0062] Figure 15 The waveform of the rotational speed at 18000 r / min with a sudden application of 1 N·m load in 0.8 s is used to illustrate the application of this invention.

[0063] Figure 16 The FFT analysis results of phase A current at a rotational speed of 18000 r / min, applicable to this invention, are shown in the figure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0065] The invention will be further explained below with reference to the accompanying drawings to facilitate understanding. Specific implementation methods are as follows: Figure 1 As shown, it includes the following steps:

[0066] S1. A control strategy for a high-speed permanent magnet synchronous motor drive system is implemented using a control architecture based on a controller (such as a DSP or MCU) and a field-programmable gate array (FPGA). The controller is mainly responsible for the implementation of the dual closed-loop control strategy and the sensorless algorithm, while the FPGA is used to implement the Delta-Sigma modulation part, which has high real-time requirements and complex logic judgments. The controller outputs the given reference voltage from the current loop controller. Transformed by coordinate transformation , Then , It is fed into the FPGA and awaits the next step of calculation;

[0067] Furthermore, in step S1, the original method was... , Selecting the switch vector requires judgment. , as well as The sign of the reference vector is used to determine the sector in which it is located; similarly, the selection of the deviation vector region in the α-β plane also requires judgment. , as well as The sign magnitude selection bias vector region, and in FPGAs using fixed-point arithmetic, the presence of irrational numbers lengthens the critical path of combinational logic, thereby reducing the highest achievable clock frequency and modulation update rate. Therefore, in the controller, It is then converted to the gh coordinate system and sent to the FPGA.

[0068] Furthermore, in step S1, the gh coordinate system is established as follows: Axis as axis, Rotating the axis counterclockwise by 60° yields The axis, at this time let the coordinates of the reference voltage vector be... The transformation from the α-β coordinate system to the gh coordinate system is as follows: .

[0069] S2, FPGA received , Then, taking advantage of its hardware parallelism, two independent processing modules are started simultaneously to perform the judgment of the reference voltage vector sector n and the selection of the deviation vector region m, respectively. Both are driven by the same clock, realizing true parallel processing and greatly reducing the computation latency.

[0070] Reference voltage vector sector n determination method: This module is based on the geometric characteristics of the gh coordinate system and only needs to determine... , and The signs of these three quantities uniquely determine the sector (n=1~6) where the voltage vector is located. The decision logic is simple, containing only comparators and combinational logic, making it very suitable for high-speed implementation on FPGAs.

[0071] Regarding the selection of the deviation vector region, this module implements the core feedback quantization of Delta-Sigma modulation. The input at time k is compared with the input... and The voltage vector corresponding to the output at the previous moment and Feedback calculation is performed to obtain and Then, by integration, we can obtain... and Select the deviation vector region m; its region can be determined by... , and Location is achieved by identifying the signs of the three sector boundaries. By combining the sign combination with whether the deviation vector amplitude is less than 0.3 times the DC bus voltage (to determine whether it is region G), region m can be quickly determined. This discrimination method also only involves addition and subtraction and sign comparison, avoiding complex trigonometric function or angle calculations.

[0072] S3 determines the final output switching vector based on the reference voltage vector sector n and the deviation vector region m, according to the set rules.

[0073] Furthermore, in step S2, the method for determining the reference vector sector n in the gh coordinate system is as follows:

[0074] The sector boundary on the gh plane is determined by three discriminants. , and Unique portrayal:

[0075] (1) When and hour, ;

[0076] (2) When and At that time, according to Distinguishing symbols : At that time, ;otherwise ;

[0077] (3) When and At that time, according to Distinguishing symbols :like At that time, ;otherwise ;

[0078] (4) Select sector in other cases 1. To ensure that the judgments are complete and mutually exclusive.

[0079] Furthermore, the method for dividing the deviation vector region in step S2 is as follows:

[0080] The voltage space vector diagram corresponding to a three-phase two-level inverter is re-divided into 7 deviation vector regions:

[0081] Area A: Angle range -30° to 30°;

[0082] Area B: Angle range 30°~90°;

[0083] Region C: Angle range 90°~150°;

[0084] Region D: Angle range 150°~210°;

[0085] Region E: Angle range 210°~270°;

[0086] Region F: Angle range 270°~330°;

[0087] To reduce the switching losses of power devices, select The region is defined as the zero vector region G, where This is the DC bus voltage.

[0088] Furthermore, the method for selecting the deviation vector region in step S2 is as follows:

[0089] In the gh coordinate system, by constructing , and The three sector boundaries are used for sign determination, among which... , and Corresponding to , and The boundary line; for any deviation vector, its region is determined by comparing the combination of signs of (u, v, w):

[0090] (1) If Then the region where the deviation vector is located ;

[0091] (2) Divide the vector space into two parts by the sign of w: If If the deviation vector is located in the upper half of AC, then it is located in the lower half of DF.

[0092] (3) When At that time, if ,but ;like and but ;otherwise, ;

[0093] (4) At that time, if ,but ;like and but ;otherwise, .

[0094] Furthermore, in step S2, the basic logic for implementing Delta-Sigma modulation based on FPGA is as follows:

[0095] The controller sends data to the FPGA. , The input data range is a Q12.4 format fixed-point number from -2048 to +2047.9375, where the most significant bit is the sign bit. The reference vector sector determination module and the deviation vector region selection module are driven by the same clock signal clk. When the FPGA receives data transmitted from the controller... , At that time, the two modules start in parallel, obtaining the reference vector sector n and the deviation vector region m.

[0096] Furthermore, when both the reference vector sector judgment module and the deviation vector region selection module have completed their judgments, the switch vector selection module is activated, and the corresponding switch vector is output. , , .

[0097] S3. Finally, the reference voltage vector sector n and the deviation vector region m jointly determine the final output switching vector according to the set rules.

[0098] Furthermore, the switching vector selection method in step S3 is as follows: The switching vector finally output by the quantizer is jointly determined by the reference voltage vector sector n and the deviation voltage region m, and the rules are as follows: (1) If the reference voltage vector sector n and the deviation vector region m have an overlapping region, then the voltage vector in the overlapping region is selected. For example, sector n Then select vector (2) If the reference voltage vector sector n and the deviation vector region m do not overlap, but the deviation vector region m overlaps with the adjacent sector of the reference voltage vector sector n, then the vector of the common edge between the reference voltage vector sector n and the adjacent sector is selected. For example, sector n If there is no overlap between the two, but region C overlaps with the adjacent sector 2 of sector 1, then the vector on the common edge of sectors 1 and 2 is selected. (3) If neither the reference voltage vector sector n nor its vector sector m overlaps with the deviation vector region m, then zero vector output is selected. If this condition is met, the reference voltage vector sector n is odd, then vector output is selected. Otherwise, select vector. .

[0099] Based on the above rules, at a certain moment, a unique output voltage vector can be determined according to the reference voltage vector sector n and the deviation vector region m. The corresponding vector selection is shown in Table 1. Table 1 Quantizer Output Voltage Vector Selection Table

[0100] Furthermore, an experimental example: In one example, simulation verification was performed based on the parameters listed in Table 2.

[0101] Table 2 Parameters of High-Speed ​​Permanent Magnet Synchronous Motor

[0102] The results are as follows: Figure 8 The three-phase current waveform is given at a speed of 1500 r / min with a sudden load of 1 N·m applied at 0.5 s. Figure 9 The waveform of the rotational speed at 1500 r / min with a sudden application of a 1 N·m load at 0.5 s. Figure 10 The FFT analysis results for the A-phase current at 1500 r / min show that when the high-speed permanent magnet motor operates at 1500 r / min, both the three-phase current waveform and the speed waveform are relatively smooth and contain fewer harmonics. Its THD value is only 3.67%, and it optimizes the inverter output current spectrum. It also shows a good response speed in the load test. Figure 11 The three-phase current waveform is given at a speed of 6000 r / min with a sudden load of 1 N·m applied at 0.5 s. Figure 12 The waveform of the rotational speed at 6000 r / min with a sudden application of a 1 N·m load at 0.5 s. Figure 13 The FFT analysis results for the A-phase current at 6000 r / min show that when the high-speed permanent magnet motor operates at 6000 r / min, both the three-phase current waveform and the speed waveform are very smooth with fewer harmonics. Its THD value is only 1.07%, and it optimizes the inverter output current spectrum. It also shows a good response speed in the load test. Figure 14 The three-phase current waveform is given at a speed of 18000 r / min with a sudden load of 1 N·m applied at 0.8 s. Figure 15 The waveform of the rotational speed at 18000 r / min with a sudden load of 1 N·m applied at 0.8 s. Figure 16 The FFT analysis results for the A-phase current at 18000 r / min show that when the high-speed permanent magnet motor operates at 6000 r / min, both the three-phase current waveform and the speed waveform are very smooth with fewer harmonics. Its THD value is only 1.45%, and it optimizes the inverter output current spectrum. It also shows a good response speed in the load test.

[0103] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor, characterized in that, Specifically, the following steps are included: S1. A control strategy for a high-speed permanent magnet synchronous motor drive system is implemented using a control architecture based on a controller and a field-programmable gate array (FPGA). The controller is responsible for implementing the dual-closed-loop control strategy and the sensorless algorithm, while the FPGA is responsible for implementing Delta-Sigma modulation. The controller outputs the reference voltage from the current loop controller. Transformed by coordinate transformation Then switch to , Send to FPGA; S2. In the FPGA, the input... Simultaneously, the reference voltage vector sector n is determined and the deviation vector region m is selected; The determination of the reference voltage vector sector n is based on the gh coordinate system. , and The symbols are used; The selection process for the deviation vector region m is as follows: at time k, input... and The voltage vector corresponding to the output at the previous moment and Feedback calculation is performed to obtain and Then, by integration, we can obtain... and ;based on , and The sign discrimination of the three sector boundaries determines the deviation vector region m; S3 determines the final output switching vector based on the reference voltage vector sector n and the deviation vector region m, according to the set rules.

2. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 1, characterized in that, In step S1, the gh coordinate system is established as follows: Axis as axis, Rotating the axis counterclockwise by 60° yields The axis, at this time let the coordinates of the reference voltage vector be... The transformation from the α-β coordinate system to the gh coordinate system is as follows: .

3. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 1, characterized in that, In step S2, the method for determining the reference vector sector n in the gh coordinate system is as follows: The sector boundary on the gh plane is determined by three discriminants. , and Unique portrayal: (1) When and hour, ; (2) When and At that time, according to Distinguishing symbols : At that time, ;otherwise ; (3) When and At that time, according to Distinguishing symbols :like At that time, ;otherwise ; (4) Select sector in other cases 1. To ensure that the judgments are complete and mutually exclusive.

4. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 1, characterized in that, The method for dividing the deviation vector region in step S2 is as follows: The voltage space vector diagram corresponding to a three-phase two-level inverter is re-divided into 7 deviation vector regions: Area A: Angle range -30° to 30°; Area B: Angle range 30°~90°; Region C: Angle range 90°~150°; Region D: Angle range 150°~210°; Region E: Angle range 210°~270°; Region F: Angle range 270°~330°; Region G: satisfies The area, in which This is the DC bus voltage.

5. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 4, characterized in that, The method for selecting the deviation vector region in step S2 is as follows: In the gh coordinate system, by constructing , and The three sector boundaries are used for sign determination, among which... , and Corresponding to , and The boundary line; for any deviation vector, its region is determined by comparing the combination of signs of (u, v, w): (1) If Then the region where the deviation vector is located ; (2) Divide the vector space into two parts by the sign of w: If If the deviation vector is located in the upper half of AC, then it is located in the lower half of DF. (3) When At that time, if ,but ;like and but ;otherwise, ; (4) At that time, if ,but ;like and but ;otherwise, .

6. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 1, characterized in that, In step S2, the basic logic for implementing Delta-Sigma modulation based on FPGA is as follows: The controller sends data to the FPGA. , The input data range is a Q12.4 format fixed-point number from -2048 to +2047.9375, where the most significant bit is the sign bit. The reference vector sector determination module and the deviation vector region selection module are driven by the same clock signal clk. When the FPGA receives data transmitted from the controller... , At that time, the two modules start in parallel, obtaining the reference vector sector n and the deviation vector region m.

7. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 6, characterized in that, When both the reference vector sector judgment module and the deviation vector region selection module have completed their judgments, the switch vector selection module is activated and outputs the corresponding switch vector. , , .

8. The method for Delta-Sigma modulation and parallel implementation of a high-speed permanent magnet synchronous motor according to claim 1, characterized in that, In step S3, the final switching vector output by the quantizer is determined by the reference voltage vector sector n and the region m where the deviation voltage is located, according to the following rules: (1) If the reference voltage vector sector n and the deviation vector region m have an overlapping region, then the voltage vector in the overlapping region is selected as the output; (2) If the reference voltage vector sector n and the deviation vector region m have no overlapping region, but the adjacent sectors of the deviation vector region m and the reference voltage vector sector n have overlapping regions, then the non-zero voltage vector corresponding to the common edge of the reference voltage vector sector n and the adjacent sector is selected as the output. (3) If the reference voltage vector sector n and its two adjacent sectors do not overlap with the deviation vector region m, then the zero vector output is selected; where, when the reference voltage vector sector n is odd, then the vector output is selected. When the reference voltage vector sector n is even, select the vector. .

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