Method for optimizing phase-locked loop spur by using additional random delay and phase-locked loop

Abstract

The application discloses a method for optimizing phase-locked loop spur by using additional random delay and a phase-locked loop. A long-time average fixed and short-time size random delay generator is added to a suitable position of the phase-locked loop, so that the fluctuation of a tuning voltage of the phase-locked loop due to non-ideal effects such as limited loop gain, system mismatch and clock feedthrough is randomized in time in each cycle, thereby distributing the energy originally gathered near the fluctuation frequency and harmonic frequencies to the full frequency spectrum, and effectively reducing the phase-locked loop spur. The application can simply and effectively reduce the phase-locked loop spur, and has universality in different architecture phase-locked loops.

Description

Technical Field

[0001] This invention belongs to the field of frequency synthesis technology, specifically relating to a method for optimizing phase-locked loop spurious emissions using additional random delays and a phase-locked loop. Background Technology

[0002] Phase-locked loops (PLLs), as frequency synthesizers, are widely used in communications, radar, and local area networks (LANs) due to their advantages such as high output frequency, strong anti-interference capability, and ease of integration. Spurious signals, a key performance indicator representing the purity of the PLL output signal, refer to the intensity of high-power interference near the PLL output carrier frequency relative to the carrier signal. They directly affect the system's frequency stability and communication quality. With the development of communication technology, the requirements for the purity of the PLL output signal are becoming increasingly stringent. Correspondingly, the requirements for PLL spurious signals are also becoming more stringent.

[0003] In practical applications, the tuning voltage of a phase-locked loop (PLL) fluctuates periodically during locking due to factors such as dead time, system mismatch, and non-ideal charge pump response, drastically worsening PLL stray emissions. In practice, PLL stray emission optimization typically targets only the known factors mentioned above, and the optimization effect is limited due to process variations. However, as PLL stray emission requirements become increasingly stringent, the stray emission performance obtained through the above optimization methods gradually fails to meet the demands. Therefore, the search for a universal PLL stray emission optimization method that is insensitive to process variations is becoming increasingly urgent. Summary of the Invention

[0004] Purpose of the invention: In view of the above-mentioned prior art, a method and phase-locked loop (PLL) for optimizing phase-locked loop spurious signals by using additional random delay are proposed, so that the PLL output signal spectrum has no obvious spurious signals on both sides of the carrier frequency.

[0005] Technical solution: A method for optimizing phase-locked loop spurious emissions by using additional random delay, comprising:

[0006] Add a random delay generator to the circuit structure of the phase-locked loop;

[0007] The random delay generator is used to provide a delay of random magnitude for the input signal and a stable average value over multiple cycles required for the phase-locked loop to lock.

[0008] Furthermore, when the phase-locked loop is a type I or type II phase-locked loop, the random delay generator is cascaded in the phase-locked loop circuit and is located before or after the phase detector; when the phase-locked loop is a subsampling phase-locked loop, the random delay generator is placed between the pulse generator and the charge pump to randomize the window for controlling the charging and discharging current.

[0009] Furthermore, a random delay generator is added to the circuit structure of the phase-locked loop (PLL), so that the fluctuations in the PLL tuning voltage appear at random times in each reference clock cycle. The energy of the originally periodic fluctuations is spread evenly across the entire spectrum, and finally the PLL output signal spectrum has no obvious spurious signals on both sides of the carrier frequency.

[0010] Furthermore, the random delay generator consists of a Δ-Σ modulator and a digital-to-time converter; the Δ-Σ modulator is controlled by a static input α and a periodic signal, and outputs an n-bit random binary signal with a frequency of f, and the random binary signal is cyclically transformed with a cycle period T, the mean of the binary signal within the cycle T being α; then the digital-to-time converter converts the binary signal into a corresponding delay.

[0011] Furthermore, by simulating the effects of different cycle periods T, the shortest cycle period that suppresses spurious emissions to below the phase noise floor is selected as the cycle period T of the output of the Δ-Σ modulator.

[0012] An optimized stray phase-locked loop (PLL) includes: a random delay generator incorporated into the circuit structure of the PLL, the random delay generator being used to provide an input signal with a delay of random magnitude and a stable mean over multiple cycle periods required for the PLL to lock.

[0013] Furthermore, when the phase-locked loop is a type I or type II phase-locked loop, the random delay generator is cascaded in the phase-locked loop circuit and is located before or after the phase detector; when the phase-locked loop is a subsampling phase-locked loop, the random delay generator is placed between the pulse generator and the charge pump to randomize the window for controlling the charging and discharging current.

[0014] Furthermore, the random delay generator consists of a Δ-Σ modulator and a digital-to-time converter; the Δ-Σ modulator is controlled by a static input α and a periodic signal, and outputs an n-bit random binary signal with a frequency of f, and the random binary signal is cyclically transformed with a cycle period T, the mean of the binary signal within the cycle T being α; the digital-to-time converter is used to convert the binary signal into a corresponding delay.

[0015] Beneficial effects: Due to the limited loop gain, system mismatch, and clock feedthrough of the phase-locked loop (PLL), the tuning voltage on the voltage-controlled oscillator (VCO) within the PLL will fluctuate periodically. This periodicity causes a high concentration of energy at the corresponding frequency and its harmonic frequencies, which is then converted by the VCO to the sides of the carrier frequency, resulting in significant spurious emissions. By adding a random delay, the timing of these periodic fluctuations in the tuning voltage is randomized. Consequently, the high energy initially concentrated at the periodic fluctuation frequencies and their harmonic frequencies is distributed across the entire spectrum. After VCO frequency conversion, no significant energy spikes appear around the carrier frequency, effectively suppressing PLL spurious emissions. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the principle of the method for optimizing phase-locked loop spurious emissions using additional random delays according to the present invention.

[0017] Figure 2A The architecture diagram for implementing the first scheme of this method for a simple phase-locked loop is shown below.

[0018] Figure 2B A timing diagram illustrating the first approach to this method for a simple phase-locked loop.

[0019] Figure 3A The architecture diagram shows the second scheme for implementing this method for a simple phase-locked loop.

[0020] Figure 3B A timing diagram illustrating the second approach to this method for a simple phase-locked loop.

[0021] Figure 4A The architecture diagram shows the first scheme for implementing this method using a type II charge pump phase-locked loop.

[0022] Figure 4B A timing diagram illustrating the first scheme of this method for a type II charge pump phase-locked loop;

[0023] Figure 5A The architecture diagram shows the second scheme for implementing this method using a type II charge pump phase-locked loop;

[0024] Figure 5B A timing diagram illustrating the second approach to this method for a type II charge pump phase-locked loop;

[0025] Figure 6A An architecture diagram of one scheme for implementing this method in a subsampling phase-locked loop;

[0026] Figure 6B A timing diagram illustrating one approach to implementing this method using a subsampling phase-locked loop;

[0027] Figure 7 This is a structural diagram of a random delay generator;

[0028] Figure 8 This is a structural diagram of a Δ-Σ modulator;

[0029] Figure 9 This is a structural diagram of a digital-to-time converter. Detailed Implementation

[0030] The invention will now be further explained with reference to the accompanying drawings.

[0031] Example 1

[0032] like Figure 2A The diagram shown is an architecture diagram of the first scheme for implementing the method for a simple phase-locked loop provided in this application, including a random delay generator, a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency divider connected in sequence.

[0033] External reference clock signal S REF and feedback frequency division clock signal S DIV Connect the input terminal of the random delay generator, and after adding the same random delay, the two clock signals S REF 'and S DIV 'Connect the phase detector. Based on the two clock signals S after adding the same random delay.' REF 'and S DIV The phase difference is such that the phase detector outputs a corresponding voltage waveform V. PD Then the voltage waveform V is filtered out by a loop filter. PD After extracting most of the high-frequency components, the tuning voltage V of the voltage-controlled oscillator is obtained. tune The voltage-controlled oscillator is subjected to a tuning voltage V. tune The voltage-controlled oscillator (VCO) output signal is controlled and output at a corresponding frequency. After passing through a frequency divider, the VCO output signal is fed back to the input of the random delay generator, forming a negative feedback loop. Through a period of negative feedback adjustment, the external reference clock signal S... REF and feedback frequency division clock signal S DIV The phase difference will remain stable and the corresponding tuning voltage will be just enough to make the feedback frequency division clock signal S DIV Frequency and external reference clock signal S REF The frequency remains consistent.

[0034] The random delay generator is used to provide a delay of random magnitude for the input signal that has a stable mean over multiple cycles required for phase-locked loop (PLL) locking.

[0035] Figure 2B This embodiment shows a timing diagram of key nodes after adding random delays.

[0036] Due to the limited loop gain in this embodiment, the external reference clock signal S is locked after locking. REF With feedback frequency division clock signal S DIV A stable phase difference will exist. After passing through the random delay generator, the waveforms of each cycle will be supplemented with the same delay: a fixed average value over a long period and a random magnitude over a short period. The two clock signals S after the added random delay... REF 'with S DIV The phase difference between the two clock signals and the additional delay between them are S. REF With S DIV The phase difference between them remains consistent.

[0037] After adding random delay, the two clock signals S REF 'with S DIV The phase detector compares the phases and obtains the output voltage V. PD In this embodiment, the phase detector is essentially an XOR gate. When the levels of the two clock signals are inconsistent, the phase detector will output a high level; when the levels of the two clock signals are consistent, the phase detector will output a low level. Due to the addition of a random delay, the two clock signals S... REF 'with S DIV 'No longer periodic, phase detector output voltage V' PD The timing of high levels in each reference clock cycle also becomes random.

[0038] Phase detector output voltage V PD The original square wave signal, after being significantly filtered out of high-frequency components by the loop filter, will become a relatively stable triangular sawtooth wave tuned voltage V with a very small amplitude. tune Because the phase detector output voltage V PD The timing of high-level events in each reference clock cycle is random, and the triangular sawtooth wave after the loop filter also exhibits randomness in each reference clock cycle. Therefore, a large amount of energy will no longer accumulate at a specific frequency in the frequency spectrum, and the phase-locked loop output will no longer exhibit significant spurious emissions. Compared to traditional simple phase-locked loops, the output spurious emissions in this embodiment are greatly reduced.

[0039] Example 2

[0040] like Figure 3A The diagram shown is an architecture diagram of the second scheme for implementing this method for a simple phase-locked loop provided in this application, including a phase detector, a random delay generator, a loop filter, a voltage-controlled oscillator, and a frequency divider connected in sequence.

[0041] External reference clock signal S REF and feedback frequency division clock signal S DIVWhen connected to a phase detector, the phase detector outputs a corresponding voltage waveform V based on the phase difference between the two. PD Voltage waveform V PD By adding random delays to each cycle using a random delay generator, the voltage waveform V after adding random delays is obtained. PD After most of the high-frequency components are filtered out by the loop filter, the tuning voltage V of the voltage-controlled oscillator is obtained. tune The voltage-controlled oscillator is subjected to a tuning voltage V. tune The voltage-controlled oscillator (VCO) output signal is controlled and output at a corresponding frequency. After passing through a frequency divider, the VCO output signal is fed back to the input of the phase detector, forming a negative feedback loop. Through a period of negative feedback adjustment, the external reference clock signal S... REF and feedback frequency division clock signal S DIV The phase difference will remain stable and the corresponding tuning voltage will be just enough to make the feedback frequency division clock signal S DIV Frequency and external reference clock signal S REF The frequency remains consistent.

[0042] The random delay generator is used to provide a delay of random magnitude for the input signal that has a stable mean over multiple cycles required for phase-locked loop (PLL) locking.

[0043] Figure 3B This embodiment shows a timing diagram of key nodes after adding random delays.

[0044] Due to the limited loop gain in this embodiment, after locking, the external reference clock signal S REF With feedback frequency division clock signal S DIV A stable phase difference will exist. Reference clock signal S REF With feedback frequency division clock signal S DIV The phase detector compares the phases and thus obtains the output voltage V. PD In this embodiment, the phase detector is essentially an XOR gate. When the levels of the two clock signals are inconsistent, the phase detector will output a high level; when the levels of the two clock signals are consistent, the phase detector will output a low level. Because the external reference clock signal S is locked... REF With feedback frequency division clock signal S DIV A phase detector with a stable phase difference and consistent frequency will output voltage V. PD The duration of the high level in each reference clock cycle will be fixed, thus exhibiting periodicity.

[0045] Phase detector output voltage V PD After passing through the random delay generator, the waveforms of each cycle will be augmented with a delay that has a fixed average value over a long period and a random magnitude over a short period. The timing of the high level occurrence in each reference clock cycle will be randomized due to the random delay.

[0046] Voltage V after adding random delay PD The original square wave signal, after being significantly filtered out of high-frequency components by the loop filter, will become a relatively stable triangular sawtooth wave tuned voltage V with a very small amplitude. tune Due to the added random delay, the output voltage V PD The timing of high-level events in each reference clock cycle is random, and the triangular sawtooth wave after the loop filter also exhibits randomness in each reference clock cycle. Therefore, a large amount of energy will no longer accumulate at a specific frequency in the spectrum, and the phase-locked loop output will no longer exhibit significant spurious emissions. Compared to traditional simple phase-locked loops, the output spurious emissions in this embodiment will be greatly reduced.

[0047] Example 3

[0048] like Figure 4A The diagram shown is an architecture diagram of the first scheme for implementing the method using a type II charge pump phase-locked loop provided in this application. It includes a random delay generator, a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider connected in sequence.

[0049] External reference clock signal S REF and feedback frequency division clock signal S DIV Connected to the input of a random delay generator, the output consists of two clock signals S with the same additional random delay. REF 'and S DIV 'Connect to the frequency and phase detector. Based on the two clock signals S after adding the same random delay.' REF 'and S DIV The phase difference between the phase and frequency discriminators corresponds to the time-domain pulses UP and DN. Under the control of the time-domain pulses UP and DN, the charge pump injects or extracts charge through the loop filter, thereby changing the tuning voltage V of the voltage-controlled oscillator. tune The voltage-controlled oscillator is subjected to a tuning voltage V. tune The voltage-controlled oscillator (VCO) output signal is controlled and output at a corresponding frequency. After passing through a frequency divider, the VCO output signal is fed back to the input of the random delay generator, forming a negative feedback loop. Through a period of negative feedback adjustment, the external reference clock signal S... REF and feedback frequency division clock signal S DIV Maintain a stable phase difference and consistent frequency.

[0050] The random delay generator is used to provide a delay of random magnitude for the input signal that has a stable mean over multiple cycles required for phase-locked loop (PLL) locking.

[0051] Figure 4B This embodiment shows a timing diagram of key nodes after adding random delays.

[0052] Due to the dead time and system mismatch in this embodiment, after locking, the external reference clock signal S REF With feedback frequency division clock signal S DIV There will be a non-zero, stable phase difference. This embodiment assumes the charging current is greater than the discharging current, so a frequency-divided clock signal S is fed back after locking. DIV The phase leads the external reference clock signal S. REF The phase of the two clock signals. After passing through a random delay generator, the waveforms of each cycle will be supplemented with the same delay: a fixed average value over a long period and a random value over a short period. The two clock signals S after the random delay are... REF 'with S DIV The phase difference between the two clocks and the additional delay before the two clocks S REF With S DIV The phase difference between them remains consistent.

[0053] Two clock signals S with added random delay REF 'with S DIV The frequency and phase detector compares the rising edge phases to obtain the corresponding time-domain pulses UP and DN. Theoretically, the external reference clock signal S... REF Phase lag results in an output signal UP pulse width of 0; feedback frequency divider clock signal S DIV When the phase is leading, the corresponding output signal DN pulse width is equal to the phase difference between the two input signals. In practice, due to the delay in the feedback reset circuit of the frequency and phase detector, this pulse width will be added to the two output time-domain pulses UP and DN, but the pulse width difference between the two time-domain pulses is still equal to the phase difference between the two input signals. Because of the added random delay, the two clock signals S... REF 'with S DIV 'No longer periodic, the timing of the output time-domain pulses UP and DN of the frequency and phase detector also becomes random in each reference clock cycle.'

[0054] The frequency and phase detector outputs time-domain pulses UP and DN, which are converted into charging and discharging currents corresponding to the time intervals via a charge pump. Since the charging current is greater than the discharging current, a net charging current exists when both charging and discharging currents are activated simultaneously, resulting in a net charging current, Vtuning. tune The voltage gradually increases; when the charging current is off and the discharging current is on, there is a net discharge current, and the tuning voltage V... tune Gradually decreasing. The corresponding amounts of charge extracted and injected are equal, and the tuning voltage V... tune It will return to its original size, therefore the tuning voltage V tune A short-duration triangular sawtooth wave exists. Because the timing of the output time-domain pulses UP and DN from the frequency and phase detector exhibits randomness in each reference clock cycle, the tuning voltage V... tuneThe timing of the triangular sawtooth wave on the circuit also becomes random, thus preventing the accumulation of large amounts of energy at a specific frequency in the spectrum, and eliminating significant spurious output from the phase-locked loop. Compared to traditional type-2 charge pump phase-locked loops, the output spurious output of this embodiment is greatly reduced.

[0055] Example 4

[0056] like Figure 5A The diagram shown is an architecture diagram of the second scheme for implementing the method using a type II charge pump phase-locked loop provided in this application. It includes a frequency and phase detector, a random delay generator, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider connected in sequence.

[0057] External reference clock signal S REF and feedback frequency division clock signal S DIV A frequency and phase detector is connected, and the detector outputs corresponding time-domain pulses UP and DN. These pulses UP and DN are then subjected to the same random delay by a random delay generator to obtain new time-domain pulses UP' and DN', which are randomized within each reference period. Under the control of these pulses UP' and DN', the charge pump injects or extracts charge through a loop filter, thereby changing the tuning voltage V of the voltage-controlled oscillator. tune The voltage-controlled oscillator is subjected to a tuning voltage V. tune The voltage-controlled oscillator (VCO) output signal is controlled and output at a corresponding frequency. After passing through a frequency divider, the VCO output signal is fed back to the input of the random delay generator, forming a negative feedback loop. Through a period of negative feedback adjustment, the external reference clock signal S... REF and feedback frequency division clock signal S DIV Maintain a stable phase difference and consistent frequency.

[0058] The random delay generator is used to provide a delay of random magnitude for the input signal that has a stable mean over multiple cycles required for phase-locked loop (PLL) locking.

[0059] Figure 5B This embodiment shows a timing diagram of key nodes after adding random delays.

[0060] Due to the dead time and system mismatch in this embodiment, after locking, the external reference clock signal S REF With feedback frequency division clock signal S DIV There will be a non-zero, stable phase difference. This embodiment assumes the charging current is greater than the discharging current, so a frequency-divided clock signal S is fed back after locking. DIV The phase leads the external reference clock signal S. REF The phase of the two clock signals is compared between their rising edges using a frequency and phase detector to obtain the corresponding time-domain pulses UP and DN. Theoretically, the external reference clock signal S... REFPhase lag results in an output signal UP pulse width of 0; feedback frequency divider clock signal S DIV When the phase leads, the corresponding output signal DN pulse width is equal to the phase difference between the two input signals. In practice, due to the delay in the feedback reset circuit of the frequency and phase detector, this pulse width will be added to the two output time-domain pulses UP and DN, but the pulse width difference between the two time-domain pulses is still equal to the phase difference between the two input signals. Since the two clock signals have the same frequency and a stable phase difference, the output time-domain pulses UP and DN of the frequency and phase detector exhibit periodicity.

[0061] After the time-domain pulses UP and DN output by the frequency and phase detector pass through the random delay generator, each period of the time-domain pulse will be given the same delay with a fixed average value over a long period and a random delay over a short period. The originally periodic time-domain pulses are transformed into time-domain pulses with random timing in each reference clock cycle.

[0062] The time-domain pulses UP' and DN', after being augmented with random delays, are converted into charging and discharging currents corresponding to the specified time by a charge pump. Since the charging current is greater than the discharging current, a net charging current exists when both charging and discharging currents are activated simultaneously, resulting in a tuning voltage V. tune The voltage gradually increases; when the charging current is off and the discharging current is on, there is a net discharge current, and the tuning voltage V... tune Gradually decreasing. The corresponding amounts of charge extracted and injected are equal, and the tuning voltage V... tune It will return to its original size, therefore the tuning voltage V tune A short-duration triangular sawtooth wave exists. Because the timing of the time-domain pulses UP' and DN' after the added random delay exhibits randomness in each reference clock cycle, the tuning voltage V... tune The timing of the triangular sawtooth wave on the circuit is also random, thus preventing the accumulation of large amounts of energy at a specific frequency in the spectrum, and eliminating significant spurious emissions in the PLL output. Compared to traditional type-2 charge pump PLLs, the output spurious emissions in this embodiment are greatly reduced.

[0063] Example 5

[0064] like Figure 6A The diagram shown is an architecture diagram of a scheme for implementing the method using a subsampling phase-locked loop provided in this application. The phase-locked loop includes a subsampling phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider connected sequentially. The charge pump is simultaneously controlled by a pulse generator and a random delay generator connected sequentially.

[0065] External reference clock signal S REF Using a subsampled phase detector to divide the feedback clock signal S DIVPeriodic voltage sampling is performed. The sampled differential voltage is converted into a corresponding charging / discharging current by a charge pump. Additionally, an external reference clock signal S... REF A differential time-domain pulse signal with controllable pulse width is obtained through a pulse generator. and Then, the differential time-domain pulse signal and After applying the same random delay using a random delay generator, new time-domain pulses are obtained, which are random in each reference period. and In the time domain pulse and Under the control of [the system], the charge pump injects or extracts charge through the loop filter, thereby changing the tuning voltage V of the voltage-controlled oscillator. tune The voltage-controlled oscillator is subjected to a tuning voltage V. tune The voltage-controlled oscillator (VCO) output signal is then fed back to the input of the random delay generator after passing through a frequency divider, forming a negative feedback loop. Through a period of negative feedback adjustment, the phase and frequency of the PLL output signal will remain stable.

[0066] The pulse generator is subject to an external reference clock signal S. REF And control the voltage to output a differential time-domain pulse signal. and Frequency and reference clock signal S REF Consistency and pulse width are controlled by the control voltage.

[0067] A random delay generator is used to provide a delay of random magnitude to the input signal that has a stable mean over the multiple cycles required for phase-locked loop (PLL) locking. To ensure the linearity of the charge pump, the maximum delay value needs to be determined by combining the charge pump and pulse generator design, ensuring that the time-domain pulse after the added random delay is stable. and During the corresponding charge pump's on-time, the charge pump's charging and discharging current remains stable.

[0068] The charge pump is a differential voltage controlled charge pump. After locking, the system mismatch will be translated into a phase difference between the reference clock signal and the feedback frequency divider signal, and the charging and discharging current will remain consistent.

[0069] Figure 6B This embodiment shows a timing diagram of key nodes after adding random delays.

[0070] External reference clock signal S REF A differential time-domain pulse signal with controllable pulse width is obtained by a pulse generator. and After the differential time-domain pulse signal passes through the random delay generator, each period of the time-domain pulse will be given the same delay with a fixed average value over a long period and a random delay over a short period. The originally periodic time-domain pulses are transformed into time-domain pulses with random timing in each reference clock cycle. and .

[0071] Because this embodiment uses a sample-and-hold phase detector and a differential voltage controlled charge pump, the system mismatch after locking will be converted into a phase difference between the reference clock signal and the feedback frequency divider signal, while the charging and discharging current remains consistent. However, in a traditional subsampling phase-locked loop, the charge pump charging and discharging switch is controlled by a periodic differential time-domain pulse signal. and Control. Due to deviations in the charge pump's charge and discharge current build-up speed, clock feedthrough, and charge injection, a periodic net charge and discharge current still exists during the periodic build-up and shutdown of the current. The tuning voltage V... tune Therefore, periodic fluctuations occur, thus generating stray energy.

[0072] In this embodiment, the charge pump is generated by random time-domain pulses in each reference clock cycle. and With this control, the net charging and discharging current during current build-up and shutdown no longer exhibits periodicity. Correspondingly, the tuning voltage V... tune The fluctuations will be random, thus preventing the accumulation of large amounts of energy at a specific frequency in the spectrum, and eliminating noticeable spurious emissions in the PLL output. Compared to traditional subsampling PLLs, the output spurious emissions in this embodiment will be significantly reduced.

[0073] Example 6

[0074] like Figure 7 The diagram shown is a structural diagram of a scheme for implementing a random delay generator provided in this embodiment, including a Δ-Σ modulator and a digital-to-time converter connected in sequence.

[0075] The Δ-Σ modulator is controlled by a static input α and a periodic signal. The frequency f of the periodic signal is usually consistent with or a multiple of the reference signal frequency of the phase-locked loop. The Δ-Σ modulator outputs an n-bit binary signal SW[0:n-1] that is stable in mean over a long period of time and random in size over a short period of time. Specifically, the Δ-Σ modulator outputs an n-bit binary signal with frequency f and a size range of [0,2]. n-1], and the output random binary signal is cyclically transformed with a cycle period T, the mean of the binary signal within cycle T being α. Then, a digital-to-time converter transforms the binary signal with a fixed mean and random magnitude into a corresponding delay with a fixed mean and random magnitude. This delay satisfies the requirement of random magnitude and stable mean within multiple cycles required for PLL locking. The cycle period T is related to the effect of distributing spurious energy across the entire spectrum and the position and magnitude of spurious spikes regenerated due to periodicity. When the cycle period T is too short, the distributing effect is insufficient, and the regenerated spurious energy is large; when the cycle period T is too long, the regenerated spurious spike energy is small but too close to the carrier signal, making it difficult to suppress by the loop filter and increasing the design complexity. Therefore, after initially completing the design of each module of the PLL and obtaining the phase noise at the output of the PLL through simulation software, the effect of different cycle periods T can be simulated to select the shortest cycle period that suppresses spurious energy to below the phase noise floor.

[0076] Figure 8 The structural diagram of a Δ-Σ modulator provided in this embodiment includes a loop consisting of an adder, an n-bit quantizer, a multiplier, a subtractor, and a delay connected in sequence. Furthermore, the output of the n-bit quantizer is connected to the other input of the adder via another delay, and the output of the adder is connected to the input of the subtractor. All modules are uniformly controlled by a periodic signal, operating at a periodic signal frequency f. When an m-bit static value α is input, the output varies at frequency f, with a magnitude ranging from 0 to (2π / 3). n -1) An n-bit binary signal SW[0:n-1] is cyclically transformed with a cycle period T. The output's average value remains stable at a static value α over a long period. The cycle period T is determined by the number of bits m of the input static value α, the number of bits n of the output binary signal (quantizer bits), and whether the two are coprime. For example, when the output bit number n is 1, the cycle period T is approximately 2. m ×1 / f. Generally, the larger the number of bits m of the input static value α and the number of bits n of the output binary signal, the longer the cycle period T. Within the cycle period T, the size of the n-bit binary output in each operation cycle can be approximated as random. For example, when α is 0.25 and the quantizer bit is 1, that is, when the number of bits m of the input static value α is 2 and the number of bits n of the output binary signal is 1, the 1-bit binary output SW[0] will cycle with the operation frequency f and the size in the order of 0, 0, 0, 1, 0, 0, 0, 1..., with a cycle period T of 2. 2 One operation cycle 1 / f, that is, T equals 2. 2 / f. Within each cycle T, the average value of the binary output SW[0] is exactly equal to the static input value α, which is 0.25.

[0077] Figure 9This embodiment provides a structural diagram of a digital-to-time converter, which consists of multiple single-input, single-output circuits controlled by the same n-bit binary signal SW[0:n-1]. The number of circuits is determined by the number of input and output signals. Each circuit consists of two CMOS inverters, n capacitive loads of different sizes, and NMOS switches of different sizes. The NMOS switches are controlled by the n-bit binary signal SW[0:n-1]. When the NMOS switch is turned on, the corresponding capacitive load is connected to the circuit, thereby changing the charging and discharging speed of the preceding CMOS inverter, and thus changing the delay between the input and output signals. To ensure the linearity of the digital-to-time converter, the size of the capacitive load and the size of the NMOS switch must be selected to ensure that the delay between the input and output signals increases linearly as the switch is gradually turned on by the binary signal SW[0:n-1].

[0078] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for optimizing phase-locked loop spurious emissions using an additional random delay, characterized in that, include: Add a random delay generator to the circuit structure of the phase-locked loop; The random delay generator is used to provide a delay of random magnitude for the input signal and a stable average value over multiple cycles required for the phase-locked loop to lock.

2. The method for optimizing phase-locked loop spurious emissions using additional random delay as described in claim 1, characterized in that: When the phase-locked loop is a type I or type II phase-locked loop, the random delay generator is cascaded in the phase-locked loop circuit and is located before or after the phase detector; when the phase-locked loop is a subsampling phase-locked loop, the random delay generator is set between the pulse generator and the charge pump to randomize the window for controlling the charging and discharging current.

3. The method for optimizing phase-locked loop spurious emissions using additional random delay as described in claim 1, characterized in that: By adding a random delay generator to the circuit structure of the phase-locked loop (PLL), the timing of fluctuations in the PLL tuning voltage during each reference clock cycle becomes random. The energy of the originally periodic fluctuations is spread evenly across the entire spectrum, and ultimately the PLL output signal spectrum has no obvious spurious signals on either side of the carrier frequency.

4. The method for optimizing phase-locked loop spurious emissions using additional random delay as described in claim 1, characterized in that: The random delay generator consists of a Δ-Σ modulator and a digital-to-time converter. The Δ-Σ modulator is controlled by a static input α and a periodic signal, and outputs an n-bit random binary signal with a frequency of f. The random binary signal is cyclically transformed with a cycle period T, and the mean value of the binary signal within the cycle T is α. The digital-to-time converter then converts the binary signal into a corresponding delay.

5. The method for optimizing phase-locked loop spurious emissions using additional random delay as described in claim 4, characterized in that: By simulating the effects of different cycle periods T, the shortest cycle period that suppresses spurious emissions to below the phase noise floor is selected as the cycle period T of the output of the Δ-Σ modulator.

6. A phase-locked loop with optimized stray emissions, characterized in that, include: A random delay generator is added to the circuit structure of the phase-locked loop. The random delay generator is used to provide a delay of random magnitude for the input signal and a stable average value over multiple cycles required for the phase-locked loop to lock.

7. The phase-locked loop as described in claim 6, characterized in that: When the phase-locked loop is a type I or type II phase-locked loop, the random delay generator is cascaded in the phase-locked loop circuit and is located before or after the phase detector; when the phase-locked loop is a subsampling phase-locked loop, the random delay generator is set between the pulse generator and the charge pump to randomize the window for controlling the charging and discharging current.

8. The phase-locked loop as described in claim 6, characterized in that: The random delay generator consists of a Δ-Σ modulator and a digital-to-time converter; the Δ-Σ modulator is controlled by a static input α and a periodic signal, and outputs an n-bit random binary signal with a frequency of f, and the random binary signal is cyclically transformed with a cycle period T, the mean of the binary signal within the cycle T being α; the digital-to-time converter is used to convert the binary signal into a corresponding delay.

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