A locking detection circuit and offset correction phase-locked loop

Abstract

This application provides a lock detection circuit and an offset correction phase-locked loop, relating to the field of integrated circuit technology. It includes a phase sequence determination module for receiving up and dn signals from a frequency and phase detector, and outputting a leading signal and a lagging signal. The frequency and phase detector compares the frequency and phase of a reference clock with a feedback clock, and outputs up and dn signals based on the comparison result. The leading signal is the phase-leading signal between the up and dn signals, and the lagging signal is the phase-lagging signal between the up and dn signals. A time-to-digital converter, connected to the phase sequence determination module, receives the leading and lagging signals, quantizes the phase difference between them, and outputs the corresponding digital codeword. A comparator module, connected to the time-to-digital converter, compares the digital codeword with a preset reference value and outputs a lock indication signal. The solution provided in this application has the advantage of enabling phase detection in high-speed scenarios.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a lock detection circuit and an offset correction phase-locked loop. Background Technology

[0002] Offset-corrected phase-locked loops (PLLs) are crucial components of clock chips, memory interface chips, and field-programmable gate arrays (FPGAs). Their primary function is to ensure that the output clock frequency is equal to and phase-aligned with the reference clock frequency, while simultaneously filtering out jitter. Lock-in detection circuits are another important part of the PLL; their main function is to determine whether the PLL loop is locked and output a lock-in signal.

[0003] The traditional lock-in detection circuit is essentially a phase detection circuit. This circuit detects the phase relationship between the reference clock and the feedback clock of the phase-locked loop in each cycle. If the phase difference between the two is less than a certain allowable value, they are considered to be in phase alignment within that cycle; if they are aligned in every cycle, they are considered to be clocks with the same frequency and phase, which means that the phase-locked loop has been locked.

[0004] Specifically, traditional offset-corrected phase-locked loop (PLL) detection circuits sample the reference clock and feedback clock after equal delays using two D flip-flops, and determine whether the phase difference is within the allowable range based on the sampling results. For traditional offset-corrected PLLs, this detection method easily meets the timing constraints due to the low frequencies of the reference and feedback clocks. However, for high-speed offset-corrected PLLs, the reference and feedback clock frequencies are extremely high (typically in the GHz range), with clock periods of only a few hundred picoseconds. Traditional structures are prone to timing violations and cannot operate stably.

[0005] In summary, existing technologies have the problem that lock-in detection circuits cannot achieve phase detection in high-speed scenarios. Summary of the Invention

[0006] The purpose of this application is to provide a lock detection circuit and an offset correction phase-locked loop to solve the problem that existing lock detection circuits cannot achieve phase detection in high-speed scenarios.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a lock detection circuit, the lock detection circuit comprising: The phase order determination module is used to receive the up signal and dn signal from the frequency and phase detector, and output a leading signal and a lagging signal. The frequency and phase detector is used to compare the frequency and phase of the reference clock and the feedback clock, and outputs the up signal and dn signal according to the comparison result. The leading signal is the phase leader of the up signal and the dn signal, and the lagging signal is the phase lag of the up signal and the dn signal. A time-to-digital converter, connected to the phase sequence determination module, is used to receive the leading signal and the lagging signal, quantize the phase difference between them, and output the corresponding digital codeword. The comparator module, connected to the time-to-digital converter, is used to compare the digital codeword with a preset reference value and output a lock indication signal.

[0008] Optionally, the phase order determination module includes: An RS latch is used to output a flag signal according to the arrival order of the rising edges of the up signal and the dn signal, wherein the flag signal indicates whether the up signal lags behind the dn signal. The first multiplexer has a first input terminal connected to the up signal, a second input terminal connected to the dn signal, a control terminal connected to the flag signal, and an output as the first intermediate signal. The second multiplexer has a first input terminal connected to the dn signal, a second input terminal connected to the up signal, a control terminal connected to the flag signal, and an output as a second intermediate signal. The gated logic unit is connected to the first multiplexer and the second multiplexer, and is used to perform glitch elimination processing on the first intermediate signal and the second intermediate signal, and output glitch-free leading signal and lagging signal.

[0009] Optionally, the gating logic unit includes: The first AND gate has its inputs connected to the first intermediate signal and a high level, and its output is a leading signal. An enable signal generation subunit has its input terminals connected to an up signal and a dn signal, and its output is an enable signal. When both the up signal and the dn signal are 0, the enable signal is 0; when both the up signal and the dn signal are 1, the enable signal is 1; when the up signal and the dn signal are different, the enable signal remains unchanged from the previous state. The second AND gate has its inputs connected to the second intermediate signal and the enable signal, respectively, and its output is a lagging signal.

[0010] Optionally, the enable signal generation subunit includes a first NOR gate, a first NAND gate, a second NAND gate, and a third NAND gate; The first NOR gate and the first NAND gate each have their two inputs connected to the up signal and the dn signal, respectively. The output of the first NAND gate is connected to the first input of the second NAND gate. The output of the first NOR gate is connected to the first input of the third NAND gate. The second input of the second NAND gate is connected to the output of the third NAND gate. The output of the second NAND gate is connected to the second input of the third NAND gate, and they are all connected to the input of the second AND gate to provide an enable signal.

[0011] Optionally, the time-to-digital converter includes: A delay chain is composed of multiple delay units connected in series, and the leading signal is input to the first stage of the delay chain; Multiple D flip-flops are used, with the clock input of each D flip-flop connected to the lagging signal and the data input connected to the input of each stage in the delay chain. The output is a phase difference quantization result in the form of thermometer code. An encoder, connected to the output of each D flip-flop, is used to convert the thermometer code into binary codewords, which are then used as the output of the time-to-digital converter.

[0012] Optionally, the comparator module includes multiple bit-by-bit comparators and a decision unit. The number of bit-by-bit comparators is equal to the number of bits in the digital codeword. Each bit-by-bit comparator includes three output terminals, and each output terminal of the bit-by-bit comparator is connected to the decision unit. Each of the bit-by-bit comparators is used to compare the corresponding bit value of the digital codeword with the preset reference value and output three comparison signals, and the multiple bit-by-bit comparators cover all bit values ​​of the digital codeword; The decision unit is connected to the output of each bit-by-bit comparator and is used to generate a lock indication signal based on the output of each bit-by-bit comparator.

[0013] Optionally, each of the bit-by-bit comparators includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fourth NAND gate, a fifth NAND gate, and a second NOR gate; The input terminal of the first inverter is connected to the bit value signal of one bit of the digital codeword, and the input terminal of the first inverter is also connected to the first input terminal of the fifth NAND gate. The output terminal of the first inverter is connected to the first input terminal of the fourth NAND gate. The input terminal of the second inverter is connected to the bit value signal of the corresponding bit of the preset reference value, and the input terminal of the second inverter is also connected to the second input terminal of the fourth NAND gate. The output terminal of the second inverter is connected to the second input terminal of the fifth NAND gate. The output of the fourth NAND gate is connected to the input of the third inverter, and the output of the fifth NAND gate is connected to the input of the fourth inverter. The output of the third inverter is connected to the first input of the second NOR gate and serves as the first signal output. The output of the fourth inverter is connected to the second input of the second NOR gate and serves as the second signal output. The output of the second NOR gate serves as the third signal output.

[0014] Optionally, when the number of bits in the digital codeword is 4 bits, the bit-by-bit comparator includes a first bit-by-bit comparator, a second bit-by-bit comparator, a third bit-by-bit comparator, and a fourth bit-by-bit comparator; the decision unit includes a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, a fifth inverter, a sixth inverter, a third NOR gate, a fourth NOR gate, a fifth NOR gate, and a sixth NOR gate; The first input of the sixth NAND gate is connected to the third signal output of the fourth bit-by-bit comparator; the second input of the sixth NAND gate is connected to the second signal output of the third bit-by-bit comparator; the output of the sixth NAND gate is connected to the first input of the third NOR gate through the fifth inverter; the second input of the third NOR gate is connected to the second signal output of the fourth bit-by-bit comparator; and the output of the third NOR gate is connected to the first input of the tenth NAND gate. The first input of the seventh NAND gate is connected to the third signal output of the fourth bit-by-bit comparator; the second input of the seventh NAND gate is connected to the third signal output of the third bit-by-bit comparator; the output of the seventh NAND gate is connected to the first input of the fourth NOR gate; the second input of the fourth NOR gate is connected to the second signal output of the second bit-by-bit comparator via the sixth inverter; and the output of the fourth NOR gate is connected to the first input of the fifth NOR gate. The first input of the eighth NAND gate is connected to the third signal output of the fourth bit-by-bit comparator, the second input of the eighth NAND gate is connected to the third signal output of the third bit-by-bit comparator, and the output of the eighth NAND gate is connected to the first input of the sixth NOR gate; the first input of the ninth NAND gate is connected to the third signal output of the second bit-by-bit comparator, the second input of the ninth NAND gate is connected to the second signal output of the first bit-by-bit comparator, and the output of the ninth NAND gate is connected to the second input of the sixth NOR gate; the output of the sixth NOR gate is connected to the second input of the fifth NOR gate, the output of the fifth NOR gate is connected to the second input of the tenth NAND gate, and the tenth NAND gate outputs a lock indication signal.

[0015] Optionally, the locking detection circuit further includes: A synchronization register, whose clock terminal is connected to the leading signal and whose data terminal is connected to the digital codeword output by the time-to-digital converter, is used to perform synchronization processing on the digital codeword to eliminate glitches and output the synchronized codeword to the comparator module.

[0016] On the other hand, embodiments of this application provide an offset correction phase-locked loop, which includes the aforementioned locking detection circuit.

[0017] Compared with the prior art, this application has the following advantages: This application provides a lock detection circuit and an offset correction phase-locked loop. The lock detection circuit includes: a phase sequence determination module, used to receive up and dn signals from a frequency and phase detector, and output a leading signal and a lagging signal, wherein the frequency and phase detector is used to compare the frequency and phase of a reference clock and a feedback clock, and outputs up and dn signals according to the comparison result; the leading signal is the phase-leading one of the up and dn signals, and the lagging signal is the phase-lagging one of the up and dn signals; a time-to-digital converter, connected to the phase sequence determination module, used to receive the leading and lagging signals, quantize the phase difference between them, and output the corresponding digital codeword; and a comparator module, connected to the time-to-digital converter, used to compare the digital codeword with a preset reference value and output a lock indication signal.

[0018] Because this application no longer directly delays and samples the reference clock and feedback clock, but instead determines the lock state by detecting the phase difference between the up / dn signals output by the frequency and phase detector, it avoids the timing violation problems of traditional structures in high-speed scenarios and can operate stably at GHz-level clocks. Furthermore, by using a time-to-digital converter to quantize the phase difference, the measurement accuracy can reach the picosecond level, and preset reference values ​​can be flexibly configured according to system requirements to achieve an adjustable lock determination threshold.

[0019] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a circuit diagram of a lock detection circuit in the prior art.

[0022] Figure 2This is a timing diagram of a lock detection circuit in the prior art.

[0023] Figure 3 This is a schematic diagram of a locking detection circuit provided in an embodiment of this application.

[0024] Figure 4 This is a circuit diagram of the phase sequence determination module provided in an embodiment of this application.

[0025] Figure 5 Timing diagram of the phase sequence determination module provided in the embodiments of this application.

[0026] Figure 6 A circuit diagram of a time-to-digital converter provided in an embodiment of this application.

[0027] Figure 7 This is another schematic diagram of a locking detection circuit provided in an embodiment of this application.

[0028] Figure 8 The circuit diagram for each bit-by-bit comparator provided in the embodiments of this application is shown.

[0029] Figure 9 This is a schematic diagram of a plurality of bit-by-bit comparators provided in an embodiment of this application.

[0030] Figure 10 A circuit diagram of the decision unit provided in an embodiment of this application.

[0031] icon: 110 - Phase sequence determination module; 111 - RS latch; 112 - Gated logic unit; 120 - Time-to-digital converter; 121 - Delay chain; 122 - D flip-flop; 123 - Encoder; 130 - Comparator module; 140 - Synchronization register; MUX1 - First multiplexer; MUX2 - Second multiplexer; AND1 - First AND gate; AND2 - Second AND gate; NAND1 - First NAND gate; NAND2 - Second NAND gate; NAND3 - Third NAND gate; NAND4 - Fourth NAND gate; NAND5 - ... NAND gate 5; NAND6 - sixth NAND gate; NAND7 - seventh NAND gate; NAND8 - eighth NAND gate; NAND9 - ninth NAND gate; NAND10 - tenth NAND gate; OR1 - first inverter; OR2 - second inverter; OR3 - third inverter; OR4 - fourth inverter; OR5 - fifth inverter; OR6 - sixth inverter; NOR1 - first NOR gate; NOR2 - second NOR gate; NOR3 - third NOR gate; NOR4 - fourth NOR gate; NOR5 - fifth NOR gate; NOR6 - sixth NOR gate. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0036] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] As described in the background section, current traditional lock detection circuit structures are not suitable for high-speed scenarios. Figure 1The diagram shows a schematic of a lock-up detection circuit in the prior art. In the diagram, clkref and clkfb are the reference clock and feedback clock of the Deskew Phase Locked Loop (Deskew PLL), respectively, while Delayline represents the delay chain used to provide the delay Td. clkref_dly and clkfb_dly are the clocks of clkref and clkfb after an equal delay Td, respectively. DFE1 and DFE2 represent two D flip-flops. Using these two D flip-flops, clkref_dly samples clkfb to obtain Q1, and clkref samples clkfb_dly to obtain Q2. The value of Q1 is passed through an inverter, and Q2 is simultaneously input into a NOR gate. Therefore, the values ​​of Q1 and Q2 can be used to determine whether the phase difference between clkref and clkfb is within the allowable range (i.e., does not exceed Td).

[0038] Figure 2 The timing diagram of the above-mentioned lock detection circuit is discussed in two cases: "clkref phase leads clkfb" and "clkref phase lags clkfb". Figure 2 The left side of the middle diagram shows the waveform when clkref's phase leads clkfb. Figure 2 The right side of the diagram shows the waveform when the clkref phase lags behind the clkfb phase. When the clkref phase leads the clkfb phase, if Td ≤ Tskew + Tsetup, the Q1 result will be incorrect; if Td + Tskew + Tsetup ≥ T / 2, the Q2 result will be incorrect. Therefore, Td should satisfy T / 2 - Tskew - Tsetup ≤ Td ≤ Tskew + Tsetup, where T is the clock period, Tskew is the static phase error between clkref and clkfb, and Tsetup is the setup time of the D flip-flop. Similarly, when the clkref phase lags behind the clkfb phase, Td should satisfy T / 2 - Tskew - Thold ≤ Td ≤ Tskew + Thold, where Thold is the hold time of the D flip-flop.

[0039] For traditional offset correction phase-locked loops, the timing constraints mentioned above are easily met due to the low frequencies of clkref and clkfb. However, for high-speed offset correction phase-locked loops, the frequencies of clkref and clkfb are very high (generally in the GHz range), and the period T is only a few hundred picoseconds, which can easily lead to timing violations.

[0040] In view of this, in order to solve the above problems, this application provides a lock detection circuit, which determines the phase order relationship between the up signal and the dn signal through a phase sequence determination module, then accurately quantifies the delay time between the rising edges of the two signals through a time-to-digital converter, and finally determines whether the delay time is less than a preset allowable value through a comparator module, thereby determining whether the offset correction phase-locked loop is locked.

[0041] The following is an exemplary description of the lock detection circuit provided in this application. For an optional implementation, please refer to [link / reference]. Figure 3 The locking detection circuit includes: The phase sequence determination module 110 receives the up signal and dn signal from the frequency and phase detector and outputs a leading signal and a lagging signal. The frequency and phase detector compares the frequency and phase of the reference clock with the feedback clock and outputs the up signal and dn signal according to the comparison result. The leading signal is the phase leader of the up signal and the dn signal, and the lagging signal is the phase lag of the up signal and the dn signal. The time-to-digital converter 120 is connected to the phase sequence determination module 110 and receives the leading signal and the lagging signal. It quantizes the phase difference between the two and outputs the corresponding digital codeword. The comparator module 130 is connected to the time-to-digital converter 120 and compares the digital codeword with a preset reference value and outputs a lock indication signal.

[0042] It should be noted that the locking detection circuit provided in this application is a dedicated circuit used in phase-locked loops (PLLs). Its core purpose is to determine whether the PLL has entered a stable operating state, that is, to determine whether locking has been completed. For a PLL to function normally, the internally generated feedback clock must be consistent with the externally input reference clock in both frequency and phase. This consistency is not achieved instantaneously but requires a certain amount of time; therefore, the locking detection circuit must determine in real time whether the locking state has been reached.

[0043] To enable the lock detection circuit to operate in high-speed scenarios, this application uses the up and dn signals output by a phase frequency detector (PFD) as direct inputs, replacing the traditional method of directly using the reference clock and feedback clock themselves. This indirectly but accurately reflects the phase relationship between the two. Specifically, the phase frequency detector compares the frequency and phase of the reference clock and the feedback clock, and outputs up and dn signals based on the comparison result. The relative timing relationship between the up and dn signals characterizes which phase leads and which phase lags between the reference clock and the feedback clock. During this process, the phase sequence determination module 110 receives the up and dn signals and outputs leading and lagging signals accordingly. A time-to-digital converter (TDC) 120 is connected to this module and receives the leading and lagging signals, quantizes the time interval between them (i.e., the phase difference), and outputs the corresponding digital codeword. A comparator module 130 is connected to the time-to-digital converter 120 and compares the digital codeword with a preset reference value, outputting a lock indication signal. Therefore, this circuit no longer uses the traditional structure that relies on delay chains and D flip-flops for sampling and judgment. Instead, it directly uses the time-to-digital converter 120 to digitally measure the phase difference and then determines whether the phase difference is less than a certain specified threshold by numerical comparison, thereby achieving an accurate and fast judgment on whether the phase-locked loop has completed locking.

[0044] In this application, the frequency and phase detector functions as a signal conversion and preprocessing module. Its core function is to convert the frequency and phase differences between the high-frequency reference clock and the feedback clock into two digital pulse signals: the up signal and the dn signal. The up pulse indicates that the reference clock is phase-leading, and the dn pulse indicates that the feedback clock is phase-leading. The pulse width is precisely equal to the time difference between the rising edges of the two clocks. Through this conversion, the timing detection problem, which was originally difficult to process directly under GHz-level high-speed clocks, is transformed into a pulse width measurement problem. This allows the subsequent phase sequence judgment module 110, time-to-digital converter 120, and comparator module 130 to stably and accurately complete the lock-in state judgment on lower-frequency pulse signals, thereby fundamentally avoiding the timing violation problems caused by directly sampling high-frequency clocks in traditional solutions.

[0045] Since the phase relationship (sequence and phase difference) of the up signal and the dn signal may be different in each cycle, it is necessary to first determine the phase sequence of the two signals. The up signal and the dn signal pass through the phase sequence determination module 110, which outputs the leading signal out_lead and the lagging signal out_lag. The phase of out_lead always leads out_lag, which is convenient for the subsequent time-to-digital converter 120 to process.

[0046] As one implementation method, please refer to Figure 4 The phase sequence determination module 110 includes an RS latch 111, a first multiplexer MUX1, a second multiplexer MUX2, and a gating logic unit 112. The RS latch 111 is used to output a flag signal according to the arrival order of the rising edges of the up signal and the dn signal. The flag signal indicates whether the up signal lags behind the dn signal. The first input terminal of the first multiplexer MUX1 is connected to the up signal, the second input terminal is connected to the dn signal, the control terminal is connected to the flag signal, and the output is a first intermediate signal. The first input terminal of the second multiplexer MUX2 is connected to the dn signal, the second input terminal is connected to the up signal, the control terminal is connected to the flag signal, and the output is a second intermediate signal. The gating logic unit 112 is connected to the first multiplexer MUX1 and the second multiplexer MUX2, and is used to perform glitch elimination processing on the first intermediate signal and the second intermediate signal, and output a glitch-free leading signal and lagging signal.

[0047] As can be seen, this application dynamically selects and outputs the always-phase-leading and always-phase-lagging signals by judging the order of arrival of the rising edges of the up signal and the dn signal, and then applies enable control to the lagging signal that may contain glitches, thereby obtaining glitches-free leading and lagging signals, so as to ensure that the subsequent time-to-digital converter 120 accurately and stably quantizes the phase difference.

[0048] Specifically, the up signal and the dn signal are first input to an RS latch 111. The RS latch 111 outputs a flag signal dn_wins according to the order in which their rising edges arrive. When dn_wins = 0, it indicates that the rising edge of the up signal arrives before the dn signal, meaning the up signal has a leading phase. When dn_wins = 1, it indicates that the rising edge of the dn signal arrives before the up signal, meaning the up signal has a lagging phase. The first input terminal ("0") of the first multiplexer MUX1 is connected to the up signal, and the second input terminal ("1") is connected to the dn signal. Its control terminal is connected to dn_wins, and its output is the first intermediate signal out_lead_pre. The first input terminal ("0") of the second multiplexer MUX2 is connected to the dn signal, and the second input terminal ("1") is connected to the up signal. Its control terminal is also connected to dn_wins, and its output is the second intermediate signal out_lag_pre.

[0049] Therefore, when dn_wins = 0, the first multiplexer MUX1 outputs the up signal as out_lead_pre, and MUX2 outputs the dn signal as out_lag_pre; when dn_wins = 1, MUX1 outputs the dn signal as out_lead_pre, and MUX2 outputs the up signal as out_lag_pre. Thus, out_lead_pre always represents the phase leader between the up signal and the dn signal, and out_lag_pre always represents the phase lag between the up signal and the dn signal.

[0050] In this process, the gated logic unit 112 is connected to the first multiplexer MUX1 and the second multiplexer MUX2, and is used to perform glitch removal processing on the first intermediate signal out_lead_pre and the second intermediate signal out_lag_pre, outputting glitch-free leading and lagging signals. Specifically, the gated logic unit 112 includes a first AND gate AND1, an enable signal generation subunit, and a second AND gate AND2. The two inputs of the first AND gate AND1 are respectively connected to the first intermediate signal out_lead_pre and a high level, and its output is the leading signal. Since the high level is always valid, the leading signal is directly equal to out_lead_pre and does not generate glitches with transient changes in the up and dn signals. The two inputs of the enable signal generation subunit are respectively connected to the up signal and the dn signal, and its output is the enable signal en. When both the up signal and the dn signal are 0, the enable signal is 0; when both the up signal and the dn signal are 1, the enable signal is 1; when the up signal and the dn signal are different, the enable signal remains unchanged from the previous state.

[0051] For example, the enable signal can be implemented through the following logical relationship: = + + ,in, This indicates the logic level of the up signal. This indicates the logic level of the dn signal. The logic level of the enable signal is indicated by the AND gate AND2. The two inputs of the AND gate AND2 are connected to the second intermediate signal out_lag_pre and the enable signal en, respectively, and its output is the lag signal. Since the enable signal en is only valid when both the up and dn signals are high or maintained high via feedback, it masks the narrow pulse glitches that may appear in the second intermediate signal out_lag_pre near the transition edges of the up and dn signals. This ensures that the lag signal is stably established within the effective window and is forced low during invalid periods, thus eliminating glitches in the second intermediate signal out_lag_pre.

[0052] For one illustration of the logical relationship for implementing the signal generation subunit, please refer to [link / reference]. Figure 4 The enable signal generation subunit includes a first NOR gate NOR1, a first NAND gate NAND1, a second NAND gate NAND2, and a third NAND gate NAND3. The two inputs of the first NOR gate NOR1 and the first NAND gate NAND1 are respectively connected to the up signal and the dn signal. The output of the first NAND gate NAND1 is connected to the first input of the second NAND gate NAND2. The output of the first NOR gate NOR1 is connected to the first input of the third NAND gate NAND3. The second input of the second NAND gate NAND2 is connected to the output of the third NAND gate NAND3. The output of the second NAND gate NAND2 is connected to the second input of the third NAND gate NAND3, and they are all connected to the input of the second AND gate AND2 to provide the enable signal.

[0053] Based on the circuit diagram, the truth table for the enable signal is shown in the following table:

[0054] From the truth table, we know that when both up and dn are 0, en is 0; when up=0 and dn=1 or up=1 and dn=0, en remains unchanged from the previous state; when both up and dn are 1, en is 1. This solves the aforementioned glitches problem, and the final output out_lead and out_lag are both glitches-free signals, where out_lead is the phase-leading signal between up and dn, and out_lag is the phase-lagning signal between up and dn.

[0055] It should be noted that the glitches in the phase sequence determination module are fundamentally caused by the combinational logic characteristics of the multiplexer and the competition between the control signal and the input signal at the time of change. Let's analyze this using the example of the up signal leading the dn signal: When the rising edge of the 'up' signal arrives first, the RS latch determines that 'up' leads and sets the flag signal 'dn_wins' to 0. At this time, the first multiplexer MUX1 selects the 'up' signal as its output, out_lead_pre = 'up', and the signal is stable. The second multiplexer MUX2 selects the 'dn' signal as its output, out_lag_pre = 'dn'. However, near the same moment the rising edge of 'up' arrives, the internal logic of the multiplexers undergoes a brief signal switching. This is mainly manifested as follows: before the rising edge of 'up' arrives, the RS latch may not have completed its judgment, and 'dn_wins' is in an uncertain state; when the rising edge of 'up' arrives, 'dn_wins' switches from the previous state to 0, and this switching process requires the propagation delay of the gate circuit; during the 'dn_wins' switching, the output of the second multiplexer will briefly exhibit an erroneous state, such as incorrectly outputting a high level of the 'up' signal, or outputting an intermediate level between 0 and 1. This brief erroneous output pulse is called a glitch. Figure 5 As shown, Figure 5 The left side of the middle section shows a waveform diagram when the up signal leads the dn signal in phase. Figure 5 The right side of the middle section shows a waveform diagram when the up signal lags behind the dn signal. From the waveform, out_lag_pre will have a brief high-level pulse during the time period that should be 0. The width of this pulse is usually equal to the propagation delay time of the gate circuit (tens to hundreds of picoseconds).

[0056] If this glitch is directly transmitted to the subsequent circuit, the time-to-digital converter may mistakenly identify the glitch as a valid rising edge of the lagging signal, thus measuring an incorrect phase difference and causing false triggering. Alternatively, it may lead to data errors, misjudgments of lockout, or other issues.

[0057] This application establishes an enable signal generation subunit, and the enable signal `en` has a memory function: it maintains its previous state when the `up` and `dn` signals are different, setting it to 1 only when both are 1, and clearing it to 0 only when both are 0. This characteristic ensures that `en` remains stable at 0 during the window period when glitches may occur. Its glitch elimination mechanism is as follows: by ANDing the lagging signal with the enable signal `en` through a second AND gate, `en` = 0 during the glitch window period, and the glitches are shielded; when the lagging signal arrives stably, `en` = 1, and normal output occurs. The rising edge of `en` naturally lags behind the end point of the glitch window, achieving perfect timing isolation. Therefore, the gating logic provided in this application utilizes the natural timing characteristics of the `up` and `dn` signals, i.e., there is a time difference between the two rising edges, the glitch window occurs after the first rising edge, and `en` only opens when the second rising edge arrives. This timing alignment can achieve complete glitch elimination without additional control circuitry, ensuring that both the leading and lagging signals in the final output are stable signals without glitches.

[0058] As can be seen, this application uses RS latch 111 to capture the rising edge sequence, multiplexer to achieve dynamic path selection, and enable signal to perform conditional gating on lagging signal, distinguishing the leading and lagging roles from the signal source. It also introduces a timing-controllable enable mechanism in the output stage, which not only retains the essential judgment of phase relationship, but also fundamentally avoids the propagation of combinational logic glitches to subsequent circuits. This provides a stable and reliable phase difference measurement reference for time-to-digital converter 120, significantly improving the reliability and anti-interference capability of lock detection.

[0059] After the up and dn signals are processed by the phase sequence determination module 110, the leading signal out_lead and the lagging signal out_lag are obtained. At this point, it is only necessary to directly measure the phase difference between the two signals using the time-to-digital converter 120. For one implementation method, please refer to [link / reference]. Figure 6 The time-to-digital converter 120 includes a delay chain 121, multiple D flip-flops 122, and an encoder 123. The delay chain 121 is composed of multiple delay units connected in series. The leading signal is input to the first stage of the delay chain 121. The clock terminal of each D flip-flop 122 is connected to the lagging signal, and the data terminal is connected to the input of each stage in the delay chain 121. The output is the phase difference quantization result in the form of thermometer code. The encoder 123 is connected to the output terminal of each D flip-flop 122 and is used to convert the thermometer code into binary codewords as the output of the time-to-digital converter 120.

[0060] Combination Figure 6 As shown, the working principle of the time-to-digital converter 120 is as follows: the leading signal out_lead passes through the delay chain 121, and the lagging signal out_lag samples the delayed out_lead at each stage. The output of each stage D flip-flop 122 is Q. <n>The output codeword Q <n:0>This allows for the quantification of the delay time between out_lead and out_lag. <n:0>The temperature code is n-bit. To facilitate subsequent processing, it needs to be converted to m-bit binary code. Therefore, the final output codeword of the time-to-digital converter 120 is TDC_out. <m:0>.

[0061] Due to TDC_out <m:0>There may be glitches that could cause errors in the comparison results of the subsequent comparator module 130. Therefore, TDC_out needs to be modified. <m:0>Perform a synchronization operation. For one possible implementation, please refer to [link / reference]. Figure 7 The lock detection circuit also includes a synchronization register 140, whose clock terminal is connected to a leading signal or a lagging signal, and whose data terminal is connected to the digital codeword output by the time-to-digital converter 120. The synchronization register 140 is used to perform synchronization processing on the digital codeword to eliminate glitches, and output the synchronized codeword to the comparator module 130.

[0062] It should be noted that the synchronization register 140 can be implemented using a D flip-flop, thereby achieving the use of the lead signal out_lead to control TDC_out. <m:0>One beat is struck, and the synchronized codeword TDC_out_sync is obtained. <m:0>To eliminate glitches. In this application, the purpose of the synchronization operation is to output the codeword TDC_out_sync. <m:0>Stability and avoiding spikes are important; therefore, this application does not limit the type of signal that hits the beat, as it can be either a leading signal or a lagging signal.

[0063] After synchronizing the codeword TDC_out_sync <m:0>After being sent to the subsequent comparator module 130, the comparator module 130 compares the digital codeword with a preset reference value and outputs a lock indication signal. Wherein, ref <m:0>The comparison reference value is set if TDC_out_sync <m:0>Less than or equal to ref <m:0>If the rising edge delay of up and dn in this cycle is within the specified range Td, then clkref and clkfb are considered to be aligned; if TDC_out_sync <m:0>Greater than ref <m:0>If the output is 0, it means that the rising edge delay of up and dn in this cycle is not within the specified range Td. In this case, it is considered that clkref and clkfb are not aligned.

[0064] In one implementation, the comparator module 130 includes multiple bit-by-bit comparators and a decision unit. The number of bit-by-bit comparators is equal to the number of bits in the digital codeword. Each bit-by-bit comparator includes three output terminals, and each output terminal of the bit-by-bit comparator is connected to the decision unit. Each bit-by-bit comparator compares the digital codeword with the corresponding bit value of a preset reference value and outputs three comparison signals. The multiple bit-by-bit comparators cover all bit values ​​of the digital codeword. The decision unit is connected to the output terminal of each bit-by-bit comparator and generates a lock indication signal based on the output of each bit-by-bit comparator.

[0065] It should be noted that each bit-by-bit comparator is used to compare one bit in the digital codeword with the corresponding bit of the preset reference value. For example, if the digital codeword is 1010 and the preset reference value is 0101, then the comparator module 130 is equipped with four bit-by-bit comparators. The inputs of the first bit-by-bit comparator are the first bit "0" of the digital codeword and the first bit "1" of the preset reference value, the inputs of the second comparator are the first bit "1" of the digital codeword and the first bit "0" of the preset reference value, and so on.

[0066] As one implementation method, please refer to Figure 8 Each bit-by-bit comparator includes a first inverter OR1, a second inverter OR2, a third inverter OR3, a fourth inverter OR4, a fourth NAND gate NAND4, a fifth NAND gate NAND5, and a second NOR gate NOR2. The input of the first inverter OR1 is connected to the bit value signal of one bit of the digital codeword, and the input of the first inverter OR1 is also connected to the first input of the fifth NAND gate NAND5. The output of the first inverter OR1 is connected to the first input of the fourth NAND gate NAND4. The input of the second inverter OR2 is connected to the bit value signal of the corresponding bit of a preset reference value, and the input of the second inverter OR2 is also connected to... The output of the fourth NAND gate (NAND4) is connected to the second input terminal, and the output of the second inverter (OR2) is connected to the second input terminal of the fifth NAND gate (NAND5). The output of the fourth NAND gate (NAND4) is connected to the input terminal of the third inverter (OR3), and the output of the fifth NAND gate (NAND5) is connected to the input terminal of the fourth inverter (OR4). The output terminal of the third inverter (OR3) is connected to the first input terminal of the second NOR gate (NOR2) and serves as the first signal output terminal. The output terminal of the fourth inverter (OR4) is connected to the second input terminal of the second NOR gate (NOR2) and serves as the second signal output terminal. The output terminal of the second NOR gate (NOR2) serves as the third signal output terminal.

[0067] Based on this, if the input signals are A and B, the output of the first signal output terminal is G, the output of the second signal output terminal is L, and the output of the first signal output terminal is E, which are used to represent the relationship between A and B. The truth table is shown below. Each bit is compared, and then combined to obtain the final comparison result.

[0068]

[0069] That is, when A is 1 and B is 0, the signals G, E and L at the three signal output terminals are 1, 0 and 0 respectively; when A is 1 and B is 1, or A is 0 and B is 0, the signals G, E and L at the three signal output terminals are 0, 1 and 0 respectively; when A is 0 and B is 1, the signals G, E and L at the three signal output terminals are 0, 0 and 1 respectively.

[0070] For example, if the number of bits in the numeric codeword is 4, please refer to [link / reference]. Figure 9 and Figure 10 The bit-by-bit comparator includes a first bit-by-bit comparator, a second bit-by-bit comparator, a third bit-by-bit comparator, and a fourth bit-by-bit comparator; the decision unit includes a sixth NAND gate (NAND6), a seventh NAND gate (NAND7), an eighth NAND gate (NAND8), a ninth NAND gate (NAND9), a tenth NAND gate (NAND10), a fifth inverter (OR5), a sixth inverter (OR6), a third NOR gate (NOR3), a fourth NOR gate (NOR4), a fifth NOR gate (NOR5), and a sixth NOR gate (NOR6); the first input of the sixth NAND gate (NAND6) is connected to the third signal output of the fourth bit-by-bit comparator, and the sixth NAND gate... The second input of NAND gate 6 is connected to the second signal output of the third bit-by-bit comparator. The output of the sixth NAND gate 6 is connected to the first input of the third NOR gate 3 via the fifth inverter OR5. The second input of the third NOR gate 3 is connected to the second signal output of the fourth bit-by-bit comparator. The output of the third NOR gate 3 is connected to the first input of the tenth NAND gate 10. The first input of the seventh NAND gate 7 is connected to the third signal output of the fourth bit-by-bit comparator. The second input of the seventh NAND gate 7 is connected to the third bit-by-bit comparator. The third signal output terminal of the seventh NAND gate (NAND7) is connected to the first input terminal of the fourth NOR gate (NOR4). The second input terminal of the fourth NOR gate (NOR4) is connected to the second signal output terminal of the second bit-by-bit comparator via the sixth inverter (OR6). The output terminal of the fourth NOR gate (NOR4) is connected to the first input terminal of the fifth NOR gate (NOR5). The first input terminal of the eighth NAND gate (NAND8) is connected to the third signal output terminal of the fourth bit-by-bit comparator. The second input terminal of the eighth NAND gate (NAND8) is connected to the third signal output terminal of the third bit-by-bit comparator. The output terminal of the eighth NAND gate (NAND8) is connected to... The first input of the sixth NOR gate (NOR6); the first input of the ninth NAND gate (NAND9) is connected to the third signal output of the second bit-by-bit comparator; the second input of the ninth NAND gate (NAND9) is connected to the second signal output of the first bit-by-bit comparator; the output of the ninth NAND gate (NAND9) is connected to the second input of the sixth NOR gate (NOR6); the output of the sixth NOR gate (NOR6) is connected to the second input of the fifth NOR gate (NOR5); the output of the fifth NOR gate (NOR5) is connected to the second input of the tenth NAND gate (NAND10); and the tenth NAND gate (NAND10) outputs a lock indication signal.

[0071] Of course, the number of bits in a digital codeword can also be 8 bits or 16 bits, etc. When the number of bits in a digital codeword changes, the number of bit-by-bit comparators changes, and the circuit of the decision unit changes accordingly, which will not be elaborated here.

[0072] In summary, the lock detection circuit provided in this application determines whether the phase difference between the reference clock clkref and the feedback clock clkfb is within the required range by directly measuring the delay of the rising edges of the up and dn signals. Compared to traditional solutions that delay and cross-sample the reference clock clkref and the feedback clock clkfb, this approach allows for more stable operation in high-speed scenarios. Furthermore, this application utilizes a time-to-digital converter for delay measurement, resulting in higher accuracy. Additionally, the comparator module following the time-to-digital converter directly outputs the measurement results, facilitating direct detection and processing of the lock state by the system.

[0073] Based on the above implementation, this application embodiment also provides an offset correction phase-locked loop, which includes the above-mentioned locking detection circuit.

[0074] In summary, this application provides a lock detection circuit and an offset correction phase-locked loop. The lock detection circuit includes: a phase sequence determination module, used to receive up and dn signals from a frequency and phase detector, and output a leading signal and a lagging signal, wherein the frequency and phase detector is used to compare the frequency and phase of a reference clock and a feedback clock, and outputs up and dn signals according to the comparison result; the leading signal is the phase-leading one of the up and dn signals, and the lagging signal is the phase-lagging one of the up and dn signals; a time-to-digital converter, connected to the phase sequence determination module, used to receive the leading and lagging signals, quantize the phase difference between them, and output the corresponding digital codeword; and a comparator module, connected to the time-to-digital converter, used to compare the digital codeword with a preset reference value and output a lock indication signal.

[0075] Because this application no longer directly delays and samples the reference clock and feedback clock, but instead determines the lock state by detecting the phase difference between the up / dn signals output by the frequency and phase detector, it avoids the timing violation problems of traditional structures in high-speed scenarios and can operate stably at GHz-level clocks. Furthermore, by using a time-to-digital converter to quantize the phase difference, the measurement accuracy can reach the picosecond level, and preset reference values ​​can be flexibly configured according to system requirements to achieve an adjustable lock determination threshold.

[0076] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0077] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims. < / n>

Claims

1. A locking detection circuit, characterized in that, The lock detection circuit includes: The phase order determination module is used to receive the up signal and dn signal from the frequency and phase detector, and output a leading signal and a lagging signal. The frequency and phase detector is used to compare the frequency and phase of the reference clock and the feedback clock, and outputs the up signal and dn signal according to the comparison result. The leading signal is the phase leader of the up signal and the dn signal, and the lagging signal is the phase lag of the up signal and the dn signal. A time-to-digital converter, connected to the phase sequence determination module, is used to receive the leading signal and the lagging signal, quantize the phase difference between them, and output the corresponding digital codeword. The comparator module, connected to the time-to-digital converter, is used to compare the digital codeword with a preset reference value and output a lock indication signal.

2. The locking detection circuit according to claim 1, characterized in that, The phase order determination module includes: An RS latch is used to output a flag signal according to the arrival order of the rising edges of the up signal and the dn signal, wherein the flag signal indicates whether the up signal lags behind the dn signal. The first multiplexer has a first input terminal connected to the up signal, a second input terminal connected to the dn signal, a control terminal connected to the flag signal, and an output as the first intermediate signal. The second multiplexer has a first input terminal connected to the dn signal, a second input terminal connected to the up signal, a control terminal connected to the flag signal, and an output as a second intermediate signal. The gated logic unit is connected to the first multiplexer and the second multiplexer, and is used to perform glitch elimination processing on the first intermediate signal and the second intermediate signal, and output glitch-free leading signal and lagging signal.

3. The locking detection circuit according to claim 2, characterized in that, The gated logic unit includes: The first AND gate has its inputs connected to the first intermediate signal and a high level, and its output is a leading signal. An enable signal generation subunit has its input terminals connected to an up signal and a dn signal, and its output is an enable signal. Specifically, when both the up signal and the dn signal are 0, the enable signal is 0; when both the up signal and the dn signal are 1, the enable signal is 1; when the up signal and the dn signal are different, the enable signal remains unchanged from the previous state. The second AND gate has its inputs connected to the second intermediate signal and the enable signal, respectively, and its output is a lagging signal.

4. The locking detection circuit according to claim 3, characterized in that, The enable signal generation subunit includes a first NOR gate, a first NAND gate, a second NAND gate, and a third NAND gate; The first NOR gate and the first NAND gate each have their two inputs connected to the up signal and the dn signal, respectively. The output of the first NAND gate is connected to the first input of the second NAND gate. The output of the first NOR gate is connected to the first input of the third NAND gate. The second input of the second NAND gate is connected to the output of the third NAND gate. The output of the second NAND gate is connected to the second input of the third NAND gate, and they are all connected to the input of the second AND gate to provide an enable signal.

5. The locking detection circuit according to claim 1, characterized in that, The time-to-digital converter includes: A delay chain is composed of multiple delay units connected in series, and the leading signal is input to the first stage of the delay chain; Multiple D flip-flops are used, with the clock input of each D flip-flop connected to the lagging signal and the data input connected to the input of each stage in the delay chain. The output is a phase difference quantization result in the form of thermometer code. An encoder, connected to the output of each D flip-flop, is used to convert the thermometer code into binary codewords, which are then used as the output of the time-to-digital converter.

6. The locking detection circuit according to claim 1, characterized in that, The comparator module includes multiple bit-by-bit comparators and a decision unit. The number of bit-by-bit comparators is equal to the number of bits in the digital codeword. Each bit-by-bit comparator includes three output terminals, and each output terminal of the bit-by-bit comparator is connected to the decision unit. Each of the bit-by-bit comparators is used to compare the corresponding bit value of the digital codeword with the preset reference value and output three comparison signals, and the multiple bit-by-bit comparators cover all bit values ​​of the digital codeword; The decision unit is connected to the output of each bit-by-bit comparator and is used to generate a lock indication signal based on the output of each bit-by-bit comparator.

7. The locking detection circuit according to claim 6, characterized in that, Each of the bit-by-bit comparators includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fourth NAND gate, a fifth NAND gate, and a second NOR gate; The input terminal of the first inverter is connected to the bit value signal of one bit of the digital codeword, and the input terminal of the first inverter is also connected to the first input terminal of the fifth NAND gate. The output terminal of the first inverter is connected to the first input terminal of the fourth NAND gate. The input terminal of the second inverter is connected to the bit value signal of the corresponding bit of the preset reference value, and the input terminal of the second inverter is also connected to the second input terminal of the fourth NAND gate. The output terminal of the second inverter is connected to the second input terminal of the fifth NAND gate. The output of the fourth NAND gate is connected to the input of the third inverter, and the output of the fifth NAND gate is connected to the input of the fourth inverter. The output of the third inverter is connected to the first input of the second NOR gate and serves as the first signal output. The output of the fourth inverter is connected to the second input of the second NOR gate and serves as the second signal output. The output of the second NOR gate serves as the third signal output.

8. The locking detection circuit according to claim 6, characterized in that, When the number of bits in the digital codeword is 4 bits, the bit-by-bit comparator includes a first bit-by-bit comparator, a second bit-by-bit comparator, a third bit-by-bit comparator, and a fourth bit-by-bit comparator; the decision unit includes a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, a fifth inverter, a sixth inverter, a third NOR gate, a fourth NOR gate, a fifth NOR gate, and a sixth NOR gate; The first input of the sixth NAND gate is connected to the third signal output of the fourth bit-by-bit comparator; the second input of the sixth NAND gate is connected to the second signal output of the third bit-by-bit comparator; the output of the sixth NAND gate is connected to the first input of the third NOR gate through the fifth inverter; the second input of the third NOR gate is connected to the second signal output of the fourth bit-by-bit comparator; and the output of the third NOR gate is connected to the first input of the tenth NAND gate. The first input of the seventh NAND gate is connected to the third signal output of the fourth bit-by-bit comparator; the second input of the seventh NAND gate is connected to the third signal output of the third bit-by-bit comparator; the output of the seventh NAND gate is connected to the first input of the fourth NOR gate; the second input of the fourth NOR gate is connected to the second signal output of the second bit-by-bit comparator via the sixth inverter; and the output of the fourth NOR gate is connected to the first input of the fifth NOR gate. The first input of the eighth NAND gate is connected to the third signal output of the fourth bit-by-bit comparator, the second input of the eighth NAND gate is connected to the third signal output of the third bit-by-bit comparator, and the output of the eighth NAND gate is connected to the first input of the sixth NOR gate; the first input of the ninth NAND gate is connected to the third signal output of the second bit-by-bit comparator, the second input of the ninth NAND gate is connected to the second signal output of the first bit-by-bit comparator, and the output of the ninth NAND gate is connected to the second input of the sixth NOR gate; the output of the sixth NOR gate is connected to the second input of the fifth NOR gate, the output of the fifth NOR gate is connected to the second input of the tenth NAND gate, and the tenth NAND gate outputs a lock indication signal.

9. The locking detection circuit according to claim 1, characterized in that, The lock detection circuit also includes: A synchronization register, whose clock terminal is connected to the leading or lagging signal and whose data terminal is connected to the digital codeword output by the time-to-digital converter, is used to perform synchronization processing on the digital codeword to eliminate glitches and output the synchronized codeword to the comparator module.

10. An offset correction phase-locked loop, characterized in that, The offset correction phase-locked loop includes the locking detection circuit as described in any one of claims 1 to 9.

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