Digital circuit based on automatic frequency calibration module and method, device and medium thereof

Abstract

The application provides a digital circuit based on an automatic frequency calibration module, a method, a device and a medium. The digital circuit comprises a pressure cavity oscillator, a first frequency divider and an automatic frequency calibration module which are connected in communication. The automatic frequency calibration module comprises: a synchronous sampling counting unit which is connected in communication with the first frequency divider and is used to obtain a counting value based on an acquired asynchronous counting window and a first voltage control feedback frequency output by the first frequency divider; and a calculation comparison processing unit which is connected in communication with the synchronous sampling counting unit and the pressure cavity oscillator respectively and is used to obtain a counting difference value based on the counting value and a target value. When the absolute value of the counting difference value is a minimum value, the calculation comparison processing unit outputs a sub-band frequency control word corresponding to the counting difference value to the pressure cavity oscillator. According to the technical scheme of the embodiment of the application, the optimal sub-band frequency control word can be automatically selected to realize frequency calibration, the calibration time is shortened, and the calibration speed is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a digital circuit based on an automatic frequency calibration module, as well as its method, apparatus and medium. Background Technology

[0002] In a phase-locked loop (PLL), the output frequency range of the PLL is related to the output frequency range of the voltage-controlled oscillator (VCO) and its voltage control gain. Increasing the voltage control gain of the VCO will lead to a deterioration in phase noise performance. If a single tuning curve is used to cover the frequency range, a large tuning gain will be generated, which will further deteriorate the phase noise performance. Therefore, the VCO uses multiple subbands to reduce the tuning gain, thereby effectively improving phase noise performance while covering a wide output range.

[0003] However, before PLL locking, the VCO output subband needs to be selected. This process is called Automatic Frequency Calibration (AFC). AFC includes two steps: sampling comparison and subband search. Sampling comparison refers to AFC acquiring and processing some parameters of the loop and comparing them with a reference signal to determine whether other subbands need to be selected. In the sampling comparison step, when using the open-loop counting comparison method, the AFC loop is disconnected from the PLL loop, and only the AFC loop operates. The VCO control voltage is connected to a fixed voltage, and the VCO subband search is controlled by comparing the acquired feedback signal with the reference signal. The VCO subband search includes a binary search method, comparing the VCO output voltage-controlled frequency with the reference frequency. If the VCO's voltage-controlled frequency is greater than the reference frequency, the intermediate subband frequency is selected downwards using the binary search method; otherwise, the intermediate subband frequency is selected upwards. However, existing automatic frequency calibration methods have long calibration times and slow calibration speeds. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a digital circuit, method, apparatus, and medium based on an automatic frequency calibration module, which can automatically select the optimal sub-band frequency control word to achieve frequency calibration, thereby shortening the calibration time and increasing the calibration speed.

[0005] In a first aspect, embodiments of the present invention provide a digital circuit based on an automatic frequency calibration module. The digital circuit includes a phase-locked loop (PLL) and an automatic frequency calibration module. The PLL includes a cavity oscillator and a first frequency divider that are communicatively connected to each other. The first frequency divider is used to divide the voltage-controlled frequency output by the cavity oscillator to obtain a first voltage-controlled feedback frequency. The automatic frequency calibration module is communicatively connected to both the cavity oscillator and the first frequency divider. The automatic frequency calibration module includes: A synchronous sampling and counting unit is communicatively connected to the first frequency divider. The synchronous sampling and counting unit is used to sample and count the first voltage-controlled feedback frequency output by the first frequency divider based on the acquired asynchronous counting window to obtain a count value. The asynchronous counting window is generated based on a reference frequency. A calculation and comparison processing unit is communicatively connected to the synchronous sampling and counting unit and the cavity oscillator. The calculation and comparison processing unit is used to compare the count value with a preset target value, and obtain a count difference based on the count value and the target value. The count difference is equal to the count value minus the target value. When the absolute value of the count difference is the minimum value, the sub-band frequency control word corresponding to the count difference is the optimal sub-band frequency control word. The calculation and comparison processing unit outputs the optimal sub-band frequency control word to the cavity oscillator. The sub-band frequency control word is used to indicate the sub-band frequency configuration of the cavity oscillator.

[0006] According to some embodiments of the present invention, the automatic frequency calibration module further includes: A state machine control unit is communicatively connected to the synchronous sampling and counting unit and the calculation and comparison processing unit, respectively. The state machine control unit is used to control the synchronous sampling and counting unit and the calculation and comparison processing unit. A timing generation unit is communicatively connected to the state machine control unit. The timing generation unit processes the acquired reference frequency to generate a runtime sequence and inputs the runtime sequence to the state machine control unit. The runtime sequence includes the asynchronous counting window, the comparison window, and the reset window. The runtime sequence is used to instruct the state machine control unit to perform a state transition. When the state machine control unit acquires the comparison window, the state machine control unit controls the calculation comparison processing unit to compare the target value and the count value, and obtain the count difference based on the target value and the count value; When the state machine acquires the reset window, the state machine control unit controls the counter of the synchronous sampling counting unit to reset.

[0007] According to some embodiments of the present invention, it further includes: A frequency and phase detector, a charge pump, and a low-pass filter are sequentially connected in communication, and the low-pass filter is communicatively connected to the voltage-controlled oscillator and the first frequency divider; The second frequency divider is communicatively connected to the output terminal of the cavity oscillator and the frequency and phase detector, respectively. The second frequency divider is used to divide the cavity frequency output by the cavity oscillator to obtain the second voltage-controlled feedback frequency, and input the second voltage-controlled feedback frequency to the frequency and phase detector.

[0008] In a second aspect, embodiments of the present invention provide a method based on an automatic frequency calibration module, applied to the digital circuit based on the automatic frequency calibration module described in the first aspect, the method comprising: Enable the phase-locked loop, enable the automatic frequency calibration module, and initialize the preset target value; Based on any voltage-controlled frequency output by the pressure cavity oscillator, the first frequency divider performs frequency division processing on the acquired voltage-controlled frequency to obtain the first voltage-controlled feedback frequency. The synchronous sampling processing unit acquires the first voltage-controlled feedback frequency and an asynchronous counting window generated based on the reference frequency. Based on the asynchronous counting window, the rising edge of the first voltage-controlled feedback frequency is counted to obtain a count value. The calculation and comparison processing unit acquires the count value and the target value. The count value is subtracted from the target value to obtain a count difference. When the count difference is equal to zero, or when the absolute value of the count difference is the minimum value among all the count differences, the sub-band frequency control word corresponding to the count difference is determined as the optimal sub-band frequency control word. The optimal sub-band frequency control word is output to the voltage-controlled oscillator, and the voltage-controlled oscillator is configured based on the optimal sub-band frequency control word to control the start of the phase-locked loop.

[0009] According to some embodiments of the present invention, the automatic frequency calibration module further includes: a state machine control unit, which is communicatively connected to the synchronous sampling counting unit and the calculation comparison processing unit, and is used to control the synchronous sampling counting unit and the calculation comparison processing unit; and a timing generation unit, which is communicatively connected to the state machine control unit, which is used to process the acquired reference frequency to generate a runtime sequence, and input the runtime sequence to the state machine control unit. The runtime sequence includes the asynchronous counting window, the comparison window, and the reset window, and is used to instruct the state machine control unit to perform a state transition. Specifically, when the state machine control unit acquires the comparison window, it controls the calculation comparison processing unit to compare the target value and the count value, and obtains the count difference based on the target value and the count value; when the state machine control unit acquires the reset window, it controls the counter of the synchronous sampling counting unit to reset. Before the synchronous sampling processing unit acquires the first voltage-controlled feedback frequency and the asynchronous counting window generated based on the reference frequency, the method further includes: The timing generation unit acquires the reference frequency, generates the runtime timing based on the reference frequency, and sends the runtime timing to the state machine control unit; When the state machine control unit acquires the asynchronous counting window, the state machine control unit enters the counting state and controls the synchronous sampling counting unit to sample and count the voltage control frequency based on the asynchronous counting window to obtain the count value. When the state machine control unit acquires the comparison window, the state machine control unit enters the comparison state, controls the calculation comparison processing unit to compare the count value and the target value, and controls the calculation comparison processing unit to output the count difference based on the count value and the target value; When the state machine control unit acquires the reset window, the state machine control unit enters the reset state and controls the counter of the synchronous sampling counting unit to be cleared and reset.

[0010] According to some embodiments of the present invention, after the calculation and comparison processing unit obtains the count value and the target value, the method further includes: The comparison window is obtained, and the count value is compared with the target value. When the count value is greater than the target value, the timing of the comparison window is set to high level, and the sub-band frequency control word is controlled to decrease. Alternatively, when the count value is less than the target value, the timing of the comparison window is set to low level, and the sub-band frequency control word is controlled to increase. The count difference is obtained by subtracting the target value from the count value. The absolute value of the count difference is compared with the candidate difference, wherein the candidate difference is the absolute value of the smallest count difference. When the absolute value of the count difference is less than the candidate difference, the absolute value of the count difference is updated to the latest candidate difference, and the sub-band frequency control word corresponding to the count difference is updated to the candidate sub-band frequency control word. Alternatively, when the absolute value of the count difference is greater than or equal to the candidate difference, the candidate sub-band frequency control word is determined as the optimal sub-band frequency control word, and the optimal sub-band frequency control word is output to the voltage-controlled oscillator.

[0011] According to some embodiments of the present invention, counting the rising edges of the first voltage-controlled feedback frequency based on the asynchronous counting window to obtain a count value includes: A first synchronous counting window is obtained by sampling the rising edge of the voltage-controlled frequency based on the asynchronous counting window, and a second synchronous counting window is obtained by sampling the rising edge of the reference frequency based on the first synchronous-asynchronous counting window. The counter of the synchronous sampling counting unit acquires the second synchronous counting window, and the voltage-controlled frequency is counted on the rising edge based on the second synchronous counting window to obtain the count value.

[0012] According to some embodiments of the present invention, the digital circuit further includes: a frequency and phase detector, a charge pump, and a low-pass filter connected in sequence, the low-pass filter being connected in communication with the voltage-controlled oscillator and the first frequency divider; and a second frequency divider, the second frequency divider being connected in communication with the output terminal of the cavity oscillator and the frequency and phase detector, the second frequency divider being used to divide the cavity frequency output by the cavity oscillator to obtain a second voltage-controlled feedback frequency, and inputting the second voltage-controlled feedback frequency to the frequency and phase detector; After enabling the phase-locked loop, the following is also included: The frequency and phase detector acquires the reference frequency and the second voltage-controlled feedback frequency, and generates a pulse signal based on the reference frequency and the second voltage-controlled feedback frequency, and inputs the pulse signal to the charge pump; The charge pump acquires the pulse signal, converts the pulse signal into a current pulse, and inputs the current pulse to the low-pass filter; The low-pass filter filters the current pulse and inputs the filtered current pulse to the pressure cavity oscillator, which outputs the voltage-controlled frequency. The second frequency divider acquires the voltage-controlled frequency, performs frequency division processing on the voltage-controlled frequency to obtain a new second voltage-controlled feedback frequency, and inputs the new second voltage-controlled feedback frequency to the frequency and phase detector.

[0013] Thirdly, embodiments of the present invention provide an apparatus based on an automatic frequency calibration module, including at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, the instructions being executed by the at least one control processor to enable the at least one control processor to perform the method based on the automatic frequency calibration module as described in the second aspect above.

[0014] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer-executable instructions for performing the method based on the automatic frequency calibration module as described in the second aspect above.

[0015] According to an embodiment of the present invention, a digital circuit based on an automatic frequency calibration module includes a phase-locked loop (PLL) and an automatic frequency calibration module. The PLL includes a cavity oscillator and a first frequency divider that are communicatively connected. The first frequency divider is used to divide the voltage-controlled frequency output by the cavity oscillator to obtain a first voltage-controlled feedback frequency. The automatic frequency calibration module is communicatively connected to both the cavity oscillator and the first frequency divider. This circuit has at least the following advantages: a synchronous sampling and counting unit, which is communicatively connected to the first frequency divider, is used to sample and count the first voltage-controlled feedback frequency output by the first frequency divider based on an acquired asynchronous counting window. The system comprises a count value, wherein the asynchronous counting window is generated based on a reference frequency; a calculation and comparison processing unit, which is communicatively connected to the synchronous sampling counting unit and the cavity oscillator, and is used to compare the count value with a preset target value, and obtain a count difference based on the count value and the target value, wherein the count difference is equal to the count value minus the target value. When the absolute value of the count difference is the minimum value, the sub-band frequency control word corresponding to the count difference is the optimal sub-band frequency control word. The calculation and comparison processing unit outputs the optimal sub-band frequency control word to the cavity oscillator, and the sub-band frequency control word is used to indicate the sub-band frequency configuration of the cavity oscillator. According to the technical solution of the present invention, automatic frequency calibration is achieved using digital circuits. The first pressure cavity feedback frequency is counted by a synchronous sampling counting unit to obtain a count value. The count difference obtained by the calculation and comparison processing unit is based on the count value and the target value to accurately select the optimal sub-band frequency control word from multiple sub-band frequency control words, thereby selecting the optimal sub-band frequency. This makes the frequency locked by the loop closer to the center of the pressure cavity oscillator's voltage control curve. While shortening the calibration time and improving the calibration accuracy, it also results in lower phase noise and less charge pump mismatch. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a digital circuit based on an automatic frequency calibration module provided in one embodiment of the present invention; Figure 2 This is a flowchart of a method based on an automatic frequency calibration module provided in another embodiment of the present invention; Figure 3 This is a flowchart of the automatic frequency calibration module provided in another embodiment of the present invention; Figure 4 This is the main timing diagram of the runtime timing output by the timing generation unit provided in another embodiment of the present invention; Figure 5 This is a state transition diagram of the state machine control unit when the calibration count is three, provided in another embodiment of the present invention; Figure 6 This is a schematic diagram of the synchronization processing of an asynchronous counting window provided in another embodiment of the present invention; Figure 7 This is a structural diagram of a device based on an automatic frequency calibration module provided in another embodiment of the present invention. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0019] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0020] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0021] This invention provides a digital circuit, method, apparatus, and medium based on an automatic frequency calibration module. The digital circuit includes a phase-locked loop (PLL) and an automatic frequency calibration module. The PLL includes a cavity oscillator and a first frequency divider, which are communicatively connected. The first frequency divider is used to divide the voltage-controlled frequency output by the cavity oscillator to obtain a first voltage-controlled feedback frequency. The automatic frequency calibration module is communicatively connected to both the cavity oscillator and the first frequency divider. The digital circuit based on the automatic frequency calibration module includes a synchronous sampling and counting unit, which is communicatively connected to the first frequency divider. The synchronous sampling and counting unit is used to calculate the first voltage-controlled feedback frequency output by the first frequency divider based on an acquired asynchronous counting window. The system samples and counts at a feed frequency to obtain a count value. The asynchronous counting window is generated based on a reference frequency. A calculation and comparison processing unit is communicatively connected to the synchronous sampling and counting unit and the cavity oscillator. The calculation and comparison processing unit compares the count value with a preset target value and obtains a count difference based on the count value and the target value. The count difference is equal to the count value minus the target value. When the absolute value of the count difference is the minimum value, the sub-band frequency control word corresponding to the count difference is the optimal sub-band frequency control word. The calculation and comparison processing unit outputs the optimal sub-band frequency control word to the cavity oscillator. The sub-band frequency control word is used to indicate the sub-band frequency configuration of the cavity oscillator. According to the technical solution of the present invention, automatic frequency calibration is achieved using digital circuits. The first pressure cavity feedback frequency is counted by a synchronous sampling counting unit to obtain a count value. The count difference obtained by the calculation and comparison processing unit is based on the count value and the target value to accurately select the optimal sub-band frequency control word from multiple sub-band frequency control words, thereby selecting the optimal sub-band frequency. This makes the frequency locked by the loop closer to the center of the pressure cavity oscillator's voltage control curve. While shortening the calibration time and improving the calibration accuracy, it also results in lower phase noise and less charge pump mismatch.

[0022] First, refer to Figure 1 , Figure 1 This is a schematic diagram of a digital circuit based on an automatic frequency calibration module according to an embodiment of the present invention. The digital circuit includes a phase-locked loop (PLL) and an automatic frequency calibration module. The PLL includes a cavity oscillator and a first frequency divider that are communicatively connected. The first frequency divider is used to divide the voltage-controlled frequency output by the cavity oscillator to obtain a first voltage-controlled feedback frequency. The automatic frequency calibration module is communicatively connected to both the cavity oscillator and the first frequency divider. The digital circuit based on an automatic frequency calibration module provided in this embodiment includes: The synchronous sampling and counting unit is communicatively connected to the first frequency divider. The synchronous sampling and counting unit is used to sample and count the first voltage-controlled feedback frequency output by the first frequency divider based on the acquired asynchronous counting window to obtain the count value. The asynchronous counting window is generated based on the reference frequency. The calculation and comparison processing unit is communicatively connected to the synchronous sampling and counting unit and the cavity oscillator. The calculation and comparison processing unit is used to compare the count value with the preset target value and obtain the count difference based on the count value and the target value. The count difference is equal to the count value minus the target value. When the absolute value of the count difference is the minimum value, the sub-band frequency control word corresponding to the count difference is the optimal sub-band frequency control word. The calculation and comparison processing unit outputs the optimal sub-band frequency control word to the cavity oscillator. The sub-band frequency control word is used to indicate the sub-band frequency configuration of the cavity oscillator.

[0023] It should be noted that the automatic frequency calibration module includes a synchronous sampling and counting unit and a calculation and comparison processing unit. The synchronous sampling and counting unit counts and samples the first voltage-controlled feedback frequency after the frequency division process to obtain the count value. The calculation and comparison processing unit performs data processing based on the count value and the preset target value to determine the optimal sub-band control word. The calculation and comparison processing unit then outputs the optimal automatic control word to the pressure cavity oscillator, thus completing the automatic calibration of the voltage-controlled frequency.

[0024] It should be noted that the synchronous sampling and counting unit is used to sample and count the voltage-controlled frequency input. The counting window is generated by a reference frequency, which is asynchronous with the voltage-controlled frequency, thus requiring synchronization.

[0025] It should be noted that the calculation and comparison processing unit is used to compare the count values ​​obtained from the synchronous sampling counting unit and finally output the optimal sub-band control word. During initialization, a target value needs to be set. Subsequently, during each calibration process, the difference between the count value and the target value needs to be calculated. Since negative numbers are not represented in digital circuit implementations, the count value needs to be compared with the target value first to determine the absolute value of the count difference. Only when the current count difference is less than the previous count difference is the sub-band control word corresponding to the current count difference output. When the current count difference is the minimum value, it indicates that the sub-band control word corresponding to the count difference is the optimal sub-band control word, and the optimal sub-band control word is output, ending the calibration process.

[0026] In existing technologies, phase-locked loops (PLLs) include voltage-controlled oscillators (VCOs). In a PLL, the output frequency range is related to the VCO's output frequency range and its voltage control gain. Increasing the VCO's voltage control gain degrades phase noise performance. If a single tuning curve covers the frequency range, a large tuning gain will occur, further worsening phase noise performance. Therefore, VCOs can employ multiple subbands to reduce tuning gain, effectively improving phase noise performance while covering a wide output range. However, before PLL locking, the VCO output subband needs to be selected. This process is called Automatic Frequency Calibration (AFC). AFC consists of two steps: sampling comparison and subband search. Sampling comparison refers to AFC acquiring and processing some loop parameters and comparing them with a reference signal to determine whether other subbands need to be selected. Common sampling comparison implementation paths include closed-loop voltage judgment processing and open-loop counting comparison processing. The closed-loop voltage judgment processing works as follows: after the PLL is locked, the control voltage at its VCO voltage control terminal is a fixed value. By judging whether the control voltage at the VCO voltage control terminal is within a certain range, it is determined whether the current sub-band meets the requirements and whether a new sub-band needs to be selected. The open-loop counting comparison processing works as follows: the AFC loop is disconnected from the PLL loop, and only the AFC loop works. The VCO control voltage is connected to a fixed voltage. By collecting feedback signals and comparing them with reference signals, the VCO sub-band search is controlled. Sub-band search algorithms are divided into linear and binary methods. The binary search method, also known as the binary search method, selects an intermediate sub-band each time by comparing the VCO output frequency with the reference frequency. If the frequency is higher, the intermediate sub-band is selected downwards using the binary search method; otherwise, the intermediate sub-band is selected upwards. However, traditional automatic frequency calibration methods are prone to problems such as inconsistencies in the parasitic layout of switched capacitor arrays, low layout utilization, and long calibration times.

[0027] This invention provides a digital circuit based on an automatic frequency calibration module, which can select the optimal sub-band. The optimal sub-band is the sub-band that makes the "loop-locked frequency closer to the center of the VCO voltage control curve". Based on the optimal sub-band control word output by the calculation and comparison processing unit, the sub-band frequency corresponding to the optimal sub-band control word makes the voltage control frequency output by the VCO closest to the reference frequency. This enables faster and more accurate automatic frequency calibration, shortens the required calibration time, and improves calibration efficiency.

[0028] Additionally, in one embodiment, reference is made to Figure 1 The automatic frequency calibration module also includes: The state machine control unit is communicatively connected to the synchronous sampling and counting unit and the calculation and comparison processing unit, and is used to control the synchronous sampling and counting unit and the calculation and comparison processing unit. The timing generation unit is communicatively connected to the state machine control unit. The timing generation unit processes the acquired reference frequency to generate the runtime sequence and inputs the runtime sequence to the state machine control unit. The runtime sequence includes an asynchronous counting window, a comparison window, and a reset window. The runtime sequence is used to instruct the state machine control unit to perform state transitions. When the state machine control unit acquires the comparison window, it controls the calculation and comparison processing unit to compare the target value and the count value, and obtains the count difference based on the target value and the count value. When the state machine acquires the reset window, the state machine control unit controls the synchronous sampling counting unit to reset the counter.

[0029] It should be noted that the automatic frequency calibration module internally includes a timing generation unit, a state machine control unit, a synchronous sampling and counting unit, and a calculation and comparison processing unit. The working principle of the automatic frequency calibration module is as follows: the timing generation unit obtains the reference frequency, processes the reference frequency to obtain the runtime timing, and sends the runtime timing to the state machine control unit; the state machine control unit performs running state transitions based on the runtime timing, and controls the synchronous sampling and counting unit to count and sample the divided-frequency voltage-controlled oscillator through different running states, and performs data processing with the calculation and comparison processing unit, and finally the calculation and comparison processing unit obtains the optimal sub-band control word and outputs it to the voltage-controlled oscillator.

[0030] It should be noted that the timing generation unit is used to process the input reference frequency to obtain the runtime timing, and then send the runtime timing to the state machine control unit. Figure 4 The main timing diagram output by the timing generation unit shows the timing of a complete calibration process of the automatic frequency calibration module, i.e., the runtime timing. It can be seen that the counting window (i.e., Figure 4 The length of the Win-Counter is 16 reference clocks (i.e., the reference clock is...). Figure 4 refClk in the comparison window (i.e. Figure 4 The Win-Cmp in the middle is 8 refClk, and the reset window (i.e. Figure 4 The Win-Rst in the system consists of 8 refClks, which are composed of a counting window, a comparison window, and a reset window. The timing sequence of a complete calibration process is given to the state machine control unit for state transition.

[0031] It should be noted that the state machine control unit is used to control the state transitions of the counting state, comparison state, reset state, and end state based on the acquired runtime sequence, thereby controlling the synchronous sampling counting unit and the calculation comparison processing unit.

[0032] It should be noted that, referring to Figure 5 , Figure 5 This is a state transition diagram for a state machine control unit with three calibration cycles provided in another embodiment of the present invention. Exemplarily, this embodiment performs three calibration processes. In practical applications, the number of calibration cycles can be adjusted according to the required number of calibrated sub-bands. State IDLE is the state that requires waiting after enabling AFC for 2 microseconds (µs). States PHW1, PHW2, and PHW3 are all counting states, with the timing provided by the counting window in the runtime sequence output by the timing generation unit. States PHC1, PHC2, and PHC3 are all comparison states, with the timing provided by the comparison window in the runtime sequence output by the timing generation unit. States PHR1, PHR2, and PHR3 are all reset states, with the timing provided by the reset window in the runtime sequence output by the timing generation unit. State DONE is the end state, used to output the end flag and the optimal sub-band control word.

[0033] It should be noted that when in counting mode, the automatic frequency calibration module controls the synchronous sampling counting unit to sample and count the input voltage-controlled frequency; when in comparison mode, the automatic frequency calibration module controls the calculation comparison processing unit to compare and process the count value from the synchronous sampling counting unit; and when in reset mode, the automatic frequency calibration module resets the counter in the synchronous sampling counting unit.

[0034] Additionally, in one embodiment, reference is made to Figure 1 It also includes: A frequency and phase detector, a charge pump, and a low-pass filter are connected in sequence for communication. The low-pass filter is connected in communication to the voltage-controlled oscillator and the first frequency divider. The second frequency divider is connected to the output of the pressure cavity oscillator and the frequency and phase detector respectively. The second frequency divider is used to divide the pressure cavity frequency output by the pressure cavity oscillator to obtain the second voltage-controlled feedback frequency, and input the second voltage-controlled feedback frequency to the frequency and phase detector.

[0035] It should be noted that, referring to Figure 1The digital circuit of the frequency synthesizer based on automatic frequency calibration consists of a phase frequency detector (PFD), a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), dividers (DIV), and an automatic frequency control circuit (AFC). The digital circuit works as follows: the reference frequency and the first VCO feedback frequency are input to the phase frequency detector. The output is connected to the charge pump, then the signal is sent to the low-pass filter, and then to the VCO to output the VCO frequency. The VCO frequency is divided by the first divider to obtain a new VCO feedback frequency, which is then returned to the phase detector. After the VCO frequency is divided by two, it and the reference frequency are simultaneously input to the automatic frequency control module. The automatic frequency control module outputs the calibrated optimal sub-band control word back to the VCO, thus completing the automatic calibration of the VCO frequency.

[0036] In addition, embodiments of the present invention provide a method based on an automatic frequency calibration module, applied to... Figure 1 The digital circuit based on the automatic frequency calibration module in the illustrated embodiment is shown with reference to... Figure 2 , Figure 2 A flowchart of a method based on an automatic frequency calibration module provided in another embodiment of the present invention is included, the method including but not limited to the following steps: S10 enables the phase-locked loop, enables the automatic frequency calibration module, and initializes the preset target value.

[0037] It should be noted that, referring to Figure 2 and Figure 3 , Figure 3 The flowchart of the automatic frequency calibration module provided in another embodiment of the present invention shows that after enabling the PLL, if the automatic frequency calibration module is not started, the PLL is directly turned on; or, if the automatic frequency calibration module is turned on, the target value is then initialized.

[0038] S20: Based on any voltage-controlled frequency output by the pressure cavity oscillator, the first frequency divider divides the acquired voltage-controlled frequency to obtain the first voltage-controlled feedback frequency. The synchronous sampling processing unit acquires the first voltage-controlled feedback frequency and the asynchronous counting window generated based on the reference frequency. Based on the asynchronous counting window, the rising edge of the first voltage-controlled feedback frequency is counted to obtain the count value. The calculation and comparison processing unit acquires the count value and the target value. The count value is subtracted from the target value to obtain the count difference. When the count difference is equal to zero, or when the absolute value of the count difference is the minimum value among all count differences, the sub-band frequency control word corresponding to the count difference is determined as the optimal sub-band frequency control word.

[0039] It should be noted that the automatic frequency calibration process includes at least one calibration cycle, which comprises three states: counting, comparing, and resetting. The number of calibration cycles is determined based on actual requirements, until the optimal sub-band frequency control word is output.

[0040] It should be noted that, for any given voltage control frequency, a first voltage control frequency and its corresponding counting difference are obtained based on the voltage control frequency. When the current counting difference is less than the candidate difference, i.e. less than the counting difference obtained in the previous round, the sub-band frequency makes the loop-locked frequency closer to the center of the voltage control curve. The candidate difference is continuously updated until the current counting difference is greater than or equal to the candidate difference, i.e., the sub-band frequency makes the loop-locked frequency farther from the center of the voltage control curve. In other words, the sub-band frequency control word corresponding to the candidate difference is determined to make the loop-locked frequency closer to the center of the voltage control curve, and the candidate sub-band frequency control word corresponding to the candidate difference is determined as the optimal sub-band frequency control word.

[0041] S30 outputs the optimal sub-band frequency control word to the voltage-controlled oscillator, configures the voltage-controlled oscillator based on the optimal sub-band frequency control word, and controls the phase-locked loop to start.

[0042] It should be noted that the cavity oscillator of this application adopts a multi-subband configuration and is configured based on the optimal subband frequency control word, so that the frequency locked by the loop is closest to the control center of the voltage control curve, thereby improving calibration accuracy and calibration speed.

[0043] In another embodiment, in step S20, before the synchronous sampling processing unit acquires the first voltage-controlled feedback frequency and the asynchronous counting window generated based on the reference frequency, the following steps are included, but are not limited to: S41, the timing generation unit obtains the reference frequency, generates the runtime timing based on the reference frequency, and sends the runtime timing to the state machine control unit; S42, when the state machine control unit acquires the asynchronous counting window, the state machine control unit enters the counting state and controls the synchronous sampling counting unit to sample and count the voltage control frequency based on the asynchronous counting window to obtain the count value; S43. When the state machine control unit obtains the comparison window, the state machine control unit enters the comparison state, controls the calculation and comparison processing unit to compare the count value with the target value, and controls the calculation and comparison processing unit to output a count difference based on the count value and the target value; S44. When the state machine control unit obtains the reset window, the state machine control unit enters the reset state, and controls the counter of the synchronous sampling counting unit to be cleared and reset.

[0044] It should be noted that referring to Figure 3 , the process of the automatic frequency calibration module is as follows: After enabling the PLL, if the automatic frequency calibration module is not started, the PLL is directly enabled; or, if the automatic frequency calibration module is enabled, the target value is then initialized. Then, the input voltage-controlled frequency is counted to obtain a count value. A difference calculation is performed based on the target value and the count value to obtain a count difference. The formula for the count difference is: △N = Nvco - Ntar, where △N is the count difference, Nvco is the count value, and Ntar is the target value; after obtaining the count difference, a minimum value comparison is performed on the count difference. The minimum value comparison formula is: min = (|△N| < min)? |△N| : min, that is, the absolute value of the count difference is compared with the minimum value among all the count differences; it is judged whether the count difference is less than 0. If the count difference is less than 0, the frequency is increased according to the binary search method; or, if the count difference is greater than 0, the frequency is decreased according to the binary search method. If the automatic frequency calibration ends, the sub-band control word corresponding to the smallest count difference is updated and output, that is, the optimal sub-band control word is output, and the PLL is started; or, if continuous calibration is still required, return to counting the voltage-controlled frequency and repeat the above process.

[0045] In addition, in one embodiment, in step S20, after the calculation and comparison processing unit obtains the count value and the target value, it specifically further includes but is not limited to the following steps: S51. Obtain the comparison window, compare the count value with the target value. When the count value is greater than the target value, set the timing of the comparison window to high level, and control the sub-band frequency control word to decrease; or, when the count value is less than the target value, set the timing of the comparison window to low level, and control the sub-band frequency control word to increase; S52. Subtract the target value from the count value to obtain a count difference, and compare the absolute value of the count difference with the candidate difference, where the candidate difference is the absolute value of the smallest count difference; S53. When the absolute value of the count difference is less than the candidate difference, update the absolute value of the count difference to the latest candidate difference, and update the sub-band frequency control word corresponding to the count difference to the candidate sub-band frequency control word; or, when the absolute value of the count difference is greater than or equal to the candidate difference, determine the candidate sub-band frequency control word as the optimal sub-band frequency control word, and output the optimal sub-band frequency control word to the voltage-controlled oscillator.

[0046] It should be noted that, referring to Figure 4 , Figure 4 The main timing diagram of the runtime sequence output by the timing generation unit provided in another embodiment of the present invention is shown. The calculation and comparison processing unit is used to compare the count values ​​obtained from the synchronous sampling counting unit and finally output the optimal sub-band control word. During initialization, a target value needs to be set. Subsequently, in each calibration process, the difference between the count value and the target value needs to be calculated. Since there is no negative number representation in digital circuit implementation, the count value needs to be compared with the target value first. If the count value is larger than the target value, the signal afcCmpH is set high, and the absolute value of the count difference is ΔN = Nvco - Ntar; if the count value is smaller than the target value, the signal afcCmpH is set low, and the absolute value of the count difference is ΔN = Ntar - Nvco. In each calibration process, according to the binary search method, when afcCmpH is high, the sub-band control word is lowered; when afcCmpH is low, the sub-band control word is raised. Next, a minimum difference comparison is required. Only when the current count difference is smaller than the previous count difference does it indicate that the sub-band control word is the optimal sub-band control word. The optimal sub-band control word is then output and the calibration process ends.

[0047] In another embodiment, in step S20, the rising edge of the first voltage-controlled feedback frequency is counted based on the asynchronous counting window to obtain a count value, which specifically includes, but is not limited to, the following steps: S61, the voltage-controlled frequency is sampled on the rising edge based on the asynchronous counting window to obtain the first synchronous counting window, and the reference frequency is sampled on the rising edge based on the first synchronous and asynchronous counting window to obtain the second synchronous counting window; S62, the counter of the synchronous sampling counting unit obtains the second synchronous counting window, and the voltage-controlled frequency is counted on the rising edge based on the second synchronous counting window to obtain the count value.

[0048] It should be noted that the counting window is generated based on a reference frequency. Since the reference frequency and the voltage-controlled frequency are asynchronous clocks, synchronization is required. Figure 6 , Figure 6 This is a schematic diagram of the synchronous processing of an asynchronous counting window provided in another embodiment of the present invention. vcoClk is the timing of the voltage-controlled frequency, and the counting window (i.e. Figure 6 The Win-Counter in the middle first performs a rising edge sampling to obtain the first synchronous counting window (i.e., Figure 6 In the sync0), then perform another rising edge sampling to obtain the second synchronization counting window (i.e. Figure 6In the process of sync1, the second synchronous counting window is ultimately used as the synchronized counting window. The counter in the synchronous sampling counting unit counts in the second synchronous counting window to obtain the count value, and then transmits the count value to the calculation and comparison processing unit. Upon reset, the counter in the synchronous sampling counting unit is cleared to zero for the next calibration count.

[0049] In another embodiment, after enabling the phase-locked loop in step S10, the following steps are included, but are not limited to: S11, the frequency and phase detector acquires the reference frequency and the second voltage-controlled feedback frequency, generates a pulse signal based on the reference frequency and the second voltage-controlled feedback frequency, and inputs the pulse signal to the charge pump; S12, the charge pump acquires the pulse signal, converts the pulse signal into a current pulse, and inputs the current pulse to the low-pass filter; S13, the low-pass filter filters the current pulse and inputs the filtered current pulse to the pressure cavity oscillator, which outputs the voltage-controlled frequency. S14, the second frequency divider obtains the voltage-controlled frequency, performs frequency division processing on the voltage-controlled frequency to obtain a new second voltage-controlled feedback frequency, and inputs the new second voltage-controlled feedback frequency to the frequency and phase detector.

[0050] It should be noted that the technical principle of using a frequency and phase detector, charge pump, low-pass filter, pressure cavity oscillator, and second frequency divider to output a second voltage-controlled feedback frequency to the frequency and phase detector can be referred to the above. Figure 1 The description of the illustrated embodiments will not be repeated here.

[0051] like Figure 7 As shown, Figure 7 This is a structural diagram of a device based on an automatic frequency calibration module according to an embodiment of the present invention. The present invention also provides a device based on an automatic frequency calibration module, comprising: The processor 701 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 702 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 702 can store operating digital circuits and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 702 and is called and executed by the processor 701 using the method based on the automatic frequency calibration module of the embodiments of this application. The input / output interface 703 is used to implement information input and output; The communication interface 704 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 705 transmits information between various components of the device (e.g., processor 701, memory 702, input / output interface 703, and communication interface 704); The processor 701, memory 702, input / output interface 703, and communication interface 704 are connected to each other within the device via bus 705.

[0052] This application embodiment also provides a storage medium, which is a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the above-described method based on the automatic frequency calibration module.

[0053] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0054] Those skilled in the art will understand that all or some of the steps and digital circuits in the methods disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0055] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A digital circuit based on an automatic frequency calibration module, characterized in that, The digital circuit includes a phase-locked loop (PLL) and an automatic frequency calibration module. The PLL includes a cavity oscillator and a first frequency divider that are communicatively connected. The first frequency divider is used to divide the voltage-controlled frequency output by the cavity oscillator to obtain a first voltage-controlled feedback frequency. The automatic frequency calibration module is communicatively connected to both the cavity oscillator and the first frequency divider. The automatic frequency calibration module includes: A synchronous sampling and counting unit is communicatively connected to the first frequency divider. The synchronous sampling and counting unit is used to sample and count the first voltage-controlled feedback frequency output by the first frequency divider based on the acquired asynchronous counting window to obtain a count value. The asynchronous counting window is generated based on a reference frequency. A calculation and comparison processing unit is communicatively connected to the synchronous sampling and counting unit and the cavity oscillator. The calculation and comparison processing unit is used to compare the count value with a preset target value, and obtain a count difference based on the count value and the target value. The count difference is equal to the count value minus the target value. When the absolute value of the count difference is the minimum value, the sub-band frequency control word corresponding to the count difference is the optimal sub-band frequency control word. The calculation and comparison processing unit outputs the optimal sub-band frequency control word to the cavity oscillator. The sub-band frequency control word is used to indicate the sub-band frequency configuration of the cavity oscillator.

2. The digital circuit based on the automatic frequency calibration module according to claim 1, characterized in that, The automatic frequency calibration module also includes: A state machine control unit is communicatively connected to the synchronous sampling and counting unit and the calculation and comparison processing unit, respectively. The state machine control unit is used to control the synchronous sampling and counting unit and the calculation and comparison processing unit. A timing generation unit is communicatively connected to the state machine control unit. The timing generation unit processes the acquired reference frequency to generate a runtime sequence and inputs the runtime sequence to the state machine control unit. The runtime sequence includes the asynchronous counting window, the comparison window, and the reset window. The runtime sequence is used to instruct the state machine control unit to perform a state transition. When the state machine control unit acquires the comparison window, the state machine control unit controls the calculation comparison processing unit to compare the target value and the count value, and obtain the count difference based on the target value and the count value; When the state machine acquires the reset window, the state machine control unit controls the counter of the synchronous sampling counting unit to reset.

3. The digital circuit based on the automatic frequency calibration module according to claim 1, characterized in that, Also includes: A frequency and phase detector, a charge pump, and a low-pass filter are sequentially connected in communication, and the low-pass filter is communicatively connected to the voltage-controlled oscillator and the first frequency divider; The second frequency divider is communicatively connected to the output terminal of the cavity oscillator and the frequency and phase detector, respectively. The second frequency divider is used to divide the cavity frequency output by the cavity oscillator to obtain the second voltage-controlled feedback frequency, and input the second voltage-controlled feedback frequency to the frequency and phase detector.

4. A method based on an automatic frequency calibration module, characterized in that, The method, applied to a digital circuit based on an automatic frequency calibration module as described in any one of claims 1 to 3, comprises: Enable the phase-locked loop, enable the automatic frequency calibration module, and initialize the preset target value; Based on any voltage-controlled frequency output by the pressure cavity oscillator, the first frequency divider performs frequency division processing on the acquired voltage-controlled frequency to obtain the first voltage-controlled feedback frequency. The synchronous sampling processing unit acquires the first voltage-controlled feedback frequency and an asynchronous counting window generated based on the reference frequency. Based on the asynchronous counting window, the rising edge of the first voltage-controlled feedback frequency is counted to obtain a count value. The calculation and comparison processing unit acquires the count value and the target value. The count value is subtracted from the target value to obtain a count difference. When the count difference is equal to zero, or when the absolute value of the count difference is the minimum value among all the count differences, the sub-band frequency control word corresponding to the count difference is determined as the optimal sub-band frequency control word. The optimal sub-band frequency control word is output to the voltage-controlled oscillator, and the voltage-controlled oscillator is configured based on the optimal sub-band frequency control word to control the start of the phase-locked loop.

5. The method based on the automatic frequency calibration module according to claim 4, characterized in that, The automatic frequency calibration module further includes: a state machine control unit, which is communicatively connected to the synchronous sampling counting unit and the calculation comparison processing unit, and is used to control the synchronous sampling counting unit and the calculation comparison processing unit; and a timing generation unit, which is communicatively connected to the state machine control unit, and is used to process the acquired reference frequency to generate a runtime sequence, and input the runtime sequence to the state machine control unit. The runtime sequence includes the asynchronous counting window, the comparison window, and the reset window, and is used to instruct the state machine control unit to perform state transitions. Specifically, when the state machine control unit acquires the comparison window, it controls the calculation comparison processing unit to compare the target value and the count value, and obtains the count difference based on the target value and the count value; when the state machine control unit acquires the reset window, it controls the counter of the synchronous sampling counting unit to reset. Before the synchronous sampling processing unit acquires the first voltage-controlled feedback frequency and the asynchronous counting window generated based on the reference frequency, the method further includes: The timing generation unit acquires the reference frequency, generates the runtime timing based on the reference frequency, and sends the runtime timing to the state machine control unit; When the state machine control unit acquires the asynchronous counting window, the state machine control unit enters the counting state and controls the synchronous sampling counting unit to sample and count the voltage control frequency based on the asynchronous counting window to obtain the count value. When the state machine control unit acquires the comparison window, the state machine control unit enters the comparison state, controls the calculation comparison processing unit to compare the count value and the target value, and controls the calculation comparison processing unit to output the count difference based on the count value and the target value; When the state machine control unit acquires the reset window, the state machine control unit enters the reset state and controls the counter of the synchronous sampling counting unit to be cleared and reset.

6. The method based on the automatic frequency calibration module according to claim 5, characterized in that, After the calculation and comparison processing unit obtains the count value and the target value, the method further includes: The comparison window is obtained, and the count value is compared with the target value. When the count value is greater than the target value, the timing of the comparison window is set to high level, and the sub-band frequency control word is controlled to decrease. Alternatively, when the count value is less than the target value, the timing of the comparison window is set to low level, and the sub-band frequency control word is controlled to increase. The count difference is obtained by subtracting the target value from the count value. The absolute value of the count difference is compared with the candidate difference, wherein the candidate difference is the absolute value of the smallest count difference. When the absolute value of the count difference is less than the candidate difference, the absolute value of the count difference is updated to the latest candidate difference, and the sub-band frequency control word corresponding to the count difference is updated to the candidate sub-band frequency control word. Alternatively, when the absolute value of the count difference is greater than or equal to the candidate difference, the candidate sub-band frequency control word is determined as the optimal sub-band frequency control word, and the optimal sub-band frequency control word is output to the voltage-controlled oscillator.

7. The method based on the automatic frequency calibration module according to claim 4, characterized in that, The count value is obtained by counting the rising edge of the first voltage-controlled feedback frequency based on the asynchronous counting window, including: A first synchronous counting window is obtained by sampling the rising edge of the voltage-controlled frequency based on the asynchronous counting window, and a second synchronous counting window is obtained by sampling the rising edge of the reference frequency based on the first synchronous-asynchronous counting window. The counter of the synchronous sampling counting unit acquires the second synchronous counting window, and the voltage-controlled frequency is counted on the rising edge based on the second synchronous counting window to obtain the count value.

8. The method based on the automatic frequency calibration module according to claim 4, characterized in that, The digital circuit further includes: a frequency and phase detector, a charge pump, and a low-pass filter connected in sequence, the low-pass filter being connected in communication with the voltage-controlled oscillator and the first frequency divider; and a second frequency divider, which is connected in communication with the output of the cavity oscillator and the frequency and phase detector, respectively. The second frequency divider is used to divide the cavity frequency output by the cavity oscillator to obtain a second voltage-controlled feedback frequency, and input the second voltage-controlled feedback frequency to the frequency and phase detector. After enabling the phase-locked loop, the following is also included: The frequency and phase detector acquires the reference frequency and the second voltage-controlled feedback frequency, and generates a pulse signal based on the reference frequency and the second voltage-controlled feedback frequency, and inputs the pulse signal to the charge pump; The charge pump acquires the pulse signal, converts the pulse signal into a current pulse, and inputs the current pulse to the low-pass filter; The low-pass filter filters the current pulse and inputs the filtered current pulse to the pressure cavity oscillator, which outputs the voltage-controlled frequency. The second frequency divider acquires the voltage-controlled frequency, performs frequency division processing on the voltage-controlled frequency to obtain a new second voltage-controlled feedback frequency, and inputs the new second voltage-controlled feedback frequency to the frequency and phase detector.

9. A device based on an automatic frequency calibration module, characterized in that, It includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the method based on the automatic frequency calibration module as described in any one of claims 4 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the method based on the automatic frequency calibration module as described in any one of claims 4 to 8.

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