Fractional phase-locked loop based on multi-path quantization noise compensation

Abstract

This invention discloses a fractional phase-locked loop (PLL) based on multi-path quantization noise compensation. It introduces a data synchronization circuit based on the falling edge of the reference clock, ensuring that the divider signals of all paths have reached steady state before the phase detector is triggered by the next rising edge of the PFD, thus completely eliminating dynamic timing interference in the mixed-signal path. By introducing a multi-path retimer with a sign bit, the compensable quantization noise range is expanded. The current-DAC type charge pump proposed in this invention adopts a charge pump architecture based on a source switch array and a static discharge current. The source switch array utilizes the low impedance characteristics of the source nodes of the current source transistors, significantly improving the switching speed and reducing the settling time. The static discharge current forces the loop to maintain a fixed non-zero phase offset in the locked state, permanently shifting the charge pump operating point out of the nonlinear region and deeply suppressing fractional spurious emissions.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency and analog integrated circuit design technology, specifically relating to a fractional phase-locked loop based on multipath quantization noise compensation. Background Technology

[0002] A phase-locked loop (PLL), a closed-loop control system based on phase feedback, is an indispensable core module for clock generation and frequency synthesis in modern electronic systems. Its basic function is to ensure that the output signal of the internal voltage-controlled oscillator (VCO) closely tracks an external reference clock in both frequency and phase. As wireless communication technologies evolve from 4G to higher standards such as 5G, 6G, and WiFi-7, communication frequency bands are continuously expanding into millimeter waves, and modulation methods are becoming increasingly complex (such as 1024-QAM and even 4096-QAM). This poses unprecedented challenges to the spectral purity, frequency coverage, and frequency hopping speed of frequency synthesizers.

[0003] Traditional integer-N phase-locked loops (PLLs) have inherent limitations in frequency planning: their output frequency resolution is strictly equal to the reference clock frequency. To achieve fine frequency steps, the reference frequency must be reduced, which forces a narrower loop bandwidth, leading to longer lock times and ineffective suppression of near-end phase noise of the VCO. In contrast, fractional-N PLLs successfully decouple frequency resolution from the reference frequency by introducing a dynamically changing division ratio (i.e., a non-integer average division ratio) in the feedback loop. This architectural advantage allows designers to use higher reference frequencies (e.g., tens or even hundreds of MHz) to achieve extremely wide loop bandwidth, enabling microsecond-level fast locking and excellent VCO noise suppression, while also achieving Hz-level ultra-high frequency resolution through Sigma-Delta modulation. This characteristic makes fractional-N PLLs the preferred solution for generating accurate local oscillator signals in radar detection, satellite communication, and high-density wavelength division multiplexing systems.

[0004] Despite the significant advantages mentioned above, the core component of the fractional-N phase-locked loop—the Sigma-Delta modulator (SDM)—inevitably introduces substantial quantization noise while implementing fractional frequency division. Although the SDM utilizes noise shaping techniques to push most of the quantization noise to higher frequencies, in practical analog circuit implementations, due to non-ideal factors (such as the nonlinearity of the power factor distribution (PFD) and the CP), this noise often folds or leaks, leading to the deterioration of the following two key performance indicators: Fractional spurs: Due to nonlinearity or periodic interference in the circuit, quantization noise accumulates at a fractional frequency offset at the output, forming discrete spurious components. These spurs are very likely to fall into adjacent channels, violate the spectral mask, or mix with interference signals at the receiver, severely reducing the receiver's signal-to-interference-plus-noise ratio (SINR) and sensitivity.

[0005] Phase noise: In high-order modulation systems, the integral phase noise of the local oscillator signal directly determines the system's error vector magnitude (EVM). Any rise in the noise floor caused by charge pump nonlinearity or quantization noise leakage will compress the signal's constellation diagram space, leading to an increase in the communication bit error rate.

[0006] To suppress this noise, the industry has widely adopted quantization noise cancellation technology based on digital time converters (DTC). Its basic principle is to control the delay of the phase detector input signal in real time according to the quantization error, so that the phase detector sees a signal that is approximately free of quantization noise. However, DTC is affected by the phase-time transformer (PVT), and its time delay and linearity are often uncertain, requiring complex on-chip background gain domain nonlinear calibration. Furthermore, in wideband charge pump phase-locked loops (CP-PLLs), DTC suffers from insufficient accuracy and difficulty in error extraction. Therefore, the most suitable technology for CP-PLLs is currently a multi-path quantization noise compensation technique. This technique utilizes multiple parallel frequency-phase detector (PFD) and charge pump (CP) paths, and achieves quantization noise cancellation in the analog domain by weighted summation of the quantization error. However, existing multi-path CP-PLLs suffer from problems such as low compensation bit depth, insufficient charge pump linearity, and complex control timing. Therefore, designing a high-performance phase-locked loop that can simultaneously solve the charge pump nonlinearity problem, has sufficient compensation accuracy, and does not require complex background calibration algorithms is a pressing need in the industry. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a fractional phase-locked loop (PLL) based on multipath quantization noise compensation. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a fractional phase-locked loop based on multipath quantization noise compensation, comprising: NP+S multimode divider is used to control the division ratio signal N. div Under the control of [the system], the dynamic frequency division ratio is switched according to the signal CLK output by the voltage-controlled oscillator. vco Output frequency divider signal CLK div ; The digital control module is used to obtain the frequency division ratio control signal N based on the fractional frequency control word and the externally input integer frequency control word. divThe fractional frequency control word is processed to obtain the symbol control code, phase selection code, and LSB extension code for quantization noise compensation. The data synchronization circuit is used to globally resample the symbol control code, phase selection code and LSB extension code according to the reference clock, and output the synchronized symbol control code, synchronized phase selection code and synchronized LSB extension code. A multipath retimer with a signed bit, used based on the CLK signal. vco For the frequency division signal CLK div Continuous sampling is performed to generate a leading phase, a reference phase, and a lagging phase with a voltage-controlled oscillator period time difference. Under the control of the synchronized symbol control code, a reference signal and a dynamic signal are generated based on the leading phase, the reference phase, and the lagging phase. Based on multiple parallel path selections, under the control of the synchronized phase selection code and the synchronized LSB extension code, a time-domain modulated feedback signal DIV[4:0] and an LSB bit signal DIV are generated based on the reference signal and the dynamic signal. LSB ; A PFD array is used to adjust the feedback signal DIV[4:0] and the LSB bit signal DIV based on a reference clock. LSB Phase detection is performed separately to generate corresponding feedback pulses UP / DN[4:0] and LSB pulses UP / DN. LSB ; A weight allocation circuit is used to convert the binary weight signal UP / DN[4:2] in the feedback pulse UP / DN[4:0] into the physical domain equal weight drive signals MSB_UP[6:0] and MSB_DN[6:0] according to the pre-allocated weights; The current-DAC type charge pump adopts a charge pump architecture based on a source switch array and static discharge current. It is used to generate a charge pump based on a reference current, according to the feedback pulse UP / DN[1:0] and LSB pulse UP / DN. LSB Equal-weighted driving signals MSB_UP[6:0] and MSB_DN[6:0] drive the charge pump current unit in the source switch array respectively, and generate a compensated analog current under the compensation of external UP_Bleed / DN_Bleed[6:0] signals; the source switch array is divided into three regions according to the weights; The low-pass filter smooths the integrated, compensated analog current into a stable tuned voltage. A voltage-controlled oscillator, under the control of a tuning voltage, generates an output signal V of a specific frequency. OUT .

[0008] In one embodiment of the present invention, the digital control module includes: The Delta-Sigma modulation link and the quantization error processing link are set sequentially; The Delta-Sigma modulation link is used to generate a modulation signal based on a fractional frequency control word, and to add the modulation signal to an externally input integer frequency control word to obtain the division ratio control signal N. div ; The quantization error processing link is used to calculate the difference between the modulation signal and the fractional frequency control word to obtain the instantaneous frequency error, and convert the instantaneous frequency error into an instantaneous phase error; the instantaneous phase error is separated into high-order main data and low-order residual data, the low-order residual data is quantized twice to obtain a carry signal, the carry signal is injected back and superimposed on the high-order main data to generate an error signal that has undergone mean conservation processing; the highest bit of the error signal is extracted as the symbol control code, and the low-order bits are processed by absolute value to obtain the phase selection code and LSB extension code.

[0009] In one embodiment of the present invention, the data synchronization circuit includes: Reference clock inverter and parallel-configured first D flip-flop, second D flip-flop, and third D flip-flop; The reference clock inverter reverses the reference clock to obtain an inverted reference clock. The first D flip-flop has a phase selection code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized phase selection code output at its Q terminal. The second D flip-flop has an LSB spreading code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized LSB spreading code output at its Q terminal. The third D flip-flop has a symbol control code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized symbol control code output at its Q terminal.

[0010] In one embodiment of the present invention, the signed multipath retimer includes: Shift register chain, delay selection logic, and parallel output retiming array; The shift register chain is in signal CLK vco Driven by the frequency division signal CLK div Continuous sampling is performed to generate a leading phase, a reference phase, and a lagging phase with a time difference of one voltage-controlled oscillator period; The delay selection logic generates a reference signal and a dynamic signal through two multiplexers; the reference signal is fixedly connected to the reference phase, and the dynamic signal dynamically switches between the leading phase and the lagging phase according to the state of the synchronized symbol control code. The parallel output retiming array comprises multiple sets of parallel selection paths and output D flip-flop arrays. Each parallel selection path selects between a reference signal and a dynamic signal based on the logic state of the synchronized phase selection code or the synchronized LSB extension code, and outputs a corresponding gating signal. The gating signals corresponding to all parallel selection paths are processed by a single stage of signal CLK. vco The output D flip-flop array is uniformly retimed to generate a time-domain modulated feedback signal DIV[4:0] and LSB bit signal DIV. LSB .

[0011] In one embodiment of the present invention, the weight allocation circuit is composed of a buffer chain of cascaded inverters; the weight allocation circuit fans out the feedback pulse UP / DN[4] representing weight 4 and converts it into an equal weight driving signal MSB_UP / MSB_DN[6:3] to drive 4 physical channels; it fans out the feedback pulse UP / DN[3] representing weight 2 and converts it into an equal weight driving signal MSB_UP / MSB_DN[2:1] to drive 2 physical channels; it fans out the feedback pulse UP / DN[2] representing weight 1 and converts it into an equal weight driving signal MSB_UP / MSB_DN[0] to drive 1 physical channel.

[0012] In one embodiment of the present invention, the current DAC type charge pump includes: Bias generation circuit, source switching current array, and programmable discharge current array; The bias generation circuit generates a dynamically adjusted P-type bias voltage VBU and a stable N-type bias voltage VBD based on the reference current and operational amplifier feedback-assisted bias. The source switch current array is divided into three regions according to weights. Under the control of the P-type bias voltage VBU and the N-type bias voltage VBD, the current is sequentially affected by the LSB pulse UP / DN. LSB Under the control of feedback pulses UP / DN[1:0] and equal-weighted drive signals MSB_UP / DN[6:0], analog current is generated; The programmable current discharge array compensates for the analog current under the control of the external UP_Bleed / DN_Bleed[6:0] signals to generate a compensated analog current.

[0013] In one embodiment of the present invention, the bias generating circuit includes: MOSFET M0, MOSFET M1, MOSFET M2, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, operational amplifier AMP1, operational amplifier AMP2, first capacitor C1, second capacitor C2, first external filter capacitor and second external filter capacitor; The source of the MOS transistor M0 is connected to the first end of the resistor R1, the gate is connected to the gate of the MOS transistor M1, and the drain is connected to its own gate and connected to a reference current. The source of the MOS transistor M1 is connected to the first end of the resistor R2, the gate is connected to the non-inverting input of the operational amplifier AMP2, and the drain is connected to the drain of the MOS transistor M2. The source of the MOS transistor M2 is connected to the second end of the resistor R3, the gate is connected to the output of the operational amplifier AMP1, and the drain is connected to the non-inverting input of the operational amplifier AMP1. The second terminal of the resistor R1 is grounded; The second terminal of the resistor R2 is grounded; The first terminal of the resistor R3 is connected to the voltage VDD; The first end of the resistor R4 is connected to the output of the operational amplifier AMP1, and the second end is connected to the first external filter capacitor, serving as the first output of the bias generation circuit. The first end of the resistor R5 is connected to the output of the operational amplifier AMP2, and the second end is connected to the second external filter capacitor, serving as the second output of the bias generation circuit. The inverting input terminal of the operational amplifier AMP1 is connected to the output terminal of the source switching current array; The inverting input terminal of the operational amplifier AMP2 is connected to its own output terminal; The first terminal of the first capacitor C1 is grounded, and the second terminal is connected to the second terminal of the resistor R4. The first terminal of the second capacitor C2 is grounded, and the second terminal is connected to the second terminal of the resistor R5.

[0014] In one embodiment of the present invention, the source switch current array is divided into three regions according to weights, namely: high-bit thermometer code array, low-bit binary code array and LSB extension branch; The high-level thermometer code array contains 7 identical physical units connected in parallel; the resistance values ​​of the first source resistor R01 and the second source resistor R02 in each physical unit are half of the first reference resistor and the second reference resistor, respectively, and the size of the current source MOS transistor in the physical unit is twice that of the reference current source transistor. The low-order binary code array contains branches with weights of 2mA and 1mA. The first resistor R11 and the second resistor R12 of the branch with a weight of 2mA have the resistance values ​​of the first reference resistor and the second reference resistor, respectively. The third resistor R13 and the fourth resistor R14 of the branch with a weight of 1mA have the resistance values ​​of twice the first reference resistor and the second reference resistor, respectively. The current source MOSFET in the branch with a weight of 2mA has the same size as the reference current source MOSFET, and the current source MOSFET in the branch with a weight of 1mA has half the size of the reference current source MOSFET. The resistance values ​​of the fifth resistor R15 and the sixth resistor R16 in the LSB extension branch are twice those of the first reference resistor and the second reference resistor, respectively. The size of the current source MOSFET in the branch is half that of the reference current source MOSFET.

[0015] In one embodiment of the present invention, the seven parallel identical physical units are designed in a uniform spatial distribution pattern of [6, 2, 4, 0, 3, 1, 5]; wherein, the physical units with index numbers 6, 5, 4, 3 correspond to the weighted driving signals MSB_UP / MSB_DN[6:3], the physical units with index numbers 2, 1 correspond to the equal weighted driving signals MSB_UP / MSB_DN[2:1], and the physical unit with index number 0 corresponds to the equal weighted driving signals MSB_UP / MSB_DN[0].

[0016] In one embodiment of the present invention, the programmable discharge current array consists of 7 groups of binary weighted current sources controlled by external UP_Bleed / DN_Bleed[6:0] signals, supporting static current regulation from microampere to milliampere level.

[0017] The beneficial effects of this invention are: In the solution provided by this invention, addressing the contradiction between compensation accuracy and circuit complexity in multi-path quantization noise compensation, the proposed digital control module employs a Delta-Sigma modulation link. Leveraging the characteristic that the quantization noise distribution converges within the -1 to 1 TVCO period, the design difficulty of compensation is reduced. Regarding bit width optimization, an amplitude + sign compensation method is adopted, achieving optimal noise suppression while keeping the hardware scale within an engineering-acceptable range. While extracting high-order quantization errors, low-order residual data, which is usually discarded, is retained and subjected to secondary quantization. The quantized output is reinjected and superimposed onto the high-order data, thereby averaging the truncation error over time. This invention introduces a data synchronization circuit based on the falling edge of the reference clock, ensuring that the frequency divider signals of all paths have reached steady state before the phase detector is triggered by the next rising edge of the PFD, completely eliminating dynamic timing interference in the mixed-signal path. By introducing a multi-path retimer with a sign bit, the compensable quantization noise range is expanded. This invention introduces an additional independent LSB compensation path into the current DAC type charge pump to ensure that the compensation charge accurately covers the error range under all quantization boundary conditions. The current DAC type charge pump adopts a charge pump architecture based on a source switch array and a static discharge current. The source switch array utilizes the low impedance characteristics of the source node of the current source transistor, significantly improving the switching speed and reducing the settling time. The static discharge current forces the loop to maintain a fixed non-zero phase offset in the locked state, permanently shifting the charge pump operating point out of the nonlinear region and deeply suppressing fractional spurious emissions. Since the discharge current is a constant DC, there is no periodic switching action, thus achieving linearity optimization with "zero switching noise". Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall architecture of a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a digital control module in a fractional phase-locked loop based on multipath quantization noise compensation, provided in an embodiment of the present invention. Figure 3 The circuit structure diagram of a data synchronization circuit in a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention; Figure 4 The circuit diagram of a multipath re-timer with a signed bit in a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention; Figure 5 A comparison diagram of the multipath compensation effect of a fractional phase-locked loop based on multipath quantization noise compensation at different bit values ​​provided in an embodiment of the present invention; Figure 6A timing diagram of a fractional phase-locked loop based on multipath quantization noise compensation using the falling edge of a reference clock to synchronize data is provided in an embodiment of the present invention. Figure 7 The circuit structure diagram of a weight allocation circuit in a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention; Figure 8 The circuit diagram of a current DAC type charge pump in a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention; Figure 9 A transient waveform diagram of VCTRL in a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention; Figure 10 The wide span diagram of the PLL locked in a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention. Figure 11 The Narrow Span spectrum of a fractional phase-locked loop based on multipath quantization noise compensation provided in an embodiment of the present invention; Figure 12 A comparison of phase noise spectra before and after Bleeding for fractional phase-locked loop (PLL) compensation based on Simulink behavioral-level modeling and multipath quantization noise compensation provided in an embodiment of the present invention. Figure 13 This invention provides a fractional phase-locked loop (PLL) based on multipath quantization noise compensation, with PLL compensation based on transistor-level simulation and a comparison of spectra before and after Bleeding. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] This invention provides a fractional phase-locked loop based on multipath quantization noise compensation, such as... Figure 1 As shown, it may include: NP+S multimode divider is used to control the division ratio signal N. div Under the control of [the system], the dynamic frequency division ratio is switched according to the signal CLK output by the voltage-controlled oscillator. vco Output frequency divider signal CLK div ; The digital control module is used to obtain the frequency division ratio control signal N based on the fractional frequency control word and the externally input integer frequency control word. div The fractional frequency control word is processed to obtain the symbol control code, phase selection code, and LSB extension code for quantization noise compensation. The data synchronization circuit is used to globally resample the symbol control code, phase selection code and LSB extension code according to the reference clock, and output the synchronized symbol control code, synchronized phase selection code and synchronized LSB extension code. A multipath retimer with a signed bit, used based on the CLK signal. vco For the frequency division signal CLK div Continuous sampling is performed to generate a leading phase, a reference phase, and a lagging phase with a voltage-controlled oscillator period time difference. Under the control of the synchronized symbol control code, a reference signal and a dynamic signal are generated based on the leading phase, the reference phase, and the lagging phase. Based on multiple parallel path selections, under the control of the synchronized phase selection code and the synchronized LSB extension code, a time-domain modulated feedback signal DIV[4:0] and an LSB bit signal DIV are generated based on the reference signal and the dynamic signal. LSB ; A PFD array is used to adjust the feedback signal DIV[4:0] and the LSB bit signal DIV based on a reference clock. LSB Phase detection is performed separately to generate corresponding feedback pulses UP / DN[4:0] and LSB pulses UP / DN. LSB ; A weight allocation circuit is used to convert the binary weight signal UP / DN[4:2] in the feedback pulse UP / DN[4:0] into the physical domain equal weight drive signals MSB_UP[6:0] and MSB_DN[6:0] according to the pre-allocated weights; The current-DAC type charge pump adopts a charge pump architecture based on a source switch array and static discharge current. It is used to generate a charge pump based on a reference current, according to the feedback pulse UP / DN[1:0] and LSB pulse UP / DN. LSB Equal-weighted driving signals MSB_UP[6:0] and MSB_DN[6:0] drive the charge pump current units in the source switch array respectively, and generate compensated analog currents under the compensation of external UP_Bleed / DN_Bleed[6:0] signals; the source switch array is divided into three regions according to the weights; The low-pass filter smooths the integrated, compensated analog current into a stable tuned voltage. A voltage-controlled oscillator, under the control of a tuning voltage, generates an output signal V of a specific frequency. OUT .

[0021] For ease of understanding, the following describes each module of the fractional phase-locked loop based on multipath quantization noise compensation provided in the embodiments of the present invention.

[0022] The NP+S multimode frequency divider uses the division ratio control signal N. div Under the control of [the system], the dynamic frequency division ratio is switched according to the signal CLK output by the voltage-controlled oscillator.vco Output frequency divider signal CLK div .

[0023] The digital control module drives the NP+S multimode divider to dynamically switch the division ratio. At this time, the divider outputs the signal CLK. div The quantization noise information is carried in the time domain and can be expressed as EQ[n] / 2. 25 ×TVCO, in its physical sense, represents the zero-delay signal CLK in multipath retimers. DIG The rising edge of the output relative to the reference clock F REF The time deviation of the rising edge. Here, EQ represents the instantaneous phase error generated by the digital control module, n represents the number of bits, and TVCO represents the period of the voltage-controlled oscillator.

[0024] Digital control modules, such as Figure 2 As shown, it may include: The Delta-Sigma modulation link and the quantization error processing link are set sequentially; The Delta-Sigma modulation link is used to generate a modulation signal based on a fractional frequency control word. This modulation signal is then added to an externally input integer frequency control word to obtain the division ratio control signal N. div ; The quantization error processing link is used to calculate the difference between the modulated signal and the fractional frequency control word to obtain the instantaneous frequency error, which is then converted into an instantaneous phase error. The instantaneous phase error is separated into high-order main data and low-order residual data. The low-order residual data is quantized twice to obtain a carry signal, which is then injected back and superimposed onto the high-order main data to generate an error signal that has undergone mean conservation processing. The highest bit of the error signal is extracted as the symbol control code, and the low-order bits are processed by absolute value to obtain the phase selection code and LSB extension code.

[0025] Specifically, the digital control module, as the all-digital operation core of the phase-locked loop, mainly consists of two parts: a Delta-Sigma modulation link and a quantization error processing link. First, in the Delta-Sigma modulation link, the MASH1-1 modulator receives a 25-bit fractional frequency control word (FCW) and generates a 3-bit integer modulation signal N. frac This signal is related to the externally input integer frequency control word N. int The summation generates the final division ratio control signal N that drives the NP+S multimode divider. div To achieve high-precision quantization noise compensation, the quantization error processing link first calculates N. fracThe difference between the frequency error and the FCW is used to obtain the instantaneous frequency error. This error is then integrated by the accumulator ACC to convert the instantaneous frequency error in the frequency domain into a 26-bit instantaneous phase error signal EQ that represents the time domain deviation. To address the static error problem caused by traditional truncation operations, the error signal EQ is separated into high 6 bits of main data and low 20 bits of residual data. The low 20 bits of data are fed into a first-order Delta-Sigma modulator (MASH1) for secondary quantization. The output 1-bit carry signal is reinjected and superimposed on the high bits to generate a 7-bit error signal EQ_quan after mean conservation processing. Subsequently, EQ_quan is fed in parallel into the absolute value operation unit (ABS) and the symbol extraction unit (SIGN) to parse out the 1-bit symbol control code SIGN_Code, the LSB extension code LSB_Code, and the 5-bit phase selection code PSEL_Code[4:0].

[0026] Data synchronization circuits, such as Figure 3 As shown, it may include: Reference clock inverter and parallel-configured first D flip-flop, second D flip-flop, and third D flip-flop; The reference clock inverter reverses the reference clock to obtain an inverted reference clock. The D terminal of the first D flip-flop is connected to the phase selection code, the clock terminal is connected to the inverted reference clock, and the Q terminal outputs the synchronized phase selection code. The D terminal of the second D flip-flop is connected to the LSB spreading code, the clock terminal is connected to the inverted reference clock, and the Q terminal outputs the synchronized LSB spreading code. The third D flip-flop has a symbol control code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized symbol control code output at its Q terminal.

[0027] The data synchronization circuit mainly consists of a reference clock inverter and multiple sets of parallel D flip-flops. It uses the inverted reference clock signal (i.e., the falling edge of the reference clock) to globally resample the symbol control code, phase selection code, and LSB extension code from the digital domain. This mechanism ensures that all control data are established and stabilized half a reference clock cycle before the PFD phase detection action, thereby effectively maximizing the timing margin of the digital-to-analog interface and avoiding metastability risks.

[0028] A multipath re-timer with a signed bit, such as Figure 4 As shown, it may include: Shift register chain, delay selection logic, and parallel output retiming array; The shift register chain at signal CLK vco Driven by the frequency division signal CLK div Continuous sampling is performed to generate a leading phase, a reference phase, and a lagging phase with a time difference of one voltage-controlled oscillator period; The delay selection logic generates a reference signal and a dynamic signal through two multiplexers; the reference signal is fixedly connected to the reference phase, and the dynamic signal dynamically switches between the leading phase and the lagging phase according to the state of the synchronized symbol control code. The parallel output retiming array comprises multiple sets of parallel selection paths and output D flip-flop arrays. Each parallel selection path selects between a reference signal and a dynamic signal based on the logic state of the synchronized phase selection code or the synchronized LSB extension code, and outputs the corresponding gating signal. The gating signals corresponding to all parallel selection paths are processed by a single stage of signal CLK. vco The output D flip-flop array is uniformly retimed to generate a time-domain modulated feedback signal DIV[4:0] and LSB bit signal DIV. LSB .

[0029] Specifically, the signed multipath retimer is mainly composed of the signal CLK. vco The multipath retimer consists of a shift register chain, delay selection logic, and a parallel output retiming array. It first utilizes the high-frequency clock signal CLK. vco The three cascaded D flip-flops drive the frequency divider signal CLK. div Continuous sampling generates three timing taps with a VCO cycle time difference: a leading phase DELAY-1, a reference phase DELAY0, and a lagging phase DELAY1. Subsequently, the intermediate stage delay selection logic generates a reference signal SEL0 and a dynamic signal SEL1 through two multiplexers. SEL0 is fixedly connected to DELAY0, while SEL1 switches between DELAY-1 and DELAY1 based on the state of the symbol control code SIGN, thus achieving lead or lag timing pre-selection at the physical layer. At the output stage, the parallel output retiming array includes corresponding to DIV[4:0] and DIV[4:0]. LSB The system employs a multi-group parallel selection path and an output D flip-flop array. Each parallel selection path selects between a reference signal and a dynamic signal based on the logic state of the synchronized phase selection code or the synchronized LSB spreading code, outputting a corresponding gating signal. Specifically, the zero-delay reference signal CLK... DIG It is hardwired to always select SEL0 as the timing reference. The strobe signals corresponding to all parallel selection paths eventually pass through a single stage controlled by CLK. vco The output D flip-flop array driven by the circuit is uniformly retiming. This circuit structure ensures that the edges of all clock signals fed back to the PFD are strictly aligned with the VCO clock grid. It not only achieves precise time modulation of ±Tvco through digital logic to match the quantization characteristics of MASH 1-1, but also effectively eliminates transient glitches and timing jitter introduced by the switching of the preceding logic stage through the final stage retiming, ensuring high accuracy and low noise characteristics in the subsequent analog phase detection process.

[0030] Understandably, to address the problems of insufficient bit width, incomplete boundary coverage, and difficulty in aligning digital and analog timing in existing quantization noise compensation schemes, this invention provides a full-link multi-path quantization noise compensation architecture for simulation optimization. This architecture covers the entire link from quantization error extraction, encoding mapping, boundary extension, and digital-analog synchronization, as detailed below: Optimal bit width and sign bit control strategy: To address the trade-off between compensation accuracy and circuit complexity in multipath quantization noise compensation, this invention determines the optimal compensation strategy through system-level loop and nonlinear modeling. Regarding modulator selection, considering that high-order SDMs require excessively high compensation bit widths, leading to PFD / CP path redundancy, this invention selects the MASH 1-1 modulator, leveraging its characteristic that the quantization noise distribution converges within the -1 to 1 TVCO period, thus reducing the complexity of the compensation design. Regarding bit width optimization: based on... Figure 5 The comparison chart of multipath compensation effects of fractional phase-locked loops with different bit widths shows that when the compensation bit width is less than 5 bits, each additional bit brings about 3dB of quantization noise suppression; however, when the bit width exceeds 5 bits, the noise suppression gain tends to saturate due to factors such as nonlinear folding noise. Based on this, the present invention establishes a 5-bit amplitude + 1-bit sign compensation scheme, achieving optimal noise suppression while keeping the hardware scale within an engineering-acceptable range.

[0031] Fine-grained compensation based on residual bit modulation and LSB path spreading: To address the residual noise leakage and static DC offset issues caused by the direct truncation method used in traditional quantization noise extraction, this invention proposes an improved error processing mechanism. While extracting the high-order quantization error, it retains the low-order residual data that is usually discarded, feeding it into a first-order SDM modulator for secondary quantization. The modulator output is reinjected and superimposed onto the high-order data, thereby averaging the truncation error over time. Furthermore, to address the data dynamic range expansion caused by the superposition operation, this embodiment introduces an additional independent LSB compensation path in the charge pump array to ensure that the compensation charge accurately covers the error range under all quantization boundary conditions.

[0032] Half-cycle pre-established data synchronization mechanism based on the falling edge of the reference clock: To address the timing race risk between digital control logic and analog phase detection circuits, this invention employs a specific clock synchronization strategy. In conventional designs, the SDM modulation sequence and noise compensation code are typically updated by the rising edge of the divider feedback clock, and the phase detection operation of the PFD / CP also occurs at this time. This "simultaneous edge triggering" leads to severe digital-analog interface interference: while the analog circuit is performing precise phase sampling, the digital control code may be in the process of flipping and transitioning, introducing transient glitches or metastability, severely degrading phase detection accuracy. This invention utilizes the characteristic that the reference clock is aligned with the rising edge of the divider feedback clock in PLL locked state, and that the reference clock has a 50% duty cycle, to introduce a retiming stage based on the falling edge of the reference clock. All digital compensation codes are resampled via the falling edge of the reference clock before being sent to the multipath selector. This operation is equivalent to forcibly inserting a half-reference cycle setup time margin before the phase detection operation occurs, as shown in the timing diagram below. Figure 6 As shown. This ensures that when the phase detector is triggered by the next rising edge of the PFD, the divider signals of all paths have reached a steady state in advance, completely eliminating dynamic timing interference in the mixed-signal path.

[0033] The PFD array is based on a reference clock to feed back the feedback signal DIV[4:0] and the LSB bit signal DIV. LSB Phase detection is performed separately to generate corresponding feedback pulses UP / DN[4:0] and LSB pulses UP / DN. LSB .

[0034] Weighting circuit such as Figure 7 As shown, the circuit consists of a buffer chain composed of cascaded inverters; the weight allocation circuit adopts a fixed hard-wired topology: the feedback pulse UP / DN[4] representing weight 4 is fanned out and converted into an equal weight driving signal MSB_UP / MSB_DN[6:3] to drive 4 physical channels; the feedback pulse UP / DN[3] representing weight 2 is fanned out and converted into an equal weight driving signal MSB_UP / MSB_DN[2:1] to drive 2 physical channels; the feedback pulse UP / DN[2] representing weight 1 is fanned out and converted into an equal weight driving signal MSB_UP / MSB_DN[0] to drive 1 physical channel.

[0035] The weight allocation circuit, as the interface module connecting the high-order output of the multi-path PFD and the segmented charge pump array, is mainly responsible for converting the weight signal output by the PFD into parallel weight driving signals in the physical domain.

[0036] Current DAC type charge pump, such as Figure 8 As shown, it may include: Bias generation circuit, source switching current array, and programmable discharge current array; The bias generation circuit generates a dynamically adjusted P-type bias voltage VBU and a stable N-type bias voltage VBD based on the reference current and the operational amplifier feedback-assisted bias. The source switching current array is divided into three regions according to weights. Under the control of the P-type bias voltage VBU and the N-type bias voltage VBD, the current is sequentially applied by the LSB pulse UP / DN. LSB Under the control of feedback pulses UP / DN[1:0] and equal-weighted drive signals MSB_UP / DN[6:0], analog current is generated; The programmable bleed current array compensates for the analog current under the control of the external UP_Bleed / DN_Bleed[6:0] signals to generate the compensated analog current.

[0037] Bias generation circuit, such as Figure 8 As shown, it may include: MOSFET M0, MOSFET M1, MOSFET M2, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, operational amplifier AMP1, operational amplifier AMP2, first capacitor C1, second capacitor C2, first external filter capacitor and second external filter capacitor; The source of MOSFET M0 is connected to the first terminal of resistor R1, the gate is connected to the gate of MOSFET M1, and the drain is connected to its own gate and connected to a reference current. The source of MOSFET M1 is connected to the first terminal of resistor R2, the gate is connected to the non-inverting input terminal of operational amplifier AMP2, and the drain is connected to the drain of MOSFET M2. The source of MOSFET M2 is connected to the second terminal of resistor R3, the gate is connected to the output terminal of operational amplifier AMP1, and the drain is connected to the non-inverting input terminal of operational amplifier AMP1. The second terminal of resistor R1 is grounded; The second terminal of resistor R2 is grounded; The first terminal of resistor R3 is connected to voltage VDD; The first end of resistor R4 is connected to the output of operational amplifier AMP1, and the second end is connected to the first external filter capacitor, serving as the first output of the bias generation circuit. The first end of resistor R5 is connected to the output of operational amplifier AMP2, and the second end is connected to the second external filter capacitor, serving as the second output of the bias generation circuit. The inverting input of operational amplifier AMP1 is connected to the output of the source-switched current array; The inverting input of operational amplifier AMP2 is connected to its own output. The first terminal of the first capacitor C1 is grounded, and the second terminal is connected to the second terminal of the resistor R4. The first terminal of the second capacitor C2 is grounded, and the second terminal is connected to the second terminal of the resistor R5.

[0038] Understandably, Figure 8 On the left is a high-precision bias generation circuit. An external reference current IREF (250uA) is injected into the core of a current mirror consisting of M0, M1, and resistors R1 and R2. A switch is placed between the second terminal of resistor R1 and ground, which controls whether the current DAC-type charge pump is turned on. A normally closed switch is placed between the second terminal of resistor R2 and ground. To improve the output impedance of the charge pump and suppress the channel length modulation effect, the circuit introduces operational amplifier feedback-assisted biasing technology. Specifically, operational amplifier AMP1 monitors the voltage of the output node CP_OUT and the replica node voltage, and dynamically adjusts the P-type bias voltage VBU. Operational amplifier AMP2 forms a voltage follower to follow the gate voltage of M1, generating a stable N-type bias voltage VBD. External filter capacitors (External CAP) are connected to the VBU and VBD nodes to filter out noise. This closed-loop biasing structure significantly improves the output impedance of the current source, ensuring the matching degree and constancy of the current over a wide output voltage swing range.

[0039] Source switch current array such as Figure 8 As shown, the system is divided into three regions based on weights: the high-order thermometer code array, the low-order binary code array, and the LSB extension branch. The high-level thermometer code array contains 7 identical physical units connected in parallel; the resistance values ​​of the first source resistor R01 and the second source resistor R02 in each physical unit are half of the first reference resistor and the second reference resistor, respectively, and the size of the current source MOS transistor in the physical unit is twice that of the reference current source transistor. The low-order binary code array contains branches with weights of 2mA and 1mA. The first resistor R11 and the second resistor R12 of the branch with a weight of 2mA have the resistance values ​​of the first reference resistor and the second reference resistor, respectively. The third resistor R13 and the fourth resistor R14 of the branch with a weight of 1mA have the resistance values ​​of twice the first reference resistor and the second reference resistor, respectively. The current source MOSFET in the branch with a weight of 2mA has the same size as the reference current source MOSFET, and the current source MOSFET in the branch with a weight of 1mA has half the size of the reference current source MOSFET. The resistance values ​​of the fifth resistor R15 and the sixth resistor R16 in the LSB extension branch are twice those of the first reference resistor and the second reference resistor, respectively. The size of the current source MOSFET in the branch is half that of the reference current source MOSFET.

[0040] The source-switched current array employs a source-switching topology. All switches (red switch symbols in the diagram) are connected in series between the source of the current-source transistor and either the power supply (VDD) or ground (GND). To optimize noise and matching, a source negative feedback resistor is connected in series in each branch.

[0041] Seven identical physical units connected in parallel are spatially designed in a uniform distribution pattern of [6, 2, 4, 0, 3, 1, 5]. Physical units with indices 6, 5, 4, and 3 correspond to the weighted driving signals MSB_UP / MSB_DN[6:3], physical units with indices 2 and 1 correspond to the equally weighted driving signals MSB_UP / MSB_DN[2:1], and physical unit with index 0 corresponds to the equally weighted driving signal MSB_UP / MSB_DN[0]. These seven physical units are responsible for the dominant charge transport, with each physical unit designed to carry a current of 4 mA. This spatial distribution ensures that heat is evenly distributed throughout the array, and the dominant signals MSB_UP / MSB_DN[6:3] simultaneously occupy the entire direction of the process gradient, averaging the mismatch caused by gradient changes (e.g., variations in doping concentration with spatial variation).

[0042] The low-order binary code array uses the ratio of MOSFETs and the ratio of resistors to ensure the accuracy of current weighting.

[0043] The LSB extension branch is designed with a current of 1mA for boundary compensation when the quantization noise is exactly an integer 1.

[0044] Programmable discharge current array, such as Figure 8 As shown, it consists of 7 sets of binary weighted current sources controlled by external UP_Bleed / DN_Bleed[6:0] signals, supporting static current regulation from microampere level (31.725uA) to milliampere level (2mA).

[0045] Programmable discharge current array is Figure 8 As shown on the right, when the phase-locked loop is working, the programmable discharge current array is configured to inject a constant DC current into the output terminal CP_OUT, forcing the system to establish a non-zero phase bias, thereby improving the linearity of PFD / CP without introducing dynamic switching noise.

[0046] Understandably, to address the nonlinearity and switching noise issues of traditional charge pumps, this invention provides a high-linearity charge pump architecture based on a source switch array and static discharge current. Compared to gate switches, source switches utilize the low impedance characteristics (1 / g) of the source node of the current source transistor. m This significantly improves switching speed and reduces setup time. Simultaneously, the switching transistor is isolated from the output node, physically blocking the clock feedthrough path of the switching control signal to the output.

[0047] This invention eliminates the need for complex switched capacitor biasing schemes and directly introduces a programmable static DC discharge current at the charge pump output. This current forces the loop to maintain a fixed non-zero phase offset in the locked state, permanently shifting the charge pump operating point out of the nonlinear region. Since this discharge current is a constant DC, there is no periodic switching action, thus achieving linearity optimization with "zero switching noise".

[0048] The core compensation principle of this invention aims to inject reverse charge through a charge pump, thereby reducing the net charge effect caused by the time deviation to zero, as detailed below: Digital coding and phase modulation: The digital control module generates symbolic control codes, phase selection codes, and LSB extension codes based on the EQ. After being synchronized by the falling edge of the reference clock, these control codes act on the multipath retiming logic to control the corresponding feedback signals DIV[4:0] and signal DIV. LSB Compared to the zero-delay signal CLK DIG Temporal relationship: When PSEL=0: Maintain alignment (no offset); When PSEL=1 and SIGN=0: Lead by one TVCO cycle; When PSEL=1 and SIGN=1: Lag by one TVCO cycle.

[0049] Current weighting and analog cancellation: The time-domain modulated feedback signal is sent to the PFD array for phase detection, generating corresponding UP / DN pulses, which drive the binary-weighted charge pump current units respectively. The current weights of each branch are configured as follows: PSEL[4] corresponds to ICP / 2; PSEL[3] corresponds to ICP / 4; PSEL[2] corresponds to ICP / 8; PSEL[1] corresponds to ICP / 16; PSEL[0] and LSB correspond to ICP / 32.

[0050] Wherein, ICP is the compensated analog current output by the current DAC type charge pump.

[0051] In the fractional-frequency division mode with compensation enabled, the total charge output by the current DAC type charge pump can be expressed as: ; in, Indicates phase detection error. This represents the instantaneous actual quantization noise code value. This indicates the period of the voltage-controlled oscillator. This represents the compensated analog current value output by a current DAC type charge pump. The first phase selection code i The value corresponding to the bit. This indicates the value corresponding to the LSB extension code value. The encoding logic of the digital module satisfies the following equation: ; Substituting the values ​​into the calculation, we can obtain the following: This indicates that the quantization error introduced by SDM is precisely canceled out in the charge domain, leaving only the normal phase detection error. T error This achieves low-noise lockout. If the system operates in integer frequency division or without compensation mode, this structure is equivalent to a conventional charge pump phase-locked loop with an ICP current.

[0052] Gain matching and linearity optimization: Compared to traditional DTC-based compensation schemes, this architecture utilizes the geometric ratio of MOS transistors to define the current weights of different branches, possessing inherent gain matching characteristics and avoiding the problem of complex back-end calibration required due to the uncertainty of delay gain caused by PVT variations in DTC. Furthermore, to address the current replication ratio mismatch (reflected in the DAC's INL) that may be caused by actual process deviations, this embodiment of the invention splits the high 3 bits of the charge pump controlled by the UP / DN[4:2] signal into 7 equally weighted physical branches and optimizes their spatial distribution, mitigating the impact of process gradients and thermal gradients on the current ratio.

[0053] To verify the performance of the fractional phase-locked loop (PLL) based on multipath quantization noise compensation proposed in this invention in actual physical implementation, a complete verification platform was built in the Cadence AMS mixed-signal simulation environment. The core modules, such as the frequency and phase detector, charge pump, frequency divider, and retimer, were built using actual transistor-level circuits, and the digital control logic was implemented using the Verilog hardware description language.

[0054] VCTRL transient waveform diagram, such as Figure 9The figure shows the transient waveform of the loop filter control voltage (VCTRL) during the locking process. Without compensation (comp_en=0), the charge pump output current fluctuates drastically due to the instantaneous frequency division ratio jump of the MASH 1-1 modulator, resulting in a significant voltage ripple exceeding 5mV at the VCTRL terminal, which directly degrades the system's phase noise performance. When the multipath quantization noise compensation proposed in this invention is enabled (comp_en=1), the VCTRL waveform converges significantly and becomes smoother, with the voltage ripple amplitude reduced to approximately 0.5mV. This time-domain result intuitively demonstrates that the "5-bit amplitude + 1-bit sign" compensation current generated by the digital logic accurately cancels the instantaneous phase error introduced by the SDM, effectively verifying the gain matching and timing synchronization of the mixed-signal path.

[0055] Figure 10 and Figure 11 The large and small span output spectra are shown respectively when the fractional PLL is locked at 20.0005 GHz (corresponding to a 500 kHz fractional frequency offset). Figure 10 As shown, without multipath compensation (comp_en=0), the output spectrum exhibits a high broadband noise floor due to the wide bandwidth setting of the CMOS PLL and the direct folding of second-order quantization noise. When multipath compensation is enabled (comp_en=1), a significant decrease in the broadband noise floor (approximately 20-30dB) can be observed. This indicates that the multipath architecture successfully cancels out most of the random quantization noise. However, as... Figure 11 As shown, the improvement in spurious amplitude at a frequency offset of 500kHz is limited, suppressing only about 3.7dBc. This is because the charge pump operates near zero phase error at this point, and a simple multipath compensation architecture cannot improve the intrinsic linearity of the charge pump. The residual small quantization error cannot be linearly converted, resulting in the retention of nonlinear spurious emissions. This phenomenon is evident from... Figure 5 The compensation effect for different digits can also be seen.

[0056] To overcome the linearity bottleneck, this invention introduces a static discharge current to improve CP linearity. Simulink-based nonlinear loop behavior-level modeling verifies the spurious suppression capability of this technique, such as... Figure 12 As shown, due to the optimization of CP linearity, the overall quantization noise compensation effect remains unchanged after enabling both compensation and Bleed. Phase noise caused by nonlinear folding at low frequencies is improved, while fractional spurious suppression reaches as high as 32dBc at a 500kHz frequency offset. The transistor-level simulation spectrum with Bleed enabled is shown below. Figure 13 As shown, the results are basically consistent with the modeling results. Compared with the case where only compensation is enabled, the fractional spurious emissions at the 500kHz frequency offset are further reduced by 30dBc while maintaining the broadband noise suppression effect.

[0057] In summary, behavioral-level modeling and transistor-level circuit simulation results jointly confirm that the "multi-path compensation + static discharge current" combined architecture proposed in this embodiment of the invention can simultaneously achieve deep suppression of broadband quantization noise and narrow-band fractional spurious noise without the need for complex background calibration algorithms, significantly improving the spectral purity of the frequency synthesizer.

[0058] The fractional phase-locked loop (PLL) provided in this invention addresses the conflict between compensation accuracy and circuit complexity in multi-path quantization noise compensation. The proposed digital control module uses a Delta-Sigma modulation link, leveraging the characteristic that the quantization noise distribution converges within the -1 to 1 TVCO period, reducing the difficulty of compensation design. For bit width optimization, an amplitude + sign compensation method is adopted, achieving optimal noise suppression while keeping the hardware scale within an engineering-acceptable range. While extracting high-order quantization errors, low-order residual data, which is usually discarded, is retained and subjected to secondary quantization. The quantized output is reinjected and superimposed onto the high-order data, thus averaging the truncation error over time. This invention introduces a data synchronization circuit based on the falling edge of the reference clock, ensuring that the frequency divider signals of all paths have reached steady state before the phase detector is triggered by the next rising edge of the PFD, completely eliminating dynamic timing interference in the mixed-signal path. By introducing a multi-path retimer with a sign bit, the compensable quantization noise range is expanded. This invention introduces an additional independent LSB compensation path in the current DAC type charge pump to ensure that the compensation charge accurately covers the error range under all quantization boundary conditions. The current DAC type charge pump adopts a charge pump architecture based on a source switch array and a static discharge current. The source switch array utilizes the low impedance characteristics of the source node of the current source transistor, significantly improving the switching speed and reducing the settling time. The static discharge current forces the loop to maintain a fixed non-zero phase offset in the locked state, permanently shifting the charge pump operating point out of the nonlinear region and deeply suppressing fractional spurious emissions. Since the discharge current is a constant DC, there is no periodic switching action, thus achieving linearity optimization with "zero switching noise".

[0059] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A fractional phase-locked loop based on multipath quantization noise compensation, characterized in that, include: NP+S multimode divider is used to control the division ratio signal N. div Under the control of [the system], the dynamic frequency division ratio is switched according to the signal CLK output by the voltage-controlled oscillator. vco Output frequency divider signal CLK div ; The digital control module is used to obtain the frequency division ratio control signal N based on the fractional frequency control word and the externally input integer frequency control word. div ; The fractional frequency control word is processed to obtain the symbol control code, phase selection code, and LSB extension code for quantization noise compensation. The data synchronization circuit is used to globally resample the symbol control code, phase selection code and LSB extension code according to the reference clock, and output the synchronized symbol control code, synchronized phase selection code and synchronized LSB extension code. A multipath retimer with a signed bit, used based on the CLK signal. vco For the frequency division signal CLK div Continuous sampling is performed to generate a leading phase, a reference phase, and a lagging phase with a time difference of one voltage-controlled oscillator period; under the control of the synchronized symbol control code, a reference signal and a dynamic signal are generated based on the leading phase, the reference phase, and the lagging phase. Based on multiple parallel path selections, and under the control of the synchronized phase selection code and the synchronized LSB spreading code, a time-domain modulated feedback signal DIV[4:0] and an LSB bit signal DIV are generated according to the reference signal and the dynamic signal. LSB ; A PFD array is used to adjust the feedback signal DIV[4:0] and the LSB bit signal DIV based on a reference clock. LSB Phase detection is performed separately to generate corresponding feedback pulses UP / DN[4:0] and LSB pulses UP / DN. LSB ; A weight allocation circuit is used to convert the binary weight signal UP / DN[4:2] in the feedback pulse UP / DN[4:0] into the physical domain equal weight drive signals MSB_UP[6:0] and MSB_DN[6:0] according to the pre-allocated weights; The current-DAC type charge pump adopts a charge pump architecture based on a source switch array and static discharge current. It is used to generate a charge pump based on a reference current, according to the feedback pulse UP / DN[1:0] and LSB pulse UP / DN. LSB Equal-weighted driving signals MSB_UP[6:0] and MSB_DN[6:0] drive the charge pump current unit in the source switch array respectively, and generate a compensated analog current under the compensation of external UP_Bleed / DN_Bleed[6:0] signals; the source switch array is divided into three regions according to the weights; The low-pass filter smooths the integrated, compensated analog current into a stable tuned voltage. A voltage-controlled oscillator, under the control of a tuning voltage, generates an output signal V of a specific frequency. OUT .

2. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 1, characterized in that, The digital control module includes: The Delta-Sigma modulation link and the quantization error processing link are set sequentially; The Delta-Sigma modulation link is used to generate a modulation signal based on a fractional frequency control word, and to add the modulation signal to an externally input integer frequency control word to obtain the division ratio control signal N. div ; The quantization error processing link is used to calculate the difference between the modulation signal and the fractional frequency control word to obtain the instantaneous frequency error, and convert the instantaneous frequency error into an instantaneous phase error; the instantaneous phase error is separated into high-order main data and low-order residual data, the low-order residual data is quantized twice to obtain a carry signal, the carry signal is injected back and superimposed on the high-order main data to generate an error signal that has undergone mean conservation processing; the highest bit of the error signal is extracted as the symbol control code, and the low-order bits are processed by absolute value to obtain the phase selection code and LSB extension code.

3. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 1, characterized in that, The data synchronization circuit includes: Reference clock inverter and parallel-configured first D flip-flop, second D flip-flop, and third D flip-flop; The reference clock inverter reverses the reference clock to obtain an inverted reference clock. The first D flip-flop has a phase selection code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized phase selection code output at its Q terminal. The second D flip-flop has an LSB spreading code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized LSB spreading code output at its Q terminal. The third D flip-flop has a symbol control code connected to its D terminal, an inverted reference clock connected to its clock terminal, and a synchronized symbol control code output at its Q terminal.

4. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 1, characterized in that, The signed multipath retimer includes: Shift register chain, delay selection logic, and parallel output retiming array; The shift register chain is in signal CLK vco Driven by the frequency division signal CLK div Continuous sampling is performed to generate a leading phase, a reference phase, and a lagging phase with a time difference of one voltage-controlled oscillator period; The delay selection logic generates a reference signal and a dynamic signal through two multiplexers; the reference signal is fixedly connected to the reference phase, and the dynamic signal dynamically switches between the leading phase and the lagging phase according to the state of the synchronized symbol control code. The parallel output retiming array comprises multiple sets of parallel selection paths and output D flip-flop arrays. Each parallel selection path selects between a reference signal and a dynamic signal based on the logic state of the synchronized phase selection code or the synchronized LSB extension code, and outputs a corresponding gating signal. The gating signals corresponding to all parallel selection paths are processed by a single stage of signal CLK. vco The output D flip-flop array is uniformly retimed to generate a time-domain modulated feedback signal DIV[4:0] and LSB bit signal DIV. LSB .

5. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 1, characterized in that, The weight allocation circuit consists of a buffer chain composed of cascaded inverters; the weight allocation circuit fans out the feedback pulse UP / DN[4] representing weight 4 and converts it into an equal weight driving signal MSB_UP / MSB_DN[6:3] to drive 4 physical channels; it fans out the feedback pulse UP / DN[3] representing weight 2 and converts it into an equal weight driving signal MSB_UP / MSB_DN[2:1] to drive 2 physical channels; it fans out the feedback pulse UP / DN[2] representing weight 1 and converts it into an equal weight driving signal MSB_UP / MSB_DN[0] to drive 1 physical channel.

6. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 1, characterized in that, The current DAC type charge pump includes: Bias generation circuit, source switching current array, and programmable discharge current array; The bias generation circuit generates a dynamically adjusted P-type bias voltage VBU and a stable N-type bias voltage VBD based on the reference current and operational amplifier feedback-assisted bias. The source switch current array is divided into three regions according to weights. Under the control of the P-type bias voltage VBU and the N-type bias voltage VBD, the current is sequentially activated by the LSB pulse UP / DN. LSB Under the control of feedback pulses UP / DN[1:0] and equal-weighted drive signals MSB_UP / DN[6:0], analog current is generated; The programmable current discharge array compensates for the analog current under the control of the external UP_Bleed / DN_Bleed[6:0] signals to generate a compensated analog current.

7. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 6, characterized in that, The bias generation circuit includes: MOSFET M0, MOSFET M1, MOSFET M2, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, operational amplifier AMP1, operational amplifier AMP2, first capacitor C1, second capacitor C2, first external filter capacitor and second external filter capacitor; The source of the MOS transistor M0 is connected to the first end of the resistor R1, the gate is connected to the gate of the MOS transistor M1, and the drain is connected to its own gate and connected to a reference current. The source of the MOS transistor M1 is connected to the first end of the resistor R2, the gate is connected to the non-inverting input of the operational amplifier AMP2, and the drain is connected to the drain of the MOS transistor M2. The source of the MOS transistor M2 is connected to the second end of the resistor R3, the gate is connected to the output of the operational amplifier AMP1, and the drain is connected to the non-inverting input of the operational amplifier AMP1. The second terminal of the resistor R1 is grounded; The second terminal of the resistor R2 is grounded; The first terminal of the resistor R3 is connected to the voltage VDD; The first end of the resistor R4 is connected to the output of the operational amplifier AMP1, and the second end is connected to the first external filter capacitor, serving as the first output of the bias generation circuit. The first end of the resistor R5 is connected to the output of the operational amplifier AMP2, and the second end is connected to the second external filter capacitor, serving as the second output of the bias generation circuit. The inverting input terminal of the operational amplifier AMP1 is connected to the output terminal of the source switching current array; The inverting input terminal of the operational amplifier AMP2 is connected to its own output terminal; The first terminal of the first capacitor C1 is grounded, and the second terminal is connected to the second terminal of the resistor R4. The first terminal of the second capacitor C2 is grounded, and the second terminal is connected to the second terminal of the resistor R5.

8. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 6, characterized in that, The source switch current array is divided into three regions according to weights: high-bit thermometer code array, low-bit binary code array, and LSB extension branch. The high-level thermometer code array contains 7 identical physical units connected in parallel; the resistance values ​​of the first source resistor R01 and the second source resistor R02 in each physical unit are half of the first reference resistor and the second reference resistor, respectively, and the size of the current source MOS transistor in the physical unit is twice that of the reference current source transistor. The low-order binary code array contains branches with weights of 2mA and 1mA. The first resistor R11 and the second resistor R12 of the branch with a weight of 2mA have the values ​​of the first reference resistor and the second reference resistor, respectively. The resistance values ​​of the third resistor R13 and the fourth resistor R14 of the branch with a weight of 1mA are twice those of the first reference resistor and the second reference resistor, respectively. The current source MOSFET in the branch with a weight of 2mA has the same size as the reference current source MOSFET, while the current source MOSFET in the branch with a weight of 1mA has half the size of the reference current source MOSFET. The resistance values ​​of the fifth resistor R15 and the sixth resistor R16 in the LSB extension branch are twice those of the first reference resistor and the second reference resistor, respectively. The size of the current source MOSFET in the branch is half that of the reference current source MOSFET.

9. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 8, characterized in that, The seven parallel identical physical units are designed in a uniform spatial distribution pattern of [6, 2, 4, 0, 3, 1, 5]; among them, the physical units with index numbers 6, 5, 4, 3 correspond to the weighted driving signals MSB_UP / MSB_DN[6:3], the physical units with index numbers 2, 1 correspond to the equal weighted driving signals MSB_UP / MSB_DN[2:1], and the physical unit with index number 0 corresponds to the equal weighted driving signals MSB_UP / MSB_DN[0].

10. A fractional phase-locked loop based on multipath quantization noise compensation according to claim 6, characterized in that, The programmable discharge current array consists of 7 sets of binary weighted current sources controlled by external UP_Bleed / DN_Bleed[6:0] signals, supporting static current regulation from microampere to milliampere levels.

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