Highly reliable anti-modeling aPUF circuit and battery passport anti-counterfeiting device

Abstract

This application relates to a high-reliability anti-modeling APUF circuit and a battery passport anti-counterfeiting device. The high-reliability anti-modeling APUF includes multiple cascaded dual-path units, at least one feedforward decision module, at least one inter-stage connection structure, and an arbitration module. The input of the feedforward decision module is connected to the output of the first dual-path unit. The feedforward decision module is used to generate a first path selection signal based on the pulse signal output by the first dual-path unit. The inter-stage connection structure is located between the second and third dual-path units. The inter-stage connection structure is used to determine the inter-row crossover transmission mode of the pulse signal in the third dual-path unit based on the first path selection signal. The arbitration module includes multiple first arbitrators and an XOR gate. The XOR gate is connected to each first arbitrator and is used to XOR the arbitration results output by each first arbitrator to obtain the target response result. This APUF improves the reliability of battery passport anti-counterfeiting.

Description

Technical Field

[0001] This application relates to the field of battery anti-counterfeiting technology, specifically to a highly reliable anti-modeling APUF circuit and a battery passport anti-counterfeiting device. Background Technology

[0002] With the increasing demand for global circulation and traceability management of products such as power batteries and energy storage systems, digital identity markers such as "battery passports" have emerged. In existing technologies, a battery passport is generated by integrating an Arbiter Physical Unclonable Function (APUF) within the battery chip, thus achieving battery anti-counterfeiting.

[0003] An Arbitrator-based Programmable Array (APUF) is a PUF that generates a hardware fingerprint by determining the delay difference of symmetrical paths through an arbitrator. Specifically, the APUF circuit mainly consists of N-stage switching blocks, two symmetrical transmission paths, and an arbitrator at the end. Each switching block consists of two 2-to-1 multiplexers. The input control signal controls the multiplexers to achieve parallel direct transmission or cross-transposition of pulse signals, thereby dynamically combining different signal transmission paths. Due to random micro-process deviations such as linewidth, doping concentration, and oxide layer thickness during chip manufacturing, the signal transmission delays of the two symmetrical paths will have slight differences. After accumulation through multiple stages, a total delay difference that can be identified by the arbitrator is formed. The arbitrator determines the arrival speed of the two signals and outputs a unique 0 / 1 response signal, which forms the hardware fingerprint of the chip. Different control signals correspond to different response signals, forming a unique excitation-response pair, providing a reliable physical basis for identity authentication and anti-counterfeiting.

[0004] However, the existing APUF structure is simple and extremely vulnerable to machine learning modeling attacks. By collecting a limited number of tag responses, other responses can be inferred, thereby counterfeiting the tags, resulting in low reliability of battery anti-counterfeiting. Summary of the Invention

[0005] Therefore, it is necessary to provide a highly reliable anti-modeling APUF circuit and a battery passport anti-counterfeiting device that can improve anti-counterfeiting reliability.

[0006] In a first aspect, this application provides a highly reliable anti-modeling APUF circuit, comprising:

[0007] Multiple cascaded two-line path units, each including multiple parallel multiplexers;

[0008] At least one feedforward decision module, the input of which is connected to the output of the first two-line path unit, is used to generate a first path selection signal based on the pulse signal output by the first two-line path unit.

[0009] At least one inter-level connection structure is provided, which is disposed between the second dual-path unit and the third dual-path unit. The input of the inter-level connection structure is connected to the output of the second dual-path unit. The control signal of the inter-level connection structure is a first path selection signal. The inter-level connection structure is used to determine the inter-row crossover transmission mode of the pulse signal in the third dual-path unit according to the first path selection signal.

[0010] The arbitration module includes multiple first arbitrators and an XOR gate. The input of each first arbitrator is any two of the pulse signals output by each multiplexer in the fourth double-path unit. The XOR gate is connected to each first arbitrator and is used to XOR the arbitration results output by each first arbitrator to obtain the target response result.

[0011] In one embodiment, the feedforward decision module includes a plurality of second arbitrators. The inputs of the second arbitrators are any two of the pulse signals output by each multiplexer in the first two-path unit, and the arbitration result output by the second arbitrators is one bit of the first selected path signal.

[0012] In one embodiment, there are multiple inter-stage connection structures, and one bit in the first path selection signal serves as a control signal for an inter-stage connection structure.

[0013] In one embodiment, the arbitrator consists of an SR latch and a dual D flip-flop detection structure. The output of the arbitrator includes the arbitration result and a metastable flag. The metastable flag is used to identify metastable states that occur during the arbitration process. The arbitrator includes a first arbitrator and a second arbitrator.

[0014] In one embodiment, the arbitration module further includes a first NOR gate, which is used to NOR the metastable flag bit output by the first arbitrator and the metastable flag bit output by the second arbitrator to obtain a reliability indication signal. The reliability indication signal is used to characterize that if one arbitrator is in a metastable state during the arbitration process, the obtained target response result is unreliable.

[0015] In one embodiment, the dual-path unit includes a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer connected in parallel, wherein the first multiplexer and the second multiplexer constitute an uplink path, and the third multiplexer and the fourth multiplexer constitute a downlink path.

[0016] The control signal for each multiplexer is the second path selection signal. Each multiplexer is used to determine the in-line transmission mode of the pulse signal in the dual-path unit based on the second path selection signal.

[0017] In one embodiment, when the second path selection signal is 0, the pulse signal is transmitted in parallel in the uplink path, or the pulse signal is transmitted in parallel in the downlink path; when the second path selection signal is 1, the pulse signal is transmitted in crossover in the uplink path, or the pulse signal is transmitted in crossover in the downlink path.

[0018] In one embodiment, when the first path selection signal is 1, the pulse signal output by the multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the downlink path of the third dual-path unit. The pulse signal output by the multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the uplink path of the third dual-path unit.

[0019] In one embodiment, when the first path selection signal is 0, the pulse signal output by the multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the uplink path of the third dual-path unit. The pulse signal output by the multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the downlink path of the third dual-path unit.

[0020] Secondly, this application provides a battery passport anti-counterfeiting device, including the high-reliability anti-modeling APUF circuit described in any of the first aspects above.

[0021] The aforementioned high-reliability anti-modeling APUF circuit and battery passport anti-counterfeiting device include a high-reliability anti-modeling APUF comprising multiple cascaded dual-path units, at least one feedforward decision module, at least one inter-stage connection structure, and an arbitration module. Each dual-path unit includes multiple parallel multiplexers. The input of the feedforward decision module is connected to the output of the first dual-path unit. The feedforward decision module generates a first path selection signal based on the pulse signal output by the first dual-path unit. The inter-stage connection structure is located between the second and third dual-path units. The input of the inter-stage connection structure is connected to the output of the second dual-path unit. The control signal of the inter-stage connection structure is the first path selection signal. The inter-stage connection structure determines the inter-row crossover transmission mode of the pulse signal in the third dual-path unit based on the first path selection signal. The arbitration module includes multiple first arbiters and an XOR gate. The input of each first arbiter is any two of the pulse signals output by each multiplexer in the fourth dual-path unit. The XOR gate is connected to each first arbiter and is used to XOR the arbitration results output by each first arbiter to obtain the target response result. In this way, the feedforward decision module generates a first path selection signal based on the real-time detected pulse signal, dynamically controls the subsequent path switch, and dynamically adjusts the transmission path of the pulse signal. Compared with the prior art where a fixed path selection signal is input from the outside, the transmission path of the pulse signal in this application changes randomly under excitation, which greatly enhances the anti-modeling attack capability of the APUF circuit and improves the reliability of the battery passport anti-counterfeiting. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the APUF circuit structure in one embodiment;

[0024] Figure 2 This is a schematic diagram of the inter-level connection structure in one embodiment;

[0025] Figure 3 This is a schematic diagram of the pulse signal transmission path in one embodiment;

[0026] Figure 4 This is a schematic diagram of the pulse signal transmission path in another embodiment;

[0027] Figure 5 This is a schematic diagram of the feedforward decision module structure in one embodiment;

[0028] Figure 6 This is a schematic diagram of the arbitrator structure in one embodiment;

[0029] Figure 7 This is a schematic diagram of the APUF circuit structure in another embodiment.

[0030] Explanation of reference numerals in the attached figures:

[0031] Two-line path unit: 10; Uplink path: 11; Downlink path: 12; Feedforward decision module: 20; Second arbiter: 201; Second NOR gate: 202; Inter-stage connection structure: 30; Arbitration module: 40; First arbiter: 401; XOR gate: 402; First NOR gate: 403. Detailed Implementation

[0032] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0034] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first two-line path element may be referred to as a second two-line path element, and similarly, a second two-line path element may be referred to as a first two-line path element. Both the first two-line path element and the second two-line path element are two-line path elements, but they are not the same two-line path element.

[0035] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0036] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0038] With the increasing demand for global circulation and traceability management of products such as power batteries and energy storage systems, digital identity markers such as "battery passports" have emerged. A key aspect of these is the use of hard-to-forge, unique, and stable hardware anti-counterfeiting labels. Currently, digital labeling solutions mainly include QR codes and RFID technology. However, these solutions have significant shortcomings in addressing battery anti-counterfeiting needs. QR codes solidify battery identity information onto the label surface through laser etching or ink printing, while RFID pre-stores battery information in non-volatile memory such as EEPROM or Flash. Attackers can physically peel off, forge, or mass-copy QR codes; for RFID tags, invasive attacks can be used to completely extract stored data and clone it to counterfeit labels.

[0039] Physically Unclonable Functions Physical Unclonable Functions (PUFs) possess the characteristics of being readily available and dynamic, as well as the unclonability of physical entropy sources. Applying them to battery tag generation can effectively address the aforementioned issues. For example, the Arbitrator Physical Unclonable Function (APUF) generates a hardware fingerprint PUF by arbitrarily determining the delay difference of symmetrical paths. Specifically, the APUF circuit mainly consists of N-stage switching blocks, two symmetrical transmission paths, and an arbitrator at the end. Each switching block comprises two 2-to-1 multiplexers. The input control signal controls the multiplexers to achieve parallel direct transmission or cross-transposition of pulse signals, thereby dynamically combining different signal transmission paths. Due to random micro-process deviations such as linewidth, doping concentration, and oxide layer thickness during chip manufacturing, the signal transmission delays of the two symmetrical paths will produce slight differences. After multiple stages of accumulation, a total delay difference that can be identified by the arbitrator is formed. The arbitrator determines the arrival speed of the two signals and outputs a unique 0 / 1 response signal, thus forming the hardware fingerprint of the chip. Different control signals correspond to different response signals, forming a unique excitation-response pair, providing a reliable physical basis for identity authentication and anti-counterfeiting.

[0040] However, while existing APUF structures are simple, they are highly vulnerable to machine learning modeling attacks. Attackers can deduce other responses by collecting a limited number of tag responses, thereby forging tags, which seriously threatens the authenticity and credibility of the battery passport.

[0041] To enhance the security of the PUF structure, one possible approach is to increase nonlinearity by adding an XOR operation after multiple PUF outputs, or to employ a multi-path dynamic selection mechanism to obfuscate signal transmission. However, while these methods often improve security, they also lead to increased bit error rates in tag responses and insufficient stability under different temperature and voltage conditions, affecting the actual authentication success rate. Some structures also require error correction circuits, increasing hardware costs and hindering deployment in large-scale, low-cost battery tags.

[0042] In another possible implementation, an inter-level cross-matrix PUF is proposed, which enhances complexity through internal cross-connections and dynamic path switching. However, its path selection signal is still externally input. In anti-counterfeiting tag applications, exposure of this path selection signal would significantly weaken security. Furthermore, while feedforward PUFs can further enhance nonlinearity, the metastability of the arbitrator leads to unreliable response outputs, often requiring limitations on structural size or the introduction of additional error correction units. This is not conducive to achieving a balance between high reliability and high security in resource-constrained battery tag chips.

[0043] Therefore, in the specific application of generating anti-counterfeiting labels for battery passports, the PUF structure often struggles to achieve a good balance between anti-attack capability, output stability, and hardware overhead. There is an urgent need for a physically unclonable function circuit that can simultaneously meet the requirements of high-strength anti-counterfeiting, low bit error rate, and low resource consumption.

[0044] In one exemplary embodiment, such as Figure 1 As shown, a highly reliable anti-modeling APUF circuit is provided, the APUF comprising:

[0045] Multiple cascaded dual-path units 10, each dual-path unit including multiple parallel multiplexers;

[0046] At least one feedforward decision module 20, the input of which is connected to the output of the first dual-path unit, and the feedforward decision module 20 is used to generate a first path selection signal based on the pulse signal output by the first dual-path unit;

[0047] At least one inter-level connection structure 30 is provided, which is disposed between the second double-path unit and the third double-path unit. The input of the inter-level connection structure 30 is connected to the output of the second double-path unit. The control signal of the inter-level connection structure 30 is a first path selection signal. The inter-level connection structure 30 is used to determine the inter-row cross-transmission mode of the pulse signal in the third double-path unit according to the first path selection signal.

[0048] Arbitration module 40 includes multiple first arbiters 401 and XOR gate 402. The input of the first arbiter 401 is any two of the pulse signals output by each multiplexer in the fourth double-path unit. XOR gate 402 is connected to each first arbiter 401 and is used to XOR the arbitration results output by each first arbiter 401 to obtain the target response result R.

[0049] Optionally, in this embodiment, taking the dual-path unit 10 including four multiplexers as an example, four symmetrical transmission paths can be constructed based on multiple cascaded dual-path units, as shown in the reference. Figure 1 The dual-path unit includes a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer connected in parallel. The first and second multiplexers constitute the uplink path 11, and the third and fourth multiplexers constitute the downlink path 12.

[0050] In other words, when the dual-path unit 10 includes four multiplexers, the uplink path 11 can include two transmission paths, and the downlink path 12 can also include two transmission paths.

[0051] The multiple multiplexers in the dual-path unit 10 can be 2-to-1 multiplexers. Pulse signals can be simultaneously input into the four multiplexers in the dual-path unit 10. According to the second control signal of the multiplexer, the pulse signals are controlled to achieve parallel pass-through or cross-transposition within the row, thereby dynamically combining different signal transmission paths.

[0052] Optionally, for the feedforward decision module 20, refer to Figure 1 It can be connected to any two-line path unit 10. For ease of description, in this embodiment, the two-line path unit 10 connected to the input end of the feedforward decision module 20 is referred to as the first two-line path unit.

[0053] The feedforward decision module 20 can generate a first path selection signal based on the four pulse signals output by the first dual-path unit.

[0054] First path selection signal S iIt can be a high level (1) or a low level (0). The generated first path selection signal can be one bit or multiple bits. In other words, the feedforward decision model 20 can generate a one-bit first path selection signal based on the four pulse signals to control an interstage connection structure 30. It can also generate multiple first path selection signals, with each first path selection signal controlling a different interstage connection structure 30. This application embodiment does not limit this.

[0055] In one possible implementation, the feedforward decision module may include multiple arbiters. The four delay paths are arbitrarily combined in pairs and connected to different arbiters. Each arbiter outputs a first path selection signal according to the arrival order of the two pulse signals in the corresponding two delay paths, and finally obtains multiple first path selection signals.

[0056] In another possible implementation, the feedforward decision model may include an arbitrator to which any two of the four delay paths are connected. The arbitrator inputs a first path selection signal based on the order in which the two pulse signals corresponding to the two delay paths arrive.

[0057] refer to Figure 1 When the APUF circuit of this application includes two or more feedforward decision modules 20, each feedforward decision module 20 can be separated by i double-row path units. In order to reduce the probability of generating unreliable excitation response pairs, the value of i should not be too small. This is because if the total delay of the front path of the feedforward decision module is too small, the delay difference of the signal is too small, which can easily lead to metastability, resulting in decision errors and thus no code.

[0058] For an inter-level connection structure 30, it can be set between two adjacent two-row path units 10. For ease of description, in this embodiment, the two-row path unit 10 located before the inter-level connection structure 30 is called the second two-row path unit, and the two-row path unit 10 located after the inter-level connection structure 30 is called the third two-row path unit. That is, the input of the inter-level connection structure 30 is connected to the output of the second two-row path unit, and the output of the inter-level connection structure 30 is connected to the input of the third two-row path unit.

[0059] The inter-level connection structure can determine the inter-row crossover transmission mode of the pulse signal in the third double-row path unit based on its control signal (first path selection signal).

[0060] The inter-line cross-transmission method includes cross-transmission between uplink path 11 and downlink path 12, or parallel transmission within uplink path 11 or downlink path 12.

[0061] For example, when the first path selection signal is a first preset value, the pulse signal is transmitted cross-transmitted between the uplink path 11 and the downlink path 12. When the first path selection signal is a second preset value, the pulse signal is transmitted in the current path instead of being transmitted across paths.

[0062] like Figure 2 The diagram shows a schematic of an inter-stage connection structure 30. The inter-stage connection structure 30 includes four lookup tables (LUTs). S represents the first path selection signal, and a, b, c, and d represent the four pulse signals output by the second dual-path unit. The pulse signals are input to the I0 / I1 ports of the LUTs, and S is input to the I2 port.

[0063] At the output of the last-stage dual-path unit 10, an arbitration module 40 can be connected. For ease of description, the last-stage dual-path unit 10 is referred to as the fourth dual-path unit. The arbitration module 40 generates the target response result according to the order of the four pulse signals output by the fourth dual-path unit.

[0064] Optionally, the arbitration module 40 may include six first arbitrators 401. The four delay paths can be combined in pairs and connected to different first arbitrators 401. Each first arbitrator 401 outputs the arbitration result according to the arrival order of the two pulse signals in the corresponding two delay paths. Then, the output of each first arbitrator 401 is connected to an XOR gate 402. The XOR gate 402 performs an XOR operation on each arbitration result to obtain the target response result R.

[0065] For example, such as Figure 1 As shown, taking pulse signals A, B, C, and D as examples, pulse signal A is the output of the delayed path corresponding to the first multiplexer in the fourth dual-path unit, pulse signal B is the output of the delayed path corresponding to the second multiplexer in the fourth dual-path unit, pulse signal C is the output of the delayed path corresponding to the third multiplexer in the fourth dual-path unit, pulse signal D is the output of the delayed path corresponding to the fourth multiplexer in the fourth dual-path unit. Inputting pulse signals A and B into a first arbitrator 401 yields an arbitration result; inputting pulse signals A and C into a first arbitrator 401 yields an arbitration result; inputting pulse signals C and D into a first arbitrator 401 yields an arbitration result, and so on.

[0066] The target response result can be 0 or 1. In the battery passport generation scenario, the target response result and the second path selection signal input by the APUF circuit can be used as the battery passport. In the battery passport verification process, the target response result can be compared with the preset response result corresponding to the second path selection signal to verify the authenticity of the battery.

[0067] The aforementioned high-reliability anti-modeling APUF circuit includes multiple cascaded dual-path units, at least one feedforward decision module, at least one inter-stage connection structure, and an arbitration module. Each dual-path unit includes multiple parallel multiplexers. The input of the feedforward decision module is connected to the output of the first dual-path unit. The feedforward decision module generates a first path selection signal based on the pulse signal output by the first dual-path unit. The inter-stage connection structure is located between the second and third dual-path units. The input of the inter-stage connection structure is connected to the output of the second dual-path unit. The control signal of the inter-stage connection structure is the first path selection signal. The inter-stage connection structure determines the inter-row crossover transmission mode of the pulse signal in the third dual-path unit based on the first path selection signal. The arbitration module includes multiple first arbiters and an XOR gate. The input of each first arbiter is any two of the pulse signals output by each multiplexer in the fourth dual-path unit. The XOR gate is connected to each first arbiter and is used to XOR the arbitration results output by each first arbiter to obtain the target response result. In this way, the feedforward decision module generates a first path selection signal based on the pulse signal detected in real time, dynamically controls the subsequent path switch, and dynamically adjusts the transmission path of the pulse signal. Compared with the prior art where a fixed path selection signal is input from the outside, the transmission path of the pulse signal in this application changes randomly under excitation, which greatly enhances the anti-modeling attack capability of the APUF circuit and improves the reliability of the battery passport anti-counterfeiting.

[0068] As can be seen from the above embodiments, the inter-level connection structure 30 can determine the inter-row cross-transmission mode of the pulse signal in the third double-row path unit according to the first path selection signal.

[0069] Specifically, when the first path selection signal is 1, the pulse signal output by the multiplexer in the uplink path of the second dual-path unit is input to the multiplexer in the downlink path of the third dual-path unit through the inter-stage connection structure, and the pulse signal output by the multiplexer in the downlink path of the second dual-path unit is input to the multiplexer in the uplink path of the third dual-path unit through the inter-stage connection structure. When the first path selection signal is 0, the pulse signal output by the multiplexer in the uplink path of the second dual-path unit is input to the multiplexer in the uplink path of the third dual-path unit through the inter-stage connection structure, and the pulse signal output by the multiplexer in the downlink path of the second dual-path unit is input to the multiplexer in the downlink path of the third dual-path unit through the inter-stage connection structure.

[0070] The intra-line transmission mode of each dual-path unit 10 can be determined based on the control signals of each multiplexer in the dual-path unit 10. The control signal for each multiplexer is the second path selection signal C. i Each multiplexer is used to select the path based on the second path selection signal C.i Determine the in-row transmission mode of the pulse signal in the dual-path unit.

[0071] Second path selection signal C i It can be an externally input control signal. In a dual-path unit 10, the second path selection signal corresponding to each multiplexer is the same.

[0072] Specifically, when the second path selection signal is 0, the pulse signal is transmitted in parallel in the uplink path, or the pulse signal is transmitted in parallel in the downlink path; when the second path selection signal is 1, the pulse signal is transmitted in crossover in the uplink path, or the pulse signal is transmitted in crossover in the downlink path.

[0073] When the second path selection signal is 0, the pulse signal is transmitted in parallel within the row. For example, the pulse signal output from the first multiplexer in the nth-level dual-path unit 10 is input to the first multiplexer in the (n+1)th-level dual-path unit 10. When the second path selection signal is 1, the pulse signal is transmitted in crosswise within the row. For example, the pulse signal output from the first multiplexer in the nth-level dual-path unit 10 is input to the second multiplexer in the (n+1)th-level dual-path unit 10, and the pulse signal output from the second multiplexer in the nth-level dual-path unit 10 is input to the first multiplexer in the (n+1)th-level dual-path unit 10; or, the pulse signal output from the third multiplexer in the nth-level dual-path unit 10 is input to the fourth multiplexer in the (n+1)th-level dual-path unit 10, and the pulse signal output from the fourth multiplexer in the nth-level dual-path unit 10 is input to the third multiplexer in the (n+1)th-level dual-path unit 10.

[0074] Next, combining the first path selection signal S i Second path selection signal C i An example illustration of switching the transmission path of the pulse signal in the APUF circuit.

[0075] like Figure 3 The diagram shown illustrates an exemplary transmission path for four pulse signals, wherein the first path selection signal S... i The second path selection signal C of the second double-path unit is 0. i-1 The second path selection signal C of the third double-path unit is 0. i The value is 1.

[0076] refer to Figure 3The pulse signal is transmitted in parallel in the second dual-path unit; the pulse signal output from the first multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the second multiplexer in the uplink path of the third dual-path unit; the pulse signal output from the second multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the first multiplexer in the uplink path of the third dual-path unit; the pulse signal output from the third multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the fourth multiplexer in the downlink path of the third dual-path unit; the pulse signal output from the fourth multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the third multiplexer in the downlink path of the third dual-path unit.

[0077] like Figure 4 The diagram shown illustrates an exemplary transmission path for four pulse signals, wherein the first path selection signal S... i 1. The second path selection signal C of the second double-path unit i-1 The second path selection signal Ci of the third double-path unit is 1, and the value is 0.

[0078] refer to Figure 4 The pulse signal is transmitted in parallel in the second dual-path unit; the pulse signal output from the first multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the fourth multiplexer in the downlink path of the third dual-path unit; the pulse signal output from the second multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the third multiplexer in the downlink path of the third dual-path unit; the pulse signal output from the third multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the second multiplexer in the uplink path of the third dual-path unit; the pulse signal output from the fourth multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure 30 and is input into the first multiplexer in the uplink path of the third dual-path unit.

[0079] Therefore, the inter-stage delay path transmission structure can be reconstructed through the first path selection signal and the second path selection signal, increasing information entropy. Specifically, when the inter-stage cross-transmission mode is not activated, the input pulse signal follows the path constraint of the classic APUF—the uplink and downlink delay paths are mutually isolated, and the information entropy is increased by the second path selection signal C. i Controls the intra-line transmission mode. When the inter-level cross-transmission mode is activated, the first path selection signal S... i Drive symmetrical cross switch, S i The Boolean state (0 / 1) directly determines the transmission mode of the pulse signal: S i=0 maintains double-row isolation, S i =1 enables inter-row signal switching. This dynamic path switching expands delay contention from two paths to four paths, and its symmetrical cross-topology can be used to ensure good output bias. Thus, on the one hand, the inter-stage connection structure 30 adopts a symmetrical cross-topology to ensure unbiased output; the randomness and diversity of inter-row signal transmission and cross-feed loops can significantly improve the diversity of entropy sources; on the other hand, the four delay paths provide the hardware foundation for the implementation of a single-stage multi-bit feedforward decision module, that is, the feedforward decision module can generate a multi-bit first selection path signal through the pulse signals output from the four delay paths.

[0080] In one exemplary embodiment, such as Figure 5 The diagram shows a structure of a feedforward decision module 20. The feedforward decision module 20 includes multiple second arbitrators 201. The input of the second arbitrator 201 is any two of the pulse signals output by each multiplexer in the first dual-path unit. The arbitration result output by the second arbitrator 201 is one bit of the first selected path signal.

[0081] refer to Figure 5 The feedforward decision module 20 may include six second arbiters 201, which generate a six-bit first selection path signal R0[5:0] for controlling the inter-stage connection structure by comparing the phase difference of the four delay paths.

[0082] As can be seen from the above embodiments, both the feedforward decision module 20 and the arbitration module 40 include an arbitrator. The structure of the arbitrator is described below, which includes a first arbitrator and a second arbitrator.

[0083] When the arbiter is a D-type flip-flop (DFF), if the arrival time difference (ΔT) of the two pulse signals is less than its setup / hold time window, the DFF will enter a metastable state. Its output will oscillate at an uncertain logic level for a long time, eventually stabilizing at '0' or '1' with randomness. This will cause the feedforward decision module 20 to have a high bit error rate. The output stability of the feedforward decision module directly determines the quality of the first path selection signal, which in turn affects the bit error rate of the entire APUF circuit.

[0084] Therefore, in this application embodiment, an arbitrator SRCA based on an SR latch is provided, such as... Figure 6 As shown, the arbitrator SRCA can be composed of an SR latch and a dual D flip-flop detection structure. The output of the arbitrator includes the arbitration result and a metastable flag. The metastable flag is used to identify metastable states that occur during the arbitration process. The arbitrator includes a first arbitrator and a second arbitrator.

[0085] refer to Figure 6The SR latch consists of two cross-coupled NOR gates, with two pulse signals connected to its S (set) and R (reset) terminals respectively. When S and R almost simultaneously transition from high to low, the latch output enters a metastable state with high-frequency oscillation. The dual D flip-flop detection structure consists of two rising-edge triggered D flip-flops (DFF1 and DFF2) cascaded to form a metastable detector. The clock terminal of DFF1 is connected to the output of the SR latch, and its D terminal is connected to a high level. The clock of DFF2 is the same as that of DFF1, and its D terminal is connected to the output R0 of DFF1. The reset terminals CLR of both D flip-flops are connected to the initialization signal Init. The output R0 of DFF1 is the arbitration result, and the output R1 of DFF2 is the metastable flag.

[0086] The SRCA structure has three output states: (1) State "10" (upper path fast): When the upper path signal is significantly faster than the lower path, that is, the R terminal signal is set to "0" first, the SR latch is set to "1", the clock terminals of DFF1 and DFF2 arrive at a rising edge, the Q output of DFF1 is high level "1", the Q output of DFF2 is low level "0", and the code is "10".

[0087] (2) State “00” (lower path fast): When the lower path signal is significantly faster than the upper path, that is, the S terminal signal is set to “0” first, the SR latch is stable in the set state, and the Q output is stable at a low level “0”. At this time, neither DFF1 nor DFF2 has a rising edge, and the encoding state is always the reset state “00”.

[0088] (3) State "11" (metastable): When ΔT≈0, the SR latch is in a metastable state, and the SR latch outputs Q, which oscillates at a high frequency. At this time, both flip-flops are always in the triggered state. When the rising edge of the clock arrives, DFF1 samples a high level and outputs "1". DFF2 will output "1" in the next stage, thus locking the final code to "11". This unique code clearly identifies the occurrence of the metastable event.

[0089] Compared to traditional DFF arbitrators, SRCA can explicitly represent metastable states, transforming difficult-to-handle metastable states that lead to random errors into a unique and reliably detectable digital code "11". For non-metastable cases (where |ΔT| is large), SRCA can provide a stable and correct "00" or "10" decision.

[0090] It is understood that the arbitrator described above can also take other forms, not limited to those mentioned in the above embodiments, as long as it can achieve the function of metastable state display.

[0091] In one exemplary embodiment, such as Figure 7As shown, the arbitration module 40 also includes a first NOR gate 403, which is used to NOR the metastable flag R1 output by the first arbiter 401 and the metastable flag R1 of the second arbiter 201 to obtain a reliability indication signal RSM. The reliability indication signal RSM is used to characterize that if one of the arbiters is in a metastable state during the arbitration process, the obtained target response result is unreliable.

[0092] In another possible implementation, refer to Figure 5 When the second arbitrator 201 is an SRCA arbitrator, the feedforward decision module 20 also includes a second NOR gate 202, which is used to NOR the metastable flag R1 output by each second arbitrator 201, and output the current metastable flag error of the feedforward decision module 20. At this time, the first NOR gate 403 in the arbitration module 40 is used to NOR the metastable flags output by each first arbitrator 401 and the metastable flag error of each feedforward decision module 20, to obtain the reliability indication signal RSM.

[0093] Understandably, if any arbiter experiences metastability during the arbitration process, its output metastability flag R1 will become "1", and the reliability indicator signal RSM will be set to "0", thus ensuring the stability of the entire circuit.

[0094] In this way, during the battery registration phase, the Reliability Indicator Signal (RSM) can be used as key data, bound to the Original Challenge-Response Pair (CRP), and reported to the authentication server. If RSM=0, it indicates that the current CRP has a potential error rate, and the system automatically removes this high-risk CRP; only stable CRPs with RSM "1" are retained for subsequent authentication processes. This proactive screening mechanism significantly reduces the systematic error rate. By pre-excluding unreliable responses, it avoids the use of unreliable responses caused by metastable perturbations, thereby ensuring the determinism of PUF output at the source. Thus, while maintaining high reliability, it strengthens the security foundation. A stable CRP library directly reduces the feasibility of machine learning attacks, preventing attack models from using noise-induced response flipping or other behaviors to accelerate attacks on the model.

[0095] In one exemplary embodiment, this application also provides a battery passport anti-counterfeiting device, including the high-reliability anti-modeling APUF circuit described in any of the above claims.

[0096] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A highly reliable anti-modeling APUF circuit, characterized in that, include: Multiple cascaded dual-path units, wherein each dual-path unit includes multiple parallel multiplexers; At least one feedforward decision module, the input of which is connected to the output of the first dual-path unit, the feedforward decision module being used to generate a first path selection signal based on the pulse signal output by the first dual-path unit; At least one inter-level connection structure is provided, the inter-level connection structure is disposed between the second dual-path unit and the third dual-path unit, the input of the inter-level connection structure is connected to the output of the second dual-path unit, the control signal of the inter-level connection structure is a first path selection signal, and the inter-level connection structure is used to determine the inter-row cross-transmission mode of the pulse signal in the third dual-path unit according to the first path selection signal. The arbitration module includes multiple first arbitrators and an XOR gate. The input of each first arbitrator is any two of the pulse signals output by each multiplexer in the fourth two-row path unit. The XOR gate is connected to each first arbitrator and is used to XOR the arbitration results output by each first arbitrator to obtain the target response result.

2. The circuit according to claim 1, characterized in that, The feedforward decision module includes multiple second arbitrators. The input of each second arbitrator is any two of the pulse signals output by each multiplexer in the first dual-path unit. The arbitration result output by the second arbitrator is one bit of the first path selection signal.

3. The circuit according to claim 2, characterized in that, The number of inter-level connection structures is multiple, and one bit in the first path selection signal serves as a control signal for one inter-level connection structure.

4. The circuit according to claim 2, characterized in that, The arbitrator consists of an SR latch and a dual D flip-flop detection structure. The output of the arbitrator includes the arbitration result and a metastable flag. The metastable flag is used to identify metastable states that occur during the arbitration process. The arbitrator includes a first arbitrator and a second arbitrator.

5. The circuit according to claim 3, characterized in that, The arbitration module further includes a first NOR gate, which is used to NOR the metastable flag output by the first arbitrator and the metastable flag output by the second arbitrator to obtain a reliability indication signal. The reliability indication signal is used to characterize that if one arbitrator is in a metastable state during the arbitration process, the obtained target response result is unreliable.

6. The circuit according to claim 1, characterized in that, The dual-path unit includes a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer connected in parallel, wherein the first multiplexer and the second multiplexer constitute an uplink path, and the third multiplexer and the fourth multiplexer constitute a downlink path. The control signal of each multiplexer is a second path selection signal, and each multiplexer is used to determine the in-line transmission mode of the pulse signal in the dual-path unit according to the second path selection signal.

7. The circuit according to claim 6, characterized in that, When the second path selection signal is 0, the pulse signal is transmitted in parallel in the uplink path, or the pulse signal is transmitted in parallel in the downlink path; When the second path selection signal is 1, the pulse signal is cross-transmitted in the uplink path, or the pulse signal is cross-transmitted in the downlink path.

8. The circuit according to claim 6, characterized in that, When the first path selection signal is 1, the pulse signal output by the multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the downlink path of the third dual-path unit. The pulse signal output by the multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the uplink path of the third dual-path unit.

9. The circuit according to claim 6, characterized in that, When the first path selection signal is 0, the pulse signal output by the multiplexer in the uplink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the uplink path of the third dual-path unit. The pulse signal output by the multiplexer in the downlink path of the second dual-path unit passes through the inter-stage connection structure and is input into the multiplexer in the downlink path of the third dual-path unit.

10. A battery passport anti-counterfeiting device, characterized in that, Includes a highly reliable anti-modeling APUF circuit according to any one of claims 1 to 9.

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