Semiconductor structure and method of manufacturing the same, storage system

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system, relating to the field of semiconductor chip technology, and aims to improve the problem of easy coupling between control gate layers in adjacent transistors. The semiconductor structure includes: a semiconductor pillar, a first gate layer, a second gate layer, a capacitor structure, and a first dielectric layer. The semiconductor pillar extends along a first direction. The first gate layer and the second gate layer are located on opposite sides of the semiconductor pillar along a second direction. The capacitor structure is connected to one end of the semiconductor pillar along the first direction. The first dielectric layer is located at one end of the first gate layer along the first direction, and is closer to the capacitor structure than the first gate layer. The first dielectric layer has a first gap, which overlaps with the second gate layer in the second direction. Since the dielectric constant of the first gap is less than that of the first gate layer, the second gate layer is less likely to couple with other conductive structures at the location of the first gap.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] With the rapid development of Dynamic Random Access Memory (DRAM), the size of DRAM continues to shrink, which places higher demands on the arrangement of transistors in DRAM.

[0003] As DRAM size continues to shrink, the spacing between adjacent memory cells in DRAM is becoming smaller and smaller. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor structure is provided. The semiconductor structure includes: a semiconductor pillar, a first gate layer, a second gate layer, a capacitor structure, and a first dielectric layer. The semiconductor pillar extends along a first direction. The first gate layer and the second gate layer are respectively located on opposite sides of the semiconductor pillar along a second direction, the second direction intersecting the first direction. The capacitor structure is connected to one end of the semiconductor pillar along the first direction. The first dielectric layer is located at one end of the first gate layer along the first direction, and the first dielectric layer is closer to the capacitor structure than the first gate layer. The first dielectric layer has a first gap, and the first gap overlaps with the second gate layer in the second direction.

[0007] In some embodiments, the second gate layer includes a metal gate and a conductive film stacked along the second direction, wherein the conductive film is located between the metal gate and the semiconductor pillar.

[0008] In some embodiments, the dimension of the second gate layer in the first direction is greater than the dimension of the first gate layer in the first direction.

[0009] In some embodiments, the end of the second gate layer is closer to the capacitor structure than the end of the first gate layer.

[0010] In some embodiments, the dimension of the first dielectric layer in the first direction is greater than the dimension of the first gate layer in the first direction.

[0011] In some embodiments, the dimension of the first dielectric layer in the first direction ranges from 50 nm to 90 nm.

[0012] In some embodiments, the system further includes: a plurality of semiconductor pillars and a plurality of capacitor structures, wherein the plurality of semiconductor pillars are spaced apart along the second direction; a plurality of capacitor structures are spaced apart along the second direction, wherein one capacitor structure is connected to one semiconductor pillar; and the first gap is located between adjacent semiconductor pillars.

[0013] In some embodiments, the device further includes: a second dielectric layer located between the first gate layer and the semiconductor pillar, and also located between the first dielectric layer and the semiconductor pillar.

[0014] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: forming a semiconductor pillar extending along a first direction; forming a first gate layer located on one side of the semiconductor pillar along a second direction, the second direction intersecting the first direction; forming a first dielectric layer located at one end of the first gate layer along the first direction, and the first dielectric layer having a first gap; forming a second gate layer located on the other side of the semiconductor pillar along the second direction, the first gap overlapping the second gate layer in the second direction; and forming a capacitor structure connected to one end of the semiconductor pillar along the first direction, wherein the first dielectric layer is closer to the capacitor structure than the first gate layer.

[0015] In some embodiments, forming semiconductor pillars includes: removing a portion of a semiconductor layer to form a plurality of semiconductor pillars spaced apart along a second direction, the semiconductor pillars extending along the first direction and having a first groove between adjacent semiconductor pillars; forming a first gate layer includes: sequentially forming a second dielectric layer and a first gate layer within the first groove, the second dielectric layer and the first gate layer surrounding a second groove; forming a first dielectric layer includes: forming the first dielectric layer within the second groove by a vapor deposition process, the first dielectric layer having a first gap located between adjacent semiconductor pillars and the first gate layer.

[0016] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0018] Figure 1 A block diagram of an electronic device according to some embodiments;

[0019] Figure 2 A block diagram of a memory according to some embodiments;

[0020] Figure 3 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 1 ;

[0021] Figure 4 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 2 ;

[0022] Figure 5 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0023] Figure 6 This is a schematic diagram of the structure after forming the semiconductor pillar according to some embodiments;

[0024] Figure 7 This is a schematic diagram of the structure after the formation of the first gate layer according to some embodiments;

[0025] Figure 8 This is a schematic diagram of the structure after the formation of the first dielectric layer according to some embodiments;

[0026] Figure 9 This is a schematic diagram of the structure after opening the first groove according to some embodiments;

[0027] Figure 10 This is a schematic diagram of the structure after forming the second gate layer according to some embodiments;

[0028] Figure 11 This is a schematic diagram of the structure after grinding the upper surface of the semiconductor pillar according to some embodiments.

[0029] Reference numerals: 9000, Electronic device; 910, Storage system; 911, Memory; 912, Controller; 920, Motherboard; 1000, Semiconductor structure; 100, Semiconductor pillar; 200, First gate layer; 300, Second gate layer; 310, Metal gate; 320, Conductive thin film; 400, Capacitor structure; 500, First dielectric layer; X, First direction; Y, Second direction; Z, Third direction; 510, First gap; 600, Second dielectric layer; 700, Semiconductor layer; 710, First groove; 720, Second groove; T, Vertical transistor; 800, Connection structure. Detailed Implementation

[0030] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0031] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0034] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0035] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0036] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0037] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0038] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0039] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0040] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0041] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, the difference between the two equalities being less than or equal to 5% of either one.

[0042] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0043] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0044] Figure 1 This is a structural block diagram of an electronic device 9000 provided in some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, server, in-vehicle equipment, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0045] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0046] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0047] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control the memory 911 to store data while also communicating with external devices (e.g., a host computer).

[0048] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram uses three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0049] In some implementations, controller 912 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., motherboard 920) according to a specific communication protocol. For example, controller 912 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0050] The controller 912 mentioned above may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0051] In this embodiment, the storage system 910 can be integrated into various types of storage devices, and is not limited to the electronic device 9000 in the above embodiment.

[0052] Figure 2 This is a structural block diagram of a memory 911 provided in some embodiments of this disclosure. For example... Figure 2 As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0053] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0054] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0055] The memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to DRAM cell arrays, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0056] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor and one or more transistors. The capacitor stores data as positive or negative charge, and the one or more transistors (also called transfer transistors) control (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0057] As DRAM sizes continue to shrink, the spacing between adjacent memory cells becomes smaller and smaller, making it easier for the gate layers in adjacent memory cells to couple, leading to memory cell failure.

[0058] Based on this, some embodiments of this disclosure provide a semiconductor structure, with reference to... Figure 3 The semiconductor structure 1000 includes: a semiconductor pillar 100, a first gate layer 200, a second gate layer 300, a capacitor structure 400, and a first dielectric layer 500.

[0059] The semiconductor pillar 100 extends along a first direction X. The semiconductor pillar 100 has a source and a drain, which are located at opposite ends of the semiconductor pillar 100 along the first direction X. The semiconductor pillar 100 is composed of semiconductor materials. The materials of the source and drain may include semiconductor materials doped with P-type or N-type dopants.

[0060] Semiconductor materials include, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0061] In some examples, the semiconductor structure 1000 may include a plurality of semiconductor pillars 100 spaced apart along a second direction Y. The semiconductor may also extend along a third direction Z, where the second direction Y intersects the first direction X, and the third direction Z intersects the plane containing the first direction X and the second direction Y. This disclosure illustrates the semiconductor structure 1000 by assuming that the first direction X, the second direction Y, and the third direction Z are mutually perpendicular. A first gate layer 200 and a second gate layer 300 are located on opposite sides of the semiconductor pillars 100 along the second direction Y. The first gate layer 200 may extend along the third direction Z, and the second gate layer 300 may also extend along the third direction Z. Thus, the extension directions of the first gate layer 200, the semiconductor pillars 100, and the second gate layer 300 are all the same, so that the first gate layer 200 and the second gate layer 300 can apply a voltage to the semiconductor pillars 100.

[0062] It should be noted that in this embodiment, the second gate layer 300 is located on one side of the semiconductor pillar 100 along the second direction Y, and the second gate layer 300 is coupled to the semiconductor pillar 100. The second gate layer 300 and the semiconductor pillar 100 can form a vertical transistor T. The second gate layer 300 can serve as a control electrode; for example, the second gate layer 300 can be configured to control the semiconductor pillar 100 to be turned on or off. The first gate layer 200 is located on the other side of the semiconductor pillar 100 along the second direction Y, and the first gate layer 200 is also coupled to the semiconductor pillar 100, but the first gate layer 200 and the second gate layer 300 are not in direct contact with each other. The first gate layer 200 and the second gate layer 300 have different functions; the first gate layer 200 can serve as an auxiliary electrode. For example, the voltage of the first gate layer 200 can be adjusted to change the barrier of the semiconductor pillar 100, thereby affecting the threshold voltage of the semiconductor pillar 100 and optimizing the electrical performance of the semiconductor pillar 100.

[0063] Exemplarily, the constituent materials of the first gate layer 200 and the second gate layer 300 may include conductive materials. Conductive materials may include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials. In this embodiment, the constituent material of the first gate layer 200 includes titanium nitride.

[0064] The capacitor structure 400 is connected to one end of the semiconductor pillar 100 along the first direction X. For example, the capacitor structure 400 may be connected to the source end of the semiconductor pillar 100.

[0065] The first dielectric layer 500 is located at one end of the first gate layer 200 along the first direction X. The first dielectric layer 500 is closer to the capacitor structure 400 than the first gate layer 200. For example... Figure 3 As shown, the first dielectric layer 500 is located above the first gate. The first dielectric layer 500 has a first gap 510. Here, it can also be understood that the first dielectric layer 500 can enclose the first gap 510. This disclosure does not limit the shape of the first gap 510. Figure 3 As shown, the second gate layer 300 may protrude beyond the first gate layer 200 in the first direction X, which can be understood as the second gate layer 300 being higher than the first gate layer 200. In this case, the second gate layer 300 overlaps with the first dielectric layer 500 in the second direction Y, so that the first gap 510 overlaps with the second gate layer 300 in the second direction Y. The overlap of the first gap 510 with the second gate layer 300 in the second direction Y means that the orthographic projection of the first gap 510 in the second direction Y overlaps with the orthographic projection of the second gate layer 300 in the second direction Y. The orthographic projection of the first gap 510 in the second direction Y refers to the orthographic projection of the closed shape enclosed by the edge of the first gap 510 in the second direction Y. It should be noted that the overlap of the first gap 510 with the second gate layer 300 in the second direction Y can be a complete overlap or a partial overlap.

[0066] The first gap 510 can be filled with air, which has a dielectric constant of approximately 1. Since the dielectric constant of air is less than that of conductive materials, the dielectric constant of the first gap 510 is less than that of the first gate layer 200, and the isolation capability of the first gap 510 is superior to that of the first gate layer 200. For example, the first gate layer 200 may be composed of titanium nitride, and the dielectric constant of air is less than that of titanium nitride. Therefore, at the location of the first gap 510, the second gate layer 300 is less likely to couple with other conductive structures. Thus, compared to simply providing the first gate layer 200 on the side of the semiconductor pillar 100 facing away from the second gate layer 300 along the second direction Y, providing the first gap 510 helps to improve the coupling problem between the second gate layer 300 and other conductive structures.

[0067] Furthermore, the dielectric constant of air is lower than that of a dielectric material (e.g., silicon oxide). Therefore, the dielectric constant of the first gap 510 is lower than that of the first dielectric layer 500, and the isolation capability of the first dielectric layer 500 with the first gap 510 is superior to that of a dielectric layer without a gap. Therefore, compared to simply providing a dielectric layer on the side of the semiconductor pillar 100 facing away from the second gate layer 300 along the second direction Y, providing the first gap 510 helps to improve the coupling problem between the second gate layer 300 and other conductive structures. In some examples, a semiconductor pillar 100 and a second gate layer 300 can constitute a vertical transistor T. The semiconductor structure 1000 can include multiple vertical transistors T spaced apart along the second direction Y. The semiconductor pillars 100 of adjacent vertical transistors T are separated by an isolation structure, and the second gate layer 300 is located on the side of the semiconductor pillar 100 away from the isolation structure. The second gate layers 300 of adjacent vertical transistors T are mirror-symmetrically distributed. In this case, the vertical transistor T is an MSG (Mirror Single Gate) vertical transistor T.

[0068] In the above example, the isolation structure may include a first gate layer 200 and a first dielectric layer 500. The first dielectric layer 500 may be located between two adjacent semiconductor pillars 100, and the first gap 510 partially overlaps with the semiconductor pillar 100 in the second direction Y, meaning that the orthographic projection of the first gap 510 in the second direction Y partially overlaps with the orthographic projection of the semiconductor pillar 100 in the second direction Y. For example, the first gap 510 overlaps with the source of the semiconductor pillar 100 in the second direction. The first gap 510 is also located between two adjacent second gate layers 300, and there is an overlap between the first gap 510 and the second gate layer 300. Through the above configuration, the first gap 510 can isolate two adjacent second gate layers 300, preventing coupling between them and improving the phenomenon of memory cell failure caused by coupling between adjacent second gate layers 300. In addition, the first gap 510 can also isolate two adjacent semiconductor pillars 100, preventing mutual interference between them, which is beneficial to improving the storage stability of the semiconductor structure 1000.

[0069] In some embodiments, reference Figure 4 The semiconductor structure 1000 also includes a connection structure 800. The two ends of the connection structure 800 along the first direction X are connected to the semiconductor pillar 100 and the capacitor structure 400, respectively. The material of the connection structure 800 includes a conductive material, such as a metallic material.

[0070] In this embodiment, the connecting structure 800 and the first gap 510 overlap in the second direction Y, that is, the orthographic projection of the connecting structure 800 in the second direction Y overlaps with the orthographic projection of the first gap 510 in the second direction Y. It should be noted that the overlap between the first gap 510 and the connecting structure 800 in the second direction Y can be all of the first gap 510 and the connecting structure 800 overlapping in the second direction Y, or it can be only a portion of the first gap 510 and the connecting structure 800 overlapping in the second direction Y.

[0071] With the above configuration, the first gap 510 can isolate the connection structure 800 to prevent the isolation structure 800 from coupling with other conductive structures, thereby improving the storage stability of the semiconductor structure 1000. For example, the first gap 510 can prevent coupling between two adjacent connection structures 800.

[0072] In some embodiments, such as Figure 3 As shown, the second gate layer 300 includes a metal gate 310 and a conductive film 320 stacked along the second direction Y, with the conductive film 320 located between the metal gate 310 and the semiconductor pillar 100. In some examples, the conductive film 320 may be located on both sides of the metal gate 310 along the second direction Y. The conductive film 320 is in contact with the metal gate 310, and the conductive film 320 and the metal gate 310 may extend in the same direction; for example, the conductive film 320 and the metal gate 310 may both extend along the first direction X.

[0073] For example, the metal gate 310 may be made of tungsten, and the conductive thin film 320 may be made of titanium nitride. The conductive thin film 320 has good conductivity, so that the second gate layer 300 can apply a voltage to the semiconductor pillar 100. Furthermore, the conductive thin film 320 also helps to prevent the metal gate 310 from diffusing into the dielectric material.

[0074] In some embodiments, such as Figure 3 As shown, the dimension d1 of the second gate layer 300 in the first direction X is greater than the dimension d2 of the first gate layer 200 in the first direction X. Here, the dimension d1 of the second gate layer 300 in the first direction X can be understood as the length of the second gate layer 300 in the first direction X. Similarly, the dimension d2 of the first gate layer 200 in the first direction X can be understood as the length of the first gate layer 200 in the first direction X.

[0075] In some examples, in the first direction X, when the second gate layer 300 is aligned with one end of the first gate layer 200, the other end of the second gate layer 300 protrudes beyond the other end of the first gate layer 200, so that the second gate layer 300 overlaps with the first dielectric layer 500 in the second direction Y, and so that the second gate layer 300 overlaps with the first gap 510 in the second direction Y.

[0076] In other examples, in the first direction X, both ends of the second gate layer 300 extend beyond both ends of the first gate layer 200, so that the second gate layer 300 overlaps with the first dielectric layer 500 in the second direction Y, and the second gate layer 300 overlaps with the first gap 510 in the second direction Y.

[0077] With the above configuration, the first gap 510 can isolate two adjacent second gate layers 300, prevent coupling between the two adjacent second gate layers 300, and improve the phenomenon of memory cell failure caused by coupling between adjacent second gate layers 300.

[0078] In some embodiments, the end of the second gate layer 300 is closer to the capacitor structure 400 than the end of the first gate layer 200. Of the two ends of the second gate layer 300 along the first direction X, the end closer to the capacitor structure 400 is designated as the first end 301. Of the two ends of the first gate layer 200 along the first direction X, the end closer to the capacitor structure 400 is designated as the second end 201. Therefore, the first end 301 is closer to the capacitor structure 400 than the second end 201.

[0079] In this embodiment, since the end of the second gate layer 300 is closer to the capacitor structure 400 than the end of the first gate layer 200, the second gate layer 300 can protrude from the first gate layer 200 in the direction from the semiconductor pillar 100 to the capacitor structure 400. This can also be understood as the second gate layer 300 being higher than the first gate layer 200. Furthermore, the portion of the second gate layer 300 protruding from the first gate layer 200 can overlap with the first gap 510 in the second direction Y.

[0080] With the above configuration, the first gap 510 can isolate two adjacent second gate layers 300, prevent coupling between the two adjacent second gate layers 300, and improve the phenomenon of memory cell failure caused by coupling between adjacent second gate layers 300.

[0081] In some embodiments, the dimension d3 of the first dielectric layer 500 in the first direction X is greater than the dimension d2 of the first gate layer 200 in the first direction X. Here, the dimension d3 of the first dielectric layer 500 in the first direction X can be understood as the length of the first dielectric layer 500 in the first direction X. Therefore, the first dielectric layer 500 is longer than the first gate layer 200 in the first direction X. Consequently, the volume of the first gap 510 in the first dielectric layer 500 can also be increased. This increases the overlapping area of ​​the first gap 510 and the second gate layer 300 in the second direction Y, which is more beneficial for isolating adjacent second gate layers 300, preventing coupling between adjacent second gate layers 300, and improving the phenomenon of memory cell failure caused by coupling between adjacent second gate layers 300.

[0082] In some embodiments, the dimension d3 of the first dielectric layer 500 in the first direction X ranges from 50 nm to 90 nm. For example, the dimension d3 of the first dielectric layer 500 in the first direction X can be 50 nm, 70 nm, or 90 nm. When the dimension d3 of the first dielectric layer 500 in the first direction X approaches 50 nm, the space left for the first gate layer 200 is larger, which is beneficial to increasing the dimension d2 of the first gate layer 200 in the first direction X, so that the first gate layer 200 can better control the threshold voltage of the semiconductor pillar 100. When the dimension d3 of the first dielectric layer 500 in the first direction X approaches 90 nm, the dimension d3 of the first dielectric layer 500 in the first direction X is larger, which is beneficial to increasing the overlap area of ​​the first gap 510 and the second gate layer 300 in the second direction Y, and is more beneficial to isolating two adjacent second gate layers 300, preventing coupling between two adjacent second gate layers 300, and improving the phenomenon of memory cell failure caused by coupling between adjacent second gate layers 300.

[0083] In some embodiments, such as Figure 3 As shown, the semiconductor structure 1000 includes: a plurality of semiconductor pillars 100, a plurality of capacitor structures 400, and a plurality of second gate layers 300. The plurality of semiconductor pillars 100 are spaced apart along a second direction Y. Correspondingly, the plurality of second gate layers 300 are arranged in a one-to-one correspondence with the plurality of semiconductor pillars 100, that is, one second gate layer 300 is located on one side of one semiconductor pillar 100 along the second direction Y. One second gate layer 300 and one semiconductor pillar 100 can constitute a vertical transistor T. The plurality of capacitor structures 400 are spaced apart along the second direction Y. One capacitor structure 400 is connected to one semiconductor pillar 100, that is, the plurality of capacitor structures 400 are connected in a one-to-one correspondence with the plurality of semiconductor pillars 100. A first gap 510 is located between two adjacent vertical transistors T along the second direction Y, and all of the first gaps 510 overlap with the semiconductor pillars 100 of the two vertical transistors T in the second direction Y, and the first gaps 510 also overlap with the second gate layers 300 of the two vertical transistors T.

[0084] By setting the first gap 510, it is beneficial to isolate the second gate layer 300 in two adjacent vertical transistors T, prevent coupling between two adjacent second gate layers 300, and improve the phenomenon of memory cell failure caused by coupling between adjacent second gate layers 300.

[0085] In some embodiments, the semiconductor structure 1000 further includes a second dielectric layer 600. The second dielectric layer 600 is located between the first gate layer 200 and the semiconductor pillar 100, and also between the first dielectric layer 500 and the semiconductor pillar 100. The second dielectric layer 600 can serve as an isolation layer between two adjacent vertical transistors T; therefore, the constituent material of the second dielectric layer 600 includes an insulating material. The insulating material may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high-dielectric-constant insulating materials, or other suitable insulating materials. The constituent material of the second dielectric layer 600 may be different from the constituent material of the first dielectric layer 500; for example, the material of the second dielectric layer 600 may include silicon oxide, while the material of the first dielectric layer 500 may include silicon nitride.

[0086] In addition, the second dielectric layer 600 is located between the first gate layer 200 and the semiconductor pillar 100, and also between the first dielectric layer 500 and the semiconductor pillar 100. In addition to isolating the semiconductor pillar 100 from the first gate layer 200 and further isolating the second gate layer 300 from other conductive structures, the second dielectric layer 600 also helps to protect the morphology of the semiconductor pillar 100 and prevent the semiconductor pillar 100 from being damaged during the fabrication of the semiconductor structure 1000.

[0087] In some embodiments, the second dielectric layer 600 may also be located between the second gate layer 300 and the semiconductor pillar 100. In this case, the second dielectric layer 600 may serve as a gate dielectric layer so that the second gate layer 300 and the semiconductor pillar 100 can be coupled.

[0088] This disclosure also provides a method for fabricating a semiconductor structure in some embodiments, which will be described below in conjunction with... Figures 5 to 11 The method for preparing semiconductor structures is explained.

[0089] like Figure 5 As shown, the semiconductor structure fabrication method includes: S1 to S5.

[0090] S1. Form a semiconductor pillar, which extends along a first direction.

[0091] In this step, refer to Figure 6 A semiconductor layer 700 is provided, and a portion of the semiconductor layer 700 is removed by a wet etching process or a dry etching process to form a plurality of semiconductor pillars 100 spaced apart along the second direction Y. The semiconductor pillars 100 extend along the first direction X, and a first groove 710 is provided between adjacent semiconductor pillars 100.

[0092] For example, the material of the semiconductor layer 700 may include, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0093] S2. A first gate layer is formed, which is located on one side of the semiconductor pillar along the second direction, where the second direction intersects the first direction.

[0094] In this step, refer to Figure 7 A second dielectric layer 600 and a first gate layer 200 can be sequentially formed within the first groove 710, and the second dielectric layer 600 and the first gate layer 200 surround the second groove 720. Furthermore, the second dielectric layer 600 can be located between the first gate layer 200 and the semiconductor pillar 100.

[0095] Here, the second dielectric layer 600 and the first gate layer 200 can be formed, for example, using a thin film deposition process. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0096] For example, the material of the second dielectric layer 600 may be silicon oxide, and the material of the first gate layer 200 may be titanium nitride.

[0097] After the second dielectric layer 600 and the first gate layer 200 are sequentially formed in the first groove 710 using a deposition process, a portion of the first gate layer 200 can be removed using, for example, a wet etching process to form the second groove 720.

[0098] S3. A first dielectric layer is formed at one end of the first gate layer along a first direction, and the first dielectric layer has a first gap.

[0099] refer to Figure 7 and Figure 8 In this step, a first dielectric layer 500 can be formed within the second groove 720 using a vapor deposition process. It should be noted that the formation rate of the first dielectric layer 500 can be adjusted using the vapor deposition process, so that the first dielectric layer 500 forms faster at both ends of the second groove 720 along the first direction X than at other locations in the second groove 720. This results in the first dielectric layer 500 ultimately formed in the second groove 720 being thicker at both ends and thinner in the middle along the first direction X, thereby creating a first gap 510. Through the above steps, the first dielectric layer 500 can have a first gap 510, which can be located between adjacent semiconductor pillars 100 and the first gate layer 200. Here, it can be understood that the first gap 510 can be located within the second groove 720.

[0100] For example, the material of the first dielectric layer 500 may include silicon nitride.

[0101] S4. A second gate layer is formed. The second gate layer is located on the other side of the semiconductor pillar along the second direction. The first gap overlaps with the second gate layer in the second direction.

[0102] In this step, refer to Figure 9 and Figure 10 A second gate layer 300 can be formed in a first groove 710 located on the semiconductor pillar 100 away from the first gate layer 200 along the second direction Y. Exemplarily, a gate dielectric layer 330, a second gate layer 300, and a gate isolation layer 340 can be formed by depositing a dielectric material, a conductive material, and an insulating material sequentially in the first groove 710 using one or more thin film deposition processes including but not limited to PVD, CVD, and ALD. The second gate layer 300 is located on the side of the semiconductor pillar 100 away from the first gate layer 200 along the second direction Y, and the second gate layer 300 can be coupled to the semiconductor pillar 100.

[0103] refer to Figure 10 and Figure 11 After the second gate layer 300 is formed, the surface of the semiconductor pillar 100 can be planarized by chemical mechanical polishing (CMP), for example, making the upper surface of the semiconductor pillar 100 flush with the upper surface of the first dielectric layer 500 and the upper surface of the gate isolation layer 340.

[0104] S5. A capacitor structure is formed, and the capacitor structure is connected to one end of the semiconductor pillar along the first direction. The first dielectric layer is closer to the capacitor structure than the first gate layer.

[0105] In this step, refer to Figure 3 A deposition process can be used to further form a connection structure and a capacitor structure 400 on the semiconductor pillar 100. The material of the connection structure includes a conductive material, so that the capacitor structure 400 is connected to one end of the semiconductor pillar 100 along the first direction X.

[0106] The semiconductor structure 1000 obtained by the above preparation method has a second gate layer 300 overlapping with a first gap 510 in the second direction Y. The first gap 510 can be filled with air, and the dielectric constant of air is approximately 1, which is less than the dielectric constant of conductive materials. Therefore, at the location of the first gap 510, the second gate layer 300 is less likely to couple with other conductive structures. Thus, by setting the first gap 510, it is beneficial to improve the coupling problem between the second gate layer 300 and other conductive structures.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor pillar extending along a first direction; A first gate layer and a second gate layer are respectively located on both sides of the semiconductor pillar along a second direction, which intersects the first direction; A capacitor structure is connected to one end of the semiconductor pillar along the first direction; A first dielectric layer is located at one end of the first gate layer along the first direction. The first dielectric layer is closer to the capacitor structure than the first gate layer. The first dielectric layer has a first gap, and the first gap overlaps with the second gate layer in the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The second gate layer includes a metal gate and a conductive film stacked along the second direction, wherein the conductive film is located between the metal gate and the semiconductor pillar.

3. The semiconductor structure according to claim 1, characterized in that, The dimension of the second gate layer in the first direction is greater than the dimension of the first gate layer in the first direction.

4. The semiconductor structure according to claim 1, characterized in that, The end of the second gate layer is closer to the capacitor structure than the end of the first gate layer.

5. The semiconductor structure according to claim 1, characterized in that, The dimension of the first dielectric layer in the first direction is greater than the dimension of the first gate layer in the first direction.

6. The semiconductor structure according to claim 1, characterized in that, The dimension of the first dielectric layer in the first direction ranges from 50 nm to 90 nm.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: A plurality of semiconductor pillars are spaced apart along the second direction; A plurality of said capacitor structures are arranged at intervals along the second direction, and one said capacitor structure is connected to one said semiconductor pillar; The first gap is located between adjacent semiconductor pillars.

8. The semiconductor structure according to claim 1, characterized in that, Also includes: The second dielectric layer is located between the first gate layer and the semiconductor pillar, and also between the first dielectric layer and the semiconductor pillar.

9. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor pillar is formed, the semiconductor pillar extending along a first direction; A first gate layer is formed, the first gate layer being located on one side of the semiconductor pillar along a second direction, the second direction intersecting the first direction; A first dielectric layer is formed at one end of the first gate layer along the first direction, and the first dielectric layer has a first gap; A second gate layer is formed, the second gate layer being located on the other side of the semiconductor pillar along the second direction, and the first gap and the second gate layer overlap in the second direction; A capacitor structure is formed, wherein the capacitor structure is connected to one end of the semiconductor pillar along the first direction, and the first dielectric layer is closer to the capacitor structure than the first gate layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The formation of the semiconductor pillar includes: A portion of the semiconductor layer is removed to form a plurality of semiconductor pillars spaced apart along the second direction, the semiconductor pillars extending along the first direction and having a first groove between adjacent semiconductor pillars; The formation of the first gate layer includes: A second dielectric layer and a first gate layer are sequentially formed in the first groove, and the second dielectric layer and the first gate layer surround the second groove. The formation of the first dielectric layer includes: The first dielectric layer is formed in the second groove by a vapor deposition process. The first dielectric layer has a first gap, which is located between the adjacent semiconductor pillar and the first gate layer.

11. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-8; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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